NAND wear leveling method based on integrated circuit ECC and read delay

Abstract

The invention relates to the technical field of intelligent chips, in particular to an NAND wear leveling method based on integrated circuit ECC (error correction code) and read delay, which comprises the following steps: acquiring read delay data and error correction code usage amount of a three-layer unit page of a target block in an NAND flash memory chip; on the basis of the read delay increment and the error correction code increment of the middle-layer page, the health index of the target block is calculated by combining the read delay difference value of the middle-layer page and the lower-layer page, the target block is divided into a plurality of health levels, and logic blocks of different health levels are mapped to different physical planes of the NAND flash memory chip; synchronously executing data migration and erasure operations of the plurality of blocks to be migrated by utilizing the parallel erasure capability of the multi-plane architecture for the target block of which the health level is degraded to a preset threshold value; and monitoring the deviation degree between the current read delay and the specification read delay in real time, and selecting the error correction strength grade of the error correction code according to the deviation degree.

Description

Technical Field

[0001] This invention relates to the field of smart chip technology, specifically to a NAND wear leveling method based on integrated circuit ECC and read latency. Background Technology

[0002] NAND flash memory, as the core medium of modern storage devices, achieves data storage through a charge trapping mechanism. However, its storage cells suffer irreversible physical damage during repeated programming and erasing operations. Triple-cell NAND flash memory increases storage density by storing three bits of data in a single cell, but its program-erase cycle life is typically only a few thousand cycles, far lower than that of single-cell flash memory. To extend the overall lifespan of NAND flash memory, wear leveling technology has become one of the core functions of flash memory controllers.

[0003] Existing wear leveling methods primarily rely on programmed erase count statistics. By recording the number of erases and writes for each storage block, when the erase count of some blocks is too high, their data is migrated to blocks with lower erase counts to achieve a balance in wear levels across blocks. However, this method is a passive, reactive management approach, triggering the leveling operation only when a block reaches a preset erase threshold or bad blocks are detected. It lacks the ability to provide early warning of deteriorating storage block health trends, leading to data security risks.

[0004] Therefore, there is an urgent need for a NAND flash memory wear leveling method that can accurately reflect the true physical health status of storage blocks and perform leveling operations, in order to solve the technical problem of inaccurate health assessment in the existing technology, which leads to a delay in leveling timing.

[0005] To address this, a NAND wear leveling method based on integrated circuit ECC and read delay is proposed. Summary of the Invention

[0006] The purpose of this invention is to provide a NAND wear leveling method based on integrated circuit ECC and read latency. By analyzing the read latency and ECC usage of NAND flash memory's three-layer cell pages, a block health index is calculated, and health levels are assigned accordingly. Data allocation is optimized by mapping logic blocks with different health levels to different physical planes. When a block's health deteriorates to a threshold, multi-plane parallel erase / write capabilities are used to synchronously migrate and erase critical blocks. During read operations, the ECC error correction strength is dynamically adjusted based on the read latency deviation, and the storage mode of sub-healthy blocks is changed from three-layer cells to single-layer cells to improve the reliability and performance of NAND flash memory.

[0007] To achieve the above objectives, the present invention provides the following technical solution: NAND wear leveling methods based on integrated circuit ECC and read latency include: Obtain read latency data and error correction code usage of the three-layer cell pages of the target block in the NAND flash memory chip. The three-layer cell pages include the lower layer page, the middle layer page, and the upper layer page. Based on the read latency increment and error correction code increment of the middle-layer page, and combined with the read latency difference between the middle-layer page and the lower-layer page, the health index of the target block is calculated. According to the health index, the target block is divided into multiple health levels, and blocks located in different physical planes are preferentially selected for data allocation, so that logical blocks of different health levels are mapped to different physical planes of the NAND flash memory chip. For target blocks whose health level deteriorates to a preset threshold, endangered blocks are selected from each physical plane containing blocks to be migrated, and the parallel erase and write capabilities of the multi-plane architecture are used to simultaneously execute data migration and erase operations of multiple blocks to be migrated. During the data reading process, the deviation between the current read latency and the specified read latency is monitored in real time, and the error correction strength level of the error correction code is selected according to the degree of deviation; for blocks with a sub-healthy health level, their storage mode is changed from three-level cell mode to single-level cell mode.

[0008] Preferably, the health index of the target block is calculated based on the read latency increment and error correction code increment of the middle-layer page, combined with the read latency difference between the middle-layer page and the lower-layer page. Specifically, this includes: obtaining the current read latency of the middle-layer page and the lower-layer page respectively, and comparing it with the corresponding baseline read latency to obtain their respective read latency increments; calculating the difference in read latency increments between the middle-layer page and the lower-layer page as a coupling interference factor, which reflects the broadening of the threshold voltage distribution caused by the accumulation of programming interference and read interference; obtaining the current number of error correction code bits of the middle-layer page, and comparing it with the baseline number of error correction bits to calculate the error correction code utilization rate increment; and weighted summing the read latency increment, error correction code utilization rate increment, and coupling interference factor of the middle-layer page to obtain the health index of the target block.

[0009] Preferably, the target block is divided into multiple health levels based on the health index, and blocks located on different physical planes are preferentially selected for data allocation. Specifically, this includes: setting multiple health index threshold ranges; classifying blocks with health indices below the first threshold as healthy and preferentially mapping them to the first physical plane to carry high-frequency write data; classifying blocks with health indices between the first and second thresholds as good and preferentially mapping them to the second physical plane to carry medium-frequency write data; classifying blocks with health indices between the second and third thresholds as sub-healthy and preferentially mapping them to the third physical plane with write operations restricted; classifying blocks with health indices exceeding the third threshold as endangered and preferentially mapping them to the fourth physical plane and marking them as awaiting migration. Different physical planes are physically coupled through a shared substrate and power path, and hierarchical mapping achieves operational timing isolation and differentiated voltage management for blocks in different health states.

[0010] Preferably, endangered blocks are selected from each physical plane containing blocks to be migrated. Utilizing the parallel erase / write capability of the multi-plane architecture, data migration and erasure operations for multiple blocks to be migrated are executed simultaneously. Specifically, this includes: selecting one endangered source block from each of the first to fourth physical planes, and simultaneously selecting corresponding target blocks from the healthy blocks of each physical plane; synchronously reading valid data from each source block into a data buffer using a multi-plane read command sequence; writing the buffer data into each target block in a pipelined manner using a multi-plane programming command sequence, where the programming operations of each physical plane time-division multiplex the high-voltage charge pump resources, and the programming pulses applied to each plane are staggered to avoid charge pump overload; synchronously erasing each source block using a multi-plane erase command sequence, ensuring overlapping erase voltage application timings across physical planes; and re-evaluating the health level of the erased source blocks based on the cumulative number of erase / write operations, prioritizing them as candidate blocks of good and / or sub-healthy levels and adding them to the idle block pool for subsequent allocation.

[0011] Preferably, the error correction strength level of the error correction code is dynamically selected based on the degree of deviation, specifically including: When the read delay deviation is less than the first deviation threshold, a low-intensity error correction level is selected, using a shortened check polynomial and / or reducing the number of iterations, and using some error correction code redundancy bytes for error correction; when the read delay deviation is between the first and second deviation thresholds, a medium-intensity error correction level is selected, using a moderate proportion of error correction code redundancy bytes for error correction; when the read delay deviation is between the second and third deviation thresholds, a high-intensity error correction level is selected, using most of the error correction code redundancy bytes for error correction; when the read delay deviation exceeds the third deviation threshold, the maximum-intensity error correction level is selected, using all error correction code redundancy bytes for error correction, and a data migration warning is triggered simultaneously.

[0012] Preferably, when low-intensity error correction fails, the error is escalated to a high-intensity level and the reference voltage is adjusted before rereading. Specifically, this includes: At the current error correction strength level, perform error correction decoding to determine if decoding is successful. If decoding fails, increase the error correction strength level by one level, increase the number of redundant bytes involved in the error correction calculation, and re-execute decoding. If decoding still fails after increasing the error correction strength, adjust the read reference voltage of the NAND flash memory chip by setting characteristic commands. The adjustment direction of the read reference voltage is determined based on the threshold voltage drift trend statistically analyzed in historical read operations. Re-read the memory cell data at the adjusted read reference voltage and decode using the current error correction strength level. If error correction still fails after multiple adjustments to the read reference voltage, record the error correction failure event and immediately trigger a data migration operation.

[0013] Preferably, the storage mode is converted from a three-level cell mode to a single-level cell mode, and the converted block is used as a read-only cache. Specifically, this includes: reading the three-level cell mode data in the sub-healthy block, where the three-level cell mode data is distributed across the lower, middle, and upper pages; migrating the valid data that needs to be retained to the healthy block and / or buffer, and then performing an erase operation on the block to clear the original multi-threshold voltage state; programming the block in single-level cell mode, writing data only to the lower page address, with each storage unit storing only one bit of information; configuring the converted block as a read-only cache, limiting the frequency of subsequent programming and erasure, and performing low-frequency updates only when the cached data becomes invalid; and marking the block as endangered and triggering a replacement process when the read latency exceeds the safety threshold of the single-level cell mode.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention introduces multi-dimensional indicators such as "intermediate layer page read latency increment," "ECC utilization increment," and "inter-page read latency difference," and constructs a coupling interference factor to reflect the broadening of threshold voltage distribution caused by programming interference and read interference, thereby enabling real-time mapping of the micro-degradation trend of NAND cells. This method not only distinguishes the aging differences of lower, middle, and upper layer pages in the TLC hierarchical structure, but also comprehensively considers the linkage between read latency offset and ECC consumption, making the health index more sensitive and predictive. Through this refined multi-dimensional weighted health index, this invention can identify potential degradation trends in advance before serious errors occur in the target block, significantly improving the sensitivity and reliability of wear detection.

[0015] 2. This invention employs a health index grading system, mapping blocks of different health levels to different physical planes. This prioritizes high-frequency write data allocation to healthy planes, while concentrating degraded blocks in lower-frequency planes, preventing interference accumulation caused by mixing blocks in different health states. Furthermore, this invention utilizes a NAND multi-plane architecture to achieve parallel reading, parallel programming, and parallel erasing across planes. This allows multiple critical blocks to simultaneously complete data migration and block erasure, significantly shortening migration time. The multi-plane command sequence shares programming pulses and charge pump resources, optimizing internal timing, improving energy efficiency, and reducing operational overhead. Simultaneously, the tiered mapping structure reduces voltage interference between blocks of different health levels, improving overall read / write stability.

[0016] 3. This invention dynamically selects the ECC error correction strength level by monitoring read latency deviation in real time, enabling redundant ECC bytes to be activated as needed. This achieves low-intensity error correction for minor wear and maximum-intensity error correction for severe wear, and further improves the error correction success rate by dynamically adjusting the read reference voltage. If multiple error correction failures occur, the event is automatically recorded and the degradation model is updated more quickly, making the migration strategy more timely and reliable. Furthermore, when a block enters a sub-healthy state, this invention automatically downgrades it from TLC mode to SLC mode, erasing the original multi-threshold voltage state and allowing the memory cell to operate in single-bit mode again. SLC has a lower programming voltage and fewer write verification cycles, significantly reducing storage stress. Simultaneously, the downgraded block serves as a read-only cache, storing frequently read data to avoid further write wear. Attached Figure Description

[0017] Figure 1 A flowchart of the NAND wear leveling method based on integrated circuit ECC and read delay provided by the present invention; Figure 2 The data migration and erasure operation flowchart provided by this invention; Figure 3 The flowchart for ECC and read latency NAND wear leveling provided by this invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the invention.

[0019] Example 1: Please see Figure 1This invention provides a NAND wear leveling method based on integrated circuit ECC and read latency. The technical solution is as follows: The read latency data and error correction code usage of the three-layer cell pages of the target block in the NAND flash memory chip are obtained. The three-layer cell pages include a lower layer page, a middle layer page, and an upper layer page. Based on the read latency increment and error correction code increment of the middle layer page, combined with the read latency difference between the middle layer page and the lower layer page, a health index of the target block is calculated. The target block is divided into multiple health levels according to the health index, and blocks located on different physical planes are preferentially selected for data allocation, so that logical blocks of different health levels are mapped to different physical planes of the NAND flash memory chip. For target blocks whose health level has deteriorated to a preset threshold, endangered blocks are selected from each physical plane containing blocks to be migrated. The parallel erase / write capability of the multi-plane architecture is used to simultaneously execute data migration and erase operations on multiple blocks to be migrated. During data reading, the deviation between the current read latency and the specified read latency is monitored in real time, and the error correction strength level of the error correction code is selected according to the deviation level. For blocks in a sub-healthy state, their storage mode is converted from a three-layer cell mode to a single-layer cell mode.

[0020] When acquiring the three-level cell page read latency data of a target block in a NAND flash memory chip, the controller starts an internal timer after sending the read command to record the time interval from command transmission to the data ready signal (R / B pin goes high). This time is the read latency. For each target block, the read latency values ​​of representative pages selected from its lower, middle, and upper layers are recorded separately, with three read latency data records for each block. These read latency data, along with the corresponding block address and page type identifier, are stored in a health management table in the controller's DRAM. The health management table uses a hash table structure, with the block address as the key. Each entry contains fields such as block address, lower-level page read latency, middle-level page read latency, upper-level page read latency, ECC error correction bits, health index, and health level.

[0021] Furthermore, based on the read latency increment and error correction code increment of the middle-layer page, combined with the read latency difference between the middle-layer page and the lower-layer page, the health index of the target block is calculated. Specifically, this includes: obtaining the current read latency of the middle-layer page and the lower-layer page respectively, and comparing it with the corresponding baseline read latency to obtain their respective read latency increments; calculating the difference in read latency increments between the middle-layer page and the lower-layer page as a coupling interference factor, which reflects the broadening of the threshold voltage distribution caused by the accumulation of programming interference and read interference; obtaining the current number of error correction code bits of the middle-layer page, and comparing it with the baseline number of error correction bits to calculate the error correction code utilization rate increment; and weighted summing the read latency increment, error correction code utilization rate increment, and coupling interference factor of the middle-layer page to obtain the health index of the target block. The baseline read latency is obtained as follows: During the NAND flash memory chip's factory initialization phase or upon first power-on, a standard read operation is performed on the brand-new memory block, measuring the initial read latency values ​​of the lower, middle, and upper layers of pages. This value is stored as the baseline read latency for the corresponding page type in the controller's non-volatile memory area. This baseline value reflects the ideal read performance of the memory cell before wear. The baseline error correction bit count is obtained as follows: During the same initialization phase, page data of the brand-new block is read, and the actual number of error bits that need to be corrected is counted using an ECC decoder. Typically, the error bit count of a brand-new block is close to zero or contains only a small number of inherent errors caused by manufacturing defects. This initial error bit count is recorded as the baseline error correction bit count. Subsequently, by comparing the difference between the current error correction bit count and the baseline value, the ECC utilization increment is calculated to accurately assess the degree of memory cell degradation.

[0022] Before weighted summing the read latency increment, error correction code utilization increment, and coupling interference factor of the mid-layer page, each parameter is first normalized. The read latency increment of the mid-layer page is divided by the maximum allowable read latency increment for that page type to obtain the normalized read latency increment, with a value ranging from 0 to 1. The error correction code utilization increment is divided by the utilization rate corresponding to the maximum error correction capability to obtain the normalized ECC utilization increment. The coupling interference factor is divided by the maximum inter-layer interference value defined in the specification to obtain the normalized coupling interference factor. Then, a weighted sum is performed according to preset weight coefficients: 0.4 for read latency increment, 0.4 for ECC utilization increment, and 0.2 for coupling interference factor. The weighted sum of these three is the health index. The weight coefficients are set based on extensive experimental data statistics, ensuring a strong correlation between the health index and the actual block failure probability. Given the differences in NAND flash memory products and operating environments, the weighting coefficients used to measure the contribution of read latency increment, ECC utilization increment, and coupling interference factor to the health index are not fixed, but can be dynamically adjusted according to the actual operating environment, NAND characteristics, and application requirements. The setting range and optimal values ​​of these weighting coefficients are obtained through statistical analysis of a large amount of actual test data or expert judgment, aiming to achieve a sensitive and accurate response to the wear and tear of storage cells.

[0023] By collecting the read latency increments of middle-layer and lower-layer pages, calculating the coupling interference factor, and combining it with the error correction code usage rate increment for weighted summation, a health index is obtained. In this embodiment, compared with the single-index evaluation method, this multi-dimensional health assessment mechanism can more accurately reflect the actual degradation degree of NAND storage cells. In particular, the coupling interference factor can quantify the cumulative effect of programming interference and read interference, thereby improving the evaluation accuracy of the health index and avoiding misjudgments caused by relying solely on erase and write count statistics. It can trigger early warnings in the early stages of actual block degradation.

[0024] The calculation of the target block's health index also includes a temperature compensation step, specifically: The operating temperature of the NAND flash memory chip is obtained in real time using a temperature sensor. A correlation model between read latency and temperature is established. Under high temperature conditions, the charge retention capability of memory cells decreases, leading to accelerated threshold voltage drift. The read latency increment includes recoverable deviations caused by temperature. The measured read delay increment is normalized according to the current temperature to eliminate the interference of temperature fluctuations on the health index assessment. When the temperature exceeds the preset safe operating temperature, the health index weighting coefficient of all target blocks is temporarily increased, and the write intensity at high temperature is reduced.

[0025] When normalizing the measured read delay increment to the current temperature, the read delay temperature coefficient for different temperature ranges is first determined based on the temperature characteristic curves in the NAND flash memory chip datasheet. The temperature offset is then subtracted from the read delay increment measured at the current temperature, where the temperature offset is equal to the difference between the current temperature and the reference temperature multiplied by the temperature coefficient for the corresponding temperature range. The normalized read delay increment represents the equivalent value converted from the measured read delay increment to the reference temperature condition, eliminating the influence of temperature fluctuations and making the health index measured at different temperatures comparable.

[0026] By acquiring the NAND operating temperature through a temperature sensor, a correlation model between read latency and temperature is established. Read latency increments are normalized for temperature, and the health index weight is temporarily increased to reduce write intensity at high temperatures. In this embodiment, the temperature compensation mechanism eliminates the interference of temperature fluctuations on health assessment, improving the accuracy of health index assessment over a wide temperature range of -40℃ to 85℃, and avoiding misclassifying normal blocks as sub-healthy blocks in high-temperature environments. Temperature normalization ensures consistency of read latency-based health assessments across different seasons and regions, reducing invalid data migration operations. The strategy of proactively reducing write intensity at high temperatures slows down the degradation rate of NAND in high-temperature environments, extending NAND lifespan in high-temperature scenarios such as industrial and automotive applications. The overall solution improves the reliability of the storage system when operating over a wide temperature range.

[0027] Furthermore, the target blocks are divided into multiple health levels based on the health index, and blocks located on different physical planes are preferentially selected for data allocation. Specifically, this includes: setting multiple health index threshold ranges; classifying blocks with health indices below the first threshold as healthy and preferentially mapping them to the first physical plane to carry high-frequency write data; classifying blocks with health indices between the first and second thresholds as good and preferentially mapping them to the second physical plane to carry medium-frequency write data; classifying blocks with health indices between the second and third thresholds as sub-healthy and preferentially mapping them to the third physical plane with write operations restricted; and classifying blocks with health indices exceeding the third threshold as endangered and preferentially mapping them to the fourth physical plane and marking them as awaiting migration. Different physical planes are physically coupled through a shared substrate and power path, and hierarchical mapping is used to achieve operational timing isolation and differentiated voltage management for blocks in different health states.

[0028] Health levels are mapped based on the actual number of physical planes in the NAND flash memory chip. For NAND chips with two physical planes, healthy and good-level blocks are preferentially mapped to the first physical plane, while sub-healthy and critical-level blocks are preferentially mapped to the second physical plane. For NAND chips with four physical planes, the four health levels are mapped to their respective four physical planes. This hierarchical mapping concentrates blocks with similar health states within the same plane, allowing for uniform timing parameters and voltage margin settings when performing multi-block operations. For planes with a concentration of critical-level blocks, the controller pre-configures higher voltage margins and longer pulse widths via feature setting commands when sending programming and erase commands, improving operation success rates. For planes with a concentration of healthy-level blocks, standard voltage and timing parameters are used to maintain optimal performance. This differentiated management is achieved through controller command parameters, rather than physically isolating the internal voltages of the chip.

[0029] The health index of the target block is obtained by weighted summing of the read latency increment of the middle-layer page, the error correction code usage rate increment, and the coupling interference factor. The higher the health index value, the more severe the block degradation and the worse its health condition. A health index of zero indicates that the block is in its initial factory state. As the erase and write cycles accumulate, the health index gradually increases until it exceeds the failure threshold.

[0030] Based on the health index, target blocks are divided into four levels: healthy, good, sub-healthy, and endangered. Blocks of different levels are mapped to different physical planes to achieve operational timing isolation and differentiated voltage management. For programming and erasing operations on different planes, differentiated timing and voltage parameters are configured via controller command parameters. Health level block concentrated plane: adopts standard programmed pulse width (set as reference value W_base, recommended value 2.0-2.5µs) and standard voltage margin (set as reference value V_base). Good-level block concentrated plane: programming pulse width is W_base×1.1, voltage margin is V_base+0.1V. Sub-health level block concentrated plane: programming pulse width is W_base×1.3, voltage margin is V_base+0.3V. Endangered level block concentrated plane: programming pulse width is W_base×1.5, voltage margin is V_base+0.5V; By interleaving the timing of the multi-plane programming command sequence, a recovery delay of 200-300ns is inserted between the programming pulses of adjacent planes to ensure that the output voltage of the high-voltage charge pump recovers to the stable operating range.

[0031] The specific implementation of the operation timing isolation is as follows: When executing a multi-plane programming command sequence, the controller does not apply programming voltages to all planes simultaneously, but instead uses a sequential interleaving method; the first physical plane starts the programming pulse first, and the pulse width is set according to the health level of the plane (e.g., 3µs for a critical plane). After the pulse ends, the controller delays for 200-300ns (this delay can be determined according to the recovery time constant in the charge pump datasheet, with a typical value of 200ns) before starting the programming pulse for the second plane. This interleaved timing avoids multiple planes simultaneously demanding high current from the charge pump, preventing the output voltage from falling below specifications, thereby ensuring the success rate of the programming operation.

[0032] The specific implementation of differentiated voltage management is as follows: The read reference voltage and programming high voltage of the NAND flash memory controller are typically generated by a dedicated DC-DC converter and charge pump. The controller sends configuration commands to these modules via GPIO or SPI interfaces to set the target value of the output voltage. For blocks of different health levels in different physical planes, the controller can pre-configure different high voltage target values ​​for each plane. For example, if the first physical plane mainly stores healthy level blocks, the programming high voltage is set to the standard value (e.g., 19V); if the fourth physical plane mainly stores endangered level blocks, the programming high voltage is set to 19.5V (an increase of 0.5V). This configuration is typically sent once before block operation via a feature setting command, and all subsequent programming operations on that plane use the corresponding high voltage setting.

[0033] In this embodiment, through a hierarchical mapping strategy, healthy blocks carrying high-frequency write data can fully utilize their excellent characteristics, while endangered blocks are isolated to an independent plane to avoid interference from their high-voltage operation on healthy blocks. This reduces the overall write latency standard deviation of the NAND and significantly improves performance stability. At the same time, differentiated voltage management allows endangered blocks to use more aggressive erase and write voltages to improve the success rate without affecting the normal operation of healthy blocks. Overall data reliability is improved, effectively slowing down the degradation rate of the overall NAND performance.

[0034] Furthermore, endangered blocks are selected from each physical plane containing blocks to be migrated. Utilizing the parallel write / erase capabilities of the multi-plane architecture, data migration and erasure operations for multiple blocks to be migrated are executed simultaneously, referring to... Figure 2Specifically, this includes: selecting one critically endangered source block from each of the first to fourth physical planes, and simultaneously selecting corresponding target blocks from the healthy level blocks of each physical plane; synchronously reading valid data from each source block into the data buffer using a multi-plane read command sequence; writing the buffer data into each target block in a pipelined manner using a multi-plane programming command sequence, where the programming operations of each physical plane time-division multiplex the high-voltage charge pump resources, and the programming pulses applied to each plane are staggered to avoid charge pump overload; synchronously erasing each source block using a multi-plane erase command sequence, so that the erasure voltage application timing of each physical plane overlaps; re-evaluating the health level of the erased source blocks based on the cumulative number of erase / write operations, and prioritizing them as candidate blocks of good and / or sub-healthy levels to be added to the free block pool for subsequent allocation.

[0035] To avoid charge pump overload, an interleaved timing approach is employed. This involves: sequentially applying programming pulses to each physical plane, with a recovery delay between programming pulses on adjacent planes. The recommended range for this recovery delay is 200-400 ns, and the specific value should be determined based on the charge pump's output voltage recovery time constant in the NAND chip datasheet; performing a programming verification read operation after each round of programming pulse application, with a verification interval of 500 ns to 1 µs. This interleaved timing arrangement ensures that the high-voltage charge pump's output voltage remains consistently at the target programming high voltage value. Within the 50mV range.

[0036] The plane read command sequence includes: first, sending a 00h command (read setup command) to the first physical plane, followed by five bytes of row and column addresses specifying the starting page address of the first source block, and then sending a 30h command to initiate the read operation without waiting for readiness. Next, sending a 00h command and address to the second physical plane, followed by a 30h command. This process is repeated for the third and fourth physical planes. After sending a 30h command to the last plane, the system waits for readiness signals from all planes. Once ready, data is read sequentially from each plane into the controller's data buffer, using the 00h-address-31h command sequence for multi-plane buffer reads. Data read from each plane is stored in the buffer in plane order. The multi-plane programming and erase command sequences use a similar structure: programming uses the 80h-address-data-11h sequence, erasure uses the 60h-address-D1h sequence, and the last plane uses a confirmation command 10h or D0h to actually execute the operation.

[0037] When erasing source blocks synchronously using a multi-plane erase command sequence, although the timing of the erase voltage application on each physical plane overlaps, the current requirements of the erase operation and the programming operation differ. After applying a high voltage to the substrate during the erase operation, each memory cell slowly releases charge through the Fowler-Nordheim tunneling mechanism. The instantaneous peak current of this process is lower than the channel hot electron injection current of the programming operation. Simultaneously, the erase voltage generation circuit and the programming voltage generation circuit within the NAND chip use independent charge pump modules, resulting in a relatively stable power load during erasure. Therefore, applying erase voltages on multiple planes simultaneously does not cause charge pump overload; instead, the long duration of the erase operation can be utilized to shorten the total erase time.

[0038] When the programming pulses for each physical plane are applied using an interleaved timing sequence, the controller triggers the programming operation sequentially according to the plane number. The first physical plane applies the programming voltage pulse first, with the pulse width dynamically adjusted based on the programming verification results. After the programming pulse for the first physical plane ends, a preset charge pump recovery time is allowed before the programming pulse application for the second physical plane is initiated. This recovery time is determined based on the output voltage recovery characteristics of the charge pump, ensuring that the charge pump output voltage has recovered to a stable operating range before programming the next physical plane. After each of the four physical planes completes one round of programming pulse application, a programming verification read is performed, and the verification results determine whether additional programming pulses are needed. This sequential interleaving method avoids output voltage drops caused by multiple planes simultaneously demanding high current from the charge pump.

[0039] By utilizing a multi-plane architecture to simultaneously perform data migration and erasure operations on multiple critical blocks, and employing a pipelined programming approach to time-division multiplex charge pump resources, the health level of erased blocks is reassessed based on the cumulative number of erase cycles. In this embodiment, the parallel operation of multiple planes reduces the total time spent on data migration. In the scenario of migrating four critical blocks, the total time is shortened, significantly reducing the blockage of normal I / O operations. The staggered timing of pipelined programming avoids programming voltage drops caused by charge pump overload, thus maintaining a stable programming success rate. The mechanism of reassessing the health level based on the cumulative number of erase cycles avoids misjudging blocks with high P / E cycles as healthy blocks, making subsequent block allocation more reasonable, improving the overall wear leveling effect, and extending the lifespan of NAND.

[0040] The multi-plane data migration process also includes a write amplification optimization step, specifically including: When selecting source blocks, prioritize endangered blocks with a valid data ratio higher than a preset threshold to avoid performing whole block migration for a small amount of valid data. For critical blocks where the percentage of valid data is below a preset threshold, garbage collection is first triggered. The small amount of valid data in the block is merged into other partially filled blocks that already contain valid data, making the block completely invalid. Completely invalid blocks can be directly erased without data migration, avoiding the need to perform a whole block data migration operation for a small amount of valid data. If a whole block migration is performed on a critical block where the percentage of valid data is only 10%, the entire block size of data needs to be migrated and it occupies a complete target block. However, through garbage collection, only the actual amount of valid data needs to be migrated, and it can be filled into the free space of other blocks, significantly reducing the total write volume. The scattered valid data is concentrated into other blocks, and then the block is directly erased and recycled. During multi-plane data migration, data compression algorithms are used to compress the data to be migrated, reducing the amount of data actually written. The write amplification factor for each migration operation is calculated. When the write amplification factor exceeds the threshold, the endangered block selection strategy is adjusted to prioritize the processing of blocks with a higher proportion of valid data.

[0041] During multi-plane data migration, critical blocks with a high percentage of valid data are prioritized, while low-percentage blocks undergo garbage collection first. Data compression algorithms are used to reduce write volume, and the selection strategy is dynamically adjusted based on the write amplification factor. In this embodiment, the strategy of prioritizing the migration of blocks with a high percentage of valid data reduces the average write amplification factor from the traditional 4.5-5.5 to 2.8-3.5, significantly reducing the actual physical write volume of NAND. Garbage collection preprocessing prevents the migration of low-percentage blocks in their entirety. Data compression algorithms (such as LZ4) can achieve compression rates of 40-60% for text and log data, further reducing the actual write volume. The dynamic adjustment strategy optimizes block selection based on real-time write amplification factor feedback, improving the adaptability of the wear leveling algorithm. The overall solution reduces the total number of erase / write cycles for NAND.

[0042] Furthermore, the error correction strength level of the error correction code is dynamically selected based on the degree of deviation, specifically including: When the read delay deviation is less than the first deviation threshold, a low-intensity error correction level is selected, using a shortened check polynomial and / or reducing the number of iterations, and using some error correction code redundancy bytes for error correction; when the read delay deviation is between the first and second deviation thresholds, a medium-intensity error correction level is selected, using a moderate proportion of error correction code redundancy bytes for error correction; when the read delay deviation is between the second and third deviation thresholds, a high-intensity error correction level is selected, using most of the error correction code redundancy bytes for error correction; when the read delay deviation exceeds the third deviation threshold, the maximum-intensity error correction level is selected, using all error correction code redundancy bytes for error correction, and a data migration warning is triggered simultaneously.

[0043] When the read delay deviation is less than the first deviation threshold, a low-intensity error correction level is selected. If the ECC module uses a BCH code architecture, the first quarter byte of the ECC redundant bytes stored in the OOB area is used for decoding, corresponding to an error correction capability of correcting 4 bits of error per 1024 bytes. If the ECC module uses an LDPC code architecture, the decoding iteration count is set to 5, and a partial parity check matrix is ​​used for confidence propagation calculation. When the read delay deviation is between the first and second deviation thresholds, a medium-intensity error correction level is selected, the first half of the redundant bytes of the BCH code are used, and the LDPC code iteration count is increased to 10. When the read delay deviation is between the second and third deviation thresholds, a high-intensity error correction level is selected, the first three-quarters of the redundant bytes of the BCH code are used, and the LDPC code iteration count is increased to 15. When the read delay deviation exceeds the third deviation threshold, the maximum-intensity error correction level is selected, all ECC redundant bytes are used, the BCH code reaches its maximum error correction capability, and the LDPC code iteration count is increased to more than 20 until convergence or the maximum iteration limit is reached.

[0044] The dynamic error correction mechanism dynamically selects four levels of error correction intensity (low, medium, high, and maximum) based on the degree of read latency deviation, and uses different proportions of ECC redundant bytes for error correction. In this embodiment, the dynamic error correction mechanism uses low-intensity error correction when the read latency deviation is small, which improves the read throughput by about 40-60%. When the read latency deviation increases, the error correction intensity is automatically increased. Compared with fixed maximum error correction intensity, this scheme reduces the average power consumption of the ECC module, which can significantly extend battery life in power-sensitive applications such as mobile devices. At the same time, the mechanism that triggers a data migration warning during maximum error correction intensity reduces the risk of data loss.

[0045] Furthermore, when low-intensity error correction fails, the error is escalated to a high-intensity level, the reference voltage is adjusted, and the reading is repeated. Specifically, this includes: At the current error correction strength level, perform error correction decoding to determine if decoding is successful. If decoding fails, increase the error correction strength level by one level, increase the number of redundant bytes involved in the error correction calculation, and re-execute decoding. If decoding still fails after increasing the error correction strength, adjust the read reference voltage of the NAND flash memory chip using a setting characteristic command. The adjustment direction of the read reference voltage is determined based on the threshold voltage drift trend statistically analyzed in historical read operations. Re-read the memory cell data at the adjusted read reference voltage and decode using the current error correction strength level. If error correction still fails after multiple adjustments to the read reference voltage, record the error correction failure event, increase the health index degradation rate of the block, and immediately trigger a data migration operation.

[0046] If increasing the error correction strength still fails, proceed with the reference voltage adjustment process: a) Analyze the results of the last 100 read operations, record the number of error bits for each failed read, and calculate the average number of error bits M_avg; b) Calculate the percentage of failures in the most recent N reads (N≥100): R_fail = number of failures / total number of operations; c) Analyze the threshold voltage drift trend: If the number of error bits in subsequent failures shows an increasing trend in the last 10 consecutive failures, it is determined to be 'drifting in the positive direction', and the reference voltage should be adjusted in the negative direction. If, in the last 10 consecutive failures, the number of error bits in subsequent failures shows a decreasing trend, it is determined to be 'drifting in the negative direction', and the reference voltage should be adjusted in the positive direction; The reference voltage adjustment step size is 50mV-100mV, and the number of adjustments should not exceed 3. The memory cell data is reread under the adjusted read reference voltage and decoded using the current error correction strength level; If the error cannot be corrected after three reference voltage adjustments, the error correction failure event is recorded, the health index degradation rate of the block is increased to 1.5 times or 2 times the normal rate, and a data migration operation is immediately triggered.

[0047] When error correction fails, the error correction intensity is gradually increased and the read reference voltage is adjusted. The adjustment direction is determined based on the historical threshold voltage drift trend. In this embodiment, the multi-level fault tolerance mechanism improves the success rate of error correction after the read reference voltage is optimized, which significantly reduces the data unrecoverable error rate. The intelligent adjustment of the read reference voltage is superior to blindly searching for the optimal voltage. The recording of error correction failure events and the dynamic adjustment of the health index degradation rate automatically reduce the subsequent write frequency of the block, avoiding accelerated degradation. The immediately triggered data migration operation reduces the risk of data loss to near zero.

[0048] Furthermore, the storage mode is converted from a three-level cell mode to a single-level cell mode, and the converted blocks are used as read-only caches. Specifically, this includes: reading three-level cell mode data from blocks in a sub-healthy state, where the data is distributed across lower, middle, and upper pages; migrating the valid data that needs to be retained to healthy blocks and / or buffers, and then performing an erase operation on the blocks to clear the original multi-threshold voltage state; programming the blocks in single-level cell mode, writing data only to the lower page address, with each storage cell storing only one bit of information; the programming voltage pulse intensity in single-level cell mode is lower than that in three-level cell mode, and the number of verification reads is reduced, thus reducing further damage to the storage cells; configuring the converted blocks as read-only caches to store frequently accessed hot data or system metadata, limiting the frequency of subsequent programming and erasure, and performing low-frequency updates only when cached data becomes invalid; periodically monitoring the read latency changes of read-only cache blocks, and marking the block as endangered and triggering a replacement process when the read latency exceeds the safety threshold of single-level cell mode.

[0049] The detailed implementation of SLC mode conversion is as follows: Data migration preprocessing: Before performing the transformation, scan all pages of the sub-healthy block to count the number of valid data pages and the total data volume; calculate the required number of target blocks based on the data volume (considering that other blocks may also store new data); check if there are enough healthy blocks in the free block pool for data migration; if not, the transformation should be delayed or additional garbage collection operations should be initiated; prioritize valid data: system metadata > user data > log data, and prioritize the migration of critical data.

[0050] Block erasure and address table update: After confirming that all valid data has been safely migrated, a block erase command is sent to the block; after erasure, the block is confirmed to be in a fully erased state (all storage cell threshold voltages < 0V) by reading the status (70h command); the FTL block table is updated: the status of the block is changed from "used" to "SLC cache"; the logical-physical address mapping table (L2P mapping table) is updated: for all logical block addresses that the block has previously mapped, they are remapped to the new target block; the mode conversion event of the block is recorded in the metadata persistent storage area (usually a reserved block of NAND), including the conversion time, the number of erase / write operations before the conversion, the reason for the conversion, etc.

[0051] SLC programming and verification: SLC programming uses a standard single-pulse programming flow and does not call multi-plane programming commands. Address mapping method: Logical page addresses are mapped 1:1 to the physical addresses of lower-level pages. Middle and upper-level page address table entries are set to 0xFFFF (invalid) or a dedicated "disabled" flag. Initialization programming: The converted block should first undergo low-load initialization programming to verify its reliability. It is recommended to write test data generated by the controller (such as all 0s, all 1s, or pseudo-random data) to fill the lower-level pages, and then perform read verification. If initialization verification fails (the read data does not match the written data or ECC cannot correct it), it indicates that the block is over-aged and unsuitable for SLC conversion. It should be directly marked as a bad block or a critically endangered block, and the conversion process should be stopped.

[0052] Health monitoring and replacement: For the converted SLC cache blocks, their read latency is monitored periodically (e.g., hourly). When the read latency exceeds the safety threshold of the single-level cell mode (usually 80%-100% of the baseline read latency), the block is marked as "endangered SLC cache". The endangered SLC cache block should immediately initiate a replacement process: allocate a new healthy block from the free block pool to expand the cache area, and migrate the valid data in the endangered block to the new block. After the data migration is completed, the original endangered block is marked as "pending recycling" and added to the next round of garbage collection queue.

[0053] When programming a block in single-level cell mode, only the physical address of the lower-level page is used for data writing; the addresses of the middle-level and upper-level pages are marked as invalid in the address mapping table. When programming in SLC (Single-Level Cell) mode, the controller maps logical page addresses to the physical addresses of the lower-level pages in a one-to-one relationship, skipping the middle-level and upper-level page addresses. Since each memory cell stores only one bit of information, the same memory cell that required three programming operations in TLC (Three-Level Cell) mode only needs to be programmed once in SLC mode, setting the threshold voltage of the memory cell to one of two discrete levels: erase or program. This address mapping method reduces the effective storage capacity of the block after conversion to one-third of the original TLC capacity, but significantly improves cell reliability.

[0054] The sub-healthy block is converted from TLC mode to SLC mode, with data written only to the lower-level pages, and configured as a read-only buffer to store hot data. In this embodiment, the TLC to SLC mode conversion allows each storage cell to store only 1 bit instead of 3 bits, and the threshold voltage window is expanded from about 2V to about 4V, making the sub-healthy block, which was originally difficult to read reliably, usable again. The programming voltage pulse intensity of SLC mode is reduced, reducing further damage to the storage cell. As a read-only buffer, the erase and write frequency of this block is reduced from hundreds of times per day to several times per week. The overall solution improves the effective capacity utilization of the sub-healthy block and increases the available storage resources of the system without increasing hardware costs.

[0055] This invention proposes a NAND wear leveling method based on ECC and read latency. By constructing a multi-dimensional, end-to-end health assessment and dynamic management mechanism, it achieves accurate judgment and efficient leveling of NAND flash memory block degradation status. First, key indicators such as read latency and ECC usage are collected from the three-layer cell pages. Combined with inter-layer interference factors and temperature compensation, a health index that can truly reflect the cumulative effects of threshold voltage drift, programming interference, and read interference is calculated. This allows health assessment to break free from the rough dependence on the number of P / E cycles and achieve cross-scenario consistency under high-temperature and wide-temperature environments. Based on the hierarchical mapping strategy of the health index, blocks with different health states are distributed to different physical planes. High-health blocks are given priority to carry high-frequency writes, while endangered blocks are isolated in an independent plane to receive operations with higher voltage margins. This effectively suppresses further degradation while maintaining performance stability. During wear leveling, this invention utilizes a multi-plane NAND architecture to achieve parallel migration of critical blocks through interleaved programming and synchronous erasure, significantly reducing migration time and avoiding charge pump overload. Combined with effective data percentage assessment, garbage collection preprocessing, and data compression write amplification optimization, the migration write-amplification coefficient is significantly reduced, decreasing the overall physical write volume and extending NAND lifespan from the ground up. During the data reading phase, this invention introduces a dynamic error correction intensity adjustment mechanism based on read latency deviation. It automatically selects four levels of ECC intensity based on the deviation, significantly improving read throughput and power consumption under normal conditions, and triggering early warnings in high-deviation scenarios to improve data reliability. Simultaneously, when low-intensity error correction fails, it can automatically increase the error correction level and adjust the read reference voltage for a second read, further enhancing the error correction success rate. (See details...) Figure 3 .

[0056] Example 2: To improve the predictability of wear leveling, this invention also includes a lifetime prediction step based on historical health data. A health index degradation database is established to record the health index evolution trajectory of each target block under different erase / write cycles. The health index degradation rate, error correction code usage rate growth rate, and read latency degradation rate are extracted as feature vectors. A time series analysis model is used to fit the feature vectors to predict the remaining erase / write cycles before the target block's health index reaches the critical threshold. Based on the predicted remaining erase / write cycles, the write frequency is reduced in advance before the block deteriorates to a critical level, and spare blocks are pre-allocated for data migration.

[0057] The specific content of this invention is as follows: To obtain the read latency data and error correction code usage of the three-layer cell pages of a target block in a NAND flash memory chip, the three-layer cell pages include a lower-layer page, a middle-layer page, and an upper-layer page; based on the read latency increment and error correction code increment of the middle-layer page, combined with the read latency difference between the middle-layer page and the lower-layer page, a health index of the target block is calculated; the target block is divided into multiple health levels according to the health index, and blocks located in different physical planes are preferentially selected for data allocation, so that logical blocks of different health levels are mapped to different physical planes of the NAND flash memory chip; for target blocks whose health level has deteriorated to a preset threshold, endangered blocks are selected from each physical plane containing blocks to be migrated, and the parallel erase / write capability of the multi-plane architecture is used to simultaneously execute data migration and erase operations on multiple blocks to be migrated; during data reading, the deviation between the current read latency and the specified read latency is monitored in real time, and the error correction strength level of the error correction code is selected according to the deviation level; for blocks in a sub-healthy state, their storage mode is converted from a three-layer cell mode to a single-layer cell mode.

[0058] It also includes a life expectancy prediction step based on historical health data, specifically: Establish a health index degradation database to record the evolution trajectory of the health index of each target block under different erase and write cycles; The rate of health index degradation, the rate of error correction code usage growth, and the rate of read latency degradation are extracted as feature vectors. A time series analysis model is used to fit the feature vector to predict the number of remaining erase / write cycles when the health index of the target block reaches the critical threshold. Based on the predicted remaining erase / write cycles, the write frequency of blocks is reduced in advance before they deteriorate to a critical level, and spare blocks are pre-allocated to prepare for data migration.

[0059] A health index degradation database is established, multi-dimensional feature vectors are extracted, and a time series analysis model is used to predict the remaining number of erase / write cycles before a block reaches the critical threshold. This allows for proactive reduction of write frequency and allocation of spare blocks. In this embodiment, a lifetime prediction model based on historical data improves the accuracy of block degradation prediction, with a prediction lead time of 1000-2000 erase / write cycles before actual degradation. Compared to passive response management, this proactive prediction mechanism reduces sudden data migration events; proactively reducing write frequency slows the degradation rate of predicted critical blocks; user-perceived performance fluctuations are reduced; and the overall solution improves the mean time between failures (MTBF) of NAND through preventative maintenance.

[0060] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A NAND wear leveling method based on integrated circuit ECC and read delay, characterized in that, include: Obtain read latency data and error correction code usage of the three-layer cell pages of the target block in the NAND flash memory chip. The three-layer cell pages include the lower layer page, the middle layer page, and the upper layer page. Based on the read latency increment and error correction code increment of the middle-layer page, and combined with the read latency difference between the middle-layer page and the lower-layer page, the health index of the target block is calculated. According to the health index, the target block is divided into multiple health levels, and blocks located in different physical planes are preferentially selected for data allocation, so that logical blocks of different health levels are mapped to different physical planes of the NAND flash memory chip. For target blocks whose health level deteriorates to a preset threshold, endangered blocks are selected from each physical plane containing blocks to be migrated, and the parallel erase and write capabilities of the multi-plane architecture are used to simultaneously execute data migration and erase operations of multiple blocks to be migrated. During the data reading process, the deviation between the current read latency and the specified read latency is monitored in real time, and the error correction strength level of the error correction code is selected according to the degree of deviation; for blocks with a sub-healthy health level, their storage mode is changed from three-level cell mode to single-level cell mode.

2. The NAND wear leveling method based on integrated circuit ECC and read delay according to claim 1, characterized in that: Based on the read latency increment and error correction code increment of the middle-layer page, combined with the read latency difference between the middle-layer page and the lower-layer page, the health index of the target block is calculated. Specifically, this includes: obtaining the current read latency of the middle-layer page and the lower-layer page respectively, and comparing it with the corresponding baseline read latency to obtain their respective read latency increments; calculating the difference in read latency increments between the middle-layer page and the lower-layer page as a coupling interference factor, which reflects the broadening of the threshold voltage distribution caused by the accumulation of programming interference and read interference; obtaining the current number of error correction code bits of the middle-layer page, and comparing it with the baseline number of error correction bits to calculate the error correction code utilization increment; and weighted summing the read latency increment, error correction code utilization increment, and coupling interference factor of the middle-layer page to obtain the health index of the target block.

3. The NAND wear leveling method based on integrated circuit ECC and read delay according to claim 1, characterized in that: Based on health indices, target blocks are divided into multiple health levels, and blocks located on different physical planes are prioritized for data allocation. Specifically, this includes: setting multiple health index threshold ranges; blocks with health indices below the first threshold are classified as healthy and are preferentially mapped to the first physical plane to carry high-frequency write data; blocks with health indices between the first and second thresholds are classified as good and are preferentially mapped to the second physical plane to carry medium-frequency write data; blocks with health indices between the second and third thresholds are classified as sub-healthy and are preferentially mapped to the third physical plane with write operations restricted; blocks with health indices exceeding the third threshold are classified as endangered and are preferentially mapped to the fourth physical plane and marked as awaiting migration. Different physical planes are physically coupled through a shared substrate and power path, and hierarchical mapping achieves operational timing isolation and differentiated voltage management for blocks in different health states.

4. The NAND wear leveling method based on integrated circuit ECC and read delay according to claim 1, characterized in that: From each physical plane containing blocks to be migrated, critical blocks are selected. Utilizing the parallel erase / write capability of the multi-plane architecture, data migration and erasure operations on multiple blocks to be migrated are executed simultaneously. Specifically, this includes: selecting one critical-level source block from each of the first to fourth physical planes, and simultaneously selecting corresponding target blocks from the healthy-level blocks of each physical plane; synchronously reading valid data from each source block into the data buffer using a multi-plane read command sequence; writing the buffer data into each target block in a pipelined manner using a multi-plane programming command sequence, where the programming operations of each physical plane time-division multiplex the high-voltage charge pump resources, and the programming pulses applied to each plane are staggered to avoid charge pump overload; synchronously erasing each source block using a multi-plane erase command sequence, ensuring the erase voltage application timing of each physical plane overlaps; and re-evaluating the health level of the erased source blocks based on the cumulative number of erase / write operations, prioritizing them as candidate blocks of good and / or sub-healthy levels and adding them to the idle block pool for subsequent allocation.

5. The NAND wear leveling method based on integrated circuit ECC and read delay according to claim 1, characterized in that: The error correction strength level of the error correction code is dynamically selected based on the degree of deviation, specifically including: When the read delay deviation is less than the first deviation threshold, a low-intensity error correction level is selected, using a shortened check polynomial and / or reducing the number of iterations, and using some error correction code redundancy bytes for error correction; when the read delay deviation is between the first and second deviation thresholds, a medium-intensity error correction level is selected, using a moderate proportion of error correction code redundancy bytes for error correction; when the read delay deviation is between the second and third deviation thresholds, a high-intensity error correction level is selected, using most of the error correction code redundancy bytes for error correction; when the read delay deviation exceeds the third deviation threshold, the maximum-intensity error correction level is selected, using all error correction code redundancy bytes for error correction, and a data migration warning is triggered simultaneously.

6. The NAND wear leveling method based on integrated circuit ECC and read delay according to claim 1, characterized in that: When low-intensity error correction fails, the system is upgraded to a high-intensity level, the reference voltage is adjusted, and the reading is re-read. Specifically, this includes: At the current error correction strength level, perform error correction decoding to determine if decoding is successful. If decoding fails, increase the error correction strength level by one level, increase the number of redundant bytes involved in the error correction calculation, and re-execute decoding. If decoding still fails after increasing the error correction strength, adjust the read reference voltage of the NAND flash memory chip by setting characteristic commands. The adjustment direction of the read reference voltage is determined based on the threshold voltage drift trend statistically analyzed in historical read operations. Re-read the memory cell data at the adjusted read reference voltage and decode using the current error correction strength level. If error correction still fails after multiple adjustments to the read reference voltage, record the error correction failure event and immediately trigger a data migration operation.

7. The NAND wear leveling method based on integrated circuit ECC and read delay according to claim 1, characterized in that: The storage mode is converted from a three-level cell mode to a single-level cell mode, and the converted blocks are used as read-only caches. Specifically, this includes: reading three-level cell mode data from blocks in a sub-healthy state, where the three-level cell mode data is distributed across lower, middle, and upper pages; migrating the valid data that needs to be retained to healthy blocks and / or buffers, and then performing an erase operation on the blocks to clear the original multi-threshold voltage state; programming the blocks in single-level cell mode, writing data only to the lower-level page address, with each storage unit storing only one bit of information; configuring the converted blocks as read-only caches, limiting the frequency of subsequent programming and erasure, and performing low-frequency updates only when cached data becomes invalid; and marking the block as endangered and triggering a replacement process when the read latency exceeds the safety threshold of the single-level cell mode.

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