Method and device for testing service life of solid state disk
By collecting and calculating test data of solid-state drives under various stress types, a systematic evaluation framework was established, which solved the problem of inaccurate life prediction in existing technologies, achieved more accurate life prediction and fault analysis, and improved data security and system reliability.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-19
- Publication Date
- 2026-03-27
AI Technical Summary
Existing technologies cannot fully reflect the performance degradation of solid-state drives during actual use, resulting in inaccurate lifespan predictions and reliability assessments.
We collect test data of solid-state drives under various stress types (P/E cycle stress, read interference stress, and data retention stress), calculate the damage degree of each stress type, establish a systematic evaluation framework, and predict the failure time of the hard drive.
It enables comprehensive performance evaluation of solid-state drives under various stress conditions, improves the accuracy of lifespan prediction and data security, provides data support for fault analysis and performance optimization, and extends the service life of devices.
Smart Images
Figure CN121747677A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the technical field of data recognition, and particularly relates to a life test method and device for a solid state disk. BACKGROUND
[0002] With the rapid development of information technology, as a new storage medium, solid state disks (SSDs) gradually replace traditional mechanical hard disks (HDDs) to become mainstream storage solutions due to their high-speed read-write performance and high anti-shock ability. However, the performance and life of solid state disks are affected by many factors, especially in high-intensity use environments, the life prediction and reliability evaluation are particularly important.
[0003] In the use process of solid state disks, various stress types they bear have a direct impact on their life. These stress types mainly include P / E cycle stress, read interference stress and data retention stress. P / E cycle stress refers to the impact on storage cells in multiple read operations, which may cause data damage or errors. Read interference stress involves mutual interference between storage cells during the read process, which may affect the accuracy of reading. Data retention stress is related to the stability of data during storage, and if the retention time is too long, it may cause data loss or distortion. Therefore, effective testing and evaluation of these stress types will help improve the design and application performance of solid state disks.
[0004] Currently, the life test of solid state disks mainly relies on static test methods, which usually cannot fully reflect the performance degradation in the actual use process. SUMMARY
[0005] Therefore, the embodiments of the present application provide a life test method and device for a solid state disk to solve the technical problem that the conventional technology cannot fully reflect the performance degradation in the actual use process.
[0006] The first aspect of the embodiments of the present application provides a life test method for a solid state disk, which comprises:
[0007] Collecting test data corresponding to each stress type of the solid state disk; wherein the stress types include P / E cycle stress type, read interference stress type and data retention stress type;
[0008] According to the test data corresponding to each stress type, calculating the damage degree corresponding to each stress type;
[0009] According to the damage degree corresponding to each stress type at different sampling times, predicting the failure time point of the solid state disk.
[0010] Further, the step of collecting test data corresponding to each of the plurality of stress types includes:
[0011] performing a full-disk write stress test on the solid state disk, and calculating an average read-write cycle number of all Block blocks and a standard deviation of read-write cycle numbers among all Block blocks;
[0012] matching a target Block block adjacent to a preselected Block block;
[0013] performing a read operation on the target Block block, and counting a current read number;
[0014] after the solid state disk writes preset data, placing the solid state disk at a preset test temperature, reading the preset data, and counting a current bit error rate corresponding to the preset data.
[0015] Further, the step of calculating a damage degree corresponding to each of the plurality of stress types according to the test data corresponding to each of the plurality of stress types includes:
[0016] obtaining pre-stored maximum tolerable read-write cycle numbers, unevenness weight coefficients, and nonlinear acceleration factors;
[0017] calculating a cycle stress damage degree according to the average read-write cycle number, the standard deviation, the maximum tolerable read-write cycle number, the unevenness weight coefficient, and the nonlinear acceleration factor;
[0018] obtaining pre-stored read interference thresholds, read damage nonlinear indexes, voltage stress factors, and read damage base coefficients;
[0019] calculating a read interference stress damage degree according to the current read number, the read interference threshold, the read damage nonlinear index, the voltage stress factor, and the read damage base coefficient;
[0020] obtaining pre-stored maximum original bit error rate thresholds, remaining damage base coefficients, and remaining damage sensitivity indexes to bit error rates;
[0021] calculating a data remaining stress damage degree according to a standing time, a preset test temperature, the current bit error rate, the maximum original bit error rate threshold, the remaining damage base coefficient, and the remaining damage sensitivity index to bit error rates.
[0022] Further, the step of calculating a cycle stress damage degree according to the average read-write cycle number, the standard deviation, the maximum tolerable read-write cycle number, the unevenness weight coefficient, and the nonlinear acceleration factor includes:
[0023] the average read-write cycle number, the standard deviation, the maximum tolerance read-write cycle number, the non-uniformity weight coefficient and the non-linear acceleration factor into function one, to obtain the cycle stress damage degree;
[0024] The function one is:
[0025]
[0026] wherein, represents the cycle stress damage degree, represents the non-uniformity weight coefficient, represents the standard deviation, represents the average read-write cycle number, represents the maximum tolerance read-write cycle number, represents the non-linear acceleration factor.
[0027] Further, the step of calculating the read disturb stress damage degree according to the current read number, the read disturb threshold, the read damage non-linear index, the voltage stress factor and the read damage base coefficient comprises:
[0028] the current read number, the read disturb threshold, the read damage non-linear index, the voltage stress factor and the read damage base coefficient into function two, to obtain the read disturb stress damage degree;
[0029] The function two is:
[0030]
[0031] wherein, represents the read disturb stress damage degree, represents the read damage base coefficient, represents the read disturb threshold, represents the current read number, represents the read damage non-linear index, represents the voltage stress factor.
[0032] Further, the step of calculating the data retention stress damage degree according to the static time, the preset test temperature, the current bit error rate, the maximum original bit error rate threshold, the retention damage base coefficient and the retention damage sensitivity index to bit error rate comprises:
[0033] the static time, the preset test temperature, the current bit error rate, the maximum original bit error rate threshold, the retention damage base coefficient and the retention damage sensitivity index to bit error rate into function three, to obtain the data retention stress damage degree.
[0034] The function three is:
[0035]
[0036] Wherein, represents the data retention stress damage degree, represents the retention damage base coefficient, represents the activation energy leading to charge leakage, represents the Boltzmann constant, represents the preset test temperature, represents the current bit error rate, represents the maximum original bit error rate threshold, represents the standing time, represents the sensitivity index of the retention damage to the bit error rate.
[0037] Further, the step of predicting the failure time point of the solid state disk according to the damage degrees corresponding to the plurality of stress types at different sampling times comprises:
[0038] Obtaining adaptive weights corresponding to the plurality of stress types respectively;
[0039] Substituting the adaptive weights and the damage degrees corresponding to the plurality of stress types respectively into function four to obtain a total damage degree;
[0040] The function four is:
[0041]
[0042] Wherein, represents the total damage degree, represents the P / E cycle stress weight, represents the read interference stress weight, represents the data retention stress weight, represents the cycle stress damage degree, represents the read interference stress damage degree, represents the data retention stress damage degree, represents the coupling coefficient;
[0043] Nonlinear regression fitting is performed on the plurality of sampling times and the total damage degrees corresponding to the plurality of sampling times respectively to obtain a fitting relationship;
[0044] Extracting a time parameter corresponding to an upper limit value of the damage degree in the fitting relationship, and taking the time parameter as the failure time point of the solid state disk.
[0045] The second aspect of the embodiment of the present application provides a life test device of a solid state disk, comprising:
[0046] The acquisition unit is used to acquire test data of the solid-state drive under various stress types; wherein, the stress types include P / E cycle stress type, read interference stress type, and data retention stress type;
[0047] The calculation unit is used to calculate the damage degree corresponding to each of the various stress types based on the test data corresponding to each of the various stress types.
[0048] The prediction unit is used to predict the failure time of the solid-state drive based on the damage degree corresponding to various stress types at different sampling times.
[0049] A third aspect of the present invention provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps in the life test method for solid-state drives described in the first aspect.
[0050] A fourth aspect of the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in the lifespan testing method for a solid-state drive described in the first aspect.
[0051] The beneficial effects of this invention compared to existing technologies are as follows: By collecting test data of solid-state drives (SSDs) under various stress types (including P / E cycle stress, read interference stress, and data retention stress), a comprehensive performance evaluation of SSDs in real-world usage environments is achieved. Compared to existing testing methods that only focus on a single stress type, this invention provides a systematic evaluation framework that can more comprehensively reflect the performance of SSDs under various stress conditions, thereby improving the accuracy of hard drive lifespan prediction. Calculating the degree of damage based on test data corresponding to multiple stress types allows for the quantification of SSD damage. This process not only enhances the scientific rigor of the evaluation but also provides data support for subsequent fault analysis and performance optimization. By accurately calculating the degree of damage for each stress type, users can gain a clearer understanding of the hard drive's health status and take appropriate maintenance measures to extend the device's lifespan. Based on the changes in the degree of damage at different sampling times, this invention can effectively predict the failure time of SSDs. Traditional lifespan prediction methods are often based on experience or simple models, lacking sufficient accuracy and practicality. This invention, however, combines the degree of damage with time factors through a scientific analysis model, providing users with failure time predictions based on actual test data. This feature allows users to take preventative measures to avoid data loss or work interruption due to hard drive failure, greatly improving data security and system reliability. Attached Figure Description
[0052] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0053] Figure 1 A schematic flowchart of a lifespan testing method for a solid-state drive provided by the present invention is shown;
[0054] Figure 2 A schematic diagram of a solid-state drive lifespan testing device according to an embodiment of the present invention is shown;
[0055] Figure 3 A schematic diagram of a terminal device provided in an embodiment of the present invention is shown. Detailed Implementation
[0056] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will understand that the invention can be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods are omitted so as not to obscure the description of the invention with unnecessary detail.
[0057] This invention provides a method and apparatus for testing the lifespan of a solid-state drive (SSD) to address the technical problem that traditional technologies cannot fully reflect the performance degradation of SSDs during actual use.
[0058] First, this invention provides a method for testing the lifespan of a solid-state drive (SSD). Please refer to [link / reference needed]. Figure 1 , Figure 1 A schematic flowchart of a lifespan testing method for solid-state drives provided by this invention is shown. Figure 1 As shown, the lifespan testing method for this solid-state drive may include the following steps:
[0059] Step 101: Collect test data of the solid-state drive under various stress types; wherein, the stress types include P / E cycle stress type, read interference stress type, and data retention stress type;
[0060] This step is the data infrastructure construction phase. Its purpose is to actively and rapidly simulate the various harsh conditions (i.e. stress) that SSDs would encounter in real-world usage scenarios in a controlled laboratory environment, and to record the performance and state changes of SSDs under these conditions.
[0061] Stress type refers to external conditions applied to an SSD that accelerate its aging or cause its performance degradation.
[0062] By applying stress and collecting data in a categorized manner, it is possible to clearly observe how each independent damage mechanism affects SSD, laying the foundation for subsequent quantitative analysis.
[0063] The P / E cycle refers to the read-write cycle.
[0064] Specifically, step 101 includes steps 1011 to 1014:
[0065] Step 1011: Perform a full disk write stress test on the solid-state drive and calculate the average number of read / write cycles for all blocks and the standard deviation of the number of read / write cycles between all blocks;
[0066] Perform continuous, random 4KB full-disk write stress tests on the SSD. Pause the stress test after approximately 50 full-disk writes (i.e., 50 P / E cycles). Understandably, during continuous high-pressure writes, the SSD's internal state is chaotic—the cache is full, the controller is performing full garbage collection, and the temperature is extremely high. Data collected under these conditions (such as RAID) contains various temporary noises and cannot accurately reflect long-term, permanent damage. Therefore, the stress test needs to be paused after 50 full-disk writes.
[0067] The erase count of all Flash Blocks is read using the diagnostic command Get_Block_Erase_Coun. The average read / write cycle count for all Blocks and the standard deviation of the read / write cycle count among all Blocks are then calculated.
[0068] Step 1012: Match the target block that is adjacent to the pre-selected block;
[0069] First, perform a certain amount of pre-wear on the SSD (e.g., 150 P / E cycles). Then, select a specific "victim" block (i.e., the pre-selected block).
[0070] It is worth noting that in NAND flash memory, memory cells are organized into arrays, with multiple pages forming a block. Multiple blocks share the same silicon substrate and are physically adjacent. When reading a page, the applied voltage causes slight electronic interference to adjacent pages on the same string (usually other pages within the same block). To most effectively stimulate and observe read interference, blocks physically adjacent to a pre-selected block are chosen as the target block because their capacitive coupling effect is strongest, resulting in the most pronounced interference.
[0071] The target blocks adjacent to the preselected block need to be addressed and matched based on the physical layout information of the SSD controller and NAND flash memory. This ensures the targetedness and effectiveness of the read interference test, enabling the acquisition of test data with the highest signal-to-noise ratio, thereby accurately quantifying the damage caused by this specific stress.
[0072] Step 1013: Perform a read operation on the target Block and count the current number of reads;
[0073] Then, the target block is continuously and intensively read only its physically adjacent blocks. This is a highly customized read interference acceleration test. During the interference reads, the "victim" pre-selected block is read periodically (e.g., every 10,000 reads), and the total number of reads of the target block (R_count) is recorded.
[0074] Step 1014: After writing preset data to the solid-state drive, place the solid-state drive at a preset test temperature, read the preset data, and calculate the current bit error rate corresponding to the preset data.
[0075] Write a specific, known set of preset data onto the SSD. Stop all read and write operations. Place the SSD in an 85°C incubator to simulate long-term data retention. In this accelerated test, it is left to stand for 24 hours to simulate retention of several weeks or months at room temperature. Every so often (e.g., 8 hours), remove the SSD from the incubator, allow it to cool to operating temperature, read the previously written data, and calculate the current bit error rate. Record the baking time (t).
[0076] The above testing process is a cyclical process, for example:
[0077] Phase 1 (Write + Read Interference): Conduct 4 hours of continuous write and targeted read interference tests.
[0078] Phase 2 (Data Retention): Stop the workload and let the SSD sit at high temperature for 8 hours.
[0079] Phase 3 (Data Inspection): Perform a comprehensive data integrity scan to collect the specific values of all the above test data.
[0080] Repeat stages 1-3 and continuously monitor the health status of the SSD.
[0081] In the embodiments corresponding to steps 1011 to 1014, comprehensive testing and data collection are conducted to gain a deeper understanding of the performance of solid-state drives under different stress conditions, providing basic data for predicting their lifespan and assessing their reliability.
[0082] Step 102: Calculate the damage degree corresponding to each stress type based on the test data corresponding to each stress type;
[0083] This step is the damage quantification stage. Its purpose is to transform the various raw test data (such as latency and bit error rate) collected in the first step into a dimensionless, comparable damage index.
[0084] Damage level is an engineering concept, with values ranging from 0 to 1 (or 0% to 100%). 0 represents complete health and no damage. 1 represents reaching the preset failure criterion, i.e., complete failure.
[0085] Standardizing different types of physical data with varying dimensions (time, error rate, delay) into a single damage level allows for the mathematical superposition and comparison of damage caused by different stress types, a crucial transformation for comprehensive life prediction.
[0086] Specifically, step 102 includes steps 1021 to 1026:
[0087] Step 1021: Obtain the pre-stored maximum tolerable read / write cycle count, non-uniformity weighting coefficient, and non-linear acceleration factor;
[0088] The non-uniformity weighting coefficient measures the penalty for uneven wear (can be set to 0.5). If the non-uniformity weighting coefficient = 0.5 (high non-uniformity), (1 + 0.5 * 0.5) = 1.25, meaning the total P / E damage is amplified by 25%. This value is calibrated by comparing the lifespan difference between uniform and uneven wear test groups. A value of 0.5 indicates that the system has moderate sensitivity to uneven wear.
[0089] The nonlinear acceleration factor is a core parameter (configurable to 1.8). β=1 represents linear damage, but in reality, oxide layer damage is accelerated. β>1 simulates this effect. For example, when the average read / write cycle count / maximum tolerable read / write cycle count = 0.8, the linear damage is 0.8, but the nonlinear damage is also 0.8. 1.8≈0.70. Although numerically 0.7 < 0.8, its significance lies in the fact that after reaching a high P / E cycle, each additional P / E cycle causes far greater damage than in the early stages. 1.8 is a typical fitted value, indicating a significant nonlinear effect.
[0090] Maximum tolerable read / write cycles refers to the maximum number of cycles a flash memory chip can maintain data reliability under nominal operating conditions (such as room temperature and nominal voltage). This value is highly dependent on the type of NAND flash memory. For SLC NAND, the maximum tolerable P / E cycle count is 50,000-100,000+ cycles; for MLC NAND, it is 3,000-10,000 cycles; and for TLC NAND, it is 500-1,500 cycles.
[0091] Step 1022: Calculate the cyclic stress damage degree based on the average number of read / write cycles, the standard deviation, the maximum tolerable number of read / write cycles, the non-uniformity weighting coefficient, and the nonlinear acceleration factor;
[0092] Specifically, step 1022 includes: substituting the average number of read / write cycles, the standard deviation, the maximum tolerable number of read / write cycles, the non-uniformity weighting coefficient, and the nonlinear acceleration factor into function one to obtain the cyclic stress damage degree;
[0093] The first function is:
[0094]
[0095] in, This indicates the degree of cyclic stress damage. This represents the non-uniformity weighting coefficient. This represents the standard deviation. This represents the average number of read / write cycles. This indicates the maximum number of read / write cycles that can be tolerated. This represents the nonlinear acceleration factor.
[0096] It is nonlinear damage accumulation. If =1, the damage is linear, but in reality, after high P / E cycles, the oxide layer trap charge accumulates continuously in flash memory, and the cell performance degradation will be accelerated. > 1 is precisely to simulate this accelerated aging effect. For example, when achieve When the damage reaches 80%, it may have already reached the level of 120% under the linear model.
[0097] This is due to the effect of wear leveling. It recognizes that an unhealthy wear distribution is itself a form of stress. Even with the same average P / E cycles, an SSD with a large number of hot spots will have significantly lower overall reliability and lifespan than an SSD with uniform wear. This multiplier amplifies the additional risks associated with uneven wear.
[0098] Step 1023: Obtain the pre-stored read interference threshold, read damage nonlinearity index, voltage stress factor, and read damage fundamental coefficient;
[0099] The read interference threshold is an empirical constant (configurable to 100,000 times), representing the approximate number of reads required to induce a detectable threshold voltage shift in a neighboring cell under typical voltage and temperature conditions. It represents the inherent resistance of a flash memory chip to read interference. The more advanced the process (smaller the cell size), the lower this value typically is, meaning it is more susceptible to interference. This value is usually provided by the flash memory manufacturer in the chip datasheet or calibrated through preliminary characterization experiments. For example, the read interference threshold for a TLC NAND chip might be around 100,000 times, while more advanced QLC might be as low as tens of thousands. In the function, it acts as a normalization factor, converting the actual number of reads into a ratio of relative stress intensity.
[0100] The read damage nonlinearity index is an exponent greater than 1 (which can be set to 2) used to describe the accelerated cumulative effect of read damage. It is obtained through fitting experimental data and its value may range from 1.5 to 3.0. For example, if the read damage nonlinearity index = 2, then when the number of reads reaches twice the threshold, the damage is not twice as much, but rather 2 to the power of 2 times.
[0101] The voltage stress factor is a quantification of the destructive power of a single read operation (configurable to 1.05). It is not a fixed voltage value, but a function relating the read voltage and the target cell state. Voltage stress factor = read voltage / nominal read voltage. If a read voltage 5% higher than the nominal value is used to compensate for cell aging, then the voltage stress factor can be set to 1.05. It quantifies the aggressiveness of each read operation.
[0102] The read damage baseline factor is a scaling factor (configurable to 0.08) used to map normalized read disturbance stress to a comparable value across the entire damage system. It is calculated by running the SSD under pure read disturbance load until failure and then working backwards. It reflects the importance of read disturbance relative to other factors over the total lifetime. 0.08 means that under typical workloads, read disturbance is an important but not dominant factor.
[0103] Step 1024: Calculate the reading interference stress damage degree based on the current number of reads, the reading interference threshold, the reading damage nonlinearity index, the voltage stress factor, and the reading damage basic coefficient;
[0104] Specifically, step 1024 includes: substituting the current number of reads, the read interference threshold, the read damage nonlinearity index, the voltage stress factor, and the read damage basic coefficient into function two to obtain the read interference stress damage degree;
[0105] The second function is:
[0106]
[0107] in, This indicates the degree of damage caused by the reading interference stress. This represents the baseline coefficient of the read damage. This indicates the read interference threshold. This indicates the current number of reads. This represents the nonlinear exponent of the readout damage. This represents the voltage stress factor.
[0108] When a read operation is performed on a word line in flash memory, the applied voltage couples to adjacent word lines through parasitic capacitance, slightly altering the threshold voltage of their floating-gate transistors. Repeated read operations cause this voltage drift to accumulate, eventually leading to data read errors. Function 2... The nonlinearity of damage accumulation was captured. Simultaneously, [the following was introduced]... This allows for the quantification of the destructive power of each read operation, rather than just the number of reads, making the model more refined.
[0109] Step 1025: Obtain the pre-stored maximum raw bit error rate threshold, the base coefficient of retained impairment, and the sensitivity index of retained impairment to bit error rate;
[0110] The retention impairment base factor (which can be set to 0.02 / day) is similar to the read impairment base factor; it is a scaling factor. It is numerically small because of the Arrhenius term exp(...) and the bit error rate term(...). θ These factors together determine the extent of residual damage. This value is also calibrated through high-temperature retention experiments.
[0111] The sensitivity index of retention impairment to bit error rate (which can be set to 1.5) describes how quickly retention impairment responds to an increase in bit error rate. θ=1.5 (>1) indicates that retention impairment accumulates at a faster rate when the bit error rate begins to rise. This simulates the following phenomenon: initially, the bit error rate remains flat, and impairment accumulates slowly; once the bit error rate begins to rise exponentially, the impairment increases rapidly in tandem.
[0112] Maximum raw bit error rate threshold (can be set to 1) -4 The error rate (ORR) refers to the maximum number of raw errors that the SSD's built-in ECC engine (usually LDPC) can correct, indicating that there is approximately one raw error per 10,000 bits.
[0113] Step 1026: Calculate the data retention stress impairment degree based on the resting time, preset test temperature, current bit error rate, maximum original bit error rate threshold, retention impairment base coefficient, and retention impairment sensitivity index to bit error rate.
[0114] Specifically, step 1026 includes: substituting the resting time, the preset test temperature, the current bit error rate, the maximum original bit error rate threshold, the retention impairment base coefficient, and the retention impairment sensitivity index to the bit error rate into function three to obtain the data retention stress impairment degree.
[0115] The third function is:
[0116]
[0117] in, This indicates the degree of stress damage retained in the data. This represents the baseline coefficient of retained damage. This represents the activation energy that leads to charge leakage. Represents Boltzmann's constant. This indicates the preset test temperature. This indicates the current bit error rate. This represents the maximum raw bit error rate threshold. This indicates the settling time. This represents the sensitivity index of the retained impairment to the bit error rate.
[0118] It is the gold standard in reliability engineering (the Arrhenius equation). It describes how the chemical reaction rate (in this case, the escape rate of charge in the floating gate) changes exponentially with temperature. Temperature is the primary accelerator of data retention. This factor allows the model to accurately extrapolate the results of high-temperature accelerated testing to the lifetime at normal operating temperatures.
[0119] This represents the cumulative damage caused over time and with an increasing error rate under given temperature conditions. This demonstrates the severity of the increase in error rates.
[0120] In the embodiments corresponding to steps 1021 to 1026, a systematic method is provided to evaluate the damage of solid-state drives (SSDs) under various stress types. Each step aims to integrate different test data and stored parameters to form a comprehensive assessment of the SSD's lifespan.
[0121] Step 103: Predict the failure time of the solid-state drive based on the damage degree corresponding to various stress types at different sampling times.
[0122] This step is the lifespan extrapolation prediction stage. Its purpose is to use the trend of damage over time to predict when the total damage of the SSD will reach a critical value (i.e., failure) at some point in the future.
[0123] Different sampling times mean that the system does not measure at a single point in time, but executes the first and second steps periodically during the test (e.g., every 24 hours, every 1000 cycles) to obtain a series of time points [t1, t2, t3, ...] and their corresponding damage [D1, D2, D3, ...].
[0124] For each stress type, the time series data (t, D) are plotted on a coordinate system. Then, nonlinear regression is used to fit these data points to obtain a damage-time curve.
[0125] Based on each damage-time curve fitted in the second step, the damage caused by each stress type alone can be predicted at any future time.
[0126] Adding these three predicted values together yields the curve of total damage over time.
[0127] Find the time point at which the total damage curve reaches 1; this time point is the predicted failure time of the solid-state drive.
[0128] It enables predictions of lifespan from limited, accelerated test data to long-term, real-world usage scenarios. Through mathematical extrapolation, it can relatively accurately predict the end of an SSD's life without actually testing it to complete failure (which could take years).
[0129] Specifically, step 103 includes steps 1031 to 1034:
[0130] Step 1031: Obtain the adaptive weights corresponding to each of the various stress types;
[0131] Three distinct health stages and their corresponding baseline weights are defined. These weights represent the default importance of each damaging factor under normal aging conditions at that stage. The three health stages are Stage A (early stage), Stage B (mid-stage), and Stage C (late stage). Stage A (early stage) is defined as follows: average read / write cycles < 0.3 times the maximum tolerable read / write cycles and current bit error rate < 10. -5 The criteria for Phase B (intermediate) are: 0.3 times the maximum tolerable read / write cycle count ≤ average read / write cycle count < 0.8 times the maximum tolerable read / write cycle count and the current bit error rate < 10. -4 The criteria for determining Stage C (final stage) are: average read / write cycle count > 0.8 times the maximum tolerable read / write cycle count and current bit error rate or current bit error rate ≥ 10. -4 When in Phase A (early stage), the P / E cyclic stress baseline weight is 0.7, the read disturbance stress baseline weight is 0.15, and the data retention stress baseline weight is 0.15. When in Phase B (mid-stage), the P / E cyclic stress baseline weight is 0.5, the read disturbance stress baseline weight is 0.2, and the data retention stress baseline weight is 0.3. When in Phase C (late stage), the P / E cyclic stress baseline weight is 0.3, the read disturbance stress baseline weight is 0.25, and the data retention stress baseline weight is 0.45.
[0132] After obtaining the baseline weights corresponding to each of the above stress types, the baseline weights are adjusted based on the adaptive weight rule base to obtain the adaptive weights (adaptive weights include, but are not limited to, cyclic stress weights, read disturbance stress weights, and data retention stress weights).
[0133] The logic of the adaptive weight rule base is as follows:
[0134] Rule 1: Handling read-intensive scenarios
[0135] Rule: IF (read IOPS > 5 times write IOPS in the past 24 hours) AND (in phase A or B) THEN;
[0136] Cyclic stress baseline weight +0.10, read disturbance stress baseline weight -0.05, data retention stress baseline weight -0.05.
[0137] This rule identifies an unconventional, read-centric workload. It immediately increases the weight of read interference, as this is the most significant risk at present. Simultaneously, it slightly decreases the weights of other workloads to maintain a total weight of 1.
[0138] Rule 2: Addressing High-Temperature Storage Scenarios
[0139] Rule: IF (preset test temperature > 75°) THEN (regardless of the stage)
[0140] Cyclic stress baseline weight +0.15, read disturbance stress baseline weight -0.10, data retention stress baseline weight -0.05.
[0141] According to the Arrhenius model, temperature has an exponentially accelerating effect on data retention lifetime. This rule prioritizes this high-risk situation, significantly increasing the weight of retention impairment.
[0142] Rule 3: Addressing uneven wear
[0143] Rule: IF (Standard deviation of P / E cyclic distribution non-uniformity > 0.4) THEN
[0144] Cyclic stress baseline weight +0.10 (because hotspot blocks may fail prematurely), read interference stress baseline weight +0.05 (because hotspot blocks have worse retention capabilities), data retention stress baseline weight -0.15.
[0145] Severe wear unevenness is a precursor to system-level failure. It not only means increased local P / E damage (reading disturbance stress baseline weight), but also amplifies residual damage (data retention stress baseline weight) through coupling effects.
[0146] Rule 4: Addressing Surges in Error Rates
[0147] Rule: IF (current bit error rate > 3 times the previous cycle's bit error rate) THEN (enter emergency weight mode)
[0148] Cyclic stress weight = 0.20, read disturbance stress weight = 0.20, data retention stress weight = 0.60.
[0149] A sharp increase in error rate is a clear signal that a flash array is about to fail. This is usually due to a significant decrease in data retention capacity after a critical point. This rule overrides the baseline weight, directly setting the data retention stress weight to an extremely high value, as this is the most imminent threat.
[0150] The three adjusted weights are normalized to obtain the adaptive weights corresponding to each stress type.
[0151] Example: An SSD is in phase B (baseline weights: 0.5, 0.2, 0.3) and triggers both rule 1 (Δw = -0.05, +0.10, -0.05) and rule 3 (Δw = +0.10, -0.15, +0.05).
[0152] Initial values: (0.5, 0.2, 0.3);
[0153] Apply rule 1: (0.45, 0.3, 0.25);
[0154] Apply rule 3: (0.55, 0.15, 0.30);
[0155] Normalization: The sum is 1.0, no adjustment is needed;
[0156] The final adaptive weights are (0.55, 0.15, 0.30).
[0157] Step 1032: Substitute the adaptive weights and damage degrees corresponding to each of the various stress types into function four to obtain the total damage degree;
[0158] The fourth function is:
[0159]
[0160] in, Indicates the total degree of damage. Represents the P / E cyclic stress weight. This indicates the reading of the interference stress weight. Indicates the stress weight for data retention. Indicates the degree of cyclic stress damage. This indicates the degree of damage caused by interference stress. Indicates the stress damage degree of data retention. Represents the coupling coefficient;
[0161] The coupling coefficient (which can be set to 2.0) is the parameter that best reflects the stress synergy effect in this model. =2.0 means: if a cell's P / E ratio is damaged If the error rate is 0.5, then the retention impairment will be amplified by (1 + 2.0 * 0.5) = 2.0 times. That is, a moderately worn cell loses data twice as fast as a brand new cell. This value was determined through a comparative test: one group used brand new disks for high-temperature retention testing, and the other group used disks that were half-worn for the same test. The latter's error rate increased much faster than the former; the difference in speed is reflected in... Above. 2.0 indicates a very strong coupling effect.
[0162] Individual Retention damage under ideal cellular conditions was calculated. However, a cell already worn down by P / E cycles has a damaged oxide layer and more pathways for charge leakage. Therefore, the same retention time and temperature result in significantly more damage on an older cell than on a newer cell. Coupling terms This is precisely to quantify this effect. It means that the damage from the P / E cycle not only contributes to... This also amplifies the damage caused by data retention stress. This is one of the most complex and critical characteristics that distinguishes this model from the simple linear superposition model.
[0163] In the early stages of an SSD's lifespan, wear and tear are low, and D_pe is small. At this time, data retention w_retention(t) is likely the most important factor, as the ability to retain data on a new drive is crucial.
[0164] As the P / E cycles increase (D_pe increases), SSDs become increasingly fragile. At this point, the weight of read interference w_read(t) may increase significantly because the anti-interference ability of worn cells decreases drastically.
[0165] This makes the model no longer static, but dynamically evolving. It recognizes that the types of stress that dominate the failure of an SSD differ at different stages of its life. This is a highly realistic simulation of the complexities of the real world.
[0166] Step 1033: Perform nonlinear regression fitting on multiple sampling times and the total damage corresponding to each sampling time to obtain the fitting relationship;
[0167] The system records a series of time points and their corresponding total damage values: (t_1, D_1), (t_2, D_2), ..., (t_n, D_n), where t_n is the current time.
[0168] The total damage degree changes over time according to a power law: D(T) = aT b D(T) represents the total damage, and T represents the sampling time.
[0169] Use a nonlinear regression algorithm (such as Levenberg-Marquardt) to find the optimal parameters a and b, so that the curve best matches all historical data points.
[0170] 'a' is a scaling factor. 'b' is the most crucial factor, describing the curvature or acceleration of damage accumulation. 'b' ≈ 1 indicates linear damage accumulation. 'b' > 1 indicates accelerated damage accumulation (a typical characteristic of late-stage SSD aging). 'b' < 1 indicates decelerated damage accumulation (almost non-existent in real-world SSDs). The solved D(T) = aT b This is for fitting the relationship.
[0171] Step 1034: Extract the time parameter corresponding to the upper limit of damage in the fitted relationship, and use the time parameter as the failure time point of the solid-state drive.
[0172] Substituting the upper limit of damage into D(T) = aT b The time parameter T is calculated and used as the failure time point of the solid-state drive. The upper limit of the damage level can be set to 0.88.
[0173] In the embodiments corresponding to steps 1031 to 1034, by considering multiple stress types and their adaptive weights, the degree of damage to the solid-state drive (SSD) can be assessed more comprehensively and accurately, thereby improving the accuracy of predicting the failure time point. The introduction of adaptive weights allows this method to adapt to different usage environments and operating conditions, enhancing the flexibility and adaptability of the prediction model and enabling reliable predictions under various operating conditions. By predicting the failure time point, users and manufacturers can better manage the lifespan of SSDs, such as performing data backup and replacement in advance, thus improving data security.
[0174] In the embodiments corresponding to steps 101 to 103, by collecting test data of the solid-state drive (SSD) under various stress types (including P / E cycle stress, read interference stress, and data retention stress), a comprehensive performance evaluation of the SSD in a real-world usage environment is achieved. Compared with existing testing methods that only focus on a single stress type, this invention provides a systematic evaluation framework that can more comprehensively reflect the performance of the SSD under various stress conditions, thereby improving the accuracy of hard drive lifespan prediction. The damage degree is calculated based on the test data corresponding to various stress types, allowing the damage status of the SSD to be quantified. This process not only enhances the scientific rigor of the evaluation but also provides data support for subsequent fault analysis and performance optimization. By accurately calculating the damage degree for each stress type, users can gain a clearer understanding of the hard drive's health status and take corresponding maintenance measures to extend the device's lifespan. Based on the changes in damage degree at different sampling times, this invention can effectively predict the failure time of the SSD. Traditional lifespan prediction methods are often based on experience or simple models, lacking sufficient accuracy and practicality. This invention, however, combines damage degree with time factors through a scientific analysis model, providing users with failure time predictions based on actual test data. This feature allows users to take preventative measures to avoid data loss or work interruption due to hard drive failure, greatly improving data security and system reliability.
[0175] like Figure 2 This invention provides a lifespan testing device for solid-state drives (SSDs). Please refer to [link / reference]. Figure 2 , Figure 2 A schematic diagram of a solid-state drive lifespan testing device provided by the present invention is shown, as follows: Figure 2 The solid-state drive lifespan testing device shown includes:
[0176] The acquisition unit 21 is used to acquire test data of the solid-state drive under various stress types; wherein, the stress types include P / E cycle stress type, read interference stress type and data retention stress type;
[0177] The calculation unit 22 is used to calculate the damage degree corresponding to each of the various stress types based on the test data corresponding to each of the various stress types.
[0178] The prediction unit 23 is used to predict the failure time of the solid-state drive based on the damage degree corresponding to various stress types at different sampling times.
[0179] This invention provides a solid-state drive (SSD) lifespan testing device. By collecting test data from SSDs under various stress types (including P / E cycle stress, read interference stress, and data retention stress), it achieves a comprehensive performance evaluation of SSDs in real-world usage environments. Compared to existing testing methods that focus only on a single stress type, this invention provides a systematic evaluation framework that more comprehensively reflects the performance of SSDs under multiple stress conditions, thereby improving the accuracy of hard drive lifespan prediction. The damage degree is calculated based on the test data corresponding to multiple stress types, allowing for the quantification of SSD damage. This process not only enhances the scientific rigor of the evaluation but also provides data support for subsequent fault analysis and performance optimization. By accurately calculating the damage degree for each stress type, users can gain a clearer understanding of the hard drive's health status and take appropriate maintenance measures to extend the device's lifespan. Based on the changes in damage degree at different sampling times, this invention can effectively predict the failure time of the SSD. Traditional lifespan prediction methods are often based on experience or simple models, lacking sufficient accuracy and practicality. This invention, however, combines damage degree with time factors through a scientific analysis model, providing users with failure time predictions based on actual test data. This feature allows users to take preventative measures to avoid data loss or work interruption due to hard drive failure, greatly improving data security and system reliability.
[0180] Figure 3 This is a schematic diagram of a terminal device provided in an embodiment of the present invention. Figure 3 As shown, a terminal device 3 in this embodiment includes: a processor 30, a memory 31, and a computer program 32 stored in the memory 31 and executable on the processor 30, such as a lifespan testing program for a solid-state drive. When the processor 30 executes the computer program 32, it implements the steps in the various embodiments of the solid-state drive lifespan testing method described above, for example... Figure 1 Steps 101 to 103 are shown. Alternatively, when the processor 30 executes the computer program 32, it implements the functions of each unit in the above-described device embodiments, for example...Figure 2 The function of the unit shown.
[0181] For example, the computer program 32 can be divided into one or more units, which are stored in the memory 31 and executed by the processor 30 to complete the present invention. The one or more units can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program 32 in the terminal device 3. For example, the specific functions of each unit of the computer program 32 can be divided as follows:
[0182] The acquisition unit is used to acquire test data of the solid-state drive under various stress types; wherein, the stress types include P / E cycle stress type, read interference stress type, and data retention stress type;
[0183] The calculation unit is used to calculate the damage degree corresponding to each of the various stress types based on the test data corresponding to each of the various stress types.
[0184] The prediction unit is used to predict the failure time of the solid-state drive based on the damage degree corresponding to various stress types at different sampling times.
[0185] The terminal device includes, but is not limited to, a processor 30 and a memory 31. Those skilled in the art will understand that... Figure 3 This is merely an example of a terminal device 3 and does not constitute a limitation on a terminal device 3. It may include more or fewer components than shown, or combine certain components, or different components. For example, the terminal device may also include input / output devices, network access devices, buses, etc.
[0186] The processor 30 can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.
[0187] The memory 31 can be an internal storage unit of the terminal device 3, such as a hard disk or memory of the terminal device 3. The memory 31 can also be an external storage device of the terminal device 3, such as a plug-in hard disk, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the terminal device 3. Furthermore, the memory 31 can include both internal and external storage units of the terminal device 3. The memory 31 is used to store the computer program and other programs and data required by the roaming control device. The memory 31 can also be used to temporarily store data that has been output or will be output.
[0188] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.
[0189] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of the present invention. For details on their specific functions and technical effects, please refer to the method embodiments section, which will not be repeated here.
[0190] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this invention. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.
[0191] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps described in the various method embodiments above.
[0192] This invention provides a computer program product that, when run on a mobile terminal, enables the mobile terminal to implement the steps described in the above-described method embodiments.
[0193] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to a photographing device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.
[0194] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.
[0195] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.
[0196] In the embodiments provided by this invention, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.
[0197] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units.
[0198] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.
[0199] It should also be understood that the term “and / or” as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0200] As used in this specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once [the described condition or event] is detected," or "in response to detection of [the described condition or event]."
[0201] Furthermore, in the description of this invention and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0202] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of the invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.
[0203] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.
Claims
1. A method for testing the lifespan of a solid-state drive, characterized in that, The lifespan testing method for the solid-state drive includes: Collect test data for solid-state drives under various stress types; wherein, the stress types include P / E cycle stress type, read interference stress type, and data retention stress type; Based on the test data corresponding to each of the various stress types, calculate the damage degree corresponding to each of the various stress types; Based on the damage levels corresponding to various stress types at different sampling times, the failure time point of the solid-state drive is predicted.
2. The lifespan testing method for a solid-state drive as described in claim 1, characterized in that, The steps for collecting test data of solid-state drives under various stress types include: Perform a full-disk write stress test on the solid-state drive and calculate the average number of read / write cycles for all blocks and the standard deviation of the number of read / write cycles between all blocks; Match the target block that is adjacent to the preselected block; Perform a read operation on the target block and count the current number of reads; After writing preset data to the solid-state drive, the solid-state drive is placed at a preset test temperature, and the preset data is read to calculate the current bit error rate corresponding to the preset data.
3. The lifespan testing method for a solid-state drive as described in claim 2, characterized in that, The step of calculating the damage degree corresponding to each of the various stress types based on the test data for each stress type includes: Obtain the pre-stored maximum tolerable read / write cycle count, unevenness weighting coefficient, and non-linear acceleration factor; The cyclic stress damage degree is calculated based on the average number of read / write cycles, the standard deviation, the maximum tolerable number of read / write cycles, the non-uniformity weighting coefficient, and the nonlinear acceleration factor. Obtain the pre-stored read interference threshold, read damage nonlinearity index, voltage stress factor, and read damage fundamental coefficient; The reading interference stress damage degree is calculated based on the current number of reads, the reading interference threshold, the reading damage nonlinearity index, the voltage stress factor, and the reading damage basic coefficient. Obtain the pre-stored maximum raw bit error rate threshold, the base coefficient of retained impairment, and the sensitivity index of retained impairment to bit error rate; The data retention stress impairment is calculated based on the settling time, preset test temperature, current bit error rate, maximum original bit error rate threshold, retention impairment base coefficient, and retention impairment sensitivity index to bit error rate.
4. The lifespan testing method for a solid-state drive as described in claim 3, characterized in that, The step of calculating the cyclic stress damage degree based on the average number of read / write cycles, the standard deviation, the maximum tolerable number of read / write cycles, the non-uniformity weighting coefficient, and the nonlinear acceleration factor includes: Substituting the average number of read / write cycles, the standard deviation, the maximum tolerable number of read / write cycles, the non-uniformity weighting coefficient, and the nonlinear acceleration factor into function one yields the cyclic stress damage degree. The first function is: ; in, This indicates the degree of cyclic stress damage. This represents the non-uniformity weighting coefficient. This represents the standard deviation. This represents the average number of read / write cycles. This indicates the maximum number of read / write cycles that can be tolerated. This represents the nonlinear acceleration factor.
5. The lifespan testing method for a solid-state drive as described in claim 3, characterized in that, The step of calculating the reading interference stress damage degree based on the current reading count, the reading interference threshold, the reading damage nonlinearity index, the voltage stress factor, and the reading damage fundamental coefficient includes: Substituting the current number of reads, the read interference threshold, the read damage nonlinearity index, the voltage stress factor, and the read damage basic coefficient into function two, the read interference stress damage degree is obtained; The second function is: ; in, This indicates the degree of damage caused by the reading interference stress. This represents the baseline coefficient of the read damage. This indicates the read interference threshold. This indicates the current number of reads. This represents the nonlinear exponent of the readout damage. This represents the voltage stress factor.
6. The lifespan testing method for a solid-state drive as described in claim 3, characterized in that, The step of calculating the data retention stress impairment degree based on the resting time, preset test temperature, current bit error rate, maximum original bit error rate threshold, retention impairment base coefficient, and retention impairment sensitivity index to bit error rate includes: Substituting the resting time, the preset test temperature, the current bit error rate, the maximum original bit error rate threshold, the retention impairment base coefficient, and the retention impairment sensitivity index to the bit error rate into function three, the data retention stress impairment degree is obtained. The third function is: ; in, This indicates the degree of stress damage retained in the data. This represents the baseline coefficient of retained damage. This represents the activation energy that leads to charge leakage. Represents Boltzmann's constant. This indicates the preset test temperature. This indicates the current bit error rate. This represents the maximum raw bit error rate threshold. This indicates the settling time. This represents the sensitivity index of the retained impairment to the bit error rate.
7. The lifespan testing method for a solid-state drive as described in claim 1, characterized in that, The step of predicting the failure time of the solid-state drive based on the damage degree corresponding to various stress types at different sampling times includes: Obtain the adaptive weights corresponding to each of the various stress types; Substitute the adaptive weights and damage degrees corresponding to each of the various stress types into function four to obtain the total damage degree. The fourth function is: ; in, Indicates the total degree of damage. Represents the P / E cyclic stress weight. This indicates the reading of the interference stress weight. Indicates the stress weight for data retention. Indicates the degree of cyclic stress damage. This indicates the degree of damage caused by interference stress. Indicates the stress damage degree of data retention. Represents the coupling coefficient; The total damage corresponding to multiple sampling times is fitted using nonlinear regression to obtain the fitting relationship. Extract the time parameter corresponding to the upper limit of damage in the fitted relationship, and use the time parameter as the failure time point of the solid-state drive.
8. A lifespan testing device for solid-state drives, characterized in that, The solid-state drive lifespan testing device includes: The acquisition unit is used to acquire test data of the solid-state drive under various stress types; wherein, the stress types include P / E cycle stress type, read interference stress type, and data retention stress type; The calculation unit is used to calculate the damage degree corresponding to each of the various stress types based on the test data corresponding to each of the various stress types. The prediction unit is used to predict the failure time of the solid-state drive based on the damage degree corresponding to various stress types at different sampling times.
9. A terminal device, characterized in that, The terminal device includes: a memory, a processor, and a lifespan testing program for a solid-state drive (SSD) stored in the memory and executable on the processor, the SSD lifespan testing program being configured to implement the steps of the SSD lifespan testing method as described in any one of claims 1 to 7.
10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps in the life test method for solid-state drives as described in any one of claims 1 to 7.