Data exchange method and device

Abstract

The invention discloses a data exchange method and device. A synchronous manager of a configuration counter divides a synchronous memory space, and the counter is used for counting the data volume of the space in real time. When data is written into or read from the space, the value of the counter is increased or decreased according to the length of the data. Therefore, the completion condition of reading / writing data in the space can be identified based on the value of the counter, the data reading / writing does not need to be matched with the memory size of the preset space, communication pause and configuration synchronization manager parameter modification are not needed when the data size is adjusted, and the flexibility and the real-time performance of the system are improved. And meanwhile, the operation is simplified, the operation and maintenance complexity is reduced, and efficient and real-time synchronization of data can be realized without influencing system operation. And the end address of the space does not need to be accurately operated, so that the problem of delay interruption due to the fact that the data does not reach the end address is avoided, the real-time performance of data exchange and the system flexibility are remarkably enhanced, and the method is suitable for the real-time control requirements of different scenes.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a method and apparatus for data exchange. Background Technology

[0002] In Ethernet for Control Automation Technology (EtherCAT) networks, each data frame sent by the master station can be copied and modified as it passes through each slave station, enabling slave stations to read or write their own data without additional network transmission time. Simply put, the data frame passes serially through all slave stations like a train, exchanging data with each slave station without stopping. To achieve data synchronization, a Synchronization Manager (SM) can be used to allocate specific synchronization memory spaces. This space is used for master-slave write and slave-slave read operations, ensuring that data can be read / written promptly, achieving real-time data exchange.

[0003] In existing technologies, the EtherCAT Slave Controller (ESC) determines the full / empty status of data by detecting access to the last address (end address) of the synchronization memory space and triggers an interrupt accordingly. Specifically, the SM sets the size of this space, and the ESC detects whether a read / write operation has reached the end address; if so, an interrupt is generated. However, with this method, the data read / written cannot exceed the size of this space, and the last read / write operation must precisely stop at the end address. This causes inconvenience in practical applications, especially when the size of the synchronization data needs to be adjusted. The SM configuration must be adjusted first, and the adjustment process requires pausing all communication, affecting the system's real-time performance and flexibility. Summary of the Invention

[0004] To address the aforementioned problems, this application provides a data exchange method and apparatus to resolve these issues in existing EtherCAT network data exchange technologies, thereby achieving efficient and real-time data synchronization and improving system flexibility and real-time performance.

[0005] This application discloses a method for data exchange, the method comprising: Configure a counter in the synchronization manager SM; the counter is used to count the amount of data in the synchronization memory space in real time; the synchronization memory space is divided by the SM. When data is written to / read from the synchronous memory space, the value of the counter is increased / decreased according to the length of the data.

[0006] Optionally, the step of increasing / decreasing the counter value according to the length of the data when data is written to / read from the synchronized memory space includes: When the master station writes the data into the synchronous memory space, the slave station protocol controller (ESC) identifies the data length of the data. Increment the value of the counter by the same amount as the data length.

[0007] Optionally, after incrementing the counter value by a value equal to the data length, the method further includes: The correctness of the frame verification sequence at the end of the data is verified to obtain the verification result. An interrupt is generated when the verification result is correct; When the verification result is incorrect, the value of the counter is cleared to zero.

[0008] Optionally, the step of increasing / decreasing the counter value according to the length of the data when data is written to / read from the synchronized memory space includes: When the slave station reads data from the synchronous memory space, it decrements the value of the counter by 1 for each address bit read, until the value of the counter is 0.

[0009] Optionally, after the value of the counter reaches 0, the method further includes: An interrupt was triggered.

[0010] Optionally, the step of increasing / decreasing the counter value according to the length of the data when data is written to / read from the synchronized memory space includes: When writing data from the station into the synchronous memory space, the value of the counter is incremented by 1 for each address bit written.

[0011] Optionally, when data is written to / read from the synchronized memory space, after incrementing / decrementing the counter value according to the length of the data, the method further includes: After the slave data processor MCU completes the data writing, it sends a write completion command to the slave protocol controller ESC. The ESC generates an interrupt and sends it to the master station.

[0012] Optionally, the step of increasing / decreasing the counter value according to the length of the data when data is written to / read from the synchronized memory space includes: When the master station reads the data from the synchronous memory space, it obtains the address of the data in the synchronous memory space according to the data length; Read the data within the address; The slave protocol controller (ESC) reduces the value of the counter by the same amount as the length of the data.

[0013] Optionally, when data is written to / read from the synchronized memory space, after incrementing / decrementing the counter value according to the length of the data, the method further includes: The slave station writes an early end read signal to notify the slave station protocol controller (ESC) to generate an interrupt and send it to the master station, thus clearing the value of the counter to zero.

[0014] Optional, When the value of the counter is 0, it is determined that the data in the synchronized memory space has been read empty; When the value of the counter is the same as the length of the data being written, it is determined that the synchronous memory space is full.

[0015] Optionally, when writing data to the synchronized memory space, the writing starts from the starting address of the synchronized memory space.

[0016] Based on the above-mentioned data exchange method, this application also discloses a data exchange apparatus, including: a configuration unit and an execution unit; The configuration unit is used to configure a counter in the synchronization manager SM; the counter is used to count the amount of data in the synchronization memory space in real time; the synchronization memory space is divided by the SM. The execution unit is configured to increase / decrease the value of the counter according to the length of the data when data is written to / read from the synchronous memory space.

[0017] Optionally, the execution unit includes: The identification subunit is used to identify the data length of the data when the master station writes the data into the synchronous memory space; An additional subunit is added to increment the value of the counter by the same amount as the data length.

[0018] Optionally, the device further includes: A verification unit is used to verify the correctness of the frame verification sequence at the end of the data and obtain the verification result. An interrupt unit is used to generate an interrupt when the verification result is correct; The zeroing unit is used to clear the value of the counter when the verification result is incorrect.

[0019] Optionally, the execution unit includes: The decrementing subunit is used to decrement the value of the counter by 1 for each address bit read from the synchronous memory space when the slave reads the data, until the value of the counter is 0.

[0020] Optionally, the subtraction subunit is further configured to: An interrupt was triggered.

[0021] Optionally, the execution unit includes: The increment subunit is used to increment the value of the counter by 1 for each address bit written when the data is written from the slave to the synchronous memory space.

[0022] Optionally, the device further includes: The sending unit is used by the slave data processor MCU to send a write completion command to the slave protocol controller ESC after the data writing is completed; The counting unit is used to send the interrupt generated by the ESC to the master station.

[0023] Optionally, the execution unit includes: The acquisition subunit is used to acquire the address of the data in the synchronous memory space according to the data length when the master station reads the data from the synchronous memory space. A read subunit is used to read data from the address; The reduction subunit is used by the slave protocol controller (ESC) to reduce the value of the counter by a value equal to the data length of the data.

[0024] Optionally, the device further includes: The advance unit is used to write an early end read signal to the slave station to inform the slave station protocol controller ESC to generate an interrupt and send it to the master station to clear the value of the counter.

[0025] Optionally, when the value of the counter is 0, it is determined that the data in the synchronized memory space has been read empty; When the value of the counter is the same as the length of the data being written, it is determined that the synchronous memory space is full.

[0026] Optionally, when writing data to the synchronized memory space, the writing starts from the starting address of the synchronized memory space.

[0027] This application discloses a method and apparatus for data exchange. A synchronization manager configured with a counter divides a synchronization memory space and uses a counter to monitor the amount of data in that space in real time. When data is written to or read from this space, the counter value increases or decreases according to the data length. Therefore, the completion status of reading / writing data in this space can be identified based on the counter value, eliminating the need to match data read / write operations to a preset memory size. Adjusting the data size also eliminates the need to pause communication or modify the configuration synchronization manager parameters, improving system flexibility and real-time performance. Simultaneously, it simplifies operation, reduces maintenance complexity, and achieves efficient, real-time data synchronization without affecting system operation. Furthermore, it eliminates the need for precise operation on the end address of the space, avoiding delays and interruptions due to data not reaching the end address, significantly enhancing the real-time performance and system flexibility of data exchange, and is suitable for real-time control requirements in various scenarios. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0029] Figure 1a This is a flowchart illustrating a data exchange method disclosed in an embodiment of this application; Figure 1b This is a schematic diagram of the EtherCAT message structure disclosed in the embodiments of this application; Figure 2a This is a flowchart illustrating another data exchange method disclosed in an embodiment of this application; Figure 2b This is a flowchart illustrating another data exchange method disclosed in an embodiment of this application; Figure 3 This is a schematic diagram of the structure of a data exchange device disclosed in an embodiment of this application. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0031] Example 1: This application discloses a method for data exchange.

[0032] For details, please refer to Figure 1aThe data exchange method disclosed in this embodiment includes the following steps: Step 101: Configure the counter in the Synchronization Manager (SM).

[0033] In the method of this embodiment, each SM is configured with a timer when exchanging data in the EtherCAT network. Each SM is managed independently and there is no correlation between them. This timer is used to count the amount of data in the synchronization memory space in real time.

[0034] Step 102: When data is written to / read from the synchronous memory space, increase / decrease the value of the counter according to the length of the data.

[0035] In the method of this embodiment, such as Figure 1b As shown, the structure of an EtherCAT message includes a command, number, address, message data length, reserved bits (Reserved, R), checksum (C), more followers (M), and interrupt request (IRQ). It is important to note that in the method of this embodiment, when writing data to the synchronization memory space, writing must begin from the starting address of the synchronization memory space. That is, the address of the first message written must be the starting address of the synchronization memory space. After writing to the starting address, subsequent data can be written to other addresses in the synchronization memory space. To ensure that the counter value represents the size of the memory occupied by the synchronization memory space, it is necessary to prevent skipping addresses during data writing and to prevent repeated writing to the same address, thereby avoiding data corruption and loss.

[0036] In this embodiment, initially, the synchronization memory space is empty, and the counter value can be defaulted to 0. When the master station writes the first message into the synchronization memory space, the slave station protocol controller (ESC) can identify the data length of the first message and increment the counter value by the same amount as the data length. As one possible implementation, when the first message is written into the synchronization memory space, its data length is as follows: Figure 1b As shown, it is embedded in the message data. At this time, ESC can directly obtain the length of the entire message and increment the counter by the same value as the length.

[0037] Furthermore, after the first message is written, the Frame Check Sequence (FCS) can be checked to see if it is correct. If the FCS is correct, an interrupt will be generated. If the FCS is incorrect, no interrupt will be generated, and the counter value will be cleared, which is equivalent to not considering that any data has been written.

[0038] In this embodiment, when the slave station reads data, a counter is decremented by 1 for each address bit read. When the counter reaches 0, it indicates that all previously written data has been read, and the ESC triggers an interrupt. Furthermore, if the slave station wants to end the reading process early and discard any unread data, it can directly write an early end-of-read signal to the "Slave Station Read Complete Indicator Register" to inform the ESC to end the reading early. The ESC responds to this instruction by clearing the counter value early and generating a read complete interrupt for the master station. In other words, the slave station does not need to read all the required data; instead, it can end the reading process early through the MCU.

[0039] In the method of this embodiment, when the slave station writes data, the ESC cannot obtain the data length and cannot predict when the writing will end. At this time, the counter value will continuously increase with the writing of the second message. After the second message is written, the ESC receives a write completion instruction from the slave station data processor MCU, and the ESC generates a completion interrupt and sends it to the master station.

[0040] For example, in the initial state, the slave station writes messages to the synchronization memory space, starting from the beginning address and writing one address at a time. The counter value increases as messages are written (i.e., addresses are occupied), changing from 0 to 1, from 1 to 2, and so on, until the message writing is complete and the value becomes n. When the MCU sends a write completion command to the ESC, the ESC can determine that the message writing is complete and generate a completion interrupt to send to the master station.

[0041] Furthermore, in the method of this embodiment, when the master station reads the target packet from the synchronization memory space, the master station can obtain which addresses the target packet occupies in the synchronization memory space based on the data content of the target packet, and directly read the data in these addresses at once to obtain the target packet. Subsequently, ESC reduces the value of the counter by the same amount as the data length of the target packet.

[0042] For example, when the master station reads a message from the synchronization memory space, it first determines that the message occupies address bits 1 to 5 in the synchronization memory space based on the start address information and length information (length is 5) in the message. The master station then copies the data from address bits 1 to 5 into the frame at once. The ESC then subtracts the message length of 5 from the current counter value of 5, setting the counter value to 0.

[0043] In the method of this embodiment, when the counter value is 0, it can be determined that there is no data in the current synchronized memory space, and therefore the synchronized memory space is read empty. Accordingly, when the counter value is the same as the length of the data to be written, it can be determined that all the data to be written has been written into the synchronized memory space.

[0044] In the method of this embodiment, an interrupt is triggered based on the completion status of reading / writing data in the synchronized memory space. Furthermore, the "whether to trigger an interrupt" setting can also be configured according to actual needs.

[0045] The method described in this embodiment eliminates the dependence on the size of the synchronous memory space. The data to be exchanged does not need to strictly match the preset memory size, and there is no need to interrupt communication or adjust the synchronous memory space configuration due to changes in data volume. This avoids concerns about real-time performance loss and reduces operational complexity. Furthermore, it allows interrupts to be triggered based on the actual amount of data transmitted (i.e., the counter value), rather than forcibly requiring data to be precisely filled to the end address of the synchronous memory space. This avoids the problem of delayed interruptions due to data not reaching the end address, significantly enhancing real-time performance. Moreover, interrupt generation can be enabled or disabled through register configuration. Even when interrupts are disabled, the counter will continue to count read / write operations for querying by the master and slave stations. The method described in this embodiment balances real-time requirements with system flexibility and is suitable for real-time control requirements in various scenarios.

[0046] Example 2: This application discloses another method for data exchange; please refer to [link / reference]. Figure 2a This embodiment describes the method for the process of data exchange between the master station and the slave station, specifically the process of the master station writing and the slave station reading.

[0047] Step 201: The master station writes message a to the synchronization memory space.

[0048] Step 202: ESC detects that the length of message a is 8, and changes the counter value from 0 to 8.

[0049] Step 203: Synchronize the memory space to store message a starting from address 1# and continue until it reaches address 8#, and verify the frame check sequence at the end of the message.

[0050] Step 204: Determine if the verification result is correct. If yes, proceed to step 205. If no, proceed to step 206.

[0051] Step 205: Trigger an interrupt. Proceed to step 207.

[0052] Step 206: Clear the counter value and delete message a. Return to step 201.

[0053] Step 207: The slave station starts reading message a bit by bit from address 1 in the synchronization memory space, up to address 8.

[0054] Step 208: As message a is read, the value of the counter changes from 8 to 7, from 7 to 6... until it becomes 0.

[0055] Step 209: Trigger an interrupt.

[0056] Example 3: This application discloses another method for data exchange; please refer to [link / reference]. Figure 2b This embodiment describes the method for the process of slave station writing and master station reading in data exchange between master station and slave station.

[0057] Step 210: The slave station starts writing message b bit by bit from address 1 of the synchronization memory space.

[0058] Step 211: As message b is written, the value of the counter increases continuously from 0 to 1, from 1 to 2, and so on, until the writing is complete, and the counter finally reaches 5.

[0059] Step 212: ESC confirms that the message writing is complete and generates a completion interrupt to send to the master station.

[0060] Step 213: Trigger an interrupt.

[0061] Step 214: The master station obtains the address occupied by message b in the synchronization memory space as address bits 1 to 5 based on the starting address information and length information of message b.

[0062] Step 215: The master station reads the data from address 1 to address 5 in the synchronous memory space, and the counter value changes from 5 to 0.

[0063] Step 216: Trigger an interrupt.

[0064] Based on the data exchange method disclosed in the above embodiments, this embodiment correspondingly discloses a data exchange apparatus. Please refer to... Figure 3 The data exchange device includes: a configuration unit 301 and an execution unit 302; The configuration unit 301 is used to configure a counter in the synchronization manager SM; the counter is used to count the amount of data in the synchronization memory space in real time; the synchronization memory space is divided by the SM. The execution unit 302 is used to increase / decrease the value of the counter according to the length of the data when the synchronous memory space is written to / read from the data.

[0065] Optionally, the execution unit 302 includes: The identification subunit is used to identify the data length of the data when the master station writes the data into the synchronous memory space; An additional subunit is added to increment the value of the counter by the same amount as the data length.

[0066] Optionally, the device further includes: A verification unit is used to verify the correctness of the frame verification sequence at the end of the data and obtain the verification result. An interrupt unit is used to generate an interrupt when the verification result is correct; The zeroing unit is used to clear the value of the counter when the verification result is incorrect.

[0067] Optionally, the execution unit 302 includes: The decrementing subunit is used to decrement the value of the counter by 1 for each address bit read from the synchronous memory space when the slave reads the data, until the value of the counter is 0.

[0068] Optionally, the subtraction subunit is further configured to: An interrupt was triggered.

[0069] Optionally, the execution unit 302 includes: The increment subunit is used to increment the value of the counter by 1 for each address bit written when the data is written from the slave to the synchronous memory space.

[0070] Optionally, the device further includes: The sending unit is used by the slave data processor MCU to send a write completion command to the slave protocol controller ESC after the data writing is completed; The counting unit is used to send the interrupt generated by the ESC to the master station.

[0071] Optionally, the execution unit 302 includes: The acquisition subunit is used to acquire the address of the data in the synchronous memory space according to the data length when the master station reads the data from the synchronous memory space. A read subunit is used to read data from the address; The reduction subunit is used by the slave protocol controller (ESC) to reduce the value of the counter by a value equal to the data length of the data.

[0072] Optionally, the device further includes: The advance unit is used to write an early end read signal to the slave station to inform the slave station protocol controller ESC to generate an interrupt and send it to the master station to clear the value of the counter.

[0073] Optionally, when the value of the counter is 0, it is determined that the data in the synchronized memory space has been read empty; When the value of the counter is the same as the length of the data being written, it is determined that the synchronous memory space is full.

[0074] Optionally, when writing data to the synchronized memory space, the writing starts from the starting address of the synchronized memory space.

[0075] The embodiments in this specification are described in a progressive manner. For the apparatus disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple; relevant details can be found in the method section.

[0076] It should also be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0077] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0078] The features described in the embodiments of this specification can be substituted for or combined with each other, so that those skilled in the art can implement or use this application.

[0079] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for data exchange, characterized in that, include: Configure the counter in the Synchronization Manager (SM); The counter is used to count the amount of data in the synchronized memory space in real time. The synchronization memory space is obtained by partitioning the SM; When data is written to / read from the synchronous memory space, the value of the counter is increased / decreased according to the length of the data.

2. The method according to claim 1, characterized in that, When data is written to / read from the synchronous memory space, increasing / decreasing the counter value according to the length of the data includes: When the master station writes the data into the synchronous memory space, the slave station protocol controller (ESC) identifies the data length of the data. Increment the value of the counter by the same amount as the data length.

3. The method according to claim 2, characterized in that, After incrementing the counter value by the same amount as the data length, the method further includes: The correctness of the frame verification sequence at the end of the data is verified to obtain the verification result. An interrupt is generated when the verification result is correct; When the verification result is incorrect, the value of the counter is cleared to zero.

4. The method according to claim 1, characterized in that, When data is written to / read from the synchronous memory space, increasing / decreasing the counter value according to the length of the data includes: When the slave station reads data from the synchronous memory space, it decrements the value of the counter by 1 for each address bit read, until the value of the counter is 0.

5. The method according to claim 4, characterized in that, After the value of the counter reaches 0, the method further includes: An interrupt was triggered.

6. The method according to claim 1, characterized in that, When data is written to / read from the synchronized memory space, after incrementing / decrementing the counter value according to the length of the data, the method further includes: The slave station writes an early end read signal to notify the slave station protocol controller (ESC) to generate an interrupt and send it to the master station, thus clearing the value of the counter to zero.

7. The method according to claim 1, characterized in that, When data is written to / read from the synchronous memory space, increasing / decreasing the counter value according to the length of the data includes: When writing data from the station into the synchronous memory space, the value of the counter is incremented by 1 for each address bit written.

8. The method according to claim 7, characterized in that, When data is written to / read from the synchronized memory space, after incrementing / decrementing the counter value according to the length of the data, the method further includes: After the slave data processor MCU completes the data writing, it sends a write completion command to the slave protocol controller ESC. The ESC generates an interrupt and sends it to the master station.

9. The method according to claim 1, characterized in that, When data is written to / read from the synchronous memory space, increasing / decreasing the counter value according to the length of the data includes: When the master station reads the data from the synchronous memory space, it obtains the address of the data in the synchronous memory space based on the starting address information and length of the data; Read the data within the address; The slave protocol controller (ESC) reduces the value of the counter by the same amount as the length of the data.

10. The method according to any one of claims 1-9, characterized in that, When the value of the counter is 0, it is determined that the data in the synchronized memory space has been read empty; When the value of the counter is the same as the length of the data being written, it is determined that the synchronous memory space is full.

11. The method according to any one of claims 1-9, characterized in that, When writing data to the synchronized memory space, the writing starts from the starting address of the synchronized memory space.

12. A data exchange apparatus, characterized in that, include: Configuration unit and execution unit; The configuration unit is used to configure counters in the synchronization manager SM; The counter is used to count the amount of data in the synchronized memory space in real time. The synchronization memory space is obtained by partitioning the SM; The execution unit is configured to increase / decrease the value of the counter according to the length of the data when data is written to / read from the synchronous memory space.

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