Configuration information determination method and related equipment

Abstract

The invention provides a configuration information determination method and related equipment, and the method is applied to electronic equipment with a split TOF camera, and can be used for determining the configuration information of a Tx module in the split TOF camera. The method comprises the steps that internal resistance of a first GPIO interface is adjusted to a first resistance position and a second resistance position respectively, state values of the first GPIO interface under the two conditions are read respectively, finally, configuration information corresponding to a Tx module is determined based on the two state values, the configuration information is associated with a first pin state of a first pin of the Tx module, and the Tx module is configured according to the configuration information. And the Tx module is connected with the first GPIO interface through the first pin, so that the state value of the first GPIO interface is related to the state of the first pin, and the configuration information of the Tx module can be determined through the state values of the GPIO interface under the two conditions.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of electronic devices, and particularly relates to a configuration information determination method and related devices. BACKGROUND

[0002] Currently, more and more electronic devices are equipped with time of flight (TOF) cameras. A TOF camera generally includes a transmitting (Tx) module and a receiving (Rx) module, wherein the Tx module is used to emit infrared light or laser pulses, and the Rx module is used to receive reflected light and form an image (TOF image). Since the Tx module can autonomously emit light signals for imaging, the TOF image is not affected by most light in the environment, and therefore the TOF image can be applied in business scenarios such as face recognition.

[0003] In actual applications, different manufacturers' Rx modules are often used on electronic devices, and the configuration information of Rx modules produced by different manufacturers is generally different. Therefore, how the electronic device determines the configuration information corresponding to the Tx module on its own TOF camera is a problem that needs to be considered at present. SUMMARY

[0004] Embodiments of the present application provide a configuration information determination method and related devices, which can be used to determine the configuration information corresponding to the Tx module in a split TOF camera.

[0005] In a first aspect, a configuration information determination method is provided. The method is applied to an electronic device having a split TOF camera, and the method includes: adjusting an internal resistance of a first general purpose input / output (GPIO) interface to a first resistance value, and reading a first state value of the first GPIO interface at present, the first GPIO interface being connected with a first pin of a Tx module in the split TOF camera; adjusting the internal resistance of the first GPIO interface to a second resistance value, and reading a second state value of the first GPIO interface at present, one of the first resistance value and the second resistance value being a pull-up resistance value, and the other being a pull-down resistance value; and determining configuration information corresponding to the Tx module according to the first state value and the second state value, the configuration information being associated with a first pin state of the first pin.

[0006] In the above scheme, the configuration information corresponding to the Tx module can be determined based on the state values of the internal resistance of the first GPIO interface at different resistance positions. Specifically, the first pin state of the first pin is associated with the configuration information in the above scheme, that is, different first pin states can be associated with different configuration information, so as long as the first pin state is identified or the associated information of the first pin state is obtained, the configuration information corresponding to the Tx module can be determined. Since the state value of the first GPIO interface is related to the internal resistance position and the level of external connection, the state value of the internal resistance of the first GPIO interface at different resistance positions can be used to identify the first pin state, so the configuration information corresponding to the Tx module can be determined according to the two state values.

[0007] After determining the configuration information corresponding to the Tx module, the Tx module and the Rx module in the TOF camera can work normally, so as to provide corresponding services for the user, such as face unlocking service. Otherwise, the work of the TOF camera will be affected, thereby affecting the user experience.

[0008] Optionally, in some possible implementation manners of the first aspect, the configuration information corresponding to the Tx module is determined according to the first state value and the second state value, including: determining the first pin state of the first pin according to the first state value and the second state value; and determining the configuration information corresponding to the Tx module based on the first pin state.

[0009] In the above scheme, the first pin state can be determined according to the state value of the first GPIO at different resistance positions, and then the configuration information corresponding to the Tx module can be determined based on the first pin state. In the scheme provided in the present application, the first pin state is associated with the configuration information of the Tx module, that is, different first pin states are associated with different configuration information, so the first pin state can be identified through the state value of the first GPIO interface, and the configuration information of the Tx module can be further determined.

[0010] Optionally, in some possible implementation manners of the first aspect, the first pin state is any one of the following three: pin high-level pull-up, or pin low-level pull-down, or pin suspension.

[0011] By setting the above three first pin states, the combination of the first state value and the second state value read by the first GPIO interface after adjusting the internal resistance to different resistance positions has no overlap, that is, the combination of the first state value and the second state value can uniquely correspond to a first pin state, so that the scheme of determining the configuration information of the Tx module through the first state value and the second state value can be implemented.

[0012] Optionally, in some possible implementation manners of the first aspect, the method further includes: adjusting an internal resistance of the second GPIO interface to a third resistance position, and reading a third state value of the second GPIO interface at present, the second GPIO interface being connected with the second pin of the Tx module; adjusting the internal resistance of the second GPIO interface to a fourth resistance position, and reading a fourth state value of the second GPIO interface at present, one of the third resistance position and the fourth resistance position being a pull-up resistance position, and the other being a pull-down resistance position; determining the configuration information corresponding to the Tx module based on the first state value and the second state value, including: determining the configuration information based on the first state value, the second state value, the third state value and the fourth state value.

[0013] In the foregoing scheme, two first GPIO interfaces are arranged, so that the state of the two pins on the Tx module can be detected. In this way, at most 9 combinations can be arranged based on the states of the two pins, that is, at most 9 different configuration information can be supported to improve the number of Tx manufacturers supported by the split TOF camera.

[0014] Optionally, in some possible implementation manners of the first aspect, adjusting the internal resistance of the first GPIO interface to the first resistance position and reading the first state value of the first GPIO interface at present includes: adjusting the internal resistance of the first GPIO interface to the first resistance position, and reading the first state value after a first preset time length, the first preset time length being greater than or equal to a first threshold; adjusting the internal resistance of the first GPIO interface to the second resistance position and reading the second state value of the first GPIO interface at present includes: adjusting the internal resistance of the first GPIO interface to the second resistance position, and reading the second state value after the first preset time length.

[0015] In this scheme, after adjusting the resistance position of the internal resistance of the first GPIO interface, the state value of the first GPIO interface is not read immediately, but is read after a first preset time length (such as 1 ms), that is, after the state of the first GPIO interface is determined to be stable, so as to avoid the case that the state value of the first GPIO interface is read before the state of the first GPIO interface is stable, which leads to inaccurate state value and affects the subsequent detection result.

[0016] It can be understood that the first preset time length is generally not too large (such as the first preset time length also needs to be less than a third threshold), because if the first preset time length is too large, the detection efficiency will also be affected.

[0017] Optionally, in some possible implementation manners of the first aspect, after adjusting the internal resistance of the first GPIO interface to the second resistance position and reading the current second state value of the first GPIO interface, the method further includes adjusting the internal resistance of the first GPIO interface back to the default resistance position.

[0018] In the above solution, after adjusting the internal resistance of the first GPIO interface to the second resistance position and reading the current second state value of the first GPIO interface, the resistance of the first GPIO interface can also be adjusted back to the default resistance position. Because the original default resistance position of the internal resistance of the first GPIO interface is not affected by the detection process (i.e., the detection process of the first pin state of the first pin of the Tx module) involved in the embodiments of the present application, the original execution logic of the first GPIO interface is avoided.

[0019] Optionally, in some possible implementation manners of the first aspect, adjusting the internal resistance of the first GPIO interface to the first resistance position includes: adjusting the internal resistance of the first GPIO interface to the first resistance position after the electronic device is powered on and a second preset time duration elapses.

[0020] Adjusting the internal resistance of the first GPIO interface to the first resistance position and the second resistance position after the electronic device is powered on is mainly to identify the first pin state as soon as possible after the electronic device is powered on, so as to determine the configuration information corresponding to the Tx module based on the first pin state. Because the user can need the TOF camera to provide service support at any time after the electronic device is powered on, if the configuration information corresponding to the Tx module is identified by adjusting the resistance position of the internal resistance of the first GPIO interface after the user calls the TOF camera, a time delay can be caused, which affects the user experience. Automatically executing the solution provided by the method 200 after the electronic device is powered on can avoid the time delay caused by subsequently executing the solution.

[0021] The second aspect provides an electronic device, including a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor executes the computer program to enable the electronic device to implement the steps of the method in any one of the above first aspect.

[0022] The third aspect provides a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement the steps of the method in any one of the above first aspect or the second aspect.

[0023] The fourth aspect provides a computer program product, which enables an electronic device to execute the method in any one of the above first aspect when the computer program product runs on the electronic device.

[0024] In a fifth aspect, a chip system is provided, which includes a processor coupled with a memory, and the processor executes a computer program stored in the memory to implement the method of any one of the first aspect.

[0025] The chip system can be a single chip or a chip module composed of multiple chips.

[0026] It can be understood that the beneficial effects of the second aspect to the fifth aspect can be referred to the related description of the first aspect, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 An application scenario of a TOF camera is shown;

[0028] Figure 2 A working principle diagram of a TOF camera is shown;

[0029] Figure 3 An exemplary flowchart of the method 200 is shown;

[0030] Figure 4 A structure and principle diagram of a GPIO interface is shown;

[0031] Figure 5 A resistance bit diagram of the internal resistance of the GPIO interface is shown;

[0032] Figure 6 Connection diagrams of six Tx modules and the first GPIO interface are shown;

[0033] Figure 7 A layered architecture diagram is shown;

[0034] Figure 8 A software module interaction entity diagram is shown;

[0035] Figure 9 A hardware architecture diagram of an electronic device is shown. DETAILED DESCRIPTION

[0036] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

[0037] Currently, more and more electronic devices are equipped with TOF cameras. The TOF camera can be used to measure depth information, and the imaging result is usually not affected by light and has the characteristics of high precision and high stability, so it is widely used in face recognition, gesture recognition, obstacle detection and other scenes. Next, the application scenarios of a TOF camera will be introduced. Figure 1 The application scenarios of a TOF camera will be introduced.

[0038] In Figure 1 , a mobile phone is taken as an example for illustration. In this example, a front camera of the mobile phone is a TOF camera, such as the TOF camera 110 shown in (a) of Figure 1 , the mobile phone can use the TOF camera to realize the automatic face unlocking function. In this application scenario, the user is currently holding the mobile phone and the screen of the mobile phone is turned on, at this time, the mobile phone displays a user interface 100a as shown in (a) of Figure 1 , the user interface 100a displays a lock icon 120a, which indicates that the mobile phone is currently in a lock screen interface (or an unlocked interface). At this time, the mobile phone automatically calls the TOF camera 110 to take one or more images containing a face and performs face recognition. For example, after the mobile phone collects a face image through the TOF camera 110, it extracts face features from the face image, and then compares the extracted face features with information in a local or cloud database to determine whether the face features match successfully. If the face recognition is successful, i.e., the face features match successfully, the mobile phone is automatically unlocked and can display a user interface 100b as shown in (b) of Figure 1 , the user interface 100b displays an unlock icon 120b, which indicates that the mobile phone is currently in an unlocked state.

[0039] When the TOF camera is working, it measures the distance between the face and the camera using infrared light beams, obtains depth information by calculating the time difference between the emission and reflection of the light beams, and then constructs a three-dimensional model of the face. This technology can achieve accurate depth perception under different lighting conditions and provides a reliable data basis for face recognition. Next, a working principle of the TOF camera will be described in detail. Figure 2 A working principle of the TOF camera will be described in detail.

[0040] As Figure 2As shown in (a) of FIG. 1, the TOF camera module includes a transmitting (Tx) module (or referred to as a transmitter) and a receiving (Rx) module (or referred to as a receiver). The Tx module can be configured to transmit light signals (infrared light or laser pulses), and the Rx module can be configured to receive images. The Tx module can be, for example, an infrared light transmitter. The Rx module can be, for example, a complementary metal oxide semiconductor (CMOS) or a charge coupled device (CCD) image sensor.

[0041] As an example, in the process of working, the TOF camera continuously transmits light signals (infrared light or laser pulses) to the target (e.g., a user) to be measured through the Tx module, and receives the light signals returned by the target to be measured at the Rx module, such as Figure 2 As shown in (b) of FIG. 1, the depth information of the target to be measured can be obtained according to the phase difference (delay) of the transmitted and received light signals.

[0042] The Tx module and the Rx module can exchange information through a bus. For example, after the Rx module determines the configuration information of the Tx module, the Rx module can send a register address (e.g., 0x11) corresponding to the configuration information of the Tx module to the Tx module through the bus (e.g., a serial peripheral interface (SPI) bus), and the Tx module can obtain its own configuration information from the storage space corresponding to the register address.

[0043] It should be understood that the configuration information of the Tx module is used for the Tx module to transmit light signals, and is also used for the Rx module to receive reflected signals corresponding to the light signals. The application does not limit the specific content of the configuration information of the Tx module.

[0044] As an example, the configuration information of the Tx module includes a working current. Based on the configuration information, the Tx module can work at a corresponding working current, so as to emit light signals with a corresponding light intensity. Correspondingly, the Rx module can obtain corresponding image data based on the reflected light of the light signals with a corresponding intensity emitted by the Tx module.

[0045] It should be noted that the Tx module can emit light signals with different light intensities when working at different working currents. For example, the Tx module can emit light signals with a first light intensity when working at a first current value. The Tx module can emit light signals with a second light intensity when working at a second current value. If the second current value is greater than the first current value, the second light intensity is greater than the first light intensity.

[0046] The image data acquired by the Rx module based on the reflected light of the light signals with different intensities is also different. For example, when the Tx module works at the first current value to emit a light signal with a first light intensity, the Rx module acquires first image data within a corresponding exposure time; when the Tx module works at the second current value to emit a light signal with a second light intensity, the Rx module acquires second image data within a corresponding exposure time.

[0047] As an example, the configuration information of the Tx module can further include a driving configuration parameter of a driver integrated circuit (Driver IC), which for example includes one or more of the following: a working mode, or a modulation frequency, or a start-up delay, etc. The Tx module can emit a light signal based on these parameters.

[0048] The TOF camera module sometimes uses Tx modules produced by different manufacturers, and the configuration information of Rx modules produced by different manufacturers is generally different. Therefore, before using the TOF camera, it is necessary to distinguish the Tx module to determine the corresponding configuration information of the Tx module.

[0049] For an integrated TOF camera, the Tx module and the Rx module are integrated in one module, and the corresponding manufacturer of the Tx module can be determined by data burning to determine the corresponding configuration information. For example, the Driver IC and the Vcsel of the Tx module are distinguished by electrically-erasable programmable read-only memory (EEPROM) burning to determine which manufacturer the Driver IC and the Vcsel correspond to, and then the customized configuration information of the manufacturer is used as the configuration information of the Tx module. The specific implementation process is not limited by the present application.

[0050] For a split TOF camera, the Tx module and the Rx module adopt a split design, for example, the Rx module is arranged in a separate module, and the Tx module is soldered on the mainboard. The Tx module cannot directly communicate with the mainboard, and in this case, the Tx module is separately supplied, so it cannot be distinguished by burning data.

[0051] In view of this, the embodiments of the present application provide a configuration information determination method for determining the configuration information of a Tx module in a split TOF camera. Specifically, the pins of Tx modules produced by different manufacturers can be set to different pin states in advance, and the pin state of the Tx module is identified by changing the resistance bit of the GPIO interface connected to the Tx module, so as to determine the corresponding manufacturer of the Tx module, that is, to determine the corresponding configuration information of the Tx module.

[0052] The following will be described in combination with Figure 3The method 200 in the method 200 exemplarily illustrates the specific implementation process of the determination method of the configuration information provided in the present application.

[0053] It should be understood that the method 200 is executed by an electronic device. The electronic device described in the embodiments of the present application can be any device installed with a TOF camera, such as a mobile phone, a tablet computer, a notebook computer, a personal computer (PC), an ultra-mobile personal computer (UMPC), a handheld computer, a netbook, a smart home device (such as a smart television, a smart screen, a large screen, a smart speaker, a smart air conditioner, etc.), a personal digital assistant (PDA), a wearable device (such as a smart watch, a smart bracelet, etc.), a vehicle-mounted device, a virtual reality device, etc., which are not limited in the embodiments of the present application.

[0054] Exemplarily, the electronic device for executing the method 200 includes a split TOF camera. As described above, the Tx module and the Rx module in the split TOF camera adopt a split design, that is, the Tx module and the Rx module are not integrated in the same module, but are arranged on different mainboards or modules.

[0055] The split TOF camera includes a first GPIO interface connected with the Tx module, for example, a first I / O pin of the first GPIO interface is connected with a first pin of the Tx module.

[0056] It should be understood that the present application does not limit the number of GPIO interfaces in the split TOF camera, and the first GPIO interface herein can refer to one of the plurality of GPIO interfaces in the split TOF.

[0057] The scheme provided in the embodiments of the present application adjusts the resistance bit of the internal resistance of the first GPIO interface connected with the Tx module, to obtain the state value of the first GPIO interface under different resistance bits of the internal resistance of the first GPIO interface, so as to determine the configuration information of the Tx module according to the state value of the first GIPO interface under different resistance bits. The specific implementation process can be referred to in the subsequent description, which is not described here.

[0058] The reason why the configuration information of the Tx module can be determined according to the state value of the first GIPO interface is that the first pin state of the first pin of the Tx module is associated with the configuration information of different manufacturers in advance, and the state value of the first GPIO interface is related to the first pin state. In order to facilitate understanding of the relationship between the state value of the first GPIO interface and the first pin state of the first pin of the Tx module, first, the relationship between the state value of the first GPIO interface and the first pin state of the first pin of the Tx module will be described in combination with Figure 4The structure and working principle of a GPIO interface provided in the embodiments of the present application are briefly described.

[0059] The GPIO interface generally refers to a general input / output interface arranged on a processor. The processor can control the input / output mode of the GPIO interface by writing data to the control register of the GPIO interface, and realize the function of controlling or collecting signals of certain devices. For example, in the application scenario corresponding to the embodiments of the present application, the processor can control the Tx module through the GPIO interface to realize the function of transmitting optical signals.

[0060] One processor generally includes multiple GPIO interfaces, and each GPIO interface generally includes multiple pins, each of which has basic input / output functions. Taking an STM32 microprocessor as an example, the GPIO interfaces of the STM32 microprocessor are divided into many groups, each group having 16 pins. For example, the chip with the model number STM32F407IGT6 has 9 groups of GPIO interfaces, namely GPIOA, GPIOB, GPIOC, …, GPIOI.

[0061] The most basic output function is to control the pins to output high and low levels by the processor, to realize switch control. For example, connecting the pins of the GPIO interface to an LED can control the brightness of the LED, and connecting the pins to a relay or a triode can control the on-off of an external high-power circuit through the relay or the triode. The most basic input function is to detect external input levels. For example, connecting the pins of the GPIO interface to a button can distinguish whether the button is pressed by the high and low levels of the pins.

[0062] Figure 4 is a possible schematic diagram of a GPIO structure. It can be understood that, Figure 4 Only part of the structure of the GPIO interface is shown, and this part of the structure is only for the convenience of explaining the scheme related to the present application, and therefore the actual internal structure of the GPIO interface can further include other modules or components, which are not limited in the present application.

[0063] As Figure 4 shown, when the pins of the GPIO interface are used for level detection, the level signal is input from the I / O pin 301. Two protection diodes on the upper and lower sides of the I / O pin are used to prevent the input of excessively high or low voltage from the outside of the pin. When the voltage of the pin is higher than VDD, the upper diode is turned on; when the voltage of the pin is lower than VSS, the lower diode is turned on, to prevent the chip from being burned out due to the introduction of abnormal voltage into the chip. After the level signal is input from the I / O pin 301, it is further transmitted to the Schmitt trigger 302. After the level signal passes through the Schmitt trigger 302, the analog signal is converted into a digital signal.

[0064] The pin of the GPIO interface can be configured as an input mode for receiving an external signal. In the input mode, the state of the pin is driven by an external circuit, and the processor reads the state. The input mode of the GPIO interface can have multiple modes, two of which are exemplarily introduced below.

[0065] One input mode is a pull-up input mode. The pull-up input mode refers to that an internal pull-up resistor is connected to the pin, and when the external circuit does not drive the pin, the pin is pulled up to a high level. This mode is suitable for the case where the external signal is effective when it is low. That is, in the pull-up input mode, the internal resistor of the GPIO interface is in a pull-up resistor position, as shown in (a) of FIG. 4, the internal resistor 410 of the GPIO interface is pulled up to be connected to the power supply, at this time, the internal resistor 410 is considered to be in the pull-up resistor position. Figure 5

[0066] In the pull-up input mode, the level signal of the I / O pin directly enters the input data register 303. However, in the case where the I / O pin is left floating (in the case of no signal input), the level of the output end can be kept at a high level; and when the I / O pin input is low, the level of the output end is still low. Generally, a logic digit "1" is used to represent the state of the output end being at a high level, and a logic digit "0" is used to represent the state of the output end being at a low level.

[0067] Another input mode is a pull-down input mode. The pull-down input mode refers to that an internal pull-down resistor is connected to the pin, and when the external circuit does not drive the pin, the pin is pulled down to a low level. This mode is suitable for the case where the external signal is effective when it is high. That is, in the pull-down input mode, the internal resistor of the GPIO interface is in a pull-down resistor position, as shown in (b) of FIG. 4, the internal resistor 420 of the GPIO interface is pulled down to be connected to the ground, at this time, the internal resistor 420 is considered to be in the pull-down resistor position. Figure 5

[0068] In the pull-down input mode, the level signal of the I / O pin directly enters the input data register 303. However, in the case where the I / O pin is left floating (in the case of no signal input), the level of the output end can be kept at a low level; and when the I / O pin input is high, the level of the output end is still high.

[0069] Based on the above introduction of the structure and working principle of the GPIO interface involved in the present application, how to obtain the state value of the first GPIO interface in the different state positions of the internal resistor will be specifically introduced in the scheme provided by the embodiments of the present application.

[0070] In S210, the internal resistor of the first GPIO interface is adjusted to a first resistor position, and a first state value of the first GPIO interface at present is read. ​​

[0071] Exemplarily, the electronic device adjusts the internal resistance of the first GPIO interface to a first resistance position, and reads a first state value of the first GPIO interface at present. Wherein, the first resistance position here can be the pull-up resistance position as shown in (a) of Figure 5 , or can be the pull-down resistance position as shown in (b) of Figure 5 . The first state value here is used to indicate whether the first GPIO interface is at a high level state or a low level state at present.

[0072] As known from the foregoing introduction about the structure and working principle of the interface GPIO interface, the state value of a GPIO interface is affected by the internal resistance position and the input level of the I / O pin, which is illustrated by examples as follows.

[0073] For example, in the pull-up input mode, i.e. the internal resistance of the GPIO interface is at the pull-up resistance position, if the I / O pin is left floating (i.e. no signal input), the output end level remains at a high level state, which can be represented by a logic number “1”; while the I / O pin input is at a low level, the output end level is still at a low level, which can be represented by a logic number “0”; while the I / O pin input is at a high level, the output end level is still at a high level, which can be represented by a logic number “1”.

[0074] For another example, in the pull-down input mode, i.e. the internal resistance of the GPIO interface is at the pull-down resistance position, if the I / O pin is left floating (i.e. no signal input), the output end level remains at a low level state, which can be represented by a logic number “0”; while the I / O pin input is at a high level, the output end level is still at a high level, which can be represented by a logic number “1”; while the I / O pin input is at a low level, the output end level is still at a low level, which can be represented by a logic number “0”.

[0075] The following is illustrated by examples in Figure 6 . In the six examples shown in (a)-(f) of Figure 6 , the Tx module is connected with the first GPIO interface, for example, the first I / O pin of the first GPIO interface is connected with the first pin of the Tx module.

[0076] Suppose the first resistance position is the pull-down resistance position, then the possible cases are shown in (a) of Figure 6 , (c) of Figure 6 and (e) of Figure 6 .

[0077] As shown in (a) of Figure 6 , the internal resistance of the first GPIO interface (R 内(Indicates) is in the pull-down resistor position. Since the state of the first pin of the Tx module is high at this time (R is used in the figure), it is in the pull-up position. 外 This represents the resistance formed by the internal circuitry of the Tx module and its first pin; therefore, R is generally... 外 < <R 内 R 外 Pull-up means that the first pin is pulled up to a high level, that is, the input of the first I / O pin of the first GPIO interface is in a high level state. Therefore, the current first state value of the first GPIO interface indicates that the output level of the GPIO interface is high, that is, the first state value can be "1".

[0078] like Figure 6 As shown in (c), the internal resistor of the first GPIO interface (R is used in the figure) 内 (Indicates) is in the pull-down resistor position. Since the state of the first pin of the Tx module is low at this time (R is used in the figure), 外 This represents the resistance formed by the internal circuitry of the Tx module and its first pin; therefore, R is generally... 外 < <R 内 R 外 Pull-down indicates that the first pin is pulled down to a low level, meaning that the input of the first I / O pin of the first GPIO interface is in a low-level state. Therefore, the current first state value of the first GPIO interface indicates that the output level is low, that is, the first state value can be "0".

[0079] like Figure 6 As shown in (e), the internal resistance of the first GPIO interface (R is used in the figure) 内 The first state value of the first GPIO interface is "0" because the first pin of the Tx module is in the pull-down resistor position. Since the first pin of the Tx module is floating at this time, that is, the first I / O pin of the first GPIO interface is floating (i.e., no signal input). Therefore, the current first state value of the first GPIO interface indicates that the output level is low, that is, the first state value can be "0".

[0080] Assuming the first resistor bit is a pull-up resistor bit, the possible scenarios are as follows: Figure 6 (b) Figure 6 (d) and Figure 6 As shown in (f) in the figure.

[0081] like Figure 6 As shown in (b) of the figure, the internal resistance of the first GPIO interface (R is used in the figure) 内 (Indicates) is in the pull-up resistor position. Since the state of the first pin of the Tx module is high at this time (R is used in the figure), 外 This represents the resistance formed by the internal circuitry of the Tx module and its first pin; therefore, R is generally... 外 < <R 内 R外 Pull-up means that the first pin is pulled up to a high level, that is, the input of the first I / O pin of the first GPIO interface is in a high level state. Therefore, the current first state value of the first GPIO interface indicates that the output level of the first GPIO interface is high, that is, the first state value can be "1".

[0082] like Figure 6 As shown in (d) in the figure, the internal resistance of the first GPIO interface (R is used in the figure) 内 (Indicated by) is in the pull-up resistor position. Since the state of the first pin of the Tx module is low at this time (R is used in the figure), 外 This represents the resistance formed by the internal circuitry of the Tx module and its first pin; therefore, R is generally... 外 < <R 内 R 外 Pull-down indicates that the first pin is pulled down to a low level, meaning that the input of the first I / O pin of the first GPIO interface is in a low-level state. Therefore, the current first state value of the first GPIO interface indicates that the output level of the first GPIO interface is low, that is, the first state value can be "0".

[0083] like Figure 6 As shown in (f), the internal resistance of the first GPIO interface (R is used in the figure) 内 The first state value of the first GPIO interface is "1" because the first pin of the Tx module is in the pull-up resistor position. Since the first pin of the Tx module is floating at this time, that is, the first I / O pin of the first GPIO interface is floating (i.e., no signal input). Therefore, the current first state value of the first GPIO interface indicates that the output level is high, that is, the first state value can be "1".

[0084] S220. Adjust the internal resistance of the first GPIO interface to the second resistance bit, and read the current second state value of the first GPIO interface.

[0085] For example, after reading the first state value of the first GPIO interface, the internal resistance of the first GPIO interface is adjusted to the second resistance bit, and the current second state value of the first GPIO interface is read.

[0086] It should be understood that the second resistor bit is different from the first resistor bit. That is, one of the first resistor bit and the second resistor bit is a pull-up resistor bit, and the other is a pull-down resistor bit. For convenience, the following explanation will use the example of the first resistor bit being a pull-down resistor bit and the second resistor bit being a pull-up resistor bit, but it should be understood that this application also applies to the case where the first resistor bit is a pull-up resistor bit and the second resistor bit is a pull-down resistor bit.

[0087] Assuming the first pin of the Tx module is in a high-level pull-up state, then step S210 corresponds to... Figure 6corresponds to the case shown in (a) of FIG. 2, i.e., the first state value indicates that the output terminal of the first GPIO interface is at a high level, i.e., the first state value can be "1"; meanwhile, step S220 corresponds to the case shown in (b) of FIG. 2, i.e., the second state value indicates that the output terminal of the first GPIO interface is also at a high level, i.e., the first state value can be "1". Therefore, the first state value and the second state value can be represented by the combined value "11". Figure 6

[0088] corresponds to the case shown in (c) of FIG. 2, i.e., the first state value indicates that the output terminal of the first GPIO interface is at a low level, i.e., the first state value can be "0"; meanwhile, step S220 corresponds to the case shown in (d) of FIG. 2, i.e., the second state value indicates that the output terminal of the first GPIO interface is also at a low level, i.e., the first state value can be "0". Therefore, the first state value and the second state value can be represented by the combined value "00". Figure 6 Figure 6

[0089] corresponds to the case shown in (e) of FIG. 2, i.e., the first state value indicates that the output terminal of the first GPIO interface is at a low level, i.e., the first state value can be "0"; meanwhile, step S220 corresponds to the case shown in (f) of FIG. 2, i.e., the second state value indicates that the output terminal of the first GPIO interface is also at a high level, i.e., the first state value can be "1". Therefore, the first state value and the second state value can be represented by the combined value "01". Figure 6 Figure 6

[0090] The present application does not limit the specific implementation process of reading the first state value and the second state value. In one possible implementation, the internal resistance of the first GPIO interface is adjusted to the first resistance position, and the first state value is read after a first preset time duration. Similarly, the internal resistance of the first GPIO interface is adjusted to the second resistance position, and the second state value is read after the first preset time duration. The above-mentioned first preset time duration is greater than or equal to a first threshold value, and as an example, the first preset time duration is equal to 1 ms. In this scheme, after adjusting the resistance position of the internal resistance of the first GPIO interface, the state value of the first GPIO interface is not read immediately, but is read after a first preset time duration (such as 1 ms), i.e., after determining that the state of the first GPIO interface is stable, so as to avoid the case that the state value of the first GPIO interface is read before the state of the first GPIO interface is stable, resulting in inaccurate reading of the state value, thereby affecting the subsequent detection result.

[0091] ​​​​​It can be understood that the first preset time length is generally not too large (e.g., the first preset time length is also required to be less than the third threshold value), because if the first preset time length is too large, the detection efficiency will also be affected.

[0092] Optionally, after adjusting the internal resistance of the first GPIO interface to the second resistance position and reading the current second state value of the first GPIO interface, the resistance of the first GPIO interface can also be adjusted back to the default resistance position. For example, the first resistance position is a pull-down resistance position, and the second resistance position is a pull-up resistance position. In this case, if the default resistance position of the internal resistance of the first GPIO interface is the pull-down resistance position, the operation of adjusting the internal resistance of the first GPIO interface to the first resistance position in step S210 can not be repeated (because the default resistance position and the first resistance position are the same). At the same time, after adjusting the internal resistance of the first GPIO interface to the second resistance position, the internal resistance of the first GPIO interface needs to be adjusted back to the default resistance position, i.e., the pull-down resistance position, because the default resistance position of the internal resistance of the first GPIO interface cannot be affected by the detection process (i.e., the detection process of the first pin state of the first pin of the Tx module, which will be described in detail in the description of step S230) of the embodiment of the present application, i.e., to avoid affecting the original execution logic of the first GPIO interface. For another example, the first resistance position is a pull-down resistance position, and the second resistance position is a pull-up resistance position. In this case, if the default resistance position of the internal resistance of the first GPIO interface is the pull-up resistance position, the resistance position of the internal resistance of the first GPIO interface needs to be switched from the default pull-up resistance position to the pull-down resistance position in step S210. At the same time, after adjusting the internal resistance of the first GPIO interface to the second resistance position, the operation of adjusting the internal resistance of the first GPIO interface to the default resistance position can not be repeated (because the default resistance position is the same as the second resistance position).

[0093] S230, determining the configuration information corresponding to the Tx module according to the first state value and the second state value.

[0094] Exemplarily, in the scheme provided by the embodiment of the present application, the first pin state is associated with the manufacturer corresponding to the Tx module in advance. Because the configuration information of the Tx module is determined by the manufacturer corresponding thereto, different manufacturers can set the Tx modules produced by themselves to different first pin states, so that different first pin states are associated with different manufacturers, i.e., different first pin states are associated with the configuration information corresponding to the Tx module.

[0095] In a possible implementation, the electronic device can determine the first pin state of the first pin according to the first state value and the second state value, and then determine the corresponding configuration information based on the first pin state. The following exemplarily describes this possible implementation.

[0096] Exemplarily, after the first state value and the second state value are acquired, the first pin state of the first pin of the Tx module is determined. It should be understood that in the embodiments of the present application, the Tx module is connected with the first I / O pin of the first GPIO interface through the first pin. As known from the foregoing introduction about the structure and principle of the GPIO interface, the state value of the first GPIO interface is related to the high or low of the level of the pin connected with the first I / O pin. That is, the first state value and the second state value are related to the first pin state of the first pin, and thus the first pin state can be determined based on the first state value and the second state value. The first pin state herein is any one of the following three: pin high level pull-up, or pin low level pull-down, or pin suspended.

[0097] Please refer to (a) in Figure 6 and (b) in Figure 6 : assuming that the first resistance position is a pull-down resistance position and the second resistance position is a pull-up resistance position, when the first pin state is pin high level pull-up, the first state value indicates that the output end level of the first GPIO interface is high level, i.e., the first state value can be "1"; the second state value indicates that the input level of the first GPIO interface is also high level, i.e., the first state value can be "1". Therefore, the first state value and the second state value can be represented by the combined value "11". That is, the combined value "11" is associated with the first pin state of "pin high level pull-up".

[0098] Please refer to (c) in Figure 6 and (d) in Figure 6 : assuming that the first resistance position is a pull-down resistance position and the second resistance position is a pull-up resistance position, when the first pin state is pin low level pull-down, the first state value indicates that the output end level of the first GPIO interface is low level, i.e., the first state value can be "0"; the second state value indicates that the input level of the first GPIO interface is also low level, i.e., the first state value can be "0". Therefore, the first state value and the second state value can be represented by the combined value "00". That is, the combined value "00" is associated with the first pin state of "pin low level pull-down".

[0099] Please refer to (e) in Figure 6 and (f) in Figure 6 : assuming that the first resistance position is a pull-down resistance position and the second resistance position is a pull-up resistance position, when the first pin state is information, the first state value indicates that the output end level of the first GPIO interface is low level, i.e., the first state value can be "0"; the second state value indicates that the input level of the first GPIO interface is high level, i.e., the first state value can be "1". Therefore, the first state value and the second state value can be represented by the combined value "01". That is, the combined value "01" is associated with the first pin state of "pin suspended".

[0100] Therefore, for the three cases of the first pin state, the combined value of the first state value and the second state value is not repeated, and thus the combined value of the first state value and the second state value can be used to uniquely determine the first pin state of the first pin of the Tx module. Specifically, when the combined value of the first state value and the second state value is "11", it indicates that the first pin state is a high-level pull-up pin; when the combined value of the first state value and the second state value is "00", it indicates that the first pin state is a low-level pull-down pin; and when the combined value of the first state value and the second state value is "01", it indicates that the first pin state is a floating pin.

[0101] It should be understood that the above examples of the present application are combined with the Figure 6 resistance bit as a pull-up resistance bit, the second resistance bit as a pull-down resistance bit, and the combined value of the first state value and the second state value is taken as an example of the first state value first and the second state value second, but the present application is not limited thereto. That is, in another implementation, the first resistance bit can be a pull-up resistance bit, and the second resistance bit is a pull-down resistance bit; or, in another possible implementation, the combined value of the first state value and the second state value is composed of the second state value first and the first state value second. One of the cases is exemplarily described below.

[0102] Please refer to Figure 6 (b) and Figure 6 (a): Assuming that the first resistance bit is a pull-up resistance bit and the second resistance bit is a pull-down resistance bit, when the first pin state is a high-level pull-up pin, the first state value indicates that the output end level of the first GPIO interface is high, i.e., the first state value can be "1"; the second state value indicates that the input level of the first GPIO interface is also high, i.e., the first state value can be "1". The combined value of the first state value and the second state value is composed of the first state value first and the second state value second, and thus the first state value and the second state value can be represented by the combined value "11".

[0103] Please refer to First state value (d) and Second state value (c): Assuming that the first resistance bit is a pull-up resistance bit and the second resistance bit is a pull-down resistance bit, when the first pin state is a low-level pull-down pin, the first state value indicates that the output end level of the first GPIO interface is low, i.e., the first state value can be "0"; the second state value indicates that the input level of the first GPIO interface is also low, i.e., the first state value can be "0". The combined value of the first state value and the second state value is composed of the first state value first and the second state value second, and thus the first state value and the second state value can be represented by the combined value "00".

[0104] Please refer toFirst pin state (f) and Configuration information In (e): Similarly, assuming the first resistor bit is a pull-up resistor bit and the second resistor bit is a pull-down resistor bit, when the first pin is floating, the first state value indicates that the output level of the first GPIO interface is high, that is, the first state value can be "1"; the second state value indicates that the input level of the first GPIO interface is low, that is, the first state value can be "0". The combined value of the first and second state values ​​is formed with the first state value first and the second state value last, so the first and second state values ​​can be represented by the combined value "10".

[0105] As the above analysis shows, the combination of the first state value and the second state value is associated with a unique first pin state. Therefore, the first pin state of the Tx module can be determined using the first state value and the second state value, and the corresponding configuration information can be determined based on this first pin state. It is understood that in this implementation, the electronic device has a pre-configured association between the combination of the first state value and the second state value, the first pin state, and the configuration information. Table 1 shows an example of this association.

[0106] Table 1

[0107] Pin high pull-up Configuration information #1 Pin low pull-down Configuration information #2 1 1 Pin left floating Configuration information #3 0 0 First state value Second state value 0 1 Configuration information Configuration information #1

[0108] It should be understood that the first state value, second state value, first pin state, and configuration information in Table 1 can all be indicated using predefined identifiers or information. For example, the three types of the first pin state can be represented by three different numbers, such as "pin high-level pull-up" represented by number a, "pin low-level pull-down" represented by number b, and "pin floating" represented by number c. Similarly, configuration information #1 to configuration information #3 can be represented by the register addresses corresponding to the configuration information.

[0109] In another possible implementation, the electronic device can also determine the manufacturer of the Tx module based on the first and second state values, and then determine the configuration information of the Tx module based on the manufacturer. In this implementation, the "First Pin State" column in Table 1 can be modified to display the identifiers of different manufacturers. The specific scheme is similar, so it will not be described in detail here.

[0110] In yet another possible implementation, after the electronic device acquires the first state value and the second state value, the electronic device directly determines the configuration information corresponding to the Tx module according to the first state value and the second state value. That is, in this implementation, although the configuration information of the Tx module is still associated with the first pin state, the first state value and the second state value are also read in the case where the first I / O pin of the GPIO interface is connected to the first pin of the Tx module, but when determining the configuration information, the step of determining the first pin state can be skipped, and the configuration information can be directly determined, because the correspondence between the combination of the first state value and the second state value and the configuration information is also unique, and skipping the step of determining the first pin state can improve the efficiency of the scheme execution. In this implementation, the electronic device is preconfigured with the association relationship between the combination of the first state value and the second state value and the configuration information, and Table 2 shows an example of such an association relationship.

[0111] Table 2

[0112] Configuration information #2 Configuration information #3 First state value 1 1 Second state value 0 0 Third state value 0 1 Fourth state value

[0113] From the above scheme, it can be known that when one GPIO is used to detect the first pin state of the Tx module, at most three first pin states are supported, that is, at most three Tx modules of different manufacturers are supported. Therefore, the present application further proposes a scheme for detecting the first pin state of the Tx module through a plurality of GPIO combinations on this basis, which is illustrated below.

[0114] It is assumed that the electronic device further includes a second GPIO interface connected to the second pin of the Tx module. In addition to the steps introduced in S210 and S220, the following operations can also be performed: adjusting the internal resistance of the second GPIO interface to a third resistance position, and reading the current third state value of the second GPIO interface; adjusting the internal resistance of the second GPIO interface to a fourth resistance position, and reading the current fourth state value of the second GPIO interface, one of the third resistance position and the fourth resistance position being a pull-up resistance position, and the other being a pull-down resistance position. It should be understood that the adjustment method of the internal resistance of the second GPIO interface, and the reading method of the third state value and the fourth state value are similar to the steps S210 and S220 described above, and for the sake of brevity, they will not be described here. In this case, step S230 can be specifically: determining the configuration information corresponding to the Tx module according to the first state value, the second state value, the third state value, and the fourth state value.

[0115] Since there are at most three states of one pin of the Tx module, and more than three manufacturers are to be supported, the states of two or more pins in the Tx module can be pre-set. Correspondingly, the electronic device also needs to use a plurality of GPIO interfaces to detect the states of the plurality of pins, respectively.

[0116] The above scheme takes two pins (i.e., the first pin and the second pin) of the Tx module as an example for illustration. A certain vendor is corresponded to a certain combination of states of the two pins, i.e., a certain configuration information. For example, if the first pin is in a high-level pull-up state and the second pin is also in a high-level pull-up state, vendor A is corresponded to; if the first pin is in a high-level pull-up state and the second pin is in a low-level pull-down state, vendor B is corresponded to, and so on.

[0117] In a possible implementation, after the electronic device obtains the first state value, the second state value, the third state value, and the fourth state value, the electronic device directly determines the configuration information of the Tx module according to the four state values. That is, in this implementation, although the configuration information of the Tx module is still associated with the first pin state, the first state value and the second state value are read in the case that the first I / O pin of the first GPIO interface is connected to the first pin of the Tx module, and the third state value and the fourth state value are read in the case that the second I / O pin of the second GPIO interface is connected to the second pin of the Tx module, when determining the configuration information, the process of determining the first pin state and the second pin state can be skipped, and the configuration information is directly determined. In this implementation, the electronic device is preconfigured with the association relationship between the combination of the first state value, the second state value, the third state value, and the fourth state value and the configuration information. Table 3 shows an example of the association relationship.

[0118] Table 3

[0119] Configuration information Configuration information #1 Configuration information #2 Configuration information #3 Configuration information #4 1 1 1 1 Configuration information #5 1 1 0 0 Configuration information #6 1 1 0 1 Configuration information #7 0 0 1 1 Configuration information #8 0 0 0 0 Configuration information #9 0 0 0 1 Figure 7 0 1 1 1 Figure 7 0 1 0 0 Figure 7 0 1 0 1 Figure 7

[0120] As can be seen from Table 3, when two GPIO interfaces are used to detect two pins on the Tx module, at most 9 combinations can be supported, i.e., at most 9 configuration information of 9 vendors can be supported.

[0121] It should be understood that Table 3 only exemplarily lists all possible cases, and in actual application, only part of the association relationships in Table 3 (e.g., only four pairs of association relationships) can be used, which is not limited in the present application.

[0122] It should also be understood that the electronic device can also use 3 or more GPIO interfaces to detect multiple pins on the Tx module to support detection of more than 9 configuration information, which will not be described in detail here.

[0123] It can be understood that the application does not limit the specific timing of the above-mentioned scheme. In one possible implementation, the internal resistance of the first GPIO interface is adjusted to the first resistance position after the electronic device is powered on and a second preset time period elapses. Then, after reading the first state value, the internal resistance of the first GPIO interface is adjusted to the second resistance position, and the configuration information corresponding to the Tx module is determined based on the first state value and the second state value. The second preset time period is greater than or equal to the second threshold value, and in one possible implementation, the second preset time period can be 0.

[0124] Adjusting the internal resistance of the first GPIO interface to the first resistance position and the second resistance position after the electronic device is powered on is mainly to identify the first pin state as soon as possible after the electronic device is powered on, so as to determine the configuration information corresponding to the Tx module based on the first pin state (for details, please refer to the description of S240 in the following part, which is not described here). Because the user may need the TOF camera to provide service support at any time after the electronic device is powered on, if the resistance position of the internal resistance of the first GPIO interface is adjusted to identify the configuration information corresponding to the Tx module after the user calls the TOF camera, it may cause a large time delay, which affects the user experience. The automatic execution of the scheme provided by the method 200 after the electronic device is powered on can avoid the time delay caused by the subsequent execution of the scheme.

[0125] Generally, the scheme provided by the application can be executed once after the electronic device is powered on each time.

[0126] In summary, the embodiment of the application provides a configuration information determination method, which can be used to determine the configuration information corresponding to the Tx module in a separated TOF camera. The scheme associates the pin state of a pin of the Tx module with the configuration information of different manufacturers in advance, so that by reading the state value of the internal resistance of the GPIO interface at different resistance positions, the pin state of the Tx module can be determined, and the configuration information corresponding to the Tx module can be further determined. The scheme can determine the configuration information of the Tx module by improving the software and controlling the change of the hardware, without adding new hardware, that is, the scheme can accurately detect the configuration information corresponding to the Tx module at a small cost, so as to provide services for users using the TOF module.

[0127] Figure 7 is a structure block diagram of a layered architecture 500 corresponding to an electronic device provided by an embodiment of the application. The steps performed by the electronic device in the method provided by the embodiment of the application can be implemented by the software and hardware modules shown in Figure 7 .

[0128] The layered architecture 500 includes software layers and hardware layers, and the software layers are further divided into several layers, each of which has a clear role and division of labor. The layers communicate with each other through a software interface. Figure 7 In the example shown, the software layers of the electronic device at least include an application layer, an application framework layer, a hardware abstraction layer (HAL), and a kernel.

[0129] It can be understood that, Figure 7 Only for example, that is, the layers divided in the electronic device are not limited to Figure 8 The layers shown, such as, between the application framework layer and the HAL layer, can also include an Android runtime and a system library layer, etc.

[0130] Exemplarily, the application layer can include a series of application packages. As Figure 7 shown, the application layer can include a camera application. Of course, in addition to the camera application, the application layer can also include other application packages, such as a gallery application, a video application, and a plurality of application packages.

[0131] Generally, an application is developed using a certain programming language (such as java), and some functions are implemented by calling the application programming interface (API) and programming framework provided by the application framework layer. Exemplarily, the application framework layer includes some pre-defined functions.

[0132] As Figure 8 shown, the application framework layer can include a camera service that can be called by the camera application to implement shooting-related functions. Of course, the application framework layer can also include a content provider, a resource manager, a notification manager, a window manager, a view system, a phone manager, and the like. Similarly, the camera application can also call the content provider, the resource manager, the notification manager, the window manager, the view system, and the like according to actual business needs, and the present application embodiments do not make any limitation on this.

[0133] The kernel layer is a layer between hardware and software. As Figure 8 shown, the kernel layer at least includes Video for linux2 (V4L2), a camera request manager (CRM), a camera driver, and an ISP driver.

[0134] The V4L2 can be called by the HAL layer. The CRM is used to manage the drivers corresponding to the camera-related devices in the kernel layer, such as a camera driver and an ISP driver. In some examples, the HAL can instruct the CRM to manage the drivers corresponding to the camera-related devices through the V4L2.

[0135] The camera driver can be used to drive a hardware module with a shooting function, such as a camera sensor. The ISP driver is used to drive the SFE in the ISP chip. In other words, the camera driver is responsible for data interaction with the camera sensor. Of course, the kernel layer can also include audio drivers, sensor drivers, and other driver software, and the embodiments of the present application do not make any limitation thereto.

[0136] In addition, the camera driver can also include a Tx detection module, which is used to obtain the state value of the internal resistance of the GPIO interface under different resistance positions from the hardware layer, and detect the configuration information corresponding to the Tx module based on the state value of the GPIO interface. For specific processes, please refer to the subsequent Figure 8 corresponding description.

[0137] In addition, the HAL layer can encapsulate the drivers in the kernel layer and provide an interface for calling of the application framework layer, and shield the implementation details of the low-level hardware.

[0138] As Figure 8 shown, the HAL layer can include a CAMX architecture and a CHI-CDK.

[0139] The CAMX part implements the HAL3 interface upward, communicates with the kernel Kernel through the V4L2 framework downward, and interacts with the CHI-CDK through mutual dlopen so library and obtaining the operation interface of the other party.

[0140] The CAMX part can include, but is not limited to, the following main directory structure: core: used to store the core implementation module of the CAMX, which also contains the Hal directory mainly used to implement the HAL3 interface, and the CHI directory responsible for interacting with the CHI; CAMX conversion interface (camera serial interface decoder, CSL): used to store the module mainly responsible for the communication between the CAMX and the camera driver, which provides a unified camera driver control interface for the CAMX. The CAMX CSL can receive camera parameters from the sensor node and convert them into I / O control instructions recognizable by the kernel layer. In addition, the above-mentioned CAMX CSL can also instruct the CRM to pass the I / O control instructions corresponding to the camera parameters to the corresponding camera driver through the V4L2 in the kernel layer, so that the camera driver writes the I / O control instructions corresponding to the camera parameters into the camera sensor, so that the camera sensor performs image output according to the specified image output mode.

[0141] The CHI-CDK can include a user mode driver. The user mode driver is a driver running in the user space of the electronic device, and the user mode driver includes an XML query interface for querying various XML files stored in the user space. For example, the Module is used to store and query the relevant information of different camera modules (including camera sensor chips, lenses, motors, eeprom storage modules, etc.). The CHI-CDK can also include an API interface for user input of the CAMX module configuration file. For details, please refer to the subsequent Figure 9 .

[0142] In order to more clearly describe the operations performed by the above-mentioned software modules when implementing the scheme provided in the present application, the internal structure and interaction process of part of the modules will be described below. Figure 9 .

[0143] As shown in Figure 9 , the Tx detection module (get_tof_tx_idpin_status) in the camera driver of the kernel layer is used to obtain the configuration parameters corresponding to the Tx module, trigger the internal resistance of the GPIO interface to switch between different resistance positions, read the state value of the internal resistance of the GPIO interface at different resistance positions, and determine the detection result based on the read state value. Details are as follows. As shown in ​As shown, the CHI-CDK includes a user mode driver, and a module (Module) in the user mode driver can be used to configure a driver configuration file in XML format (caepmuf_m0xx.xml). In the embodiment of the present application, a configuration parameter corresponding to the Tx module can be configured in the driver configuration file, and the configuration parameter includes state value combination information corresponding to the Tx module, such as "11", or "00", or "01". It should be understood that different combination information usually corresponds to different configuration files. That is, one configuration parameter can be added to the Module at a time, and the configuration parameter is used to indicate a specific configuration parameter of the Tx module, and the configuration parameter is associated with a preconfigured pin state of the Tx module. It can be understood that the configuration parameter can also include a control parameter for the GPIO interface, and the control parameter is used to control the internal resistance of the GPIO interface to switch between different resistance positions. It can also be understood that the configuration parameter can also include identification information of the configuration information, such as the register address of the configuration information. It should be understood that the configuration information corresponds to the state value combination in the configuration parameter, that is, is associated with a pin state of the Tx module. The probe function (probe()) obtains camera module data (CameraModuleData) from the Module after the electronic device is powered on, and the camera module data includes the foregoing configuration parameter.

[0144] The CAMX architecture can communicate with the V4L2 in the kernel layer through the ioct1 function in the csl, so the foregoing configuration parameter can be transmitted to the V4L2 in the kernel layer via the csl. The Tx detection module in the camera driver can obtain the configuration parameter from the V4L2, and send a control instruction to the GPIO based on the configuration parameter, and the control instruction is used to instruct the GPIO to switch the internal resistance between different resistance positions. For example, the control instruction instructs the GPIO to switch the internal resistance to the pull-down resistance position, and after a first preset time period, the internal resistance is switched to the pull-up resistance position, and finally after the first preset time period, the internal resistance is switched back to the default resistance position. The Tx detection module reads the state value (such as the first state value and the second state value) of the GPIO interface when the internal resistance of the GPIO interface is in different resistance positions in this process, and detects based on the first state value and the second state value. For example, the Tx module compares the combination of the read first state value and the second state value with the state value combination carried in the configuration parameter, and finally returns the detection result to the CAMX architecture. The return result is used to indicate whether the detection is successful, if so, the probe function determines that the Tx module is successfully detected, and stores the identification of the configuration information corresponding to the Tx module in the probe information. If the detection is not successful, a new configuration file needs to be replaced in the Module in the CHI-CDK, and the foregoing detection process needs to be re-executed until the detection is successful.

[0145] As ​ shown, ​ A hardware structure schematic diagram of an electronic device is provided in the present application. The electronic device 600 can include a processor 601 and a camera 602. Optionally, it can also include a display screen 603, a sensor 604, a memory 605, a mobile communication module 606, and a wireless communication module 607.

[0146] It can be understood that the structure shown in the embodiment does not constitute a specific limitation on the electronic device 600. In other embodiments, the electronic device 600 can include more or fewer components than shown, or combine certain components, or split certain components, or different component arrangements. The components shown can be implemented in hardware, software, or a combination of software and hardware.

[0147] The processor 601 can include one or more processing units, for example: the processor 601 can include an application processor (AP), a modem processor, a graphics processing unit (GPU), an image signal processor (ISP), a controller, a video codec, a digital signal processor (DSP), a baseband processor, and / or a neural-network processing unit (NPU), etc. Different processing units can be independent devices or integrated in one or more processors. In the scenario introduced in the embodiments of the present application, Rx can control Tx through the ISP.

[0148] In some embodiments, the processor 601 can include one or more interfaces, including at least a GPIO interface. In addition, the interfaces in the processor 601 can also include an inter-integrated circuit (I2C) interface, an inter-integrated circuit sound (I2S) interface, a pulse code modulation (PCM) interface, a universal asynchronous receiver / transmitter (UART) interface, a mobile industry processor interface (MIPI), a subscriber identity module (SIM) interface, and / or a universal serial bus (USB) interface, etc., without limitation.

[0149] It can be understood that the interface connection relationship between the modules shown in the embodiments is only illustrative and does not limit the structure of the electronic device 600. In other embodiments of the present application, the electronic device 600 can also use different interface connection modes or combinations of multiple interface connection modes.

[0150] The processor 601 can also be connected to or internally provided with a memory 605 for storing instructions and data. In some embodiments, the memory in the processor 601 is a cache memory. The memory can store instructions or data that have just been used or are repeatedly used by the processor 601. If the processor 601 needs to use the instructions or data again, it can directly call from the memory. This avoids repeated access and reduces the waiting time of the processor 601, thereby improving the efficiency of the system.

[0151] The camera 602 can include 1-N. For example, the electronic device 600 can include 2 front cameras and 4 rear cameras. Among them, the front camera can include a TOF camera. The TOF camera includes Tx and Rx, Tx can be used to emit light signals (infrared light or laser pulses), and Rx can be used for imaging. Tx and Rx can exchange information through a bus. For example, Rx can send configuration parameters to Tx through the bus (for example, a serial peripheral interface (SPI) bus), which indicates the address of the register corresponding to Tx and the value for the register. For example, the address of the register corresponding to Tx can be 0x11, and the storage space corresponding to 0x11 can store the configuration information corresponding to Tx.

[0152] In the embodiment of the present application, the Tx module in the TOF camera is connected with the GPIO in the processor 601, such as a pin in the Tx module is connected with an I / O pin in the GPIO. In the present application, by adjusting the internal resistance of the GPIO interface at different resistance positions, the pin state of the Tx module can be identified, so as to determine the corresponding configuration information of the Tx module. For details, refer to the description in the method 200, which will not be repeated here.

[0153] The display screen 603 is used to display images, videos, etc. The display screen 603 includes a display panel. The display panel can adopt a liquid crystal display (LCD), an organic light-emitting diode (OLED), an active-matrix organic light-emitting diode (AMOLED), a flexible light-emitting diode (FLED), a MiniLED, a MicroLED, a Micro-OLED, a quantum dot light-emitting diode (QLED), etc. In some embodiments, the electronic device 600 can include 1 or N display screens 603, and N is a positive integer greater than 1.

[0154] The electronic device 600 realizes the display function through the GPU, the display screen 603, and the application processor, etc., and realizes the shooting function through the ISP, the camera 602, the video codec, the GPU, the display screen 603, and the application processor, etc. The specific process is not limited in the present application.

[0155] The sensor 604 can include a pressure sensor, a gyroscope sensor, a distance sensor, a touch sensor, a temperature sensor, etc. of various types, for collecting various environmental data, distance data, etc.

[0156] The wireless communication function of the electronic device 600 can be realized through the antenna 1, the antenna 2, the mobile communication module 606, the wireless communication module 607, the modem processor, and the baseband processor, etc. The specific mode is not limited in the present application.

[0157] In addition, on the above-mentioned components, an operating system is running. For example, an iOS operating system, an Android operating system, a Windows operating system, etc. Application programs can be installed and run on the operating system.

[0158] The methods in the embodiments of the present application can be implemented in the electronic device 600 with the hardware structure described above.

[0159] The hardware structure of the electronic device is introduced here. It can be understood that, ​ The components included in the hardware structure shown do not constitute a specific limitation on the electronic device. The electronic device can have more or fewer components than those shown in the figure, can combine two or more components, or can have a different component configuration. The various components shown in the figure can be implemented in hardware, software, or a combination of hardware and software, including one or more signal processing and / or application specific integrated circuits.

[0160] The embodiments of the present application also provide a computer readable storage medium, which stores a computer program. The computer program is executed by a processor to implement the steps in each of the above method embodiments.

[0161] The embodiments of the present application provide a computer program product. When the computer program product is run on an apparatus, the apparatus is caused to implement the steps in each of the above method embodiments.

[0162] The embodiments of the present application provide a chip for executing instructions. When the chip is running, the technical solutions in the above embodiments are executed. The implementation principles and technical effects are similar, and will not be repeated here.

[0163] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions can be transferred from one website, computer, server or data center to another website, computer, server or data center through wired (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (such as infrared, wireless, microwave, etc.) The computer-readable storage medium can be any available medium accessible by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be magnetic media (such as floppy disk, hard disk, magnetic tape), optical media (such as high-density digital video disc (digital video disc, DWD)), or semiconductor media (such as solid state disk (solid state disk, SSD)) and the like.

[0164] The integrated unit, if implemented in the form of a software function unit and sold or used as an independent product, can be stored in a computer-readable storage medium. Based on such understanding, the present application can implement all or part of the processes in the above-mentioned embodiment methods, which can be completed by instructing related hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and when the computer program is executed by a processor, the steps of the above-mentioned various method embodiments can be implemented. The computer program includes computer program code, which can be in the form of source code, object code, executable file or some intermediate form, etc. The computer-readable medium at least includes any entity or device capable of carrying the computer program code to the photographing device / electronic device, recording medium, computer memory, read-only memory (read-only memory, ROM), random access memory (random access memory, RAM), electrical carrier signal, telecommunication signal and software distribution medium. For example, U disk, mobile hard disk, magnetic disk or optical disk, etc. In some jurisdictions, according to legislation and patent practice, the computer-readable medium cannot be an electrical carrier signal and a telecommunication signal.

[0165] In the above embodiments, the description of each embodiment has its own focus, and the parts not described or recorded in a certain embodiment can be referred to the relevant description of other embodiments.

[0166] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solutions. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0167] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the above-described device embodiments are only schematic, and the division of the units is only a logical function division, and actual implementation can have another division manner, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interface, device or unit, and can be electrical, mechanical or other forms.

[0168] It should be understood that the "embodiments" mentioned throughout the specification mean that the specific features, structures or characteristics related to the embodiments are included in at least one embodiment of the present application. Therefore, the various embodiments throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the sequence number of the above processes does not mean the execution order, and the execution order of the processes should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0169] The above-described embodiments are only used to illustrate the technical solutions of the present application, but not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

[0170] In addition, it needs to be explained that various numbers involved in the present application (such as the terms "first", "second", "third", "fourth" and other various term labels in the description and claims and the above-mentioned drawings (if any) and the like) are only for the convenience of description and do not limit the scope of the present application. The size of the serial number of each process does not mean the order of execution, and the execution order of each process should be determined according to its function and inherent logic.

[0171] The terms "comprise" and "have" and any variations thereof mean "including but not limited to", unless otherwise specifically emphasized, for example, a process, method, system, product or device including a series of steps or units does not have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0172] In the embodiments of the present application, the words "exemplarily" or "for example" are used to represent as an example, illustration or description. Any embodiment or design scheme described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words "exemplarily" or "for example" are intended to present the relevant concept in a specific manner.

[0173] In various embodiments of the present application, the terms and / or descriptions between different embodiments are consistent and can be referred to each other if there is no special description and logical conflict, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationship. The specific operation method in the method embodiment of the present application can also be applied to the device embodiment or the system embodiment.

Claims

1. A method of determining configuration information, characterized by, The method is applied to an electronic device including a split TOF camera, and the method includes: adjusting an internal resistance of a first GPIO interface to a first resistance position, and reading a first state value of the first GPIO interface at present, the first GPIO interface being connected with a first pin of a Tx module in the split TOF camera; adjusting the internal resistance of the first GPIO interface to a second resistance position, and reading a second state value of the first GPIO interface at present, one of the first resistance position and the second resistance position being a pull-up resistance position, and the other being a pull-down resistance position; determining configuration information corresponding to the Tx module according to the first state value and the second state value, the configuration information being associated with a first pin state of the first pin.

2. The method of claim 1, wherein, The determining of the configuration information corresponding to the Tx module according to the first state value and the second state value includes: determining the first pin state of the first pin according to the first state value and the second state value; determining the configuration information corresponding to the Tx module based on the first pin state.

3. The method according to claim 1 or 2, characterized in that, The first pin state is any one of the following three: a pin high-level pull-up, or a pin low-level pull-down, or a pin suspension.

4. The method of claim 1 or 2, further comprising: adjusting an internal resistance of a second GPIO interface to a third resistance position, and reading a third state value of the second GPIO interface at present, the second GPIO interface being connected with a second pin of the Tx module; adjusting the internal resistance of the second GPIO interface to a fourth resistance position, and reading a fourth state value of the second GPIO interface at present, one of the third resistance position and the fourth resistance position being a pull-up resistance position, and the other being a pull-down resistance position; The determining of the configuration information corresponding to the Tx module according to the first state value and the second state value includes: determining the configuration information according to the first state value, the second state value, the third state value and the fourth state value.

5. The method of claim 1 or 2, wherein the adjusting of the internal resistance of the first GPIO interface to the first resistance position and the reading of the first state value of the first GPIO interface at present include: adjusting the internal resistance of the first GPIO interface to the first resistance position, and reading the first state value after a first preset time period, the first preset time period being greater than or equal to a first threshold value; The adjusting of the internal resistance of the first GPIO interface to the second resistance position and the reading of the second state value of the first GPIO interface at present include: adjusting the internal resistance of the first GPIO interface to the second resistance position, and reading the second state value after the first preset time period. After the adjusting of the internal resistance of the first GPIO interface to the second resistance position and the reading of the second state value of the first GPIO interface at present, the method further includes: adjusting the internal resistance of the first GPIO interface back to a default resistance position.

6. The method of claim 1 or 2, wherein, ​ ​ 7. The method according to claim 1 or 2, characterized in that, The adjusting the internal resistance of the first GPIO interface to the first resistance position comprises: The adjusting the internal resistance of the first GPIO interface to the first resistance position comprises:

8. An electronic device, comprising: The electronic device comprises one or more processors and a memory; The memory is coupled to the one or more processors, and the memory is configured to store computer program codes, the computer program codes comprising computer instructions, and the one or more processors are configured to invoke the computer instructions to cause the electronic device to perform the method according to any one of claims 1 to 7.

9. A chip system, characterized by The chip system is applied to an electronic device, and the chip system comprises one or more processors configured to invoke computer instructions to cause the electronic device to perform the method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium comprises instructions configured to cause an electronic device to perform the method according to any one of claims 1 to 7 when the instructions are executed on the electronic device.

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