Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof. The method comprises the following steps: forming a plurality of fin structures which extend along a first direction and are arranged at intervals along a second direction on a substrate, and first oxide layers filled between adjacent fin structures; etching the fin structure and the first oxide layer to form a plurality of first grooves which extend along the second direction and are arranged at intervals along the first direction; the plurality of first grooves comprise a plurality of first sub-grooves and a plurality of second sub-grooves which are alternately arranged along the first direction, and the residual fin structures located between the adjacent first grooves form a plurality of semiconductor columns which are arranged at intervals along the first direction; forming a second oxide layer covering the side wall of the first sub-trench; removing a part of the first oxide layer and a part of the second oxide layer to expose two opposite side walls of the semiconductor column along the second direction and a side wall of the semiconductor column close to the first sub-trench along the first direction; and at least forming a gate oxide layer and a gate layer which are stacked on the exposed side wall of the semiconductor column.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a semiconductor structure and a manufacturing method thereof. BACKGROUND

[0002] A memory array of a dynamic random access memory (DRAM) is composed of memory cells each consisting of a transistor and a capacitor. The gate of the transistor is connected to a word line, the drain is connected to a bit line, and the source is connected to the capacitor.

[0003] As the DRAM process continues to shrink, the decreasing word line pitch leads to a significant increase in its parasitic capacitance, causing serious signal crosstalk and delay. At the same time, the shrinking of the transistor size also leads to a decrease in its gate control ability, directly threatening the stability of the stored charge. Both have become key challenges to the performance and reliability of DRAM. SUMMARY

[0004] Therefore, embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof.

[0005] The technical solutions of the embodiments of the present disclosure are implemented as follows: In one aspect, the present disclosure provides a manufacturing method of a semiconductor structure, the method comprising: forming a plurality of fin structures extending along a first direction parallel to the substrate and spaced apart along a second direction parallel to the substrate on a substrate, and a first oxide layer filled between adjacent fin structures; etching the fin structures and the first oxide layer to form a plurality of first trenches extending along the second direction and spaced apart along the first direction; wherein the plurality of first trenches comprises a plurality of first sub-trenches and a plurality of second sub-trenches alternately arranged along the first direction, and the remaining fin structures between adjacent first trenches form a plurality of semiconductor pillars spaced apart along the first direction; forming a second oxide layer covering the sidewalls of the first sub-trenches; removing part of the first oxide layer and part of the second oxide layer to expose two sidewalls of the semiconductor pillars opposite along the second direction and the sidewalls of the semiconductor pillars close to the first sub-trenches along the first direction within a preset height interval in a third direction perpendicular to the substrate; forming a stacked gate oxide layer and a gate layer at least on the exposed sidewalls of the semiconductor pillars.

[0006] In some embodiments, the forming a stacked gate oxide layer and a gate layer at least on the exposed sidewalls of the semiconductor pillars comprises: oxidizing at least sidewalls of the semiconductor pillars in situ to form gate oxide layers; forming a gate layer covering the gate oxide layers.

[0007] In some embodiments, the method further comprises: filling insulating material in the second sub-trenches to form first insulating layers; alternatively, sequentially forming first insulating layers and back gate structures in the second sub-trenches; the first insulating layers enclosing the back gate structures.

[0008] In some embodiments, the removing part of the first oxide layer and part of the second oxide layer to expose, within a preset height range in the third direction, two sidewalls of the semiconductor pillars opposite in the second direction and a sidewall of the semiconductor pillar close to the first sub-trench, comprises: removing part of the first oxide layer and part of the second oxide layer to form a second trench extending in the second direction; the second trench comprises a plurality of first portions between the semiconductor pillars adjacent in the second direction and a second portion communicating the plurality of first portions in the first trench; forming a first barrier layer on sidewalls of the second trench, the first barrier layer filling the second portion of the second trench; based on the second trench, removing part of the first oxide layer and part of the second oxide layer between the second trench and the substrate to form a third trench extending in the second direction; the third trench comprises a plurality of first portions between the semiconductor pillars adjacent in the second direction and a second portion communicating the plurality of first portions in the first trench; wherein, within a preset height range in the third direction, the first portion of the third trench exposes two sidewalls of the semiconductor pillars opposite in the second direction, and the second portion of the third trench exposes a sidewall of the semiconductor pillar close to the first trench in the first direction.

[0009] In some embodiments, the method further comprises: forming a plurality of contact structures on a first end of the semiconductor pillars away from the substrate in the third direction, each of the contact structures corresponding to one of the semiconductor pillars; the contact structures covering at least part of the surface of the semiconductor pillars at the first end and at least part of the side surface of the semiconductor pillars; wherein the plurality of contact structures are arranged in an array in the second direction and a fourth direction; the fourth direction is perpendicular to the third direction and intersects the first direction and the second direction respectively.

[0010] In some embodiments, the method further comprises: While forming the contact structure, the portion of the semiconductor pillar not covered by the contact structure is removed, so that the contact structure covers the entire surface of the semiconductor pillar located at the first end.

[0011] In some embodiments, the method further includes: A plurality of capacitor structures are formed on the side of the contact structure away from the semiconductor pillar, corresponding to and connected to each of the contact structures; the plurality of capacitor structures are arranged in an array along the second direction and the fifth direction; the fifth direction is perpendicular to the third direction and intersects the first direction and the second direction respectively.

[0012] In some embodiments, the method further includes: Remove the substrate to expose the surface of the fin structure along the third direction near the second end of the substrate; A bit line extending along the first direction is formed on the surface of the second end of the fin structure; A shielding structure is formed that is at least partially located between adjacent bit lines.

[0013] On the other hand, embodiments of this disclosure provide a semiconductor structure comprising: A plurality of isolation structures extending along a second direction and spaced apart along a first direction; wherein the plurality of isolation structures include a plurality of first sub-isolation structures and a plurality of second sub-isolation structures alternately arranged in the first direction; A plurality of transistor structures are arranged at intervals along the second direction between adjacent first sub-isolation structures and second sub-isolation structures in the first direction; each transistor structure includes a semiconductor pillar that contacts the second sub-isolation structure and extends along the third direction, and a gate layer that is connected to the semiconductor pillar and extends along the second direction. Within the predetermined height range of the third direction, the gate layer surrounds the two opposite sidewalls of the semiconductor pillar along the second direction, and the sidewall of the semiconductor pillar away from the second sub-isolation structure along the first direction; the first direction, the second direction, and the third direction are perpendicular to each other.

[0014] In some embodiments, the semiconductor pillar includes a first active region, a channel region, and a second active region arranged sequentially along the third direction; wherein the gate layer surrounds the semiconductor pillar located on the sidewall of the channel region; the dimension of the channel region along the second direction is smaller than the dimension of either the first active region or the second active region in the second direction.

[0015] In some embodiments, the transistor structure further includes: A gate oxide layer that is at least partially located between the semiconductor pillar and the gate layer.

[0016] In some embodiments, the second sub-isolation structure includes: First insulating layer; or, The back grid structure and the first insulating layer surrounding the back grid structure.

[0017] In some embodiments, the semiconductor structure further includes: Multiple contact structures are located at the first end of the plurality of semiconductor pillars in the third direction, each contact structure being connected to one semiconductor pillar in a one-to-one correspondence; the contact structures cover at least a portion of the surface of the semiconductor pillar at the first end and at least a portion of the side surface of the semiconductor pillar.

[0018] In some embodiments, the semiconductor structure further includes: A plurality of capacitor structures are located on the side of the contact structure away from the semiconductor pillar and are connected to each of the contact structures. The plurality of semiconductor pillars are arranged in an array along the first direction and the second direction; the plurality of contact structures are arranged in an array along the second direction and the fourth direction; the plurality of capacitor structures are arranged in an array along the second direction and the fifth direction; the fourth direction is perpendicular to the third direction and intersects the first direction and the second direction respectively; the fifth direction is perpendicular to the third direction and intersects the first direction and the second direction respectively.

[0019] In some embodiments, the semiconductor structure further includes: A bit line located at the second end of the semiconductor pillar along the third direction, the bit line extending along the first direction and connecting to the plurality of semiconductor pillars; and... A shielding structure located at least partially between adjacent bit lines.

[0020] This embodiment of the present disclosure forms a stacked gate oxide layer and a gate layer on two opposing sidewalls of the semiconductor pillar along the second direction and on the sidewall near the first sub-trench along the first direction. This results in a final transistor structure that is a fin-type field-effect transistor structure where the gate surrounds the channel on three sides and the gate is mirror-symmetrical in the first direction. While maintaining a constant distance between the center lines of two adjacent word lines, the channel size, the gate oxide layer thickness, and the gate layer thickness, the transistor structure provided by this embodiment can effectively increase the distance between adjacent word lines, reduce the parasitic capacitance between adjacent word lines, and effectively increase the gate area. Attached Figure Description

[0021] Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to embodiments of this disclosure; Figures 2 to 74A step diagram illustrating a method for manufacturing a semiconductor structure provided in the disclosed embodiments; Figures 75 to 76 A schematic diagram of a first semiconductor structure provided in an embodiment of this disclosure; Figure 77 A schematic diagram of a second semiconductor structure provided in an embodiment of this disclosure; Figure 78 A schematic diagram of a third semiconductor structure provided in the embodiments of this disclosure; Figure 79 A schematic diagram of a fourth semiconductor structure provided in this disclosure embodiment; Figure 80 This is a schematic diagram of a semiconductor structure including a memory array layer, a bonding layer, and a logic circuit layer, provided in an embodiment of this disclosure.

[0022] Figure label: Substrate-101; Fin structure-102; First oxide layer-103; First sub-trench-104; Second sub-trench-105; Semiconductor pillar-106; First mask-107; Sacrificial layer-108; Second mask-170; First insulating layer-109; Second oxide layer-110; Second insulating layer-111; Second trench-112; First portion of the second trench-113; Second portion of the second trench-114; First barrier layer-115; Third trench-116; First portion of the third trench-117; Second portion of the third trench-118; Gate Oxide layer - 119; Gate layer - 120; Active region - 121; Contact region - 122; First lead - 123; Third insulating layer - 124; Contact structure - 125; First contact layer - 126; Second contact layer - 127; Third contact layer - 128; Capacitor structure - 129; Lower electrode - 130; Interlayer dielectric layer - 131; Upper electrode - 132; Bit line - 134; Second lead - 135; Shielding structure - 136; Back gate structure - 137; Air gap - 138; Memory array layer - 200; Bonding layer - 300; Logic circuit layer - 400. Detailed Implementation

[0023] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0024] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0025] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0026] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0027] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0028] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0029] To fully understand this disclosure, detailed steps and structures will be presented in the following description to illustrate the technical solutions of this disclosure. Preferred embodiments of this disclosure are described in detail below; however, other embodiments may also be implemented in addition to these detailed descriptions.

[0030] The transistor involved in the embodiments of this disclosure refers to a device that includes at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode). The gate can control the conductivity of the channel region, thereby enabling current to flow between the source, the channel region, and the drain based on gate control.

[0031] The deposition processes involved in the embodiments of this disclosure include, but are not limited to: chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), sputtering, metal organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), and combinations thereof.

[0032] The etching processes disclosed herein include, but are not limited to, dry etching, wet etching, and combinations thereof.

[0033] This disclosure provides a method for manufacturing a semiconductor structure, the main steps of which are as follows: Figure 1 As shown, the specific process can be found by referring to [the diagram]. Figures 2 to 74 (For ease of explanation, the directions of the cross-section are marked in each figure: X direction, Y direction, and Z direction, with the X direction perpendicular to the Y direction.) The method includes: Step S101: A plurality of fin structures 102 extending along a first direction parallel to the substrate 101 and spaced apart along a second direction parallel to the substrate 101 are formed on the substrate 101, and a first oxide layer 103 is filled between adjacent fin structures 102, such as... Figure 2 and Figure 4 As shown, where, Figure 4 for Figure 2 and Figure 3 A schematic diagram of the XY cross-sectional structure at point AA.

[0034] here, Figures 2 to 74 The first direction can be understood based on the Y direction, but is not limited to the Y direction; the second direction can be understood based on the X direction, but is not limited to the X direction; and the third direction can be understood based on the Z direction, but is not limited to the Z direction.

[0035] This disclosure does not specifically limit the constituent materials of the substrate described above. As an example, substrate 101 can be constructed from semiconductor materials, insulating materials, conductive materials, or any combination thereof. Substrate 101 can be a single-layer structure or a multi-layer structure. For example, substrate 101 can be a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V or II / VI semiconductor substrates. Alternatively, substrate 101 can be a layered substrate comprising, for example, a stack of Si and SiGe, a stack of Si and SiC, silicon-on-insulator (SOI), or silicon-germanium-on-insulator.

[0036] In some examples, the material of the fin structure 102 is the same as that of the substrate 101, and the fin structure 102 can be formed on the surface of the substrate 101 by etching the substrate 101.

[0037] In some embodiments, the material of the first oxide layer 103 includes silicon oxide. In one example, after the fin structure 102 is formed, an oxide material can be deposited between adjacent fin structures 102 in the second direction using a deposition process. Thus, fin structures 102 and the first oxide layer 103, which are alternately arranged in the second direction (X direction) and both extend along the first direction (Y direction), are formed, as shown below. Figure 4 As shown.

[0038] Step S102: Etch the fin structure 102 and the first oxide layer 103 to form a plurality of first trenches extending along a second direction and spaced apart along a first direction; wherein, the plurality of first trenches include a plurality of first sub-trenches 104 and a plurality of second sub-trenches 105 alternately arranged along the first direction, and the remaining fin structure 102 located between adjacent first trenches forms a plurality of semiconductor pillars 106 spaced apart along the first direction, such as... Figures 5 to 7 As shown, where, Figure 7 for Figure 5 and Figure 6 A schematic diagram of the XY cross-sectional structure at point AA.

[0039] Specifically, a patterned first mask 107 is formed on the surfaces of the fin structure 102 and the first oxide layer 103. This patterned first mask 107 is used to etch areas in the fin structure 102 and the first oxide layer 103 not covered by the first mask 107, forming a plurality of first trenches extending along a second direction and spaced apart along a first direction. The plurality of first trenches include a plurality of first sub-trenches 104 and a plurality of second sub-trenches 105 alternately arranged along the first direction. At this time, the remaining portion of each fin structure 102 between adjacent first sub-trenches 104 and second sub-trenches 105 forms a plurality of semiconductor pillars 106 extending along a third direction (Z direction) and spaced apart along the first direction. Thus, the remaining portions of the plurality of fin structures 102 between adjacent first sub-trenches 104 and second sub-trenches 105 form a plurality of semiconductor pillars 106 extending along a third direction and arranged in an array along both the first and second directions. Each semiconductor pillar 106 defines the distribution location of a transistor structure.

[0040] Here, the etching depth of the first trench in the third direction can be less than the length of the fin structure 102 in the third direction, so that the bit line (BL) located at the bottom of the fin structure 102 can be formed in subsequent processes.

[0041] In some embodiments, the first mask 107 may be a hard mask. The material of the first mask 107 includes, but is not limited to, silicon nitride, amorphous carbon, polycrystalline silicon, metal, etc.

[0042] In this embodiment of the disclosure, the projection of the semiconductor pillar 106 onto the substrate 101 includes, but is not limited to, square, circular or other achievable shapes.

[0043] It should be noted that the array of semiconductor pillars 106 formed in this embodiment is specifically arranged along a first direction and a second direction, with the first direction perpendicular to the second direction. This solution has low manufacturing difficulty and is easy to implement in terms of process.

[0044] In some embodiments, after forming the array of semiconductor pillars 106, a first active region and a second active region can be formed at opposite ends of the semiconductor pillars 106 along a third direction. In a specific embodiment, the first active region can be located at the end of the semiconductor pillar 106 away from the substrate 101 along a third direction, and the first active region can serve as the source region of a transistor structure. The second active region can be located at the end of the semiconductor pillar 106 closer to the substrate 101 along a third direction, and the second active region can serve as the drain region of a transistor structure.

[0045] Here, the methods for forming the first active region and the second active region include, but are not limited to, doping processes and diffusion processes.

[0046] In some embodiments, the semiconductor pillar 106 can be an N-type doped semiconductor pillar, or it can be a P-type doped semiconductor pillar. When the semiconductor pillar 106 is N-type doped, the N-type impurity source can be phosphorus (P), arsenic (As), etc., and is not limited to these. When the semiconductor pillar 106 is P-type doped, the P-type impurity source can be boron (B), aluminum (Al), etc., and is not limited to these.

[0047] In some embodiments, after forming the first trench, a sacrificial material is deposited within the first trench and on the surface of the first mask 107 to form a sacrificial layer 108 located within the first trench. Subsequently, a chemical mechanical polishing (CMP) process is used to remove the sacrificial material on the surface of the first mask 107, so that the surface of the sacrificial layer 108 is flush with the surface of the first mask 107. Figures 8 to 10 As shown, where, Figure 10 for Figure 8 and Figure 9 A schematic diagram of the XY cross-sectional structure at point AA.

[0048] Here, the sacrificial materials used to form the sacrificial layer 108 include, but are not limited to, silicon dioxide (SiO2), carbon (C), etc.

[0049] After the sacrificial layer 108 is formed, a patterned second mask 170 is formed on the surfaces of the first mask 107 and the sacrificial layer 108. Specifically, the second mask 170 covers the surface of the sacrificial layer 108 located within the first sub-trench 104, but does not cover the surface of the sacrificial layer 108 located within the second sub-trench 105, as shown below. Figures 11 to 13 As shown, where, Figure 13 for Figure 11 and Figure 12 A schematic diagram of the XY cross-sectional structure at AA. Subsequently, the sacrificial layer 108 located within the second sub-trench 105 can be etched away using a patterned second mask 170.

[0050] In some embodiments, the material of the second mask 170 includes oxides, such as silicon dioxide.

[0051] In some embodiments, after forming the second mask 170, the method of manufacturing the semiconductor structure further includes filling the second sub-trench 105 with insulating material to form a first insulating layer 109.

[0052] Specifically, such as Figures 14 to 16 As shown, where, Figure 16 for Figure 14 and Figure 15 A schematic diagram of the XY cross-sectional structure at point AA. Insulating material, such as silicon nitride, is deposited within the second sub-trench 105, on the sides of the first mask 107, and on the sides and surface of the second mask 170 to form an insulating material layer. A portion of the insulating material layer located within the second sub-trench 105 forms the first insulating layer 109.

[0053] In some embodiments, the insulating material fills the second sub-trench 105. In other embodiments, the insulating material only covers the bottom surface and inner wall of the second sub-trench 105, without filling it completely. In this case, the area within the second sub-trench 105 not filled by the first insulating layer 109 forms an air gap extending in the second direction. This air gap is used to enhance the electrical isolation between adjacent transistors in the first direction and prevent signal crosstalk.

[0054] In other embodiments, after forming the second mask 170, the method for manufacturing the semiconductor structure further includes: sequentially forming a first insulating layer 109 and a back gate structure within the second sub-trench 105. Figure 15 and Figure 16 (not shown in the image); the first insulating layer 109 surrounds the back grid structure.

[0055] Specifically, insulating material is deposited on the inner wall and bottom surface of the second sub-trench 105, the side surface of the first mask 107, and the side surface and surface of the second mask 170 to form a first insulating layer 109, wherein the first insulating layer 109 does not completely fill the second sub-trench 105. Then, the areas within the second sub-trench 105 not filled by the first insulating layer 109 are filled with metallic material to form a back gate structure extending along the second direction. At this point, the first insulating layer 109 surrounds the back gate structure.

[0056] Here, the back gate structure can be brought out through an additional metal line. By applying a bias voltage to the back gate structure using this metal line, the threshold voltage of the transistor structure can be adjusted to suppress leakage current and enhance the gate control capability of the transistor.

[0057] After the first insulating layer 109 is formed, the insulating material on the surface of the second mask 170 can be removed using a CMP process so that the surface of the first insulating layer 109 is flush with the surface of the second mask 170.

[0058] In some embodiments, after the first insulating layer 109 is formed, the second mask 170 and the sacrificial layer 108 located in the first sub-trench 104 are removed using an etching process. At this time, the semiconductor pillars 106 are exposed along the first direction near the sidewalls of the first sub-trench 104, such as... Figures 17 to 19 As shown, where, Figure 19 for Figure 17 and Figure 18 A schematic diagram of the XY cross-sectional structure at point AA.

[0059] Here, the second mask 170 and the sacrificial layer 108 located in the first sub-trench 104 can be removed simultaneously using a one-step etching process, or the second mask 170 and the sacrificial layer 108 located in the first sub-trench 104 can be removed separately using a two-step etching process.

[0060] Step S103: Form a second oxide layer 110 covering the sidewall of the first sub-groove 104.

[0061] Specifically, using a deposition process, a second oxide layer 110 is formed on the sidewalls of the first sub-trench 104, the top surface and exposed sides of the first insulating layer 109, and the surface and sides of the first mask 107, such as... Figures 20 to 22 As shown, where, Figure 22 for Figure 20 and Figure 21 A schematic diagram of the XY cross-sectional structure at AA. Here, the second oxide layer 110 is used to define the boundary of the subsequently formed gate layer on one side in the first direction.

[0062] After the second oxide layer 110 is formed, a second insulating layer 111 is formed on the surface of the second oxide layer using a deposition process. The second oxide layer 110 and the second insulating layer 111 fill the first sub-trench 104. Here, the second insulating layer 111 is used to achieve isolation between the semiconductor pillars 106 in the first direction.

[0063] After forming the second insulating layer 111, a portion of the second oxide layer 110, a portion of the second insulating layer 111, a portion of the first insulating layer 109, and the first mask 107 are removed using a CMP process, so that the surfaces of the remaining second oxide layer 110, second insulating layer 111, and first insulating layer 109 are flush with the first surface 106a of the first end of the semiconductor pillar 106 located away from the substrate 101 in a third direction. At this time, the first surface 106a of the semiconductor pillar 106 is exposed, as shown below. Figures 23 to 25 As shown, where, Figure 25 for Figure 23 andFigure 24 A schematic diagram of the XY cross-sectional structure at point AA.

[0064] In some embodiments, the deposition process for forming the second oxide layer 110 includes an ALD process. The material of the second oxide layer 110 includes silicon dioxide. The material of the second insulating layer 111 includes silicon nitride.

[0065] Step S104: Remove part of the first oxide layer 103 and part of the second oxide layer 110 to expose two sidewalls of the semiconductor pillar 106 opposite each other in the second direction and the sidewall of the semiconductor pillar 106 close to the first sub-trench 104 in the first direction within a preset height range in the third direction perpendicular to the substrate 101.

[0066] Here, the preset height range in the third direction specifically refers to the position range of the transistor's channel region in the third direction. Since the semiconductor pillar 106 is composed of a source region, a channel region, and a drain region arranged sequentially along the third direction, the preset height range in the third direction can be understood as the middle section of the semiconductor pillar 106 along the third direction. In this embodiment, the preset height range corresponding to the transistor's channel region can be adjusted according to actual needs, and this embodiment does not limit this adjustment.

[0067] In some embodiments, step S104 includes: Step S401: Remove a portion of the first oxide layer 103 and the second oxide layer 110 to form a second trench 112 extending along a second direction; the second trench 112 includes a plurality of first portions 113 located between adjacent semiconductor pillars 106 in the second direction, and a second portion 114 located within the first sub-trench 104 communicating with the plurality of first portions 113, such as... Figures 26 to 29 As shown, where, Figure 28 for Figure 26 and Figure 27 Schematic diagram of the XY cross-section structure at point AA Figure 29 for Figure 26 and Figure 27 A schematic diagram of the XY cross-sectional structure at point BB.

[0068] Here, the etching depth of the second trench 112 is less than the height of the semiconductor pillar 106. After the second trench 112 is formed, portions of the two opposing sidewalls of the semiconductor pillar 106 along the second direction, and the portion of the sidewall of the semiconductor pillar 106 along the first direction near the first sub-trench 104, are exposed. Specifically, the first portion 113 of the second trench 112 exposes the two opposing sidewalls of the semiconductor pillar 106 along the second direction, and the second portion 114 of the second trench 112 exposes the sidewall of the semiconductor pillar 106 along the first direction near the first sub-trench 104, as shown below. Figure 28 As shown.

[0069] Step S402: A first barrier layer 115 is formed on the sidewall of the second trench 112, and the first barrier layer 115 fills the second portion 114 of the second trench, as shown. Figures 30 to 33 As shown, where, Figure 32 for Figure 30 and Figure 31 Schematic diagram of the XY cross-section structure at point AA Figure 33 for Figure 30 and Figure 31 A schematic diagram of the XY cross-sectional structure at point BB.

[0070] At this time, the semiconductor pillar 106 exposed on the sidewall of the second trench 112 is covered by the first barrier layer 115.

[0071] In some embodiments, the first barrier layer 115 may be formed using an ALD process.

[0072] It should be noted that the first barrier layer 115 does not fill the first portion 113 of the second trench 112, so that the first oxide layer 103 and the second oxide layer 110 located below the second trench 112 can be etched through the first portion 113 of the second trench 112.

[0073] Step S403: Based on the second trench 112, remove a portion of the first oxide layer 103 and a portion of the second oxide layer 110 located between the second trench 112 and the substrate 101 to form a third trench 116 extending along the second direction; the third trench 116 includes a plurality of first portions 117 located between adjacent semiconductor pillars 106 in the second direction, and a second portion 118 located within the first sub-trench 104 connecting the plurality of first portions 117, such as... Figures 34 to 37 As shown, where, Figure 36 for Figure 34 and Figure 35 Schematic diagram of the XY cross-section structure at point AA Figure 37 for Figure 34 and Figure 35 A schematic diagram of the XY cross-sectional structure at point BB.

[0074] Here, the sum of the etching depths of the second trench 112 and the third trench 116 is less than the height of the semiconductor pillar 106. The third trench 116 can define the position of the channel region of the transistor in the third direction. Specifically, in the third direction, the top height of the third trench 116 determines the top height of the channel region, while the bottom height of the third trench 116 determines the bottom height of the channel region.

[0075] After the third trench 116 is formed, within a preset height range in the third direction, the two opposing sidewalls of the semiconductor pillar 106 along the second direction, and the sidewall of the semiconductor pillar 106 near the first sub-trench 104 along the first direction, are exposed. Specifically, the first portion 117 of the third trench 116 exposes the two opposing sidewalls of the semiconductor pillar 106 along the second direction, and the second portion 118 of the third trench 116 exposes the sidewall of the semiconductor pillar 106 near the first sub-trench 104 along the first direction. Simultaneously, the first portion 117 of the third trench 116 exposes a portion of the sidewall of the first insulating layer 109, and the second portion 118 of the third trench 116 exposes a portion of the sidewall of the second insulating layer 111.

[0076] Step S105: Form a stacked gate oxide layer 119 and gate layer 120 at least on the exposed sidewalls of the semiconductor pillar 106.

[0077] In some embodiments, step S105 includes: Step S501: At least the exposed sidewalls of the semiconductor pillar 106 are oxidized in situ to form the gate oxide layer 119; Step S502: Form a gate layer 120 covering the gate oxide layer 119.

[0078] In some embodiments, step S501 includes: performing in-situ oxidation only on the exposed sidewalls of the semiconductor pillar 106 to form a gate oxide layer 119 in the region inside the semiconductor pillar 106 that contacts the sidewalls of the semiconductor pillar 106. Thus, after the subsequent formation of the gate layer 120, the gate oxide layer 119 is located only between the semiconductor pillar 106 and the gate layer 120, as... Figures 38 to 41 As shown, where, Figure 40 for Figure 38 and Figure 39 Schematic diagram of the XY cross-section structure at point AA Figure 41 for Figure 38 and Figure 39 A schematic diagram of the XY cross-sectional structure at point BB.

[0079] In some embodiments, step S501 includes in-situ oxidation of the entire sidewall of the third trench 116 to form a gate oxide layer 119 on the sidewall of the third trench 116. Specifically, the sidewalls exposed by the semiconductor pillar 106, the sidewalls exposed by the first insulating layer 109, and the sidewalls exposed by the second insulating layer 111 are oxidized in situ to form the gate oxide layer 119. Thus, after the subsequent formation of the gate layer 120, the gate oxide layer 119 is partially located between the semiconductor pillar 106 and the gate layer 120, partially located between the first insulating layer 109 and the gate layer 120, and partially located between the second insulating layer 111 and the gate layer 120.

[0080] It should be noted that, since the gate oxide layer 119 is formed inside the semiconductor pillar 106 through in-situ oxidation, the dimensions of the channel region of the transistor structure along both the first and second directions are reduced, making the dimensions of the channel region along the first and second directions smaller than the dimensions of the first and second active regions in the first and second directions. The unoxidized semiconductor pillar 106 has a dumbbell shape with larger dimensions at both ends and a smaller dimension in the middle along the third direction. In this way, the larger dimensions of the first and second active regions are beneficial to the on-state current Ion, while the smaller dimensions of the channel region are beneficial to the formation of a fully depleted channel, reducing leakage current, and leaving a larger spacing between adjacent word lines (WL), thus reducing coupling between adjacent word lines.

[0081] In some embodiments, step S502 includes: filling the third trench 116 with conductive material through the second trench 112 to fill both the second trench 112 and the third trench 116; and etching back the conductive material through the second trench 112 so that the surface of the conductive material located in the first portion 117 of the third trench 116 and not covered by the first barrier layer 115 is lowered to a certain height to form the gate layer 120, such as... Figures 42 to 45 As shown, where, Figure 44 for Figure 42 and Figure 43 Schematic diagram of the XY cross-section structure at point AA Figure 45 for Figure 42 and Figure 43 A schematic diagram of the XY cross-sectional structure at BB. At this point, the gate layer 120 covers the two opposite sidewalls of the semiconductor pillar 106 along the second direction, as well as the sidewall of the semiconductor pillar 106 near the first sub-trench 104. The semiconductor pillar 106, the gate oxide layer 119, and the gate layer 120 together constitute a transistor structure, and multiple transistor structures are arranged in an array along a direction parallel to the surface of the substrate 101.

[0082] It should be noted that after filling the third trench 116 with conductive material, some of the conductive material lies below the first barrier layer 115. Due to the obstruction of the first barrier layer 115, the conductive material located below the first barrier layer 115 cannot be etched away. Therefore, in the etch-back process, only the portion of conductive material not covered by the first barrier layer 115 can be etched.

[0083] In other words, the dimensions of the portion of the gate layer 120 formed by the conductive material located below the first barrier layer 115 in the third direction are fixed after the conductive material is filled. The dimensions of the portion of the gate layer 120 formed by the conductive material not covered by the first barrier layer 115 in the third direction can only be determined after the etch-back process. Therefore, the dimensions of the gate layer 120 covered by the first barrier layer 115 in the third direction can be the same as the dimensions of the gate layer 120 not covered by the first barrier layer 115 in the third direction. Alternatively, the dimensions of the gate layer 120 covered by the first barrier layer 115 in the third direction can be different from the dimensions of the gate layer 120 not covered by the first barrier layer 115 in the third direction. Specifically, when the two dimensions are different, the dimension of the gate layer 120 covered by the first barrier layer 115 along the third direction can be larger than the dimension of the gate layer 120 not covered by the first barrier layer 115 along the third direction, or the dimension of the gate layer 120 covered by the first barrier layer 115 along the third direction can be smaller than the dimension of the gate layer 120 not covered by the first barrier layer 115 along the third direction.

[0084] In this embodiment of the disclosure, the gate layer 120 forms a word line extending along a second direction. In some examples, the material of the gate layer 120 includes a conductive material, such as titanium nitride (TiN).

[0085] Here, it should be noted that in the word line formation process, the metal material used to form the word lines can be simultaneously formed in the active region 121 of the substrate 101 and the contact region 122 outside the active region 121. Specifically, a portion of the metal material in the active region 121 can form multiple word lines extending along the second direction and spaced apart along the first direction, while a portion of the metal material in the contact region 122 connects the two word lines located on both sides of the second insulating layer 111. Therefore, after filling with metal material, the portion of metal material located in the contact region needs to be etched away to separate the multiple word lines. In some embodiments, a staggered etching method can be used to remove a portion of the metal material to separate the two word lines located on both sides of the second insulating layer, such as... Figure 46 As shown. Here, each character line can be led out from the back side to the outside via a first lead 123 located in the contact area 122. In some embodiments, the first lead 123 of the character line is located on the side of the metal material removal area away from the character line along the second direction.

[0086] The transistor structure provided in this embodiment is actually a FinFET structure where the gate surrounds the channel on three sides and the gate is mirror-symmetrical in the first direction. While maintaining a constant distance between the center lines of adjacent word lines, channel size, gate oxide thickness, and gate layer thickness, compared to a Gate-All-Around Transistor (GAA), the transistor structure provided in this embodiment can effectively increase the distance between adjacent word lines and reduce parasitic capacitance between adjacent word lines. Furthermore, compared to a mirror-symmetrical single-sided gate structure transistor, the transistor structure provided in this embodiment can effectively increase the gate area.

[0087] In some embodiments, after step S105, the method for manufacturing the semiconductor structure further includes: filling the second trench 112 with an insulating material, such as silicon nitride, using a deposition process and a CMP process to form a third insulating layer 124 within the second trench 112. The third insulating layer 124 fills the third trench 116, and the surface of the third insulating layer 124 is flush with the surface of the semiconductor pillar 106, such as... Figures 47 to 49 As shown, where, Figure 49 for Figure 47 and Figure 48 A schematic diagram of the XY cross-sectional structure at point AA.

[0088] In some embodiments, after forming the third insulating layer 124, a portion of the first insulating layer 109, a portion of the second insulating layer 111, a portion of the third insulating layer 124, and a portion of the first barrier layer 115 of the silicon nitride material located between adjacent semiconductor pillars 106 are etched away to expose the end of each of the arrayed semiconductor pillars 106 away from the substrate 101. Specifically, a portion of the side surface of the semiconductor pillar 106 located at this end is exposed, such as... Figures 50 to 52 As shown, where, Figure 52 for Figure 50 and Figure 51 A schematic diagram of the XY cross-sectional structure at point AA.

[0089] In some embodiments, after step S105, the method for manufacturing the semiconductor structure further includes: Step S106: A plurality of contact structures 125 are formed at the first end of the plurality of semiconductor pillars 106 away from the substrate 101 along a third direction, and each contact structure 125 is connected to a semiconductor pillar 106 in a one-to-one correspondence; the contact structure 125 covers at least a portion of the surface of the semiconductor pillar 106 at the first end and at least a portion of the side surface of the semiconductor pillar; wherein, the plurality of contact structures 125 are arranged in an array along a second direction and a fourth direction; the fourth direction is perpendicular to the third direction and intersects the first direction and the second direction respectively.

[0090] Specifically, a first contact layer 126 is formed at the exposed end of the semiconductor pillar 106, and the surface of the first contact layer 126 is planar. At this time, the first contact layer 126 simultaneously covers the surface of the semiconductor pillar 106 away from the substrate 101 and at least a portion of the side surface of the semiconductor pillar 106. Subsequently, a second contact layer 127 and a third contact layer 128 are sequentially formed on the surface of the first contact layer 126. The first contact layer 126, the second contact layer 127, and the third contact layer 128 together form a contact layer for connecting the semiconductor pillar 106 and the capacitor structure, such as... Figures 53 to 55 As shown, where, Figure 55 for Figure 53 and Figure 54 A schematic diagram of the XY cross-sectional structure at point AA.

[0091] The first contact layer 126 is made of materials such as polycrystalline silicon and silicon-germanium, and is used to form an ohmic contact with the semiconductor pillar and provide support. The second contact layer 127 is made of metal silicides, such as titanium silicon compound (TiSiX), and is used to reduce contact resistance. The third contact layer 128 is made of materials such as titanium nitride (TiN) and tungsten (W), and is used to achieve good electrical connection of the semiconductor pillar-to-capacitor structure.

[0092] After the contact layer is formed, it is etched along a third direction to form a plurality of contact structures 125 arranged in an array along the second and fourth directions. Each contact structure 125 is correspondingly connected to a semiconductor pillar 106, and each contact structure 125 covers at least a portion of the surface (i.e., the first surface) of its corresponding semiconductor pillar 106, and at least a portion of its side surface, such as... Figures 56 to 58 As shown, where, Figure 58 for Figure 56 and Figure 57 A schematic diagram of the XY cross-sectional structure at point AA, with the fourth direction being... Figure 58 The direction indicated by the dashed arrow.

[0093] It should be noted that since the contact structure 125 covers both the surface and the side of the semiconductor pillar 106, there is a large contact area between the contact structure 125 and the semiconductor pillar 106, which effectively reduces the resistance and is beneficial to improving the electrical performance of the device.

[0094] In some embodiments, the method of manufacturing a semiconductor structure further includes: while forming a contact structure 125, removing a portion of the semiconductor pillar 106 not covered by the contact structure 125, so that the contact structure 125 covers the entire surface of the semiconductor pillar 106 at the first end.

[0095] like Figures 56 to 58As shown, multiple contact structures 125 are arranged in an array along the second and fourth directions, and multiple semiconductor pillars 106 are arranged in an array along the first and second directions. The fourth direction is perpendicular to the third direction and intersects the first and second directions respectively. Therefore, each contact structure 125 and its corresponding semiconductor pillar are actually misaligned. That is, the geometric centers of the projections of the contact structure 125 and its corresponding semiconductor pillar 106 onto the substrate 101 are offset, so that part of the surface of the semiconductor pillar 106 may not be covered by the contact structure 125. In this case, the portion of the semiconductor pillar not covered by the contact structure 125 can be removed while forming the contact structure 125 to increase the distance between adjacent semiconductor pillars 106 and contact structures 125 in the second direction, thereby reducing the risk of short circuit.

[0096] In other embodiments, while forming the contact structure 125, the portion of the semiconductor pillar 106 not covered by the contact structure 125 is not removed, so that the contact structure 125 covers the portion of the surface of the semiconductor pillar 106 located at the first end, such as... Figure 59 As shown.

[0097] In some embodiments, after the contact structure 125 is formed, insulating material can be filled between adjacent contact structures 125 using deposition and CMP processes to achieve isolation between adjacent contact structures 125, such as... Figures 60 to 62 As shown, where, Figure 62 for Figure 60 and Figure 61 A schematic diagram of the XY cross-sectional structure at point AA.

[0098] In some embodiments, the method for manufacturing a semiconductor structure further includes: Step S107: A plurality of capacitor structures 129 are formed on the side of the contact structure 125 away from the semiconductor pillar 106, corresponding to and connected to each contact structure 125; the plurality of capacitor structures 129 are arranged in an array along the second direction and the fifth direction; the fifth direction is perpendicular to the third direction and intersects the first direction and the second direction respectively, as shown below. Figures 63 to 65 As shown, where, Figure 65 for Figure 63 and Figure 64 A schematic diagram of the XY cross-sectional structure at point C, with the fifth direction being... Figure 65 The direction indicated by the dashed arrow.

[0099] Specifically, using deposition and etching processes, the lower electrode 130, interlayer dielectric layer 131, and upper electrode 132 of capacitor structures 129 are sequentially formed on the surface of each contact structure 125 to form multiple capacitor structures 129 arranged in an array along the second and fifth directions. Each capacitor structure 129 is correspondingly connected to a contact structure 125. At this time, any transistor structure and its corresponding capacitor structure 129 together form a memory cell. Multiple memory cells are arranged in an array along a direction parallel to the substrate surface, that is, a memory array is formed.

[0100] Here, the material of the lower electrode 130 includes metal compounds such as heavily doped polycrystalline silicon and titanium nitride (TiN), the material of the upper electrode 132 includes (TiN), and the material of the interlayer dielectric layer 131 includes a high dielectric constant material, such as hafnium oxide (HfO2).

[0101] In this embodiment of the disclosure, the capacitor structure 129 includes, but is not limited to, cup-type capacitors, cylinder-type capacitors, and pillar-type capacitors. Figures 63 to 65 The capacitor structure 129 shown is a cylindrical capacitor, and the lower electrode 130 of the cylindrical capacitor is cylindrical.

[0102] In some embodiments, the fourth direction is the same as the fifth direction. In other embodiments, the fourth direction is different from the fifth direction.

[0103] In this embodiment of the disclosure, by forming multiple capacitor structures 129 arranged in an array along the second and fifth directions, the area utilization rate of the capacitors is effectively improved, thereby obtaining a larger capacitance value without increasing the chip area.

[0104] In some embodiments, after step S107, insulating material can be filled between adjacent capacitor structures 129 to achieve isolation between adjacent capacitor structures 129.

[0105] In some embodiments, after forming the capacitor structure 129, the method for manufacturing the semiconductor structure further includes: Step S108: Remove substrate 101 to expose the surface of fin structure 102 along a third direction near the second end of substrate 101.

[0106] like Figures 66 to 68 As shown, substrate 101 is removed using a backside CMP process. At this time, the second surface 106b of the second end of the fin structure 102 that contacts the substrate 101 along a third direction, and the side of the first oxide layer 103 located between adjacent fin structures 102 that contacts the substrate 101 are exposed.

[0107] Step S109: A bit line 134 extending along the first direction is formed on the surface of the second end of the fin structure 102 (i.e., the second surface 106b), as shown. Figures 69 to 71 As shown, where, Figure 71 for Figure 69 and Figure 70 A schematic diagram of the XY cross-sectional structure at DD.

[0108] In some embodiments, step S109 includes: etching the second surface of the fin structure 102 to form a plurality of bit line trenches located between adjacent first oxide layers 103 in the second direction, extending along the first direction and spaced apart along the second direction; filling the bit line trenches with metal material to form a plurality of bit lines 134 extending along the first direction and spaced apart along the second direction. At this time, the plurality of semiconductor pillars 106 spaced apart along the first direction in any fin structure 102 share a single bit line 134.

[0109] In some embodiments, each bit line 134 can be led out from the back side via a second lead 135, and the second leads 135 corresponding to multiple bit lines are arranged in an alternating manner. Specifically, the second lead 135 of bit line A is located at the first end of bit line A along the first direction, and the second lead 135 of bit line B, which is adjacent to bit line A, is located at the second end of bit line B along the first direction. Here, A can represent an odd number, and B can represent an even number, such as... Figure 74 As shown.

[0110] Step S110: Form a shielding structure 136 that is at least partially located between adjacent bit lines, such as Figures 72 to 74 As shown, where, Figure 74 for Figure 72 and Figure 73 A schematic diagram of the XY cross-sectional structure at DD.

[0111] In some examples, step S110 includes: depositing an insulating material on the bit line 134 and the first oxide layer 103 on the side away from the capacitor structure 129 along a third direction to form a spacer layer; etching a portion of the spacer layer and a portion of the first oxide layer 103 along the third direction to form a shielding trench extending in a first direction between any adjacent bit lines 134; and depositing an insulating material on the surface of the spacer layer and within the shielding trench to form a shielding structure 136. Here, the shielding structure 136 is used to reduce the parasitic capacitance between adjacent bit lines.

[0112] In some embodiments, the material of the shielding structure 136 includes a low dielectric constant material, such as silicon dioxide.

[0113] Based on the same inventive concept, this disclosure also provides a semiconductor structure, such as... Figures 75 to 76As shown, the semiconductor structure includes: a plurality of isolation structures extending along a second direction and spaced apart along a first direction; wherein the plurality of isolation structures include a plurality of first sub-isolation structures and a plurality of second sub-isolation structures alternately arranged in the first direction; a plurality of transistor structures spaced apart in the second direction between adjacent first and second sub-isolation structures in the first direction; the transistor structures include a semiconductor pillar 106 in contact with the second sub-isolation structure and extending in a third direction, and a gate layer 120 connected to the semiconductor pillar 106 and extending in the second direction; wherein, within a predetermined height range in the third direction, the gate layer 120 surrounds two opposing sidewalls of the semiconductor pillar 106 in the second direction, and the sidewall of the semiconductor pillar 106 away from the second sub-isolation structure in the first direction; the first direction, the second direction, and the third direction are perpendicular to each other.

[0114] Here, the first isolation structure can be understood based on the second insulating layer 111 in the above embodiment. The first isolation structure is located on the two gate layers 120 arranged back-to-back (e.g., Figure 76 The second isolation structure can be understood based on the first insulating layer 109 in the above embodiment. The second isolation structure is located between the two gate layers 120 arranged face-to-face (as shown in the dashed box on the right). Figure 76 Between (as shown in the dotted line box on the left).

[0115] In some embodiments, the semiconductor pillar 106 includes a first active region, a channel region, and a second active region arranged sequentially along a third direction; wherein, the gate layer 120 surrounds the sidewall of the channel region of the semiconductor pillar; the dimension of the channel region along the second direction is smaller than the dimension of either the first active region or the second active region in the second direction.

[0116] Here, the first active region and the second active region correspond to one of the source region and the drain region of the transistor structure, respectively.

[0117] In some embodiments, the transistor structure further includes a gate oxide layer 119 located at least partially between the semiconductor pillar 106 and the gate layer 120.

[0118] Here, at least in part, it means that the gate oxide layer 119 may be located only between the semiconductor pillar 106 and the gate layer 120; or, the gate oxide layer 119 may be partially located between the semiconductor pillar 106 and the gate layer 120, partially located between the first isolation structure and the gate layer 120, and partially located between the second isolation structure and the gate layer 120, such as... Figure 77 As shown.

[0119] In some embodiments, the second sub-isolation structure includes: a first insulating layer 109; or, a back gate structure 137 and a first insulating layer 109 surrounding the back gate structure 137, such as Figure 79 As shown.

[0120] Here, an air gap 138 extending in the second direction can be formed within the first insulating layer 109, such as... Figure 78 As shown. The height of the air gap 138 in the third direction can be the same as or different from the height of the gate layer 120 in the third direction.

[0121] The material of the back gate structure 137 may be the same as or different from the material of the gate layer 120. The height of the back gate structure 137 in the third direction may be the same as or different from the height of the gate layer 120 in the third direction.

[0122] In some embodiments, the semiconductor structure further includes: a plurality of contact structures 125 located at the first end of the plurality of semiconductor pillars in a third-direction orientation, each contact structure 125 being connected to a semiconductor pillar 106 in a one-to-one correspondence; the contact structure 125 covering at least a portion of the surface of the semiconductor pillar 106 at the first end and at least a portion of the side surface of the semiconductor pillar 106.

[0123] In some embodiments, the semiconductor structure further includes: a plurality of capacitor structures 129 located on the side of the contact structure 125 away from the semiconductor pillars and connected to each contact structure 125; wherein the plurality of semiconductor pillars 106 are arranged in an array in a first direction and a second direction; the plurality of contact structures 125 are arranged in an array along a second direction and a fourth direction; the plurality of capacitor structures 129 are arranged in an array along a second direction and a fifth direction; the fourth direction is perpendicular to the third direction and intersects the first direction and the second direction respectively; the fifth direction is perpendicular to the third direction and intersects the first direction and the second direction respectively.

[0124] In some embodiments, the semiconductor structure further includes: a bit line 134 located at a second end of a semiconductor pillar along a third direction, the bit line 134 extending along a first direction and connected to a plurality of semiconductor pillars 106; and a shielding structure 136 located at least partially between adjacent bit lines 134.

[0125] In some embodiments, the semiconductor structure includes a memory array layer 200 having the aforementioned memory array, a bonding layer 300 and a logic circuit layer 400 located on any third-upward side of the memory array layer 200, wherein the logic circuit layer 400 includes CMOS devices, such as... Figure 80 As shown. Among them, the logic circuit layer 400 serves as the control core. After receiving the processor's instructions, its address decoder precisely activates the transistors in specific rows (word lines) and columns (bit lines) in the memory array through the vertical interconnection of the bonding layer 300. Subsequently, the sensitive amplifier amplifies, latches, and writes back the weak charge signal on the capacitor, thereby realizing the complete electronic control process of reading, refreshing, and writing each memory cell.

[0126] The semiconductor structure disclosed herein is at least a portion of the structure that will be used in subsequent processes to form the final device structure. Here, the final device may be a memory, such as DRAM, or other memory chips or processing chips containing DRAM memory cells.

[0127] The above description is only a preferred embodiment of this disclosure and does not limit the patent scope of this disclosure. All equivalent structural transformations made under the concept of this disclosure using the contents of this specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, The method includes: A plurality of fin structures are formed on a substrate, extending along a first direction parallel to the substrate and spaced apart along a second direction parallel to the substrate, and a first oxide layer is filled between adjacent fin structures; The fin structure and the first oxide layer are etched to form a plurality of first trenches extending along the second direction and spaced apart along the first direction; wherein, the plurality of first trenches include a plurality of first sub-trenches and a plurality of second sub-trenches arranged alternately along the first direction, and the remaining fin structure located between adjacent first trenches forms a plurality of semiconductor pillars arranged spaced apart along the first direction. A second oxide layer is formed covering the sidewalls of the first sub-trench; Remove a portion of the first oxide layer and a portion of the second oxide layer to expose the two opposing sidewalls of the semiconductor pillar along the second direction and the sidewall of the semiconductor pillar near the first sub-trench along the first direction within a predetermined height range in a third direction perpendicular to the substrate. At least a stacked gate oxide layer and gate layer are formed on the exposed sidewalls of the semiconductor pillar.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The formation of a stacked gate oxide layer and gate layer at least on the exposed sidewalls of the semiconductor pillar includes: At least the exposed sidewalls of the semiconductor pillar are oxidized in situ to form a gate oxide layer; A gate layer is formed covering the gate oxide layer.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The method further includes: The second sub-groove is filled with insulating material to form a first insulating layer; Alternatively, a first insulating layer and a back gate structure are sequentially formed within the second sub-groove; the first insulating layer surrounds the back gate structure.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The removal of a portion of the first oxide layer and a portion of the second oxide layer to expose, within a predetermined height range in the third direction, two opposing sidewalls of the semiconductor pillar along the second direction, and the sidewall of the semiconductor pillar near the first sub-trench along the first direction, includes: A portion of the first oxide layer and a portion of the second oxide layer are removed to form a second trench extending along the second direction; the second trench includes a plurality of first portions located between adjacent semiconductor pillars in the second direction, and a second portion located within the first trench connecting the plurality of first portions; A first barrier layer is formed on the sidewall of the second trench, and the first barrier layer fills a second portion of the second trench; Based on the second trench, a portion of the first oxide layer and a portion of the second oxide layer located between the second trench and the substrate are removed to form a third trench extending along the second direction; the third trench includes a plurality of first portions located between adjacent semiconductor pillars in the second direction, and a second portion located within the first trench connecting the plurality of first portions; wherein, within a predetermined height range in the third direction, the first portions of the third trench expose two opposite sidewalls of the semiconductor pillars along the second direction, and the second portions of the third trench expose the sidewalls of the semiconductor pillars near the first trench along the first direction.

5. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The method further includes: Multiple contact structures are formed at a first end of the plurality of semiconductor pillars in a third direction away from the substrate, and each contact structure is connected to one of the semiconductor pillars in a one-to-one correspondence; the contact structures cover at least a portion of the surface of the semiconductor pillar at the first end and at least a portion of the side surface of the semiconductor pillar; The multiple contact structures are arranged in an array along the second and fourth directions; the fourth direction is perpendicular to the third direction and intersects the first and second directions respectively.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The method further includes: While forming the contact structure, the portion of the semiconductor pillar not covered by the contact structure is removed, so that the contact structure covers the entire surface of the semiconductor pillar located at the first end.

7. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The method further includes: A plurality of capacitor structures are formed on the side of the contact structure away from the semiconductor pillar, corresponding to and connected to each of the contact structures; the plurality of capacitor structures are arranged in an array along the second direction and the fifth direction; the fifth direction is perpendicular to the third direction and intersects the first direction and the second direction respectively.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The method further includes: Remove the substrate to expose the surface of the fin structure along the third direction near the second end of the substrate; A bit line extending along the first direction is formed on the surface of the second end of the fin structure; A shielding structure is formed that is at least partially located between adjacent bit lines.

9. A semiconductor structure, characterized in that, include: A plurality of isolation structures extending along a second direction and spaced apart along a first direction; wherein the plurality of isolation structures include a plurality of first sub-isolation structures and a plurality of second sub-isolation structures alternately arranged in the first direction; A plurality of transistor structures are arranged at intervals along the second direction between adjacent first sub-isolation structures and second sub-isolation structures in the first direction; each transistor structure includes a semiconductor pillar that contacts the second sub-isolation structure and extends along the third direction, and a gate layer that is connected to the semiconductor pillar and extends along the second direction. Within the predetermined height range of the third direction, the gate layer surrounds the two opposite sidewalls of the semiconductor pillar along the second direction, and the sidewall of the semiconductor pillar away from the second sub-isolation structure along the first direction; the first direction, the second direction, and the third direction are perpendicular to each other.

10. The semiconductor structure according to claim 9, characterized in that, The semiconductor pillar includes a first active region, a channel region, and a second active region arranged sequentially along the third direction; wherein the gate layer surrounds the semiconductor pillar and is located on the sidewall of the channel region; the dimension of the channel region along the second direction is smaller than the dimension of either the first active region or the second active region in the second direction.

11. The semiconductor structure according to claim 9, characterized in that, The transistor structure also includes: A gate oxide layer that is at least partially located between the semiconductor pillar and the gate layer.

12. The semiconductor structure according to claim 9, characterized in that, The second sub-isolation structure includes: First insulating layer; or, The back grid structure and the first insulating layer surrounding the back grid structure.

13. The semiconductor structure according to claim 9, characterized in that, Also includes: Multiple contact structures are located at the first end of the plurality of semiconductor pillars in the third direction, each contact structure being connected to one semiconductor pillar in a one-to-one correspondence; the contact structures cover at least a portion of the surface of the semiconductor pillar at the first end and at least a portion of the side surface of the semiconductor pillar.

14. The semiconductor structure according to claim 13, characterized in that, Also includes: A plurality of capacitor structures are located on the side of the contact structure away from the semiconductor pillar and are connected to each of the contact structures. The plurality of semiconductor pillars are arranged in an array along the first direction and the second direction; the plurality of contact structures are arranged in an array along the second direction and the fourth direction; the plurality of capacitor structures are arranged in an array along the second direction and the fifth direction; the fourth direction is perpendicular to the third direction and intersects the first direction and the second direction respectively. The fifth direction is perpendicular to the third direction and intersects with the first direction and the second direction, respectively.

15. The semiconductor structure according to claim 9, characterized in that, Also includes: A bit line located at the second end of the semiconductor pillar along the third direction, the bit line extending along the first direction and connecting to the plurality of semiconductor pillars; as well as, A shielding structure located at least partially between adjacent bit lines.

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