Novel EEPROM storage unit and preparation method thereof

Abstract

The invention discloses a novel EEPROM (Electrically Erasable Programmable Read-Only Memory) storage unit and a preparation method thereof. The novel EEPROM storage unit is compatible with a logic process, and the withstand voltage of a selection tube junction reaches more According to the invention, the CHISEL programming mechanism is fully utilized to overcome the short channel effect, and the programming efficiency is effectively improved through the unique device structure and process design. The storage tube and the selection tube of the structure are of a single-polycrystal structure and are compatible with a logic process, a mask plate does not need to be additionally arranged, and the process preparation cost is greatly reduced. According to the structure and the preparation method, the development of the EEPROM is greatly promoted, and powerful support is provided for the preparation of the EEPROM. The EEPROM device is low in preparation cost and has a great market application prospect.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, and in particular to a novel EEPROM memory cell and its fabrication method. Background Technology

[0002] EEPROM (Electrically Erasable Programmable Read-Only Memory) is a type of non-volatile memory (NVM) characterized by its ability to retain stored information even after power is lost. EEPROM offers flexible operation, supporting byte-by-byte programming. Traditional EEPROM cell structures can be categorized into charge-trapping and floating-gate types. Most floating-gate structures consist of two polysilicon layers separated by a dielectric layer. Under an applied electric field, electrons can be injected into the floating gate (channel in the off state, called the programming state, representing logic "0") or flow out of the floating gate (channel in the on state, called the erasing state, representing logic "1"). The threshold voltage of the memory transistor differs between these two different storage states.

[0003] A typical EEPROM memory cell consists of a select transistor and a storage transistor. Because each memory cell has a select transistor, the cell size is relatively large, the storage density is relatively low, and the manufacturing cost is relatively high. This also limits the application of EEPROM to most scenarios with low storage capacity requirements.

[0004] With the evolution of EEPROM technology and the shrinking of EEPROM cell size, the short-channel effect has become significant and is now one of the main problems affecting the miniaturization of EEPROM memory cells. Therefore, proposing a novel and low-cost EEPROM memory cell structure has become one of the urgent problems to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this invention is to provide a novel EEPROM memory cell and its fabrication method to solve the problems in the background art.

[0006] To solve the above-mentioned technical problems, the present invention provides a novel EEPROM memory cell, comprising: a P-type substrate, an active region, an STI, a P-well doped region, a first P-type doped region, a first N-type doped region, a gate oxide layer, a polysilicon layer, a second P-type doped region, source and drain doped regions, contact holes, and a metal layer. STI is formed by etching a P-type substrate; The first P-type doped region is located above and outside the P-well doped region. The first N-type doped region and the second P-type doped region are both located in the P-well doped region. The second P-type doped region is located below the first P-type doped region, and the two partially overlap. The source and drain doped regions are located below the second P-type doped region. The gate oxide layer and the polysilicon layer are located above the first P-type doped region, and the gate oxide layer and the polysilicon layer are stacked. The contact hole and the metal layer are located above the first P-type doped region, and the contact hole and the metal layer are stacked.

[0007] In one embodiment, the novel EEPROM memory cell is based on a 0.18μm CMOS process. The storage transistor and select transistor of the EEPROM memory cell are of single-polysilicon structure, which is compatible with the logic process and does not require additional mask.

[0008] In one embodiment, the doping concentration of the first P-type doped region determines the threshold voltage of the EEPROM memory cell; as the doping concentration decreases, the threshold voltage of the EEPROM memory cell decreases; the threshold voltage of the memory cell is controlled by adjusting the doping concentration of the first P-type doped region.

[0009] In one embodiment, the first N-type doped region is implanted multiple times to deplete the select transistor and increase the drain junction breakdown voltage of the select transistor. When the EEPROM memory cell is in operation, a voltage is applied to the select transistor, and the gate senses a potential through coupling, thereby realizing the operation of the EEPROM memory cell. The implantation dose and energy of the first N-type doped region determine the characteristics of the select transistor and affect the performance of the EEPROM memory cell.

[0010] In one embodiment, the second P-type doped region is implanted at a high angle using Halo implantation, forming a locally high concentration of doped region at the edge of the drain junction to increase the lateral electric field at the drain junction and ensure high programming efficiency.

[0011] In one embodiment, the drain of the memory transistor is used as the bit line BL terminal, the source is used as the source terminal, and the gate of the select transistor is used as the word line WL terminal. The aforementioned ports and the substrate are led out through contact holes and metal layers.

[0012] The present invention also provides a method for fabricating the above-mentioned novel EEPROM memory cell, comprising the following steps: Step 1: Form the active region and STI on the P-type substrate; Step 2: Implant P-type impurities into the P-type substrate and form a P-well doped region through an annealing process; Step 3: Implant P-type impurities into the P-well doped region to form the first P-type doped region; Step 4: Implant N-type impurities into the P-well doped region to form the first N-type doped region; Step 5: Grow a thick gate oxide layer on the surface of the P-type substrate, remove the thick gate oxide in the low-voltage region, and then grow a thin gate oxide layer through a deposition process to form the high and low voltage regions. Step 6: Deposit a polysilicon layer on the surface of the P-type substrate, and form a polysilicon gate using photolithography and etching processes; Step 7: Implant P-type impurities into the P-well doped region to form a second P-type doped region, which partially overlaps with the first P-type doped region; Step 8: Implant N-type impurities to form source / drain doped regions; Step 9: Deposit dielectric layer. Using photolithography and etching processes, deposit tungsten plugs to form contact holes; Step 10: Form a metal layer using deposition, photolithography, and etching processes.

[0013] In one embodiment, the resistivity of the P-type substrate in step 1 is 8~12 Ω·cm; In step 3, the doping concentration of the P-type impurity is 1×10⁻⁶. 13 cm -2 ; In step 7, the doping concentration of the P-type impurity is 4 × 10⁻⁶. 13 cm -2 .

[0014] This invention provides a novel EEPROM memory cell and its fabrication method. The CHISEL (channel-induced secondary electron) programming mechanism generates electron-hole pairs through two collisions, accelerating the injection of electrons into the floating gate, resulting in high programming efficiency. This invention fully utilizes the CHISEL programming mechanism to overcome the short-channel effect, while effectively improving programming efficiency through unique device structure and process design. On one hand, the process employs multiple implantation to increase the drain junction breakdown voltage of the select transistor to meet the breakdown voltage requirements during programming; on the other hand, high-angle Halo implantation is used to form a locally highly concentrated doped region at the edge of the drain junction, increasing the lateral electric field at the drain junction and ensuring high programming efficiency. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the first step of the manufacturing process of the present invention (left is a cross-sectional view in the X direction, right is a cross-sectional view in the Y direction). Figure 2 This is a schematic diagram of the second step of the manufacturing process of the present invention (left is a cross-sectional view in the X direction, right is a cross-sectional view in the Y direction). Figure 3 This is a schematic diagram of the third step of the manufacturing process of the present invention (left is a cross-sectional view in the X direction, right is a cross-sectional view in the Y direction). Figure 4 This is a schematic diagram of the fourth step of the manufacturing process of the present invention (left is a cross-sectional view in the X direction, right is a cross-sectional view in the Y direction). Figure 5 This is a schematic diagram of the fifth step of the manufacturing process of the present invention (left is a cross-sectional view in the X direction, right is a cross-sectional view in the Y direction). Figure 6This is a schematic diagram of the sixth step of the manufacturing process of the present invention (left is a cross-sectional view in the X direction, right is a cross-sectional view in the Y direction). Figure 7 This is a schematic diagram of the seventh step of the manufacturing process of the present invention (left is a cross-sectional view in the X direction, right is a cross-sectional view in the Y direction). Figure 8 This is a schematic diagram of the eighth step of the manufacturing process of the present invention (left is a cross-sectional view in the X direction, right is a cross-sectional view in the Y direction); Figure 9 This is a schematic diagram of the ninth step of the manufacturing process of the present invention (left is a cross-sectional view in the X direction, right is a cross-sectional view in the Y direction). Figure 10 This is a schematic diagram of the tenth step of the manufacturing method of the present invention (left is a cross-sectional view in the X direction, right is a cross-sectional view in the Y direction). Figure 11 This is a layout and cross-sectional view of a novel EEPROM storage cell provided by the present invention.

[0016] In the figure, 11 is the P-type substrate; 12 is the active region; 23 is the STI; 21 is the P-well doped region; 41 is the first P-type doped region; 42 is the first N-type doped region; 61 is the gate oxide layer; 62 is the polysilicon layer; 31 is the second P-type doped region; 32 is the source / drain doped region; 63 is the contact hole; and 71 is the metal layer. Detailed Implementation

[0017] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a further detailed explanation of a novel EEPROM memory cell and its fabrication method proposed in this invention. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0018] This invention provides a novel EEPROM memory cell, the structural layout and cross-sectional view of which are shown below. Figure 11 As shown, it includes: a P-type substrate 11, an active region 12, an STI 23, a P-well doped region 21, a first P-type doped region 41, a first N-type doped region 42, a gate oxide layer 61, a polysilicon layer 62, a second P-type doped region 31, a source / drain doped region 32, a contact hole 63, and a metal layer 71.

[0019] The method for preparing the EEPROM storage cell in this invention is as follows: like Figure 1 and Figure 2 On the P-type substrate 11, active regions 12 and STI 23 are formed by etching and deposition processes; P-type impurities are implanted into the P-type substrate 11 by ion implantation, and P-well doped regions 21 are formed by annealing. like Figure 3 and Figure 4 Using an ion implantation process, P-type impurities are implanted into the P-well doped region 21 to form a first P-type doped region 41; N-type impurities are implanted to form a first N-type doped region 42; both the first P-type doped region 41 and the first N-type doped region 42 are located above the P-well doped region 21. like Figure 5 and Figure 6 A gate oxide layer 61 and a polysilicon layer 62 are grown on a P-type substrate 11 using a furnace tube and etching process, and then etched. like Figure 7 and Figure 8 Using an ion implantation process, P-type impurities are implanted into the P-well doped region 21 to form a second P-type doped region 31, which is located below the first P-type doped region 41; N-type impurities are implanted to form a source / drain doped region 32, which is located below the second P-type doped region 31. like Figure 9 and Figure 10 The contact hole 63 and the metal layer 71 are formed by deposition and etching processes; the contact hole 63 is located above the first P-type doped region 41, and the metal layer 71 is located above the contact hole 63.

[0020] This invention proposes a novel EEPROM memory cell. To better explain the structure of the EEPROM memory cell, the operating conditions of the cell will be described in detail: Programming: The substrate and source are grounded, and a positive bias of approximately 6V is applied to the bit line BL. Electrons are accelerated towards the drain, colliding to form the first electron-hole pair near the drain. A positive high voltage VPP is applied to the gate of the selector. Through capacitive coupling, the floating gate terminal senses a positive bias equal to VPP-VQ (VQ is the voltage drop of the capacitive coupling, which is related to the gate oxide thickness and polysilicon width). This causes holes to accelerate towards the substrate in the vertical electric field between the gate and the substrate, resulting in a secondary collision and generating electron-hole pairs. When the electrons gain sufficient kinetic energy, they pass through the tunneling oxide layer to reach the floating gate, completing the writing of "0".

[0021] Erase: The bit line BL is left floating, and a negative bias is applied to the substrate. A positive bias VPP' is applied to the gate of the select transistor. Through capacitive coupling, the floating gate terminal senses the positive bias VPP'-VQ'. Electrons in the floating gate pass through the tunneling oxide layer under the action of the vertical electric field of the gate substrate and leave the floating gate, completing the writing of "1".

[0022] Read: Apply a very small positive bias voltage, approximately 1V, to the bit line BL terminal. With the source and substrate grounded, scan the selector gate from 0V. arrive VPP records the current at the bit line terminal. By reading the current of the memory transistor, it is determined whether the channel is turned off or on. When the current of the memory transistor reaches 1uA, the voltage of the select transistor is Vt.

[0023] This invention provides a novel EEPROM memory cell based on 0.18μm CMOS technology, and its layout and cross-sectional view are shown below. Figure 11 As shown in the figure. Testing and evaluation have shown that this structure can achieve a threshold window of approximately 5V, overcoming the challenges of short channels and providing strong support for the fabrication of novel EEPROM memories.

[0024] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A novel EEPROM storage unit, characterized in that, include: P-type substrate, active region, STI, P-well doped region, first P-type doped region, first N-type doped region, gate oxide layer, polysilicon layer, second P-type doped region, source / drain doped region, contact hole, metal layer; STI is formed by etching a P-type substrate; The first P-type doped region is located above and outside the P-well doped region. The first N-type doped region and the second P-type doped region are both located in the P-well doped region. The second P-type doped region is located below the first P-type doped region, and the two partially overlap. The source and drain doped regions are located below the second P-type doped region. The gate oxide layer and the polysilicon layer are located above the first P-type doped region, and the gate oxide layer and the polysilicon layer are stacked. The contact hole and the metal layer are located above the first P-type doped region, and the contact hole and the metal layer are stacked.

2. The novel EEPROM storage unit as described in claim 1, characterized in that, The novel EEPROM memory cell is based on 0.18μm CMOS technology. The storage transistor and select transistor of the EEPROM memory cell have a single-polysilicon structure, which is compatible with logic technology and does not require additional mask.

3. The novel EEPROM storage unit as described in claim 1, characterized in that, The doping concentration of the first P-type doped region determines the threshold voltage of the EEPROM memory cell. As the doping concentration decreases, the threshold voltage of the EEPROM memory cell decreases. The threshold voltage of the memory cell is controlled by adjusting the doping concentration of the first P-type doped region.

4. The novel EEPROM storage unit as described in claim 1, characterized in that, The first N-type doped region is implanted multiple times to deplete the select transistor and increase the drain junction breakdown voltage of the select transistor. When the EEPROM memory cell is in operation, a voltage is applied to the select transistor, and the gate senses a potential through coupling, thereby realizing the operation of the EEPROM memory cell. The implantation dose and energy of the first N-type doped region determine the characteristics of the select transistor and affect the performance of the EEPROM memory cell.

5. The novel EEPROM storage unit as described in claim 1, characterized in that, The second P-type doped region is implanted with a high-angle halo ring, forming a locally high-concentration doped region at the edge of the drain junction to increase the lateral electric field at the drain junction and ensure high programming efficiency.

6. The novel EEPROM storage unit as described in claim 1, characterized in that, The drain of the memory transistor serves as the bit line BL terminal, the source as the source terminal, and the gate of the select transistor serves as the word line WL terminal. All of the above ports and the substrate are led out through contact holes and metal layers.

7. A method for fabricating a novel EEPROM memory cell based on any one of claims 1-6, characterized in that, Includes the following steps: Step 1: Form the active region and STI on the P-type substrate; Step 2: Implant P-type impurities into the P-type substrate and form a P-well doped region through an annealing process; Step 3: Implant P-type impurities into the P-well doped region to form the first P-type doped region; Step 4: Implant N-type impurities into the P-well doped region to form the first N-type doped region; Step 5: Grow a thick gate oxide layer on the surface of the P-type substrate, remove the thick gate oxide in the low-voltage region, and then grow a thin gate oxide layer through a deposition process to form the high and low voltage regions. Step 6: Deposit a polysilicon layer on the surface of the P-type substrate, and form a polysilicon gate using photolithography and etching processes; Step 7: Implant P-type impurities into the P-well doped region to form a second P-type doped region, which partially overlaps with the first P-type doped region; Step 8: Implant N-type impurities to form source / drain doped regions; Step 9: Deposit dielectric layer. Using photolithography and etching processes, deposit tungsten plugs to form contact holes; Step 10: Form a metal layer using deposition, photolithography, and etching processes.

8. The method for fabricating the novel EEPROM memory cell as described in claim 7, characterized in that, The resistivity of the P-type substrate in step 1 is 8~12 Ω·cm; In step 3, the doping concentration of the P-type impurity is 1×10⁻⁶. 13 cm -2 ; In step 7, the doping concentration of the P-type impurity is 4 × 10⁻⁶. 13 cm -2 .

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