Stacked ferroelectric random access memory

By employing a stacked configuration and high-temperature FEOL process to fabricate access transistors in memory cells, the interference problem in compact memory cell arrangement is solved, enabling high-density and high-performance memory design.

CN121751649APending Publication Date: 2026-03-27INTEL CORP
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-08-27
Publication Date
2026-03-27

AI Technical Summary

Technical Problem

In the prior art, when the ferroelectric or antiferroelectric memory cells of embedded memory are arranged in a compact manner, it is difficult to avoid the interference of read/write operations on adjacent memory cells, which affects the performance and density of the memory.

Method used

A stacked configuration is used, with the first FE/AFE capacitor placed above the access transistor and the second FE/AFE capacitor placed below the access transistor. The access transistor is manufactured using a high-temperature FEOL process to improve the density and performance of the memory cells.

Benefits of technology

This achieves a high-density arrangement of storage cells, reduces the footprint, and improves the performance and reliability of the memory while reducing access latency and power consumption.

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Abstract

An integrated circuit die includes an array of memory cells between a first surface and a second surface opposite the first surface. A first memory cell proximate the first surface includes a first capacitor over the first transistor. A second memory cell under the first memory cell includes a second capacitor under the second transistor. The first transistor may be stacked on the second transistor. The capacitor may include a ferroelectric material or an anti-ferroelectric material. The first capacitor is coupled with a first plate line between the first surface and the memory cell array. A via hole couples the second capacitor with the second plate line between the first surface and the memory cell array.
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