Semiconductor device and preparation method thereof, and electronic equipment

Abstract

The invention provides a semiconductor device, a preparation method thereof and electronic equipment. The semiconductor device disclosed by the invention comprises a substrate and a semiconductor layer arranged on the substrate. The semiconductor layer comprises a plurality of first semiconductor structures arranged side by side along a first direction and a plurality of second semiconductor structures arranged side by side along a second direction; the first semiconductor structure comprises P-type semiconductors and N-type semiconductors which are alternately arranged along the second direction; and the second semiconductor structure comprises the P-type semiconductors and the N-type semiconductors which are alternately arranged along the first direction.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor technology, specifically relating to a semiconductor device and its fabrication method, and electronic equipment. Background Technology

[0002] Currently, some glass-based switching devices are fabricated using LTPS (Low Temperature Poly-Silicon) technology. However, due to limitations in LTPS crystallization and other processes, the thickness of a single LTPS layer is typically only around 50 nm, resulting in a relatively high on-state resistance. Furthermore, multilayer LTPS processes carry the risk of film bursting. Parallel connection of multiple switching devices also increases parasitic capacitance. Therefore, it is necessary to reduce the on-state resistance and parasitic capacitance of switching devices. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and to provide a semiconductor device and its preparation method, and an electronic device.

[0004] This disclosure provides a semiconductor device, comprising: a substrate and a semiconductor layer disposed on the substrate;

[0005] The semiconductor layer includes a plurality of first semiconductor structures arranged side by side along a first direction, and a plurality of second semiconductor structures arranged side by side along a second direction;

[0006] The first semiconductor structure includes P-type semiconductors and N-type semiconductors alternately arranged along the second direction;

[0007] The second semiconductor structure includes the P-type semiconductor and the N-type semiconductor alternately arranged along the first direction.

[0008] The semiconductor layer further includes an intrinsic semiconductor disposed between any two adjacent P-type semiconductors and N-type semiconductors.

[0009] This also includes:

[0010] A first interlayer insulating layer is disposed on the side of the semiconductor layer opposite to the substrate.

[0011] The source and drain are disposed on the side of the first interlayer insulating layer away from the substrate. The source and drain are respectively connected to the P-type semiconductor and N-type semiconductor of the first semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer. Alternatively, the source and drain are respectively connected to the P-type semiconductor and N-type semiconductor of the second semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer.

[0012] This also includes:

[0013] A first interlayer insulating layer is disposed on the side of the semiconductor layer opposite to the substrate.

[0014] The source and drain are disposed on the side of the first interlayer insulating layer away from the substrate. The source and drain are respectively connected to the P-type semiconductor and N-type semiconductor of the first semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer. Alternatively, the source and drain are respectively connected to the P-type semiconductor and N-type semiconductor of the second semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer.

[0015] The second interlayer insulating layer is disposed on the side of the source and the drain that is away from the substrate.

[0016] A first connection electrode and a second connection electrode are disposed on the side of the second interlayer insulating layer away from the substrate. The first connection electrode is connected to the source electrode through a third connection via penetrating the second interlayer insulating layer, and the second connection electrode is connected to the drain electrode through a fourth connection via penetrating the second interlayer insulating layer.

[0017] It also includes a storage capacitor, wherein the first plate of the storage capacitor is disposed in the same layer as the source and drain, and the second plate is disposed in the same layer as the first connecting electrode and the second connecting electrode.

[0018] The system also includes an inductor, which comprises a first substructure and a second substructure. The first substructure is disposed on the same layer as the source and drain, and the second substructure is disposed on the same layer as the first connecting electrode and the second connecting electrode. The first substructure and the second substructure are connected by a fifth connecting via penetrating the second interlayer insulating layer.

[0019] The semiconductor device includes a transistor, and the semiconductor device further includes:

[0020] A first interlayer insulating layer is disposed on the side of the semiconductor layer opposite to the substrate.

[0021] A gate is disposed on the side of the first interlayer insulating layer away from the substrate, and the orthographic projection of the gate on the substrate at least partially overlaps with the orthographic projection of the intrinsic semiconductor on the substrate.

[0022] A second interlayer insulating layer is disposed on the side of the gate opposite to the substrate.

[0023] The source and drain are disposed on the side of the second interlayer insulating layer away from the substrate.

[0024] Wherein, the source is connected to the P-type semiconductor of the first semiconductor structure through a sixth connection via penetrating the first and second interlayer insulating layers, and the drain is connected to the N-type semiconductor of the first semiconductor structure through a seventh connection via penetrating the first and second interlayer insulating layers; or, the source is connected to the P-type semiconductor of the second semiconductor structure through a sixth connection via penetrating the first and second interlayer insulating layers, and the drain is connected to the N-type semiconductor of the second semiconductor structure through a seventh connection via penetrating the first and second interlayer insulating layers.

[0025] Wherein, the P-type semiconductor is quadrilateral, and / or, the N-type semiconductor is quadrilateral; or

[0026] The P-type semiconductor is triangular, and / or the N-type semiconductor is triangular.

[0027] Wherein, the P-type semiconductor and the N-type semiconductor in the first semiconductor structure are symmetrical about the midpoint of the line connecting their opposite sides; and / or

[0028] The P-type semiconductor and the N-type semiconductor in the second semiconductor structure are centrally symmetrical about the midpoint of the line connecting the midpoints of their opposite sides.

[0029] This disclosure provides a method for fabricating a semiconductor device, comprising:

[0030] Provide substrates;

[0031] A semiconductor layer is formed on the substrate.

[0032] The formation of the semiconductor layer includes: forming a plurality of first semiconductor structures arranged side by side along a first direction, and forming a plurality of second semiconductor structures arranged side by side along a second direction, wherein the first semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the second direction, and the second semiconductor structures include the P-type semiconductors and the N-type semiconductors alternately arranged along the first direction.

[0033] This also includes:

[0034] An intrinsic semiconductor is formed between any two adjacent P-type semiconductors and N-type semiconductors.

[0035] This also includes:

[0036] A first interlayer insulating layer is formed on the side of the semiconductor layer opposite to the substrate.

[0037] A source and a drain are formed on the side of the first interlayer insulating layer away from the substrate. The source and the drain are respectively connected to the P-type semiconductor and the N-type semiconductor of the first semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer. Alternatively, the source and the drain are respectively connected to the P-type semiconductor and the N-type semiconductor of the second semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer.

[0038] This also includes:

[0039] A first interlayer insulating layer is formed on the side of the semiconductor layer opposite to the substrate.

[0040] A source and a drain are formed on the side of the first interlayer insulating layer away from the substrate. The source and the drain are respectively connected to the P-type semiconductor and the N-type semiconductor of the first semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer. Alternatively, the source and the drain are respectively connected to the P-type semiconductor and the N-type semiconductor of the second semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer.

[0041] A second interlayer insulating layer is formed on the side of the source and drain electrodes away from the substrate.

[0042] A first connection electrode and a second connection electrode are formed on the side of the second interlayer insulating layer away from the substrate. The first connection electrode is connected to the source electrode through a third connection via penetrating the second interlayer insulating layer, and the second connection electrode is connected to the drain electrode through a fourth connection via penetrating the second interlayer insulating layer.

[0043] This also includes:

[0044] A first interlayer insulating layer is formed on the side of the semiconductor layer opposite to the substrate.

[0045] A gate is formed on the side of the first interlayer insulating layer away from the substrate, and the orthographic projection of the gate onto the substrate at least partially overlaps with the orthographic projection of the intrinsic semiconductor onto the substrate.

[0046] A second interlayer insulating layer is formed on the side of the gate opposite to the substrate.

[0047] A source and a drain are formed on the side of the second interlayer insulating layer away from the substrate. The source is connected to the P-type semiconductor of the first semiconductor structure through a sixth connection via penetrating the first and second interlayer insulating layers, and the drain is connected to the N-type semiconductor of the first semiconductor structure through a seventh connection via penetrating the first and second interlayer insulating layers. Alternatively, the source is connected to the P-type semiconductor of the second semiconductor structure through a sixth connection via penetrating the first and second interlayer insulating layers, and the drain is connected to the N-type semiconductor of the second semiconductor structure through a seventh connection via penetrating the first and second interlayer insulating layers.

[0048] This disclosure provides an electronic device that includes any of the semiconductor devices described above. Attached Figure Description

[0049] Figure 1 This is a top view schematic diagram of a semiconductor layer including multiple PN junctions in related technologies;

[0050] Figure 2 This is a schematic cross-sectional view of a semiconductor device including a PN junction according to an embodiment of the present disclosure;

[0051] Figure 3A This is a top view schematic diagram of a semiconductor layer including multiple PN junctions according to an embodiment of the present disclosure;

[0052] Figure 3B This is a top view schematic diagram of a semiconductor layer including multiple PN junctions according to an embodiment of the present disclosure;

[0053] Figure 4 This is a top view schematic diagram of a semiconductor layer that includes multiple PIN junctions in the related technology;

[0054] Figure 5 This is a schematic cross-sectional view of a semiconductor device including a PIN junction according to an embodiment of the present disclosure;

[0055] Figure 6A This is a top view schematic diagram of a semiconductor layer including multiple PIN junctions according to an embodiment of the present disclosure;

[0056] Figure 6B This is a top view schematic diagram of a semiconductor layer including multiple PIN junctions according to an embodiment of the present disclosure;

[0057] Figure 7 This is a schematic cross-sectional view of a PIN diode according to an embodiment of the present disclosure;

[0058] Figure 8A This is a top perspective view of a semiconductor layer including multiple PIN diodes, according to an embodiment of this disclosure.

[0059] Figure 8B This is a top perspective view of a semiconductor layer including multiple PIN diodes, according to an embodiment of this disclosure.

[0060] Figure 9 This is a cross-sectional schematic diagram of a PIN radio frequency switch device according to an embodiment of the present disclosure;

[0061] Figure 10 This is a schematic cross-sectional view of a transistor according to an embodiment of the present disclosure;

[0062] Figure 11 This is a top perspective view of a plurality of transistors according to an embodiment of the present disclosure. Detailed Implementation

[0063] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0064] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0065] like Figure 1 The diagram illustrates a semiconductor layer design in related technologies that includes multiple lateral PN junctions. P-type and N-type semiconductors extend along a first direction D1 and are alternately arranged along a second direction D2 to form multiple lateral PN junctions. However, switching devices based on this type of PN junction suffer from high on-state resistance and insertion loss due to the limited width W of the PN junction per unit area. Furthermore, for multiple such switching devices connected in parallel using intercalation electrodes, high parasitic capacitance is generated between the intercalation electrodes, affecting the isolation between the devices. The width W of the PN junction can be the horizontal dimension of the interface between the P-type and N-type semiconductors perpendicular to the carrier migration direction, and the length S of the PN junction can be the maximum length of either the P-type or N-type semiconductor in the carrier migration direction.

[0066] like Figure 2 As shown, this disclosure provides a semiconductor device, which includes a substrate 100 and a semiconductor layer 300 disposed on the substrate 100. For example... Figure 3A and Figure 3B As shown, the semiconductor layer 300 includes a plurality of first semiconductor structures arranged side by side along a first direction D1, and a plurality of second semiconductor structures arranged side by side along a second direction D2; the first semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the second direction D2; the second semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the first direction D1.

[0067] In this embodiment, the semiconductor device utilizes a plurality of first semiconductor structures and a plurality of second semiconductor structures arranged side-by-side in two directions of the semiconductor layer 300. This allows P-type and N-type semiconductors to be arranged alternately in both the first and second directions. Without increasing the size of the PN junction, the width of the PN junction per unit area is increased, effectively reducing the on-state resistance of the semiconductor device, increasing the on-state current, reducing insertion loss, and improving device performance. For multiple semiconductor devices connected in parallel using intercalation electrodes, the area occupied by the same number of PN junctions is reduced, thus reducing the device size. The exponent of the intercalation electrodes is also reduced, which can effectively reduce parasitic capacitance and improve the isolation between semiconductor devices.

[0068] To more clearly illustrate the semiconductor devices in the embodiments of this disclosure, the semiconductor devices in the embodiments of this disclosure will be described in detail below with reference to specific examples.

[0069] First example: such as Figure 2 As shown, the semiconductor device is a PN junction, specifically including a substrate 100 and a semiconductor layer 300 disposed on the substrate 100. The semiconductor layer 300 includes a plurality of first semiconductor structures arranged side by side along a first direction D1 and a plurality of second semiconductor structures arranged side by side along a second direction D2. The first semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the second direction D2, and the second semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the first direction D1.

[0070] In one embodiment, such as Figure 3A As shown, the semiconductor layer 300 includes a plurality of first semiconductor structures 311 arranged side by side along a first direction D1, and a plurality of second semiconductor structures 312 arranged side by side along a second direction D2. The first semiconductor structures 311 include P-type semiconductors and N-type semiconductors alternately arranged along the second direction D2, and the second semiconductor structures 312 include P-type semiconductors and N-type semiconductors alternately arranged along the first direction D1.

[0071] exist Figure 3AIn this configuration, the first semiconductor structure 311 and the second semiconductor structure 312 each include multiple PN junctions, wherein both the P-type and N-type semiconductors are quadrilateral. In other embodiments, the P-type and N-type semiconductors can also be of other shapes; their shapes can be the same or different. Furthermore, in... Figure 3A In this configuration, one side of the P-type semiconductor is adjacent to one side of the N-type semiconductor, and the P-type and N-type semiconductors are centrally symmetrical about the midpoint of the adjacent sides. In other embodiments, the P-type and N-type semiconductors may also have other relative positional relationships. The P-type and N-type semiconductors in the first semiconductor structure 311 and the P-type and N-type semiconductors in the second semiconductor structure 312 may have different relative positional relationships, as long as they can form a PN junction, they are all within the scope of protection of this disclosure.

[0072] Compared with related technologies, the semiconductor device of this embodiment increases the width of the PN junction per unit area to 2W without changing the length S of the PN junction in the semiconductor layer. This reduces the on-state resistance of the PN junction, increases the on-state current, and reduces the insertion loss of the device. At the same time, the number of PN junctions per unit area increases. That is, compared with related technologies, the area occupied by the same number of PN junctions is reduced, which is beneficial to reduce the device size. This can reduce the exponent of the intercalation electrode and reduce the parasitic capacitance of the intercalation electrode, which is beneficial to improve the isolation.

[0073] In one embodiment, such as Figure 3B As shown, the semiconductor layer 300 includes a plurality of first semiconductor structures 321 arranged side by side along a first direction D1, and a plurality of second semiconductor structures 322 arranged side by side along a second direction D2. The first semiconductor structures 321 include P-type semiconductors and N-type semiconductors alternately arranged along the second direction D2, and the second semiconductor structures 322 include P-type semiconductors and N-type semiconductors alternately arranged along the first direction D1.

[0074] exist Figure 3B In this configuration, the first semiconductor structure 321 and the second semiconductor structure 322 each include multiple PN junctions, wherein both the P-type and N-type semiconductors are triangular. In other embodiments, the P-type and N-type semiconductors can also be of other shapes; their shapes can be the same or different. Furthermore, in... Figure 3BIn this configuration, one side of the P-type semiconductor is adjacent to one side of the N-type semiconductor, and the P-type and N-type semiconductors are centrally symmetrical about the midpoint of the adjacent sides. In other embodiments, the P-type and N-type semiconductors may also have other relative positional relationships. The P-type and N-type semiconductors in the first semiconductor structure 311 and the P-type and N-type semiconductors in the second semiconductor structure 312 may have different relative positional relationships, as long as they can form a PN junction, they are all within the scope of protection of this disclosure.

[0075] The semiconductor device in this embodiment, and Figure 3A In comparison, without changing the width of a single PN junction, P-type and N-type semiconductors are arranged in the closest possible configuration, increasing the width of the PN junction per unit area to 3W. This further reduces the on-state resistance and increases the on-state current of the PN junction, further reducing device insertion loss. Simultaneously, the number of PN junctions per unit area increases further, meaning the area occupied by the same number of PN junctions is further reduced, which is beneficial for further reducing device size. This allows for a further reduction in the index of the intercalation electrodes and the parasitic capacitance of the intercalation electrodes, thus improving isolation. In one embodiment, the semiconductor device may further include a buffer layer 200 disposed between the substrate 100 and the semiconductor layer 300, and a first interlayer insulating layer 400 disposed on the side of the semiconductor layer 300 facing away from the substrate 100. The buffer layer 200 can be used to prevent impurities on the substrate 100 from contaminating the semiconductor layer 300.

[0076] The method for fabricating a semiconductor device in this example may include: providing a substrate, and forming a semiconductor layer on the substrate. Forming the semiconductor layer includes: forming a plurality of first semiconductor structures arranged side-by-side along a first direction, and forming a plurality of second semiconductor structures arranged side-by-side along a second direction, wherein the first semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the second direction, and the second semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the first direction.

[0077] Processes for forming semiconductor layers on a substrate can include magnetron sputtering, reactive sputtering, anodizing, spin coating, etc. For LTPS semiconductor layers, crystallization processes such as excimer laser annealing (ELA) or laser activation can be used.

[0078] Forming P-type and N-type semiconductors may include: forming a first mask layer on a semiconductor layer, patterning the first mask layer, using the patterned first mask layer as a mask to dope the semiconductor layer with boron to form a P-type semiconductor; removing the first mask layer, forming a second mask layer on the semiconductor layer, patterning the second mask layer, using the patterned second mask layer as a mask to dope the semiconductor layer with phosphorus to form an N-type semiconductor; and removing the second mask layer.

[0079] The processes for forming a first mask layer and a second mask layer on the semiconductor layer can include CVD (Chemical Vapor Deposition) and PVD (Physical Vapor Deposition). The processes for patterning the first and second mask layers can include photolithography and etching, with etching including wet etching and dry etching. The processes for boron and phosphorus doping of the semiconductor layer can include selective ion implantation. After ion implantation, activation can be achieved using RTA (Rapid Thermal Annealing) or laser methods.

[0080] The materials of the first and second mask layers can include metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloys, and copper (Cu), or alloys of the above metals. The first and second mask layers can be single-layer structures or composite layer structures.

[0081] In one embodiment, a buffer layer may be formed on the substrate before forming the semiconductor layer. In another embodiment, a first interlayer insulating layer may be formed on the side of the semiconductor layer facing away from the substrate. The processes for forming the buffer layer and the first interlayer insulating layer may include CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), etc. The processes for forming the buffer layer and the first interlayer insulating layer may be the same or different.

[0082] like Figure 4 The diagram illustrates a semiconductor layer design in related technologies that includes multiple lateral pin junctions. P-type and N-type semiconductors extend along a first direction D1 and are alternately arranged along a second direction D2. An intrinsic semiconductor I is disposed between any adjacent P-type and N-type semiconductors, forming multiple lateral pin junctions. For a unit area of ​​this lateral pin junction, the width ratio of the intrinsic semiconductor I can be obtained as follows: Where L represents the width of intrinsic semiconductor I and S represents the length of the PIN junction. If S = 4μm and L = 2μm, then the width of intrinsic semiconductor I accounts for 33%.

[0083] The second example: (e.g.) Figure 5 As shown, the semiconductor device is a PIN device, specifically including a substrate 100 and a semiconductor layer 300 disposed on the substrate 100. The semiconductor layer 300 includes a plurality of first semiconductor structures arranged side-by-side along a first direction D1 and a plurality of second semiconductor structures arranged side-by-side along a second direction D2; the first semiconductor structures include alternating P-type and N-type semiconductors arranged along the second direction D2, and the second semiconductor structures include alternating P-type and N-type semiconductors arranged along the first direction D1. The semiconductor layer 300 also includes an intrinsic semiconductor I disposed between any adjacent P-type and N-type semiconductors.

[0084] In one embodiment, such as Figure 6A As shown, the semiconductor layer 300 includes a plurality of first semiconductor structures 331 arranged side-by-side along a first direction D1, and a plurality of second semiconductor structures 332 arranged side-by-side along a second direction D2. The first semiconductor structures 331 include alternating P-type and N-type semiconductors arranged along the second direction D2, and the second semiconductor structures 332 include alternating P-type and N-type semiconductors arranged along the first direction D1. The semiconductor layer 300 also includes an intrinsic semiconductor I disposed between any two adjacent P-type and N-type semiconductors.

[0085] exist Figure 6A In this configuration, the first semiconductor structure 331 and the second semiconductor structure 332 each include multiple pin junctions, wherein both the P-type and N-type semiconductors are quadrilateral. In other embodiments, the P-type and N-type semiconductors can also be other shapes; their shapes can be the same or different. Furthermore, in... Figure 6A In this configuration, one side of the P-type semiconductor is opposite to one side of the N-type semiconductor, and the P-type and N-type semiconductors are centrally symmetrical about the midpoint of the line connecting their opposite sides. In other embodiments, the P-type and N-type semiconductors may also have other relative positions. The P-type and N-type semiconductors in the first semiconductor structure 331 and the P-type and N-type semiconductors in the second semiconductor structure 332 may have different relative positions, as long as they can form a PIN junction, all of which are within the scope of protection of this disclosure.

[0086] exist Figure 6A In this context, for this lateral PIN junction per unit area, the width ratio of the intrinsic semiconductor I can be obtained as follows: Where L represents the width of intrinsic semiconductor I and S represents the length of the PIN junction. If S = 4 μm and L = 2 μm, then the width of intrinsic semiconductor I accounts for 55.6%.

[0087] Compared with related technologies, the semiconductor device of this embodiment has a significantly increased width ratio of intrinsic semiconductor I per unit area, which can reduce the on-state resistance of the PIN junction, increase the on-state current of the PIN junction, and reduce device insertion loss. At the same time, the number of PIN junctions per unit area increases, that is, the area occupied by the same number of PIN junctions is reduced, which is conducive to reducing the device size, thereby reducing the exponent of the intercalation electrode and reducing the parasitic capacitance of the intercalation electrode, which is conducive to improving isolation.

[0088] In one embodiment, such as Figure 6B As shown, the semiconductor layer 300 includes a plurality of first semiconductor structures 341 arranged side-by-side along a first direction D1, and a plurality of second semiconductor structures 342 arranged side-by-side along a second direction D2. The first semiconductor structures 341 include alternating P-type and N-type semiconductors arranged along the second direction D2, and the second semiconductor structures 342 include alternating P-type and N-type semiconductors arranged along the first direction D1. The semiconductor layer 300 also includes an intrinsic semiconductor I disposed between any two adjacent P-type and N-type semiconductors.

[0089] exist Figure 6B In this configuration, the first semiconductor structure 341 and the second semiconductor structure 342 each include multiple pin junctions, wherein both the P-type and N-type semiconductors are triangular. In other embodiments, the P-type and N-type semiconductors can also be of other shapes; their shapes can be the same or different. Furthermore, in... Figure 6B In this configuration, one side of the P-type semiconductor is opposite to one side of the N-type semiconductor, and the P-type and N-type semiconductors are centrally symmetrical about the midpoint of the line connecting their opposite sides. In other embodiments, the P-type and N-type semiconductors may also have other relative positions. The P-type and N-type semiconductors in the first semiconductor structure 341 and the P-type and N-type semiconductors in the second semiconductor structure 342 may have different relative positions, as long as they can form a PIN junction, all of which are within the scope of protection of this disclosure.

[0090] exist Figure 6B In this context, for this lateral PIN junction per unit area, the width ratio of the intrinsic semiconductor I can be obtained as follows: Where L represents the width of intrinsic semiconductor I and S represents the length of the PIN junction. If S = 4 μm and L = 2 μm, then the width of intrinsic semiconductor I accounts for 77.8%.

[0091] The semiconductor device in this embodiment, and Figure 6AIn comparison, the width ratio of intrinsic semiconductor I is further increased per unit area, which further reduces the on-state resistance of the PIN junction, increases the on-state current of the PIN junction, and reduces device insertion loss. At the same time, the number of PIN junctions per unit area is further increased, that is, the area occupied by the same number of PIN junctions is further reduced, which is conducive to reducing device size. This can reduce the index of the intercalation electrode and reduce the parasitic capacitance of the intercalation electrode, which is conducive to further improving isolation.

[0092] In one embodiment, the semiconductor device may further include a buffer layer 200 disposed between the substrate 100 and the semiconductor layer 300, and a first interlayer insulating layer 400 disposed on the side of the semiconductor layer 300 facing away from the substrate 100. The buffer layer 200 can be used to prevent impurities in the substrate 100 from contaminating the semiconductor layer 300.

[0093] The method for fabricating a semiconductor device according to this embodiment may include: providing a substrate, and forming a semiconductor layer on the substrate. Forming the semiconductor layer includes: forming a plurality of first semiconductor structures arranged side-by-side along a first direction, and forming a plurality of second semiconductor structures arranged side-by-side along a second direction, wherein the first semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the second direction, and the second semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the first direction; and an intrinsic semiconductor is formed between any adjacent P-type semiconductors and N-type semiconductors.

[0094] Forming an intrinsic semiconductor between any two adjacent P-type and N-type semiconductors may include: controlling the size and position of the first and second mask layers by adjusting the patterning process of the first and second mask layers to form an intrinsic semiconductor between any two adjacent P-type and N-type semiconductors.

[0095] In related technologies, a PIN diode is a variable impedance device controlled by bias current in the radio frequency and microwave bands. Its structure includes the P-junction and N-junction of a semiconductor diode, and an intrinsic I-region with high resistance sandwiched between them. Under forward current bias, holes and electrons are injected into the I-region. These charges do not immediately cancel each other out and disappear, but persist for a certain period of time, thus generating and storing a certain amount of charge. This charge reduces the impedance of the I-region, allowing radio frequency signals to pass through. When the PIN is reverse biased, the I-region does not store charge, and the PIN diode behaves as a parallel combination of a capacitor and a resistor, acting as a disconnector in the radio frequency circuit.

[0096] For PIN diodes based on interdigitated electrodes, their parasitic capacitance is mainly the interdigitated electrode capacitance C. off Its on-state resistance R onPrimarily determined by the width of the I-region, these two parameters directly affect the insertion loss and isolation of the PIN diode, respectively. on With C off The smaller the product of R and R, the better the performance of the PIN diode. However, in related technologies, PIN diodes have limitations due to their on-state resistance R. on and the off-state capacitor C off Excessive size leads to excessive insertion loss and isolation of the device, resulting in unsatisfactory performance at high frequencies.

[0097] The third example: such as Figure 7 As shown, the semiconductor device is a PIN diode, which specifically includes a substrate 100 and a semiconductor layer 300 disposed on the substrate 100. The semiconductor device also includes a first interlayer insulating layer 400, a source 510 and a drain 520. The first interlayer insulating layer 400 is disposed on the side of the semiconductor layer 300 away from the substrate 100, and the source 510 and the drain 520 are disposed on the side of the first interlayer insulating layer 400 away from the substrate 100.

[0098] like Figure 8A and Figure 8B As shown, the semiconductor layer 300 includes a plurality of first semiconductor structures arranged side-by-side along a first direction D1, and a plurality of second semiconductor structures arranged side-by-side along a second direction D2. The first semiconductor structures include alternating P-type and N-type semiconductors arranged along the second direction D2, and the second semiconductor structures include alternating P-type and N-type semiconductors arranged along the first direction D1. The semiconductor layer 300 also includes an intrinsic semiconductor I disposed between any two adjacent P-type and N-type semiconductors.

[0099] The source 510 is connected to the P-type semiconductor of the first semiconductor structure through a first connection via penetrating the first interlayer insulating layer 400, and the drain 520 is connected to the N-type semiconductor of the first semiconductor structure through a second connection via penetrating the first interlayer insulating layer 400. Alternatively, the source 510 is connected to the P-type semiconductor of the second semiconductor structure through a first connection via penetrating the first interlayer insulating layer 400, and the drain 520 is connected to the N-type semiconductor of the second semiconductor structure through a second connection via penetrating the first interlayer insulating layer 400.

[0100] In one embodiment, such as Figure 8AAs shown, the semiconductor layer 300 includes a plurality of first semiconductor structures 351 arranged side-by-side along a first direction D1, and a plurality of second semiconductor structures 352 arranged side-by-side along a second direction D2. The first semiconductor structures 351 include alternating P-type and N-type semiconductors arranged along the second direction D2, and the second semiconductor structures 352 include alternating P-type and N-type semiconductors arranged along the first direction D1. The semiconductor layer 300 also includes an intrinsic semiconductor I disposed between any two adjacent P-type and N-type semiconductors. The source 510 and drain 520 each extend along a third direction D3, which is different from the first direction D1 and the second direction D2. The orthographic projection of a source electrode 510 onto the substrate 100 overlaps with the orthographic projection of a plurality of P-type semiconductors arranged along the third direction D3 onto the substrate. The source electrode 510 is connected to the plurality of P-type semiconductors arranged along the third direction D3 through a plurality of first connection vias penetrating the first interlayer insulating layer 400. The plurality of P-type semiconductors are both P-type semiconductors of the first semiconductor structure 351 and P-type semiconductors of the second semiconductor structure 352. The orthographic projection of a drain electrode 520 onto the substrate 100 overlaps with the orthographic projection of a plurality of N-type semiconductors arranged along the third direction D3 onto the substrate. The drain electrode 520 is connected to the plurality of N-type semiconductors arranged along the third direction D3 through a plurality of second connection vias penetrating the first interlayer insulating layer 400. The plurality of N-type semiconductors are both N-type semiconductors of the first semiconductor structure 351 and N-type semiconductors of the second semiconductor structure 352.

[0101] In one embodiment, such as Figure 8BAs shown, the semiconductor layer 300 includes a plurality of first semiconductor structures 361 arranged side-by-side along a first direction D1, and a plurality of second semiconductor structures 362 arranged side-by-side along a second direction D2. The first semiconductor structures 361 include P-type semiconductors and N-type semiconductors alternately arranged along the second direction D2, and the second semiconductor structures 362 include P-type semiconductors and N-type semiconductors alternately arranged along the first direction D1. The semiconductor layer 300 also includes an intrinsic semiconductor I disposed between any two adjacent P-type semiconductors and N-type semiconductors. The source 510 and drain 520 each extend along the first direction D1. The orthographic projection of a source 510 onto the substrate 100 overlaps with the orthographic projection of a plurality of P-type semiconductors arranged along the first direction D1 onto the substrate. The source 510 is connected to the plurality of P-type semiconductors arranged along the first direction D1 through a plurality of first connection vias penetrating the first interlayer insulating layer 400. The plurality of P-type semiconductors are both P-type semiconductors of the first semiconductor structure 361 and P-type semiconductors of the second semiconductor structure 362. The orthographic projection of a drain 520 onto the substrate overlaps with the orthographic projection of a plurality of N-type semiconductors arranged along the first direction D1 onto the substrate. The drain 520 is connected to the plurality of N-type semiconductors arranged along the first direction D1 through a plurality of second connection vias penetrating the first interlayer insulating layer 400. The plurality of N-type semiconductors are both N-type semiconductors of the first semiconductor structure 361 and N-type semiconductors of the second semiconductor structure 362.

[0102] Compared with related technologies, the semiconductor device in this example has a significantly increased width ratio of intrinsic semiconductor I per unit area, which can reduce the on-state resistance of PIN diodes, increase the on-state current of PIN diodes, and reduce device insertion loss. At the same time, the number of PIN diodes per unit area increases, that is, the area occupied by the same number of PIN diodes is reduced, which is conducive to reducing device size. This can reduce the index of intercalation electrodes and reduce the parasitic capacitance of intercalation electrodes, which is conducive to improving device isolation.

[0103] The method for fabricating a semiconductor device in this embodiment may include: providing a substrate, forming a semiconductor layer on the substrate, forming a first interlayer insulating layer on the side of the semiconductor layer away from the substrate, and forming a source and a drain on the side of the first interlayer insulating layer away from the substrate.

[0104] Forming a semiconductor layer includes: forming a plurality of first semiconductor structures arranged side by side along a first direction, and forming a plurality of second semiconductor structures arranged side by side along a second direction, wherein the first semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the second direction, and the second semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the first direction; and forming an intrinsic semiconductor between any adjacent P-type semiconductors and N-type semiconductors.

[0105] The source and drain are respectively connected to the P-type semiconductor and N-type semiconductor of the first semiconductor structure through the first connection via and the second connection via penetrating the first interlayer insulating layer; or, the source and drain are respectively connected to the P-type semiconductor and N-type semiconductor of the second semiconductor structure through the first connection via and the second connection via penetrating the first interlayer insulating layer.

[0106] The process for forming the first interlayer insulating layer can include CVD, PVD, vacuum evaporation, or spin coating. The process for forming the source and drain electrodes can include sequential photolithography, etching, and deposition.

[0107] Fourth example: such as Figure 9 As shown, the semiconductor device is a PIN radio frequency switch device, which includes a substrate 100 and a semiconductor layer 300 disposed on the substrate 100. The semiconductor device also includes a first interlayer insulating layer 400, a source electrode 510 and a drain electrode 520, a second interlayer insulating layer 600, a first connection electrode 710 and a second connection electrode 720. The first interlayer insulating layer 400 is disposed on the side of the semiconductor layer 300 facing away from the substrate 100. The source electrode 510 and the drain electrode 520 are disposed on the side of the first interlayer insulating layer 400 facing away from the substrate 100. The second interlayer insulating layer 600 is disposed on the side of the source electrode 510 and the drain electrode 520 facing away from the substrate 100. The first connection electrode 710 and the second connection electrode 720 are disposed on the side of the second interlayer insulating layer 600 facing away from the substrate 100.

[0108] Semiconductor layer 300 includes a plurality of first semiconductor structures arranged side-by-side along a first direction, and a plurality of second semiconductor structures arranged side-by-side along a second direction. The first semiconductor structures include alternating P-type and N-type semiconductors arranged along the second direction, and the second semiconductor structures include alternating P-type and N-type semiconductors arranged along the first direction. Semiconductor layer 300 also includes an intrinsic semiconductor I disposed between any two adjacent P-type and N-type semiconductors.

[0109] The source 510 is connected to the P-type semiconductor of the first semiconductor structure through a first connection via penetrating the first interlayer insulating layer 400, and the drain 520 is connected to the N-type semiconductor of the first semiconductor structure through a second connection via penetrating the first interlayer insulating layer 400. Alternatively, the source 510 is connected to the P-type semiconductor of the second semiconductor structure through a first connection via penetrating the first interlayer insulating layer 400, and the drain 520 is connected to the N-type semiconductor of the second semiconductor structure through a second connection via penetrating the first interlayer insulating layer 400.

[0110] The first connecting electrode 710 is connected to the source electrode 510 through a third connecting via penetrating the second interlayer insulating layer 600, and the second connecting electrode 720 is connected to the drain electrode 520 through a fourth connecting via penetrating the second interlayer insulating layer 600.

[0111] The semiconductor device in this example includes PIN diodes and other film structures. Within a unit area, the width of the intrinsic semiconductor I of the PIN diode is greatly increased, which can reduce the on-state resistance of the PIN diode, increase the on-state current of the PIN diode, and reduce the insertion loss of the device. At the same time, the number of PIN diodes per unit area increases, that is, the area occupied by the same number of PIN diodes is reduced, which is conducive to reducing the device size. This can reduce the index of the intercalation electrode and reduce the parasitic capacitance of the intercalation electrode, which is conducive to improving the device isolation. In addition, by setting other film structures, film space is reserved for adding other devices.

[0112] In one embodiment, such as Figure 9 As shown, the PIN radio frequency switch device also includes a storage capacitor. The first electrode 530 of the storage capacitor is disposed on the same layer as the source electrode 510 and the drain electrode 520, and the second electrode 730 is disposed on the same layer as the first connection electrode 710 and the second connection electrode 720.

[0113] In one embodiment, such as Figure 9 As shown, the PIN RF switch device also includes an inductor, which includes a first substructure 540 and a second substructure 740. The first substructure 540 is disposed on the same layer as the source 510 and the drain 520, and the second substructure 740 is disposed on the same layer as the first connection electrode 710 and the second connection electrode 720. The first substructure 540 and the second substructure 740 are connected through a fifth connection via penetrating the second interlayer insulating layer 600.

[0114] By setting storage capacitors and / or inductors, isolation between the RF signal path and the DC path is achieved. This PIN RF switch device can simultaneously perform the functions of an RF switch and a phase shifter, making it compatible with LTPS technology and suitable for large-scale mass production.

[0115] The method for fabricating a semiconductor device in this example may include: providing a substrate, forming a semiconductor layer on the substrate, forming a first interlayer insulating layer on the side of the semiconductor layer away from the substrate, forming a source and a drain on the side of the first interlayer insulating layer away from the substrate, forming a second interlayer insulating layer on the side of the source and drain away from the substrate, and forming a first connection electrode and a second connection electrode on the side of the second interlayer insulating layer away from the substrate.

[0116] Forming a semiconductor layer includes: forming a plurality of first semiconductor structures arranged side by side along a first direction, and forming a plurality of second semiconductor structures arranged side by side along a second direction, wherein the first semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the second direction, and the second semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the first direction; and forming an intrinsic semiconductor between any adjacent P-type semiconductors and N-type semiconductors.

[0117] The source and drain are respectively connected to the P-type semiconductor and N-type semiconductor of the first semiconductor structure through the first connection via and the second connection via penetrating the first interlayer insulating layer; or, the source and drain are respectively connected to the P-type semiconductor and N-type semiconductor of the second semiconductor structure through the first connection via and the second connection via penetrating the first interlayer insulating layer.

[0118] The first connection electrode is connected to the source electrode through a third connection via penetrating the second interlayer insulating layer, and the second connection electrode is connected to the drain electrode through a fourth connection via penetrating the second interlayer insulating layer.

[0119] The process for forming the second interlayer insulating layer can include CVD, PVD, vacuum evaporation, or spin coating. The process for forming the first and second connecting electrodes can include sequential photolithography, etching, and deposition.

[0120] Fifth example: such as Figure 10 As shown, the semiconductor device is a transistor, which includes a substrate 100 and a semiconductor layer 300 disposed on the substrate 100. The semiconductor device also includes a first interlayer insulating layer 400, a gate 550, a second interlayer insulating layer 600, a source 750, and a drain 760. The first interlayer insulating layer 400 is disposed on the side of the semiconductor layer 300 facing away from the substrate 100; the gate 550 is disposed on the side of the first interlayer insulating layer 400 facing away from the substrate 100, and the orthographic projection of the gate 550 onto the substrate 100 at least partially overlaps with the orthographic projection of the intrinsic semiconductor I onto the substrate 100; the second interlayer insulating layer 600 is disposed on the side of the gate 550 facing away from the substrate 100; the source 750 and the drain 760 are disposed on the side of the second interlayer insulating layer 600 facing away from the substrate 100.

[0121] Semiconductor layer 300 includes a plurality of first semiconductor structures arranged side-by-side along a first direction, and a plurality of second semiconductor structures arranged side-by-side along a second direction. The first semiconductor structures include alternating P-type and N-type semiconductors arranged along the second direction, and the second semiconductor structures include alternating P-type and N-type semiconductors arranged along the first direction. Semiconductor layer 300 also includes an intrinsic semiconductor I disposed between any two adjacent P-type and N-type semiconductors.

[0122] The source 750 is connected to the P-type semiconductor of the first semiconductor structure through a sixth connection via penetrating the first interlayer insulating layer 400 and the second interlayer insulating layer 600, and the drain 760 is connected to the N-type semiconductor of the first semiconductor structure through a seventh connection via penetrating the first interlayer insulating layer 400 and the second interlayer insulating layer 600. Alternatively, the source 750 is connected to the P-type semiconductor of the second semiconductor structure through a sixth connection via penetrating the first interlayer insulating layer 400 and the second interlayer insulating layer 600, and the drain 760 is connected to the N-type semiconductor of the second semiconductor structure through a seventh connection via penetrating the first interlayer insulating layer 400 and the second interlayer insulating layer 600.

[0123] In one embodiment, such as Figure 11 As shown, the semiconductor layer 300 includes a plurality of first semiconductor structures 371 arranged side-by-side along a first direction D1, and a plurality of second semiconductor structures 372 arranged side-by-side along a second direction D2. The first semiconductor structures 371 include alternating P-type and N-type semiconductors arranged along the second direction D2, and the second semiconductor structures 372 include alternating P-type and N-type semiconductors arranged along the first direction D1. The semiconductor layer 300 also includes an intrinsic semiconductor I disposed between any two adjacent P-type and N-type semiconductors. The source 750 and drain 760 each extend along a third direction D3, which is different from the first direction D1 and the second direction D2. A source electrode 750 has its orthographic projection on the substrate 100 overlapping with the orthographic projection of a plurality of P-type semiconductors arranged along the third direction D3 on the substrate 100. The source electrode 750 is connected to the plurality of P-type semiconductors arranged along the third direction D3 through a plurality of sixth connection vias penetrating the first interlayer insulating layer 400. The plurality of P-type semiconductors are both P-type semiconductors of the first semiconductor structure 371 and P-type semiconductors of the second semiconductor structure 372. A drain electrode 760 has its orthographic projection on the substrate 100 overlapping with the orthographic projection of a plurality of N-type semiconductors arranged along the third direction D3 on the substrate 100. The drain electrode 760 is connected to the plurality of N-type semiconductors arranged along the third direction D3 through a plurality of seventh connection vias penetrating the first interlayer insulating layer 400. The plurality of N-type semiconductors are both N-type semiconductors of the first semiconductor structure 371 and N-type semiconductors of the second semiconductor structure 372. The gate 550 extends along a first direction D1 and / or a second direction D2, and the orthographic projection of the gate 550 onto the substrate 100 at least partially overlaps with the orthographic projection of the intrinsic semiconductor I onto the substrate 100.

[0124] In this example transistor, the source contact region (P-type semiconductor) and drain contact region (N-type semiconductor) of the semiconductor layer have different types of ion doping. This example transistor can be a tunneling TFT. In related technologies, the on-state current of a tunneling TFT is mainly affected by band-to-band tunneling (rather than drift diffusion). When the device is in the off state, the potential barriers of the source / drain contact region and the channel region (intrinsic semiconductor) are very wide, resulting in no charge carriers in the channel, thus the off-state current is extremely low. In the on state, the gate voltage pulls down the channel band. Once the conduction band of the channel region is lower than the valence band of the source / drain contact region, electrons in the valence band of the source / drain contact region can easily tunnel into the channel region and form a tunneling current, the magnitude of which is determined by the tunneling rate. The advantages of tunneling TFTs are extremely low off-state current and a subthreshold swing (SS) that can break through the 60mV / dec limit of standard TFTs, but their on-state current is relatively low.

[0125] In this example, the width of the intrinsic semiconductor I is greatly increased per unit area, which can reduce the on-state resistance of the transistor, increase the on-state current of the transistor, and reduce the insertion loss of the device. At the same time, the number of transistors per unit area increases, that is, the area occupied by the same number of transistors is reduced, which is conducive to reducing the device size, thereby reducing parasitic capacitance and improving device isolation.

[0126] In another embodiment, the transistor in this example may also be an LTPS-TFT.

[0127] The method for fabricating a semiconductor device in this example may include: providing a substrate, forming a semiconductor layer on the substrate, forming a first interlayer insulating layer on a side of the semiconductor layer away from the substrate, forming a gate on a side of the first interlayer insulating layer away from the substrate, wherein the orthographic projection of the gate onto the substrate at least partially overlaps with the orthographic projection of the intrinsic semiconductor onto the substrate; forming a second interlayer insulating layer on a side of the gate away from the substrate; and forming a source and a drain on a side of the second interlayer insulating layer away from the substrate.

[0128] Forming a semiconductor layer includes: forming a plurality of first semiconductor structures arranged side by side along a first direction, and forming a plurality of second semiconductor structures arranged side by side along a second direction, wherein the first semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the second direction, and the second semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the first direction; and forming an intrinsic semiconductor between any adjacent P-type semiconductors and N-type semiconductors.

[0129] The source is connected to the P-type semiconductor of the first semiconductor structure through a sixth connection via penetrating the first and second interlayer insulating layers, and the drain is connected to the N-type semiconductor of the first semiconductor structure through a seventh connection via penetrating the first and second interlayer insulating layers. Alternatively, the source is connected to the P-type semiconductor of the second semiconductor structure through a sixth connection via penetrating the first and second interlayer insulating layers, and the drain is connected to the N-type semiconductor of the second semiconductor structure through a seventh connection via penetrating the first and second interlayer insulating layers.

[0130] The process for forming the gate can include magnetron sputtering, electron beam evaporation, thermal evaporation, and optical coating.

[0131] The substrate can be formed from rigid or flexible materials. For example, rigid materials include rigid glass, silicon substrates, germanium substrates, and silicon-coated insulating substrates; flexible materials include polyethylene naphthalate, polyethylene terephthalate, polyimide, and flexible glass. The buffer layer can be made of silicon oxide, silicon nitride, etc.

[0132] The semiconductor layer material can include LTPS, IGZO (Indium Gallium Zinc Oxide), ITZO (Indium Tin Oxide Zinc), IGZXO (Indium Gallium Zinc X Oxide), ITZXO (Indium Tin Zinc X Oxide), etc., where X and Y represent tin doping, and the doping ratios of X and Y are different. P-type semiconductors can be formed by P-type doping (e.g., boron doping) of the semiconductor layer material, and N-type semiconductors can be formed by N-type doping (e.g., phosphorus doping) of the semiconductor layer.

[0133] The materials of the first and second interlayer insulating layers include one or more of silicon oxide, silicon nitride, aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide, such as hydrogen-free SiNx:F. The materials of the first and second interlayer insulating layers can be the same or different.

[0134] The source and drain electrodes can be made of one or more of the following metals: molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloys, and copper (Cu). The source and drain electrodes can be made of the same or different materials.

[0135] The materials of the first and second connecting electrodes may include one or a combination of metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloys, and copper (Cu). The materials of the first and second connecting electrodes may be the same or different.

[0136] The materials of the first and second plates of the capacitor can include one or a combination of metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloys, and copper (Cu). The materials of the first and second plates can be the same or different. The materials of the first and second substructures of the inductor can include one or a combination of metals such as molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloys, and copper (Cu). The materials of the first and second substructures can be the same or different. The processes for forming the first and second plates of the capacitor and the first and second substructures of the inductor can include electroplating with Cu, etc.

[0137] The gate material can include one or more of the following metals: molybdenum (Mo), chromium (Cr), titanium (Ti), aluminum (Al), aluminum alloys, and copper (Cu). The gate material can also include one or more of the following transparent conductive materials: indium tin oxide, aluminum-doped zinc oxide, and boron-doped zinc oxide. The gate can be a single-layer structure or a composite structure with two or more layers.

[0138] This disclosure provides an electronic device that includes any of the semiconductor devices described above.

[0139] The electronic device can be an array substrate. It can also be a display device or a radio frequency (RF) device, which may include the aforementioned array substrate. The display device can be a liquid crystal display panel, an organic light-emitting diode (OLED) display panel, a micro-LED display panel, an X-ray sensor array, or other devices requiring transistors.

[0140] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A semiconductor device comprising: A substrate, and a semiconductor layer disposed on the substrate; The semiconductor layer includes a plurality of first semiconductor structures arranged side by side along a first direction, and a plurality of second semiconductor structures arranged side by side along a second direction; The first semiconductor structure includes P-type semiconductors and N-type semiconductors alternately arranged along the second direction; The second semiconductor structure includes the P-type semiconductor and the N-type semiconductor alternately arranged along the first direction.

2. The semiconductor device according to claim 1, wherein, The semiconductor layer also includes an intrinsic semiconductor disposed between any two adjacent P-type semiconductors and N-type semiconductors.

3. The semiconductor device according to claim 2, wherein, Also includes: A first interlayer insulating layer is disposed on the side of the semiconductor layer opposite to the substrate. The source and drain are disposed on the side of the first interlayer insulating layer away from the substrate. The source and drain are respectively connected to the P-type semiconductor and N-type semiconductor of the first semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer. Alternatively, the source and drain are respectively connected to the P-type semiconductor and N-type semiconductor of the second semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer.

4. The semiconductor device according to claim 2, wherein, Also includes: A first interlayer insulating layer is disposed on the side of the semiconductor layer opposite to the substrate. The source and drain are disposed on the side of the first interlayer insulating layer away from the substrate. The source and drain are respectively connected to the P-type semiconductor and N-type semiconductor of the first semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer. Alternatively, the source and drain are respectively connected to the P-type semiconductor and N-type semiconductor of the second semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer. The second interlayer insulating layer is disposed on the side of the source and the drain that is away from the substrate. A first connection electrode and a second connection electrode are disposed on the side of the second interlayer insulating layer away from the substrate. The first connection electrode is connected to the source electrode through a third connection via penetrating the second interlayer insulating layer, and the second connection electrode is connected to the drain electrode through a fourth connection via penetrating the second interlayer insulating layer.

5. The semiconductor device according to claim 4, wherein, It also includes a storage capacitor, wherein the first plate of the storage capacitor is disposed in the same layer as the source and drain, and the second plate is disposed in the same layer as the first connecting electrode and the second connecting electrode.

6. The semiconductor device according to claim 4, wherein, It also includes an inductor, which includes a first substructure and a second substructure. The first substructure is disposed on the same layer as the source and drain, and the second substructure is disposed on the same layer as the first connection electrode and the second connection electrode. The first substructure and the second substructure are connected through a fifth connection via penetrating the second interlayer insulating layer.

7. The semiconductor device according to claim 2, wherein, The semiconductor device includes a transistor, and the semiconductor device further includes: A first interlayer insulating layer is disposed on the side of the semiconductor layer opposite to the substrate. A gate is disposed on the side of the first interlayer insulating layer away from the substrate, and the orthographic projection of the gate on the substrate at least partially overlaps with the orthographic projection of the intrinsic semiconductor on the substrate. A second interlayer insulating layer is disposed on the side of the gate opposite to the substrate. The source and drain are disposed on the side of the second interlayer insulating layer away from the substrate. Wherein, the source is connected to the P-type semiconductor of the first semiconductor structure through a sixth connection via penetrating the first and second interlayer insulating layers, and the drain is connected to the N-type semiconductor of the first semiconductor structure through a seventh connection via penetrating the first and second interlayer insulating layers; or, the source is connected to the P-type semiconductor of the second semiconductor structure through a sixth connection via penetrating the first and second interlayer insulating layers, and the drain is connected to the N-type semiconductor of the second semiconductor structure through a seventh connection via penetrating the first and second interlayer insulating layers.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The P-type semiconductor is quadrilateral, and / or the N-type semiconductor is quadrilateral; or The P-type semiconductor is triangular, and / or the N-type semiconductor is triangular.

9. The semiconductor device according to any one of claims 1 to 7, wherein, The P-type semiconductor and the N-type semiconductor in the first semiconductor structure are centrally symmetrical about the midpoint of the line connecting their opposite sides; and / or The P-type semiconductor and the N-type semiconductor in the second semiconductor structure are centrally symmetrical about the midpoint of the line connecting the midpoints of their opposite sides.

10. A method for fabricating a semiconductor device, comprising: Provide substrates; A semiconductor layer is formed on the substrate. The formation of the semiconductor layer includes: forming a plurality of first semiconductor structures arranged side by side along a first direction, and forming a plurality of second semiconductor structures arranged side by side along a second direction, wherein the first semiconductor structures include P-type semiconductors and N-type semiconductors alternately arranged along the second direction, and the second semiconductor structures include the P-type semiconductors and the N-type semiconductors alternately arranged along the first direction.

11. The method for fabricating a semiconductor device according to claim 10, wherein, Also includes: An intrinsic semiconductor is formed between any two adjacent P-type semiconductors and N-type semiconductors.

12. The method for fabricating a semiconductor device according to claim 11, wherein, Also includes: A first interlayer insulating layer is formed on the side of the semiconductor layer opposite to the substrate. A source and a drain are formed on the side of the first interlayer insulating layer away from the substrate. The source and the drain are respectively connected to the P-type semiconductor and the N-type semiconductor of the first semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer. Alternatively, the source and the drain are respectively connected to the P-type semiconductor and the N-type semiconductor of the second semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer.

13. The method for fabricating a semiconductor device according to claim 11, wherein, Also includes: A first interlayer insulating layer is formed on the side of the semiconductor layer opposite to the substrate. A source and a drain are formed on the side of the first interlayer insulating layer away from the substrate. The source and the drain are respectively connected to the P-type semiconductor and the N-type semiconductor of the first semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer. Alternatively, the source and the drain are respectively connected to the P-type semiconductor and the N-type semiconductor of the second semiconductor structure through a first connection via and a second connection via penetrating the first interlayer insulating layer. A second interlayer insulating layer is formed on the side of the source and drain electrodes away from the substrate. A first connection electrode and a second connection electrode are formed on the side of the second interlayer insulating layer away from the substrate. The first connection electrode is connected to the source electrode through a third connection via penetrating the second interlayer insulating layer, and the second connection electrode is connected to the drain electrode through a fourth connection via penetrating the second interlayer insulating layer.

14. The method for fabricating a semiconductor device according to claim 11, wherein, Also includes: A first interlayer insulating layer is formed on the side of the semiconductor layer opposite to the substrate. A gate is formed on the side of the first interlayer insulating layer away from the substrate, and the orthographic projection of the gate onto the substrate at least partially overlaps with the orthographic projection of the intrinsic semiconductor onto the substrate. A second interlayer insulating layer is formed on the side of the gate opposite to the substrate. A source and a drain are formed on the side of the second interlayer insulating layer away from the substrate. The source is connected to the P-type semiconductor of the first semiconductor structure through a sixth connection via penetrating the first and second interlayer insulating layers, and the drain is connected to the N-type semiconductor of the first semiconductor structure through a seventh connection via penetrating the first and second interlayer insulating layers. Alternatively, the source is connected to the P-type semiconductor of the second semiconductor structure through a sixth connection via penetrating the first and second interlayer insulating layers, and the drain is connected to the N-type semiconductor of the second semiconductor structure through a seventh connection via penetrating the first and second interlayer insulating layers.

15. An electronic device comprising a semiconductor device as claimed in any one of claims 1 to 9.

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