LDMOS device and manufacturing method thereof

Abstract

The invention discloses an LDMOS device and a manufacturing method thereof, and the manufacturing method comprises the steps: providing a semiconductor substrate, forming an active region, a drain region, a body region and a drift region in the semiconductor substrate, and forming a gate structure on the semiconductor substrate; forming a multi-layer field plate dielectric layer covering the gate structure and the semiconductor substrate; forming a patterned photoresist layer on the multiple field plate dielectric layers, wherein the patterned photoresist layer comprises a window region exposing the field plate dielectric layers and a shielding region covering the field plate dielectric layers; etching the field plate dielectric layer exposed in the initial window area by taking the patterned photoresist layer as a mask; trimming the photoresist layer at least once to enlarge the window area; and after each trimming, taking the trimmed photoresist layer as a mask, and performing selective etching on the field plate dielectric layer exposed in the expanded window area so as to form a step-shaped field plate dielectric layer. According to the invention, the step-shaped field plate dielectric layer can be formed based on the photoresist layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to an LDMOS device and a method for manufacturing the same. Background Technology

[0002] Laterally diffused metal-oxide-semiconductor (LDMOS) employs a double-diffusion technique, performing boron and phosphorus diffusions sequentially within the same window. The difference in lateral junction depth between the two impurity diffusions precisely determines the channel length. LDMOS devices are primarily used in power integrated circuits, offering advantages such as high breakdown voltage, fast switching speed, and compatibility with complementary metal-oxide-semiconductor (CMOS) device processes.

[0003] Contact field plate technology is one of the key technologies for improving the breakdown voltage of LDMOS devices. By connecting the field plate electrode to the source potential, the electric field distribution on the surface of the drift region can be effectively modulated, thereby improving the device's breakdown voltage without significantly increasing the specific on-resistance.

[0004] However, with increasing voltage withstand requirements, the size requirements for contact field plates also increase. Etching large-size field plate structures faces significant challenges: First, due to differences in pattern size, sharing the same etching process with conventional contact holes can result in severe etching load effects, leading to abnormal etching morphology in the field plate area. Second, etching large-size deep holes is difficult to control precisely, easily resulting in insufficient bottom critical dimensions and excessive top critical dimensions, affecting the electric field modulation effect of the field plate and device reliability. If multiple small-size contact field plates are used to replace large-size contact field plates, multiple photolithography and etching processes are required for the field plate dielectric layer, making the process complex and difficult to guarantee overlay accuracy. Summary of the Invention

[0005] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0006] To address the existing problems, this application provides a method for manufacturing an LDMOS device, comprising: A semiconductor substrate is provided, wherein an active region, a drain region, a body region and a drift region are formed in the semiconductor substrate, and a gate structure is formed on the semiconductor substrate; A multilayer field plate dielectric layer is formed covering the gate structure and the semiconductor substrate, with adjacent field plate dielectric layers made of different materials; A patterned photoresist layer is formed on the multilayer field plate dielectric layer, the patterned photoresist layer including a window area exposing the field plate dielectric layer and a masking area covering the field plate dielectric layer; Using the patterned photoresist layer as a mask, the field plate dielectric layer exposed in the initial window area is etched. The photoresist layer is trimmed at least once to enlarge the window area; After each trimming, the field plate dielectric layer exposed in the enlarged window area is etched using the trimmed photoresist layer as a mask, thereby forming a stepped field plate dielectric layer.

[0007] In one embodiment, the multilayer field plate dielectric layer includes at least a topmost first field plate dielectric layer and a second field plate dielectric layer located below the first field plate dielectric layer. The etching of the field plate dielectric layer exposed in the initial window area using the patterned photoresist layer as a mask includes etching the first field plate dielectric layer exposed in the initial window area to form a first opening in the first field plate dielectric layer corresponding to the initial window area. The step of trimming the photoresist layer at least once to expand the window area includes: performing a first trimming on the photoresist layer to expand the initial window area into a first expanded window area; The etching of the field plate dielectric layer exposed in the enlarged window area to form a stepped field plate dielectric layer includes: The second field plate dielectric layer exposed by the first opening is etched at a first etching rate to form a second opening in the second field plate dielectric layer corresponding to the first opening; The first field plate dielectric layer exposed in the first enlarged window area is etched at a second etching rate to enlarge the first opening, wherein the second etching rate is less than the first etching rate.

[0008] In one embodiment, the multilayer field plate dielectric layer further includes a third field plate dielectric layer located below the second field plate dielectric layer; The step of trimming the photoresist layer at least once to enlarge the window area further includes: after forming the second opening in the second field plate dielectric layer, trimming the photoresist layer a second time to enlarge the first enlarged window area into the second enlarged window area; The etching of the field plate dielectric layer exposed in the enlarged window area to form a stepped field plate dielectric layer includes: The third field plate dielectric layer exposed by the second opening is etched at a third etching rate to form a third opening in the third field plate dielectric layer corresponding to the second opening; The second field plate dielectric layer exposed by the first opening is etched at a fourth etching rate to enlarge the second opening, wherein the fourth etching rate is less than the third etching rate; The first field plate dielectric layer exposed in the second enlarged window area is etched at a fifth etching rate to enlarge the first opening, wherein the fifth etching rate is greater than the fourth etching rate, such that the width of the enlarged first opening is greater than the width of the enlarged second opening.

[0009] In one embodiment, the first field plate dielectric layer is made of the same material as the third field plate dielectric layer, but is made of a different material than the second field plate dielectric layer.

[0010] In one embodiment, the first and third field plate dielectric layers are made of silicon oxide, and the second field plate dielectric layer is made of silicon nitride; or... The first and third field plate dielectric layers are made of silicon nitride, and the second field plate dielectric layer is made of silicon oxide.

[0011] In one embodiment, the thickness of the first field plate dielectric layer is 0.5 μm to 1 μm, the thickness of the second field plate dielectric layer is 0.3 μm to 1.5 μm, and the thickness of the third field plate dielectric layer is 0.2 μm to 0.5 μm.

[0012] In one embodiment, the total thickness of the multilayer field plate dielectric layer is 1 μm to 3 μm.

[0013] In one embodiment, the initial thickness of the patterned photoresist layer is 0.5 μm to 5 μm, and the width of the window region is increased by 0.05 μm to 0.5 μm with each trimming of the photoresist layer.

[0014] In one embodiment, after forming the stepped field plate medium, the method further includes: An interlayer dielectric layer is deposited to cover the stepped field plate dielectric layer; The interlayer dielectric layer is etched to form at least two field plate contact holes that expose the stepped field plate dielectric layer, with different field plate contact holes stopping at different field plate dielectric layers; A contact field plate is formed within the contact hole of the field plate.

[0015] In one embodiment, the method further includes: simultaneously etching the interlayer dielectric layer to form at least one of a source contact hole, a drain contact hole, and a gate contact hole during the etching process of the interlayer dielectric layer to form the field plate contact hole.

[0016] Another embodiment of this application provides an LDMOS device, which is manufactured using the method described above.

[0017] According to the manufacturing method of LDMOS device provided in this application, a stepped field plate dielectric layer structure is formed by multiple trimming and selective etching processes of a single layer of photoresist. This avoids the multiple photoresist coating, alignment and stripping steps required by traditional multi-photolithography processes, significantly simplifying the process flow and reducing manufacturing costs and overlay error risks. By forming the stepped field plate dielectric layer structure in advance, only the same interlayer dielectric layer needs to be etched during the etching of the field plate contact holes, resulting in better etching stop performance and better uniformity of the landing point of the field plate contact holes. Attached Figure Description

[0018] The following drawings, which are incorporated herein by reference and are used to understand this application, illustrate embodiments of the invention and their descriptions to explain the principles of the invention.

[0019] In the attached image: Figure 1 A schematic flowchart illustrating a method for manufacturing an LDMOS device according to a specific embodiment of this application is shown; Figures 2A-2J This illustration shows a cross-sectional schematic diagram of an LDMOS device obtained by sequentially performing each step of a manufacturing method according to a specific embodiment of this application. Detailed Implementation

[0020] The following description provides numerous specific details to offer a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with this application.

[0021] It should be understood that this application can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the widths of layers and regions, as well as their relative widths, may be exaggerated. The same reference numerals denote the same elements throughout.

[0022] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0023] Spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0025] In view of the aforementioned technical problems, this application proposes an LDMOS device and a method for manufacturing the same. Below, reference is made to... Figures 1 to 2J The fabrication method of the LDMOS device according to the embodiments of this application is described in detail, wherein, Figure 1A schematic flowchart illustrating a method for manufacturing an LDMOS device according to a specific embodiment of this application is shown. Figures 2A-2J This paper shows a cross-sectional view of an LDMOS device obtained by implementing a manufacturing method according to a specific embodiment of this application.

[0026] First, execute step S101, as follows: Figure 2A As shown, a semiconductor substrate 200 is provided, in which a drift region 201, a body region 202, a drain region 203 and a source region 204 are formed, and a gate structure 205 is formed on the semiconductor substrate 200.

[0027] For example, a semiconductor substrate 200 is first provided. The material of the semiconductor substrate 200 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon on dielectric (S-SiGeOI), silicon on dielectric (SiGeOI), and germanium on dielectric (GeOI).

[0028] For example, the semiconductor substrate 200 has doped ions of a first conductivity type, which can be P-type or N-type doped ions. When the formed LDMOS is an N-type LDMOS device, the first conductivity type is P-type; when the formed LDMOS is a P-type LDMOS device, the first conductivity type is N-type. The following explanation mainly uses P-type as the first conductivity type, that is, the semiconductor substrate 200 has P-type doped ions.

[0029] Next, a drift region 201 is formed in the semiconductor substrate 200. Exemplarily, before forming the drift region 201, the semiconductor substrate 200 may also be implanted with dopant ions of a second conductivity type to form a well region, exemplarily having N-type dopant ions. Then, the drift region 201 is formed in the well region, the drift region 201 having dopant ions of a second conductivity type, such as N-type dopant ions. The drift region 201 has a low doping concentration; due to its light doping characteristics, when a high voltage is applied to the drain, the depletion region will mainly extend into the drift region 201, thereby bearing most of the voltage drop and preventing the channel region from being broken down due to excessively high electric field. The drift region 201, by optimizing the doping concentration and length, can also minimize the on-resistance of the device while ensuring breakdown voltage.

[0030] For example, a shallow trench isolation structure 206 is also formed in the drift region 201. The shallow trench isolation structure 206 may be formed after the drift region or before the drift region 201.

[0031] After the drift region 201 is formed, a body region 202 is formed in the semiconductor substrate 200. The body region 202 has doped ions of a first conductivity type, such as p-type doped ions. The body region 202 is disposed side by side with the drift region 201 in the semiconductor substrate 200 to form a channel region during operation. Optionally, the body region 202 may also be formed after the gate structure 205.

[0032] Next, a gate structure 205 is formed on the semiconductor substrate 200. Exemplarily, a thermal oxidation process can be used to oxidize the surface of the semiconductor substrate 200 to form a gate dielectric layer. Next, a gate electrode layer is formed on the gate dielectric layer. Specifically, a deposition process such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition can be performed to form the gate electrode layer, and the material of the gate electrode layer can include conductive materials such as polysilicon or metal. Next, the gate electrode layer and the gate dielectric layer are patterned to form a gate structure. Specifically, a mask layer can be formed on the gate electrode layer, and the gate electrode layer and the gate dielectric layer can be etched based on the mask layer to obtain the gate structure 205. The gate structure 205 may also include spacers for protecting the sidewalls of the gate structure. The gate structure 205 can serve as a self-aligned mask for forming the source region 204 and the drain region 203.

[0033] Next, a drain region 203 is formed in the drift region 201, and a source region 204 is formed in the body region 202. The source region 204 and drain region 203 have doped ions of a second conductivity type, such as N-type doped ions. Furthermore, a body contact region can be formed in the body region 202, having doped ions of a first conductivity type, such as P-type doped ions. The source region 204, drain region 203, and body contact region have high doping concentrations. After forming the source region 204 and drain region 203, a high-temperature annealing process is performed to create a gradual doping distribution with the previously implanted doped ions.

[0034] Next, step S102 is performed to form a multilayer field plate dielectric layer 207 covering the gate structure 205 and the semiconductor substrate 200. Adjacent field plate dielectric layers 207 are made of different materials, thus exhibiting different etching selectivity. The field plate dielectric layer 207 can also serve as a metal silicide barrier layer. The total thickness of the multilayer field plate dielectric layer 207, the number of field plate dielectric layers 207, and the thickness of each field plate dielectric layer 207 can be set according to the required breakdown voltage of the LDMOS device. For example, the total thickness of the multilayer field plate dielectric layer 207 is 1 μm to 3 μm.

[0035] For example, the multilayer field plate dielectric layer 207 includes at least a first field plate dielectric layer 207A located at the top and a second field plate dielectric layer 207B located below the first field plate dielectric layer 207A, that is, the number of layers can be two; further, the multilayer field plate dielectric layer 207 also includes a third field plate dielectric layer 207C located below the second field plate dielectric layer 207B, that is, the number of layers is three; there may also be other field plate dielectric layers below the third field plate dielectric layer 207C, that is, the number of layers can be greater than three.

[0036] In one embodiment, the field plate dielectric layer 207 may be composed of two different materials stacked alternately, i.e., the first field plate dielectric layer 207A and the third field plate dielectric layer 207C are made of the same material, while the second field plate dielectric layer 207B is made of a different material. The two different materials may be silicon oxide and silicon nitride. For example, the first field plate dielectric layer 207A and the third field plate dielectric layer 207C may be made of silicon oxide, and the second field plate dielectric layer 207B may be made of silicon nitride; or the first field plate dielectric layer 207A and the third field plate dielectric layer 207C may be made of silicon nitride, and the second field plate dielectric layer 207B may be made of silicon oxide. Exemplarily, the thickness of the first field plate dielectric layer is 0.5 μm to 1 μm, the thickness of the second field plate dielectric layer is 0.3 μm to 1.5 μm, and the thickness of the third field plate dielectric layer is 0.2 μm to 0.5 μm.

[0037] Next, the multilayer field plate dielectric layer 207 is etched by photoresist trimming to form a stepped field plate dielectric layer 207.

[0038] Specifically, first, step S103 is executed, such as... Figure 2C As shown, a patterned photoresist layer 208 is formed on the multilayer field plate dielectric layer 207. The patterned photoresist layer 208 includes a window area that exposes the field plate dielectric layer 207 and a masking area that covers the field plate dielectric layer 207.

[0039] Next, proceed to step S104, as follows: Figure 2D As shown, the patterned photoresist layer 208 is used as a mask to etch the field plate dielectric layer 207 exposed in the initial window area; Next, step S105 is performed to trim the photoresist layer 208 at least once to expand the window area; After each trimming, the field plate dielectric layer 207 exposed in the enlarged window area is etched using the trimmed photoresist layer 208 as a mask, thereby forming a stepped field plate dielectric layer 207.

[0040] For example, the initial thickness of the patterned photoresist layer 208 is 0.5 μm to 5 μm. Appropriately increasing the thickness of the photoresist layer 208 can compensate for the thickness loss during the trimming process. In each trimming of the photoresist layer 208, the width of the window region is increased by 0.05 μm to 0.5 μm, so that the width difference between the different field plate dielectric layers subsequently formed is 0.05 μm to 0.5 μm. This width difference is beneficial for forming field plate contact holes.

[0041] In step S104, the patterned photoresist layer 208 is first used as a mask to etch the first field plate dielectric layer 207A exposed in the initial window area, so as to form a first opening in the first field plate dielectric layer 207A corresponding to the initial window area. The width of the initial masking area is D1, so the width of the remaining first field plate dielectric layer 207A after the first etching is also D1.

[0042] Next, as Figure 2E As shown, the photoresist layer 208 is trimmed for the first time to expand the initial window area into a first enlarged window area. Correspondingly, the width of the masking area is reduced from D1 to D2. Since the trimmed window area is enlarged compared to the initial window area, the trimmed window area not only exposes the second field plate dielectric layer 207B located below the first opening, but also exposes a portion of the first field plate dielectric layer 207A that was originally masked by the initial masking area.

[0043] Exemplary methods include dry trimming, wet trimming, and thermal reflow to trim the photoresist layer 208. Dry trimming involves using plasma to perform isotropic, slight etching of the photoresist layer 208, controlling the trimming width by adjusting RF power and process time. Thermal reflow involves heating the photoresist layer 208 to soften and flow, thereby altering the pattern shape. Wet trimming involves using solvent vapor to swell and slightly dissolve the surface of the photoresist layer 208 to achieve width adjustment. This application does not limit the specific trimming process described.

[0044] Next, as Figure 2F As shown, the field plate dielectric layer 207 exposed in the first enlarged window region is etched. Specifically, the second field plate dielectric layer 207B exposed in the first opening is etched at a first etching rate to form a second opening corresponding to the first opening in the second field plate dielectric layer 207B; the first field plate dielectric layer 207A exposed in the first enlarged window region is etched at a second etching rate to enlarge the first opening, wherein the second etching rate is less than the first etching rate.

[0045] Specifically, a selective etching process with a higher etching rate for the second field plate dielectric layer 207B is used to etch the first field plate dielectric layer 207A and the second field plate dielectric layer 207B. During the etching process, because the etching rate of the first field plate dielectric layer 207A is slower, it can protect the second field plate dielectric layer 207B during the etching process. This results in the width of the second opening formed in the second field plate dielectric layer 207B being smaller than the width of the first enlarged window region, but close to the width of the first opening, i.e., the width of the initial window region. As the etching progresses, the first field plate dielectric layer 207A exposed in the first enlarged window region is slowly removed, thereby eventually expanding the width of the first opening to match the width of the first enlarged window region. Thus, a step is formed between the first field plate dielectric layer 207A and the second field plate dielectric layer 207B.

[0046] After the second opening is formed in the dielectric layer 207B of the second field plate, as Figure 2G As shown, the photoresist layer 208 is trimmed a second time to expand the first enlarged window area into the second enlarged window area, and correspondingly, the width of the masking area is reduced to D3.

[0047] Next, as Figure 2H As shown, the field plate dielectric layer 207 exposed in the second enlarged window region is etched. The field plate dielectric layer 207 exposed in the second enlarged window region includes a portion of the first field plate dielectric layer 207A that was originally covered by a shielded area, a second field plate dielectric layer 207B exposed by a first opening in the first field plate dielectric layer 207A, and a third field plate dielectric layer 207C exposed by a second opening in the second field plate dielectric layer 207B.

[0048] In this etching process, a selective etching process with higher etching rates for the third field plate dielectric layer 207C and the first field plate dielectric layer 207A is employed to etch each of the field plate dielectric layers 207. Specifically, the third field plate dielectric layer 207C, which exposes the second opening, is etched at a third etching rate to form a third opening corresponding to the second opening in the third field plate dielectric layer 207C. The second field plate dielectric layer 207B, which exposes the first opening, is etched at a fourth etching rate to enlarge the second opening, wherein the fourth etching rate is lower than the third etching rate. The first field plate dielectric layer 207A, which exposes the enlarged window area, is etched at a fifth etching rate to enlarge the first opening, wherein the fifth etching rate is greater than the fourth etching rate, such that the width of the enlarged first opening is greater than the width of the enlarged second opening. For example, when the material of the first field plate dielectric layer 207A is the same as the material of the third field plate dielectric layer 207C, the fifth etching rate is equal to the third etching rate, both being greater than the fourth etching rate.

[0049] During the etching process, because the etching rate of the second field plate dielectric layer 207B is slower, it can protect the third field plate dielectric layer 207C during etching. This allows the width of the third opening formed in the third field plate dielectric layer 207C to be close to the width of the second opening, i.e., the width of the initial window region. Simultaneously, the first field plate dielectric layer 207A also has a faster etching rate, so the width of its first opening rapidly expands to the width of the expanded second window region. As etching progresses, the second field plate dielectric layer 207B exposed by the first opening is slowly removed, causing the width of the second opening to eventually expand to the width between the first and third openings. Thus, a step is formed between the first field plate dielectric layer 207A, the second field plate dielectric layer 207B, and the third field plate dielectric layer 207C.

[0050] Similarly, after each trimming of the photoresist layer 208, the exposed portion of the upper field dielectric layer 207 can act as a mask to protect the lower field dielectric layer 207, so that the width of the opening formed in the lower field dielectric layer 207 is smaller than the width of the window area in the current photoresist layer, ultimately forming a stepped field dielectric layer 207.

[0051] Next, as Figure 2I As shown, the photoresist layer 208 is removed, and an interlayer dielectric layer 209 covering the stepped field dielectric layer 207 is deposited. The photoresist layer 208 can be removed using processes such as wet cleaning or ashing, and then the interlayer dielectric layer 209 covering the stepped field dielectric layer 207 is deposited using processes such as chemical vapor deposition. This interlayer dielectric layer 209 is typically composed of a dielectric material such as silicon oxide, and its main function is to achieve surface planarization of the structure and provide electrical isolation for the subsequently formed metal interconnects.

[0052] Next, as Figure 2JAs shown, the interlayer dielectric layer 209 is etched to form at least two field plate contact holes exposing the stepped field plate dielectric layer 207, and contact field plates 210 are formed within the field plate contact holes. The contact field plates 210 are used to improve the electric field concentration problem at the edge of the planar junction, suppressing hot carrier effects and reducing on-resistance. Different field plate contact holes are respectively positioned on different field plate dielectric layers 207, thereby forming multiple stepped contact field plates 210. For example, the field plate contact holes include at least a first contact hole exposing the first field plate dielectric layer 207A, a second contact hole exposing the second field plate dielectric layer 207B, and a third contact hole exposing the third field plate dielectric layer 207C, thereby forming three stepped contact field plates 210. The stepped arrangement of the contact field plates 210 can replace a large-width contact field plate, thus avoiding problems such as insufficient bottom width and excessive top width of the field plate contact holes, requiring a thicker metal filler thickness, which can lead to misalignment during the first layer of metal lithography. This effectively reduces the peak volume electric field in the reverse blocking state and maximizes the doping concentration of the drift region 210 while ensuring the breakdown voltage meets requirements, thereby reducing the on-resistance of the device. For example, the more dielectric layers 207 of the field plate, the higher the breakdown voltage of the LDMOS device.

[0053] In addition to forming field plate contact holes, the interlayer dielectric layer 209 can be etched in the same etching process or different etching processes to form at least one of source contact holes, drain contact holes, and gate contact holes, and filled with metal material to form source contact structures, drain contact structures, and gate contact structures for leading out source region 204, drain region 203, and gate structure 205. For example, the field plate contact holes have substantially the same width as the source contact holes, drain contact holes, and gate contact holes, which avoids the etching load effect caused by forming large-width field plate contact holes and normal-width contact holes in the same etching process. By forming a stepped field plate dielectric layer structure in advance, only the same interlayer dielectric layer needs to be etched during the etching of the field plate contact holes, resulting in better etching stop performance and better uniformity of the field plate contact hole placement.

[0054] Thus, the process steps of the manufacturing method of the LDMOS device according to the first aspect embodiment of this application are completed. It is understood that the manufacturing method of the LDMOS device in this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included in the scope of the manufacturing method in this embodiment.

[0055] According to the LDMOS device manufacturing method provided in the embodiments of this application, a stepped field plate dielectric layer structure is formed by multiple trimming and selective etching processes of a single layer of photoresist. This avoids the multiple photoresist coating, alignment and stripping steps required by traditional multi-photolithography processes, significantly simplifying the process flow and reducing manufacturing costs and overlay error risks. By utilizing the etching selectivity between adjacent field plate dielectric layers, precise control of the opening width of the lower field plate dielectric is achieved. The resulting stepped field plate structure effectively modulates the electric field in the drift region, simultaneously increasing the breakdown voltage of the device and reducing its on-resistance.

[0056] This application also provides an LDMOS device, which can be prepared by the methods described in the foregoing embodiments, but is not limited thereto.

[0057] The LDMOS device of this application will be described in detail below. It is worth mentioning that, in order to avoid repetition, only a brief description will be given for the same components and structures as in the foregoing embodiments. For specific explanations and descriptions, please refer to the description in Embodiment 1.

[0058] Specifically, such as Figure 2J As shown, the LDMOS device of this application embodiment includes: a semiconductor substrate 200, in which an active region 204, a drain region 203, a body region 202, and a drift region 201 are formed, and a gate structure 205 is formed on the semiconductor substrate 200; a multilayer field plate dielectric layer 207 covering a portion of the gate structure 205 and at least a portion of the drift region 201, wherein adjacent field plate dielectric layers 207 are made of different materials, and the width of the multilayer field plate dielectric layer 207 gradually decreases from top to bottom, thereby forming a stepped field plate dielectric layer 207. Further, it also includes an interlayer dielectric layer 209 covering the semiconductor substrate 200, the gate structure 205, and the field plate dielectric layer 207, wherein at least two contact field plates 210 are formed in the interlayer dielectric layer 209 to connect the field plate dielectric layer 207, and different contact field plates 210 stop at different field plate dielectric layers 207. Furthermore, it also includes source contact structures, drain contact structures and gate contact structures formed in the interlayer dielectric layer 209, with the contact field plate 210 having a width substantially the same as that of the source contact structures, drain contact structures and gate contact structures.

[0059] The LDMOS device in this embodiment uses a stepped-arranged contact field plate 210 instead of a large-width contact field plate, which can effectively reduce the peak value of the bulk electric field in the reverse blocking state, and maximize the doping concentration of the drift region while ensuring that the breakdown voltage meets the requirements, thereby reducing the on-resistance of the device. At the same time, due to the use of a stepped field plate dielectric layer, the uniformity of the landing points of the field plate contact holes is better.

[0060] This application also provides an electronic device, including the aforementioned semiconductor device, which can be prepared according to the aforementioned method.

[0061] The electronic device in this embodiment can be any electronic product or device such as a mobile phone, tablet computer, laptop computer, netbook, television, VCD player, DVD player, navigator, digital photo frame, camera, camcorder, voice recorder, MP3 player, MP4 player, PSP, etc., or any intermediate product including circuitry. The electronic device in this embodiment, due to the use of the aforementioned semiconductor devices, has better performance.

[0062] This application has been described through the above embodiments. However, it should be understood that the above embodiments are for illustrative purposes only and are not intended to limit this application to the scope of the described embodiments. Furthermore, those skilled in the art will understand that this application is not limited to the above embodiments, and many more variations and modifications can be made based on the teachings of this application, all of which fall within the scope of protection claimed in this application. The scope of protection of this application is defined by the appended claims and their equivalents.

Claims

1. A method of manufacturing an LDMOS device, characterized by, The manufacturing method comprises: providing a semiconductor substrate in which an active region, a drain region, a body region and a drift region are formed, and a gate structure is formed on the semiconductor substrate; forming a multi-layer field plate dielectric layer covering the gate structure and the semiconductor substrate, materials of adjacent field plate dielectric layers being different; forming a patterned photoresist layer on the multi-layer field plate dielectric layer, the patterned photoresist layer comprising a window region exposing the field plate dielectric layer and a shielding region covering the field plate dielectric layer; masking the field plate dielectric layer exposed by the initial window region and etching the field plate dielectric layer; trimming the photoresist layer at least once to expand the window region; after each trimming, masking the field plate dielectric layer exposed by the expanded window region with the trimmed photoresist layer and etching the field plate dielectric layer, thereby forming a stepped field plate dielectric layer.

2. The production method according to claim 1, wherein The multi-layer field plate dielectric layer comprises at least a first field plate dielectric layer as an uppermost layer and a second field plate dielectric layer below the first field plate dielectric layer; the etching the field plate dielectric layer exposed by the initial window region comprises etching the first field plate dielectric layer exposed by the initial window region to form a first opening in the first field plate dielectric layer corresponding to the initial window region; the trimming the photoresist layer at least once to expand the window region comprises trimming the photoresist layer for the first time to expand the initial window region into a first expanded window region; the etching the field plate dielectric layer exposed by the expanded window region comprises: etching the second field plate dielectric layer exposed by the first opening at a first etching speed to form a second opening in the second field plate dielectric layer corresponding to the first opening; etching the first field plate dielectric layer exposed by the first expanded window region at a second etching speed to expand the first opening, wherein the second etching speed is less than the first etching speed.

3. The production method according to claim 2, wherein The multi-layer field plate dielectric layer further comprises a third field plate dielectric layer below the second field plate dielectric layer; the trimming the photoresist layer at least once to expand the window region further comprises, after forming the second opening in the second field plate dielectric layer, trimming the photoresist layer for the second time to expand the first expanded window region into a second expanded window region; the etching the field plate dielectric layer exposed by the expanded window region comprises: etching the third field plate dielectric layer exposed by the second opening at a third etching speed to form a third opening in the third field plate dielectric layer corresponding to the second opening; etching the second field plate dielectric layer exposed by the first opening at a fourth etching speed to expand the second opening, wherein the fourth etching speed is less than the third etching speed. exposing the first field plate dielectric layer of the second enlarged window region at a fifth etching speed to etch the first field plate dielectric layer, wherein the fifth etching speed is greater than the fourth etching speed, so that the width of the first enlarged opening is greater than the width of the second enlarged opening.

4. The production method according to claim 3, wherein The first field plate dielectric layer and the third field plate dielectric layer are made of the same material, and the material of the second field plate dielectric layer is different from the material of the first field plate dielectric layer and the third field plate dielectric layer. The material of the first field plate dielectric layer and the third field plate dielectric layer is silicon oxide, and the material of the second field plate dielectric layer is silicon nitride. The material of the first field plate dielectric layer and the third field plate dielectric layer is silicon nitride, and the material of the second field plate dielectric layer is silicon oxide.

5. The production method according to claim 3 or 4, characterized by, The thickness of the first field plate dielectric layer is 0.5 μm to 1 μm, the thickness of the second field plate dielectric layer is 0.3 μm to 1.5 μm, and the thickness of the third field plate dielectric layer is 0.2 μm to 0.5 μm.

6. The production method according to claim 1, wherein The total thickness of the multi-layer field plate dielectric layer is 1 μm to 3 μm.

7. The production method according to claim 1, wherein The initial thickness of the patterned photoresist layer is 0.5 μm to 5 μm, and the width of the window region is enlarged by 0.05 μm to 0.5 μm in each trimming of the photoresist layer.

8. The production method according to claim 1, wherein After forming the stepped field plate dielectric, the method further comprises: depositing an interlayer dielectric layer covering the stepped field plate dielectric layer; etching the interlayer dielectric layer to form at least two field plate contact holes exposing the stepped field plate dielectric layer, and different field plate contact holes stop at different field plate dielectric layers; forming a contact field plate in the field plate contact hole.

9. The production method according to claim 8, wherein The method further comprises: During etching the interlayer dielectric layer to form the field plate contact hole, synchronously etching the interlayer dielectric layer to form at least one of a source contact hole, a drain contact hole and a gate contact hole.

10. An LDMOS device, characterized by, The LDMOS device is manufactured by the method of any one of claims 1-9.

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