Preparation method of power semiconductor device and power semiconductor device
By selectively etching mask layers of different materials in the fabrication of trench gate power semiconductor devices to form a self-aligned hard mask, the threshold voltage fluctuation problem caused by the fluctuation of the contact hole and trench distance is solved, achieving higher consistency and performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-30
- Publication Date
- 2026-03-27
AI Technical Summary
In the fabrication of trench gate power semiconductor devices, reducing the cell pitch causes fluctuations in the distance between the contact hole and the trench, resulting in significant fluctuations in the threshold voltage and affecting device performance.
By employing two or more mask layers of different materials, selective etching is performed during the etching process to form lateral grooves and a thicker dielectric layer. The thicker dielectric layer is used as a self-aligned hard mask to form a smaller first opening and a larger second opening, adjusting the distance from the electrode contact hole to the trench sidewall.
It improves the consistency of the distance from the electrode contact hole to the trench, reduces the dependence on high-end lithography machines, reduces the fluctuation of the threshold voltage, and improves the device performance.
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Figure CN121751671A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of power semiconductor technology, specifically providing a method for fabricating a power semiconductor device and a power semiconductor device. Background Technology
[0002] For power semiconductor devices, especially trench-gate power semiconductor devices, taking trench-gate MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) as an example, electrode contact holes are typically fabricated between two adjacent trenches during the fabrication process to bring out the source of the MOSFET. Currently, to reduce specific on-resistance, improve power density and switching performance, shrink chip area, and lower costs, while also adapting to high-frequency and high-efficiency applications, reducing cell pitch is the optimal solution. However, this leads to a reduction in the distance between the contact holes and trenches. Consequently, fluctuations in the distance between the contact holes and trenches often result in significant fluctuations in threshold voltage, potentially leading to failure. Summary of the Invention
[0003] This application aims to solve the above-mentioned technical problems and provide a power semiconductor device and its fabrication method to effectively adjust the distance from the electrode contact hole to the trench sidewall, thereby improving the flexibility of device design.
[0004] To achieve the above objectives, the method for fabricating a power semiconductor device provided in this application includes:
[0005] A mask structure is formed on a semiconductor substrate, the mask structure comprising at least a first mask layer and a second mask layer stacked together, the first mask layer and the second mask layer being made of different materials;
[0006] The semiconductor substrate is etched using the mask structure to form multiple spaced trenches;
[0007] Selective etching is performed on the mask structure so that the first mask layer is partially etched to expose a first area on the surface of the semiconductor substrate, thereby forming a transverse groove between the semiconductor substrate and the second mask layer. The first mask layer left by the lateral etching is the first mask portion.
[0008] A gate structure is formed in a trench and a second mask layer is removed. The formation of the gate structure includes forming a gate dielectric layer and forming a gate. The formation of the gate dielectric layer includes at least forming a first dielectric layer, which includes a first portion covering the trench sidewall and a second portion filling the transverse groove, and the thickness of the second portion is greater than the thickness of the first mask portion.
[0009] A well region is formed in a semiconductor substrate between adjacent trenches, and a source region is formed in the well region;
[0010] Remove the first mask portion to expose a second region on the surface of the semiconductor substrate, while retaining at least a portion of the second portion;
[0011] A first opening is formed in a second region of the semiconductor substrate, the distance between the first opening and the trench is defined by the width of the second portion, and the depth of the first opening is greater than the depth of the source region;
[0012] A second dielectric layer is formed on the gate structure and the second part, and the second dielectric layer is patterned to form a second opening through the second dielectric layer. The second opening corresponds to the first opening, and the width of the second opening is greater than that of the first opening.
[0013] A source metal is formed, which is electrically contacted with the source region through the first opening and the second opening.
[0014] In some embodiments, the mask structure further includes a third mask layer disposed on the second mask layer, the third mask layer being made of the same material as the first mask layer.
[0015] In some embodiments, the semiconductor substrate is a silicon substrate, the first mask layer is a silicon oxide layer, and the second mask layer is a silicon nitride layer.
[0016] In some embodiments, a thermal oxidation process is used to react and generate a silicon oxide layer in a first region on the trench sidewalls and the surface of the semiconductor substrate, which serves as the first dielectric layer.
[0017] In some embodiments, the sidewalls of the first and second portions facing the center of the trench are both closer to the center of the trench than the edge of the second mask layer adjacent to the trench.
[0018] In some embodiments, forming the grid structure in the trench further includes:
[0019] A first gate is formed in the trench where the first dielectric layer is formed;
[0020] An isolation dielectric layer is formed on top of the first gate;
[0021] Remove the first dielectric layer that protrudes above the isolation dielectric layer on the sidewall of the trench;
[0022] A third dielectric layer is formed on the sidewall of the trench, the third dielectric layer being higher than the isolation dielectric layer and connected to the isolation dielectric layer;
[0023] A second gate is formed on the isolation dielectric layer.
[0024] In some embodiments, forming a second gate on the isolation dielectric layer further includes:
[0025] A first polysilicon layer is formed in a trench located above the isolation dielectric layer, wherein the top surface of the first polysilicon layer is lower than the surface of the semiconductor substrate;
[0026] The first polysilicon layer is thermally oxidized to form a silicon oxide layer in the top region of the first polysilicon layer, and the unoxidized first polysilicon layer serves as the second gate.
[0027] In some embodiments, forming the grid structure in the trench includes:
[0028] A second polysilicon layer is formed in a trench in which the first dielectric layer is formed, wherein the top surface of the second polysilicon layer is lower than the surface of the semiconductor substrate;
[0029] The second polysilicon layer is thermally oxidized to form a silicon oxide layer in the top region of the second polysilicon layer, and the unoxidized second polysilicon layer serves as the gate.
[0030] In some embodiments, removing the first mask portion to expose a second region on the surface of the semiconductor substrate includes:
[0031] Simultaneously etch the first mask portion and the second portion until the surface of the semiconductor substrate below the first mask portion is exposed, and thin the second portion is made.
[0032] The power semiconductor device provided in this application includes:
[0033] Semiconductor substrate;
[0034] Multiple trenches located in and spaced apart in the semiconductor substrate;
[0035] The gate structure located in the trench includes a gate dielectric layer and a gate, wherein the gate dielectric layer is used to isolate the gate and the semiconductor substrate;
[0036] The well regions located on both sides of the trench and the source regions located within the well regions;
[0037] A dielectric isolation portion located on the semiconductor substrate, the isolation dielectric portion being located on both sides of the trench;
[0038] A first opening is located in the semiconductor substrate on both sides of the trench, and the distance between the first opening and the trench is defined by the width of the dielectric isolation portion;
[0039] A dielectric layer covering the gate structure and the dielectric isolation portion, wherein the dielectric layer has a second opening, the second opening corresponding to the first opening, and the width of the second opening being greater than the width of the first opening;
[0040] The source metal is electrically contacted with the source region through the first opening and the second opening.
[0041] The method for fabricating a power semiconductor device provided in this application involves forming a mask structure on a semiconductor substrate, which includes two or more mask layers of different materials. During selective etching of the mask structure, different etching selectivity ratios are used to allow the first mask layer to be laterally etched, exposing a first region of the semiconductor substrate. When the first dielectric layer is subsequently formed, a second portion of the first dielectric layer is formed in the first region. The second portion and the remaining first mask portion after lateral etching have a step difference. By using the thicker second portion as a self-aligned hard mask for subsequent electrode contact hole etching, a relatively small first opening is formed. When a larger second opening is subsequently formed, the distance from the trench to the electrode contact hole is not affected by the critical dimensions of trench photolithography, contact hole photolithography, and contact hole alignment deviation. This helps to improve the consistency of the distance from the electrode contact hole to the trench and ensure the performance of the power semiconductor device. Attached Figure Description
[0042] The preferred embodiments of this application are described below with reference to the accompanying drawings, in which:
[0043] Figure 1 This is a schematic flowchart of a method for fabricating a power semiconductor device according to an embodiment of this application;
[0044] Figure 2a This is a schematic diagram of the structure obtained after step S11 according to an embodiment of this application. Figure 2b This is a schematic diagram of the structure obtained after executing S11 according to another embodiment of this application;
[0045] Figures 3 to 4 This is a schematic diagram of the structure obtained after performing each step S12 to S13 according to the embodiments of this application;
[0046] Figure 5 This is a schematic diagram of the structure obtained by forming a gate dielectric layer according to an embodiment of this application;
[0047] Figures 6a to 6f This is a schematic diagram of the structure obtained by each step of forming the gate structure according to an embodiment of this application;
[0048] Figures 7a to 7b This is a schematic diagram of the structure obtained by each step of forming the gate structure according to another embodiment of this application;
[0049] Figure 8aThis is a schematic diagram of the structure obtained after executing S15 according to an embodiment of this application. Figure 8b This is a schematic diagram of the structure obtained after executing S15 according to another embodiment of this application;
[0050] Figure 9a This is a schematic diagram of the structure obtained after executing S16 according to an embodiment of this application. Figure 9b This is a schematic diagram of the structure obtained after executing S16 according to another embodiment of this application;
[0051] Figure 10a This is a schematic diagram of the structure obtained after executing S17 according to an embodiment of this application. Figure 10b This is a schematic diagram of the structure obtained after performing S17 according to another embodiment of this application;
[0052] Figures 11a to 11b This is a schematic diagram of the structure obtained by performing each step in the S18 process according to an embodiment of this application;
[0053] Figures 12a to 12b This is a schematic diagram of the structure obtained by performing each step in S18 according to another embodiment of this application;
[0054] Figure 13 This is a schematic diagram of the structure obtained after executing S19 according to an embodiment of this application;
[0055] Figure 14 This is a schematic diagram of the structure obtained after executing S19 according to another embodiment of this application. Detailed Implementation
[0056] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the described embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0057] The terms “first,” “second,” “third,” and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components.
[0058] Figure 1 This is a schematic diagram of a method for fabricating a power semiconductor device according to an embodiment of this application, as shown below. Figure 1 As shown in the accompanying drawings, the preparation method specifically includes the following steps.
[0059] A semiconductor substrate is provided. In this embodiment, the semiconductor substrate is an epitaxial wafer, which includes a substrate 10 and an epitaxial layer 11 located on the substrate 10. (Refer to...) Figure 2a and Figure 2b In this embodiment, substrate 10 can be a silicon substrate, and epitaxial layer 11 can be a silicon epitaxial layer; both have the same doping type, and the doping concentration can be the same or different, generally the doping concentration of epitaxial layer 11 is slightly lower than that of substrate 10. In other embodiments, the semiconductor substrate can also be other types, especially semiconductor substrates commonly used in power semiconductor devices, such as single-crystal silicon substrates, SOI (silicon-on-insulator), etc. The following explanation uses an epitaxial wafer as an example of a semiconductor substrate.
[0060] S11: A mask structure 12 is formed on a semiconductor substrate. The mask structure 12 includes at least a first mask layer 121 and a second mask layer 122 stacked together and made of different materials. Here, the mask structure 12 exposes the surface of the epitaxial layer 11 to which the trench is to be formed.
[0061] In one implementation, see Figure 2a As shown, the mask structure 12 includes only a first mask layer 121 and a second mask layer 122 sequentially stacked on the epitaxial layer 11, wherein the first mask layer 121 is, for example, a silicon dioxide layer, and the second mask layer 122 is, for example, a silicon nitride layer.
[0062] In another implementation, see Figure 2b As shown, the mask structure 12 includes a first mask layer 121, a second mask layer 122, and a third mask layer 123 sequentially stacked on the epitaxial layer 11. The third mask layer 123 is made of the same material as the first mask layer 121. Both the first mask layer 121 and the third mask layer 123 can be silicon oxide layers, while the second mask layer 122 can be a silicon nitride layer. Therefore, the mask structure 12 is a typical ONO hard mask layer. To provide protection during subsequent etching, the third mask layer 123 can be made thicker, for example, greater than the thickness of the first mask layer 121.
[0063] In the aforementioned mask structure 12, the silicon nitride layer can be deposited at a high temperature using LPCVD (low-pressure chemical vapor deposition), with a deposition temperature of 900℃ to 1100℃, and silane is used as the process gas. ) and nitrogen ( This is to ensure that the bird's beak effect is minimized in the subsequent oxidation process, meaning that oxygen molecules have difficulty diffusing from the bottom of the silicon nitride edge into the silicon surface, thus making it difficult to oxidize the silicon at that location.
[0064] S12: The semiconductor substrate is etched using the mask structure 12 to form multiple spaced trenches V0. Each trench V0 extends in the thickness direction of the epitaxial layer 11, and the bottom of the trench V0 is located in the epitaxial layer 11. Figure 3 The diagram illustrates the structure of a single trench V0. In reality, power semiconductor devices typically have multiple trenches V0, spaced apart, for example, along... Figure 3 The horizontal spacing is arranged in the middle.
[0065] S13: Selectively etch the mask structure 12 to expose the first region S1 on the surface of the semiconductor substrate by partial lateral etching of the first mask layer 121, so as to form a transverse groove between the semiconductor substrate and the second mask layer 122. The first mask layer 121 left by the lateral etching is the first mask portion 121'.
[0066] Specifically, the first mask layer 121, which is closer to the epitaxial layer 11 in the mask structure 12, is etched, while the second mask layer 122 is preserved as much as possible. This results in the first mask layer 121 being partially etched laterally to form a transverse groove, exposing the first region S1 on the surface of the epitaxial layer 11. The portion of the second mask layer 122 near the trench V0 is suspended above the exposed surface of the epitaxial layer 11, forming the aforementioned transverse groove between the suspended second mask layer 122 and the epitaxial layer 11. The opposing surfaces of the two layers serve as the sides of the transverse groove, resulting in the following... Figure 4 The intermediate structure shown.
[0067] When the mask structure 12 adopts, as shown in the example Figure 2b In the structure shown, during the selective etching of the mask structure 12, the third mask layer 123 is also laterally etched and its thickness is reduced, resulting in the etched third mask portion 123', as shown. Figure 4 As shown.
[0068] In step S13, wet etching of the first mask layer 121 (and the third mask layer 123) can be used. Since wet etching is isotropic, when the mask structure 12 is used as shown in the figure, the first mask layer 121 (and the third mask layer 123) can be etched. Figure 2b In the structure shown, since the first mask layer 121 and the third mask layer 123 are made of the same material, the side near the trench V0 is laterally etched for a certain distance. In addition, the etched third mask portion 123' is thinned, as shown. Figure 4 As shown. Alternatively, dry etching can be used, in which the first mask layer 121 is partially removed and the second mask layer 122 is fully preserved by controlling the etching selectivity.
[0069] S14: Form a gate structure in trench V0 and remove the second mask layer 122. Forming the gate structure includes forming a gate dielectric layer and forming a gate. Forming the gate dielectric layer includes at least forming a first dielectric layer 13. The first dielectric layer 13 includes a first portion 131 covering the trench sidewall and a second portion 132 filling the transverse groove. The thickness of the second portion 132 is greater than the thickness of the first mask portion 121'. See [reference needed]. Figure 5 As shown.
[0070] In some embodiments, forming the first dielectric layer 13 includes thermal oxidation, which causes the silicon epitaxial layer 11 exposed in the trench VO sidewalls and lateral grooves to undergo an oxidation reaction to form silicon oxide. Specifically, thermal oxidation can be dry oxidation, and the oxidation temperature can generally be controlled between 850°C and 900°C.
[0071] like Figure 4 As shown, before thermal oxidation, the sidewalls of trench V0 and the sidewalls of the second mask layer 122 can be considered aligned; however, due to the characteristics of thermal oxidation, silicon is oxidized to silicon dioxide and expands in volume, therefore, as Figure 5 As shown, the sidewalls of the first part 131 and the second part 132 facing the center of the trench V0 are both closer to the center of the trench V0 than the sidewall of the second mask layer 122. Figure 5 In the middle, the vertical dashed line corresponds to the initial boundary of the sidewall of the trench V0 before thermal oxidation, which can be regarded as flush with the sidewall of the second mask layer 122.
[0072] In this embodiment, the sidewalls of the first part 131 and the second part 132 facing the center of the trench V0 are approximately on the same plane. However, this is not a limitation. In other embodiments, the sidewalls of the first part 131 and the second part 132 may not be on the same plane. For example, the sidewall of the first part 131 may be closer to the center of the trench V0 than the sidewall of the second part 132. This depends on various factors such as the thermal oxidation process and the size of the transverse groove.
[0073] like Figure 4 and Figure 5 As shown, the width of the first region S1 is denoted as x1. During the thermal oxidation process, the epitaxial layer 11 at the first region S1 is also oxidized and expands in volume, making the thickness of the second part 132 of the first dielectric layer 13 greater than the thickness of the first mask layer 121 and the first mask part 121'.
[0074] The method for fabricating power semiconductor devices provided in this application can be applied to the fabrication of SGT (Shielded Gate Trench) MOSFETs or trench MOSFETs. Furthermore, it can also be used to fabricate other trench gate semiconductor devices, such as bidirectional conduction devices, which include a control gate located at the bottom of the trench and a shielding gate located at the top of the trench. The gate structure differs for different types of trench gate MOSFETs.
[0075] When applied to the fabrication of an SGT MOSFET, the gate structure 14 includes a gate dielectric layer and a gate. The gate includes a shield gate 141 and a control gate 143 located within a trench V0, with the shield gate 141 positioned below the control gate 143. The gate dielectric layer includes a first dielectric layer 13 located between the shield gate 141 and the inner wall of the trench V0, a third dielectric layer 1431 located between the control gate 143 and the trench sidewall, and an isolation dielectric layer 142 located between the control gate 143 and the shield gate 141. Step 14 may specifically include:
[0076] A first gate (or shielding gate 141 for an SGT MOSFET) is formed in a trench V0 where the first dielectric layer 13 is formed, resulting in... Figure 6a The structure shown is as follows. Specifically, N-type doped polysilicon can be deposited in the trench V0, with a doping concentration of 5E19 to 5E20 and a doping thickness of not less than 1 / 2 of the current width of the trench V0 to fill the entire trench V0. Then, the polysilicon is etched to the required depth by surface planarization, dry etching, etc., to obtain the shielding gate 141.
[0077] An isolation medium layer 142 is formed on the shielding grid 141 to obtain the following: Figure 6b The structure is shown. Specifically, silicon dioxide can be deposited first to fill the remaining trench V0, and then, using the second mask layer 122 as a mask, the silicon dioxide is etched to the required depth using dry etching. The portion of the remaining silicon dioxide covering the top of the shielding gate 141 is used as the isolation dielectric layer 142. During this process, if the mask structure 12 includes a third mask layer 123, the third mask portion 123' is also removed simultaneously, and the thickness of the first portion 131 above the isolation dielectric layer 142 is naturally reduced.
[0078] Remove the first dielectric layer 13 on the sidewall of trench V0, which is located above (obliquely above) the isolation dielectric layer 142, that is, remove the first dielectric layer 13 that protrudes above the isolation dielectric layer 142, exposing the trench sidewall obliquely above the isolation dielectric layer 142, to obtain the following: Figure 6c The structure shown. Specifically, the first dielectric layer 13 near the top region of the inner wall of trench V0 can be removed by wet etching. The side of the second part 132 near the trench will also be etched laterally, but this will not affect subsequent steps.
[0079] Then, the third dielectric layer 1431 and the second gate (for the SGT MOSFET, the second gate is the control gate 143) are formed, and the second mask layer 122 is removed, exposing the first mask portion 121' and the remaining second portion 132; see also Figures 6d to 6f As shown.
[0080] A third dielectric layer 1431 is formed on the sidewall of the trench above the isolation dielectric layer 142, after the removal of the first dielectric layer 13, resulting in the following: Figure 6d In the structure shown, the third dielectric layer 1431 is connected to the isolation dielectric layer 142. When the silicon epitaxial layer 11 is used, a thermal oxidation process can be used to form a gate oxide layer as the third dielectric layer 1431. Depending on the product performance requirements, the thickness of the third dielectric layer 1431 can be less than the thickness of the first part 131, and the top surface of the third dielectric layer 1431 is lower than the surface of the epitaxial layer 11.
[0081] Depending on the deposition method of the third dielectric layer 1431, the removal order of the second mask layer 122 can vary. If thermal oxidation is used, the second mask layer 122 can be removed after film deposition; if deposition is used, the second mask layer 122 can be removed first before deposition and removal of the dielectric layer deposited on the semiconductor substrate surface. This embodiment does not impose any particular limitation on the removal process of the second mask layer 122; commonly used wet etching or dry etching processes in the art can be used to remove the second mask layer 122.
[0082] Forming a second gate (or control gate 143 for an SGT MOSFET) on the isolation dielectric layer 142 includes: forming a first polysilicon layer 1432 above the isolation dielectric layer 142, thereby obtaining... Figure 6e The structure shown is then subjected to thermal oxidation of the first polysilicon layer 1432, resulting in a first silicon oxide layer 1433 forming on the top region of the first polysilicon layer 1432. The unoxidized first polysilicon layer then forms the control gate 143, resulting in the structure shown. Figure 6f The structure shown.
[0083] The specific steps for forming the control gate 143 are as follows: N-type doped polysilicon is deposited in the trench V0, with a doping concentration of 2E19 to 5E20 and a thickness sufficient to fill the remaining space above the trench V0. Then, the polysilicon is polished to be on the same plane as the upper surface of the second part 132 by planarization methods such as CMP. Then, the polysilicon is etched to the required depth by dry etching. Finally, the exposed polysilicon is oxidized by thermal oxidation to form a first silicon oxide layer 1433. The thermal oxidation temperature can be 850°C to 900°C, and the process gas can be oxygen and hydrogen. The first silicon oxide layer 1433 should have sufficient thickness to protect the control gate 143 from being etched in subsequent fabrication processes.
[0084] In some embodiments, when applied to the fabrication of a bidirectional conducting device, the aforementioned first gate is a control gate and the second gate is a shielding gate. The specific process conditions can be determined based on the specific parameters of the bidirectional conducting device, and will not be elaborated further here.
[0085] In some embodiments, when applied to fabricating a trench MOSFET, the gate structure 14' may include a first portion 131 of the first dielectric layer 13 and a second polysilicon layer 144, with the first portion 131 serving as the gate dielectric layer. Step S14 may specifically include:
[0086] Combination Figure 5 A second polysilicon layer 144 is formed in the trench V0 where the first dielectric layer 13 is formed, resulting in... Figure 7a The structure can be specifically as follows: depositing N-type doped polysilicon to fill the entire trench V0, with a doping concentration of 5E19 to 5E20. Then, through planarization, dry etching, or other methods, the polysilicon in the trench V0 is etched to the required depth to obtain a polysilicon layer, the top surface of which is lower than the surface of the epitaxial layer 11, and at least part of the etched third mask portion 123' is removed.
[0087] Then, the second polysilicon layer 144 is thermally oxidized to form a second silicon oxide layer 145 in the top region of the polysilicon layer, and the unoxidized second polysilicon layer serves as the gate; the second mask layer 122 is then removed to obtain... Figure 7b In the structure shown, when there is still a third mask portion 123' remaining after etching, the remaining third mask portion 123' can be removed by wet etching first, and then a second silicon oxide layer 145 can be formed, which is used to protect the gate structure 14' from etching during subsequent fabrication. Finally, the second mask layer 122 is etched clean.
[0088] S15: A well region 15 is formed in the semiconductor substrate between adjacent trenches, and a source region 16 is formed in the well region 15, to obtain... Figure 8a or Figure 8b The intermediate structure.
[0089] S16: Remove the first mask portion 121' to expose the second region S2 on the surface of the semiconductor substrate, while retaining at least a portion of the second portion, see [link to previous section]. Figure 9a As shown in 9b. The second region S2 is the surface of the epitaxial layer 11 covered by the first mask portion 121', or in other words, the second region S2 is the surface region of the epitaxial layer 11 located between adjacent second portions 132.
[0090] In some embodiments, the first mask portion 121' and the second portion 132 are made of the same material. Specifically, S15 can be: simultaneously etching the first mask portion 121' and the second portion 132 until the epitaxial layer 11 below the first mask portion 121' is exposed, while the second portion 132 is thinned. The thinned second portion 132 can be used as a self-aligned hard mask when forming electrode contact holes in the future.
[0091] S17: A first opening V1 is formed in the second region S2 of the semiconductor substrate. The distance between the first opening V1 and the trench V0 is defined by the width of the second part 132. The depth of the first opening V1 is greater than or equal to the depth of the source region 16. See [link to relevant documentation]. Figure 10a or Figure 10b As shown. To easily illustrate the position of the first opening V1, Figure 10a or Figure 10b Two trenches V0 are shown, and a first opening V1 between two adjacent trenches V0. The first opening V1 penetrates the source region 16 and extends into the well region 15.
[0092] Step S17 can be specifically described as follows: using the thinned second part 132 as a mask, dry etching is performed on the epitaxial layer 11 between adjacent trenches V0, with the etching depth being greater than the source region 16 and limited to the well region 15, forming the first opening V1. Clearly, the distance from the first opening V1 to the two trenches V0 is determined by the width of the second part 132, and the width of the second part 132 is determined by the width of the first region S1 multiplied by 1 (see...). Figure 4 The width x1 of the first region S1 is determined to be formed by wet etching of the first mask layer 121 with the trench V0 boundary self-aligned after the trench V0 is formed. Therefore, it is not affected by the change in the width of the trench V0, and is naturally not affected by the subsequent contact hole photolithography.
[0093] S18: A second dielectric layer 17 is formed above the gate structure (14, 14') and the second part, and the second dielectric layer 17 is patterned to form a second opening V2 penetrating the second dielectric layer 17. The second opening V2 corresponds to the first opening V1. See [link to documentation]. Figures 11a to 11b As shown, or Figures 12a to 12b As shown.
[0094] In some embodiments, step S18 may specifically involve: depositing an interlayer dielectric layer (ILD) as a second dielectric layer 17, the ILD covering the second portion 132, the first opening V1, and the gate structure (14, 14'), and then using photolithography to form a photoresist mask PR on the ILD, resulting in... Figure 11a or Figure 12a The structure shown, Figure 11a In the diagram, the two dashed lines between two adjacent trenches represent the boundaries of the photoresist mask PR used to form the electrode contact holes. The etching window between the two dashed lines corresponds to the first opening V1, and the etching window is larger than the first opening V1. Based on the photoresist mask PR, the interlayer dielectric layer (ILD) is etched to expose the first opening V1 again, resulting in the following... Figure 11b Or the structure shown in 12b, wherein the second opening V2 is connected to the first opening V1, or in other words, the first opening V1 is located at the bottom of the second opening V2, and the width of the second opening V2 is greater than the width of the first opening V1.
[0095] Among them, under the protection of the photoresist mask PR, the exposed interlayer dielectric layer ILD, such as the interlayer dielectric layer ILD partially located on the second part 132 and inside the first opening V1, can be removed to form an electrode contact hole. The electrode contact hole may include the first opening V1 and the second opening V2. Since the width of the second opening V2 is greater than that of the second opening V1, part of the second part 132 may also be etched in this step, and only the surface of the semiconductor substrate under this part of the second part 132 is exposed. That is, the semiconductor substrate can be used as an etch stop layer. Therefore, the electrode contact hole is generally in an inverted "convex" shape, and its actual effective area is the first opening V1. Therefore, due to the pre-formation of the first opening V1, even if there is an offset in the lithography alignment in the current step and the etch window is not completely centered with the first opening V1, it will not affect the effectiveness of the electrode contact hole, thus achieving the "self-alignment" of the electrode contact hole.
[0096] In addition, as Figure 11b and Figure 12b shown, due to the prior preparation of the first opening V1, during the formation of the photoresist mask PR, the etch window can be significantly larger than the size of the first opening V1, thereby reducing the dependence on high-precision lithography machines. Coupled with the reduction of the aspect ratio, the difficulty of etching to form the second opening V2 is also reduced to a certain extent. Compared with the scheme of directly forming a through hole with a high aspect ratio in the interlayer dielectric layer ILD, it can not only reduce the lithography and etching difficulties, improve the process tolerance, reduce the dependence on high-precision lithography machines, but also reduce the filling difficulty of the metal in the subsequent steps.
[0097] It should be noted that in the above embodiments, the interlayer dielectric layer ILD uses the same material as the second part 132. Therefore, while etching the interlayer dielectric layer ILD based on the photoresist mask PR, part of the second part 132 is also etched to obtain the structure shown in Figure 11b or 12b. In other embodiments, if the interlayer dielectric layer ILD and the second part 132 are made of different materials, all of the second part 132 can also be retained by controlling the etching selectivity ratio.
[0098] S19: Form the source metal 18. The source metal 18 is in electrical contact with the source region 16 through the first opening V1 and the second opening V2. Refer to the structure shown in Figure 13 or Figure 14 shown.
[0099] This step can specifically include: depositing a metal layer that fills the electrode contact hole and covers the surface of the interlayer dielectric layer ILD, and then performing patterning to obtain the source metal 18. Of course, in practice, a step-by-step method can also be used, first forming the first metal layer to fill the electrode contact hole, and then forming the second metal layer that covers the surface of the interlayer dielectric layer ILD.
[0100] In other embodiments, subsequent process steps may include wafer thinning, backside metallization, etc., wherein, depending on the device requirements, thinning may remove part or all of the substrate 10, and then a drain metal layer is formed on the backside of the wafer. All of the above are prior art and will not be elaborated further.
[0101] The method for fabricating a power semiconductor device provided in this application utilizes the different materials of the second mask layer 122 and the first mask layer 121. After etching the trench V0, the first mask layer 121 is etched with the trench V0 as the boundary, exposing the first surface area S1 of the semiconductor substrate. This results in a step difference (thickness difference) between the second part 132 and the first mask part 121' in the subsequently formed first dielectric layer. The thicker second part 132 serves as a self-aligned hard mask for the subsequent first opening V1, allowing the second opening V2 to have a relatively large width when etching to form the electrode contact hole. This ensures that the distance from the trench V0 to the electrode contact hole is largely unaffected by the trench V0 width, the critical contact hole lithography dimension CD, and the contact hole alignment deviation, thereby reducing reliance on high-end lithography machines. Using this method, the distance from the electrode contact hole to the trench V0 achieves extremely high consistency, avoiding the influence on parameters such as the threshold voltage. Even with a very small trench V0 spacing, parameters such as the threshold voltage will not fluctuate significantly due to random deviations in the trench V0 and contact hole processes.
[0102] Furthermore, compared with conventional preparation methods, since the size of the second opening V2 can be larger, the aspect ratio is reduced, thus reducing the etching difficulty.
[0103] This application also provides a power semiconductor device, see [link to relevant documentation] Figure 13 or Figure 14 In conjunction with other accompanying drawings, it may include:
[0104] A semiconductor substrate; a plurality of trenches V0 disposed in the semiconductor substrate and spaced apart; a gate structure (14, 14') disposed in the trenches V0, the gate structure (14, 14') including a gate dielectric layer and a gate, the gate dielectric layer being used to isolate the gate and the semiconductor substrate; a well region 15 disposed on both sides of the trenches V0 and a source region 16 disposed in the well region 15; a dielectric isolation portion disposed on the semiconductor substrate, the dielectric isolation portion being located on both sides of the trenches V0; a first opening V1 disposed in the semiconductor substrate on both sides of the trenches V0, the distance of the first opening V1 from the trenches V0 being defined by the width of the dielectric isolation portion; a dielectric layer covering the gate structure (14, 14') and the dielectric isolation portion, the dielectric layer having a second opening V2, the second opening V2 corresponding to the first opening V1, and the width of the second opening being greater than that of the first opening V1; a source metal 18, the source metal 18 being electrically contacted with the source region 16 through the first opening V1 and the second opening V2.
[0105] This power semiconductor device can be obtained using the fabrication method of the power semiconductor device described in the above embodiment. The dielectric isolation portion is obtained by thinning the second portion 132 of the first dielectric layer 13 during the fabrication process, or by partially etching the second portion 132 during the etching of the second opening V2. The dielectric layer can be, for example,... Figure 13 and Figure 14 The second dielectric layer 17 is obtained in the same way.
[0106] The technical solutions of this application have been described above with reference to the preferred embodiments shown in the accompanying drawings. However, it will be readily understood by those skilled in the art that the scope of protection of this application is obviously not limited to these specific embodiments. Without departing from the principles of this application, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will all fall within the scope of protection of this application.
Claims
1. A method for fabricating a power semiconductor device, characterized in that, include: A mask structure is formed on a semiconductor substrate, the mask structure comprising at least a first mask layer and a second mask layer stacked together, the first mask layer and the second mask layer being made of different materials; The semiconductor substrate is etched using the mask structure to form multiple spaced trenches; Selective etching is performed on the mask structure so that the first mask layer is partially etched to expose a first area on the surface of the semiconductor substrate, thereby forming a transverse groove between the semiconductor substrate and the second mask layer. The first mask layer left by the lateral etching is the first mask portion. A gate structure is formed in a trench and a second mask layer is removed. The formation of the gate structure includes forming a gate dielectric layer and forming a gate. The formation of the gate dielectric layer includes at least forming a first dielectric layer, which includes a first portion covering the trench sidewall and a second portion filling the transverse groove, and the thickness of the second portion is greater than the thickness of the first mask portion. A well region is formed in a semiconductor substrate between adjacent trenches, and a source region is formed in the well region; Remove the first mask portion to expose a second region on the surface of the semiconductor substrate, while retaining at least a portion of the second portion; A first opening is formed in a second region of the semiconductor substrate, the distance between the first opening and the trench is defined by the width of the second portion, and the depth of the first opening is greater than the depth of the source region; A second dielectric layer is formed on the gate structure and the second part, and the second dielectric layer is patterned to form a second opening through the second dielectric layer. The second opening corresponds to the first opening, and the width of the second opening is greater than that of the first opening. A source metal is formed, which is electrically contacted with the source region through the first opening and the second opening.
2. The preparation method according to claim 1, characterized in that, The mask structure further includes a third mask layer disposed on the second mask layer, the third mask layer being made of the same material as the first mask layer.
3. The preparation method according to claim 1 or 2, characterized in that, The semiconductor substrate is a silicon substrate, the first mask layer is a silicon oxide layer, and the second mask layer is a silicon nitride layer.
4. The preparation method according to claim 3, characterized in that, A thermal oxidation process is used to react and generate a silicon oxide layer in the first region on the trench sidewalls and the surface of the semiconductor substrate, which serves as the first dielectric layer.
5. The preparation method according to any one of claims 1-4, characterized in that, The sidewalls of both the first and second parts facing the center of the trench are closer to the center of the trench than the edge of the second mask layer adjacent to the trench.
6. The preparation method according to any one of claims 1-4, characterized in that, The process of forming a grid structure in the trench also includes: A first gate is formed in a trench in which the first dielectric layer is formed; An isolation dielectric layer is formed on top of the first gate; Remove the first dielectric layer that protrudes above the isolation dielectric layer on the sidewall of the trench; A third dielectric layer is formed on the sidewall of the trench, the third dielectric layer being higher than the isolation dielectric layer and connected to the isolation dielectric layer; A second gate is formed on the isolation dielectric layer.
7. The preparation method according to claim 6, characterized in that, The second gate is formed on the isolation dielectric layer, and the method further includes: A first polysilicon layer is formed in a trench located above the isolation dielectric layer, wherein the top surface of the first polysilicon layer is lower than the surface of the semiconductor substrate; The first polysilicon layer is thermally oxidized to form a silicon oxide layer in the top region of the first polysilicon layer, and the unoxidized first polysilicon layer serves as the second gate.
8. The preparation method according to any one of claims 1-4, characterized in that, The formation of the grid structure in the trench includes: A second polysilicon layer is formed in a trench in which the first dielectric layer is formed, and the top surface of the second polysilicon layer is lower than the surface of the semiconductor substrate; The second polysilicon layer is thermally oxidized to form a silicon oxide layer in the top region of the second polysilicon layer, and the unoxidized second polysilicon layer serves as the gate.
9. The preparation method according to claim 1 or 2, characterized in that, The removal of the first mask portion to expose the second region on the surface of the semiconductor substrate includes: Simultaneously etch the first mask portion and the second portion until the surface of the semiconductor substrate below the first mask portion is exposed, and thin the second portion is made.
10. A power semiconductor device, characterized in that, include: Semiconductor substrate; Multiple trenches located in and spaced apart in the semiconductor substrate; The gate structure located in the trench includes a gate dielectric layer and a gate, wherein the gate dielectric layer is used to isolate the gate and the semiconductor substrate; The well regions located on both sides of the trench and the source regions located within the well regions; A dielectric isolation portion located on the semiconductor substrate, the isolation dielectric portion being located on both sides of the trench; A first opening is located in the semiconductor substrate on both sides of the trench, and the distance between the first opening and the trench is defined by the width of the dielectric isolation portion; A dielectric layer covering the gate structure and the dielectric isolation portion, wherein the dielectric layer has a second opening corresponding to the first opening, and the width of the second opening is greater than the width of the first opening; The source metal is electrically contacted with the source region through the first opening and the second opening.