Transistor device, preparation method and electronic product
By designing a groove and a multi-step gate metal structure in GaN-based HEMT devices, the structural damage and leakage current path problems caused by electric field concentration are solved, thereby improving the reliability and high-frequency performance of the devices.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-29
- Publication Date
- 2026-03-27
AI Technical Summary
In GaN-based high electron mobility transistors (HEMTs), the maximum electric field of the device is concentrated at the edge of the gate near the drain, which leads to damage to the gate edge structure and leakage channels, affecting the reliability of the device and its small-signal AC characteristics. In addition, the parasitic capacitance of the traditional fin gate structure increases, affecting high-frequency performance.
Design a transistor device structure in which a groove is formed between every two adjacent fins, a dielectric layer covers the fins and the groove, a gate metal extends across the fins and the groove through the dielectric layer and forms an outwardly extending extension on the cross section, with multiple steps at the edge to optimize the electric field distribution.
It effectively disperses the electric field, reduces structural damage and leakage channels caused by concentrated high electric fields at the edges, improves device reliability, reduces leakage current, maintains high gate control capability and suppresses short-channel effects, and reduces parasitic capacitance.
Smart Images
Figure CN121751687A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a transistor device and its fabrication method, and electronic products. Background Technology
[0002] Currently, in the design of GaN-based high electron mobility transistors (HEMTs), the structural design of transistor devices is as follows: Figure 1 As shown, the maximum electric field of the device often occurs at the edge of the gate near the drain, which severely affects the breakdown characteristics of the device and easily causes damage to the gate edge structure. At the same time, under the drive of radio frequency signals, the gate current of the GaN transistor device in the on state increases exponentially, causing the Schottky contact to degrade. When the device operates continuously under radio frequency signals, a leakage channel is generated at the gate edge, resulting in a high gate leakage current, which will affect the long-term reliability of the device.
[0003] Meanwhile, as transistor sizes shrink and device operating frequencies increase, gate lengths become shorter, making the short-channel effect of traditional high electron mobility transistors (HEMTs) increasingly pronounced, and further challenging gate control capabilities. AlGaN / GaN HEMT devices fabricated using FinFET structures employ a three-dimensional structure, allowing the gate to wrap around the channel from three directions, improving gate control capability and mitigating the short-channel effect. However, compared to traditional planar gate structures, the three-dimensional Fin gate structure also exhibits increased parasitic capacitance, affecting the AC small-signal characteristics of the HEMT. Furthermore, while the Fin gate can further reduce gate length while maintaining stable gate control with increasing operating frequencies, the gate resistance also increases with decreasing gate length. Summary of the Invention
[0004] To address the existing technical problems, this application provides a transistor device and its fabrication method, as well as an electronic product, that are highly reliable, have low parasitic characteristics, and can be applied in high-frequency fields.
[0005] In a first aspect, embodiments of this application provide a transistor device, comprising: a substrate, a semiconductor stack, a dielectric layer, a gate metal, a source metal, and a drain metal; the semiconductor stack is disposed on the substrate, the semiconductor stack includes a source region, a drain region, and a plurality of fins, the fins being connected between the source region and the drain region; the source metal is located on the source region, and the drain metal is located on the drain region; A groove is formed between every two adjacent fins, the dielectric layer covers the fins and the grooves, and the gate metal extends through the dielectric layer in a first direction across the plurality of fins and the grooves; On the cross-section formed by the second direction and the third direction, outwardly extending portions are formed on both sides of the cross-sectional shape of the gate metal, and the edge of each extension portion includes at least two steps; wherein, the cross-sectional shape is the cross-sectional shape of the gate metal on the fin or in the groove; the second direction is the direction in which the semiconductor stack and the substrate are stacked, and the third direction is the direction in which the length of the fin extends.
[0006] In a second aspect, a method for fabricating a transistor device is provided, comprising: providing a substrate; forming a semiconductor stack on the substrate; forming fins and grooves by etching the semiconductor stack; depositing a dielectric layer on the fins and in the grooves; coating spaced first photoresist layers on the dielectric layer; forming openings in the dielectric layer through the spaced intervals between the first photoresist layers; coating spaced second photoresist layers above the first photoresist layers; evaporating gate metal into the spaced intervals between the first photoresist layers, the spaced intervals between the second photoresist layers, and the openings; forming a first step at the edge of the gate metal through the spaced intervals between the first photoresist layers, and forming a second step at the edge of the gate metal through the spaced intervals between the second photoresist layers; and removing the first photoresist layers and the second photoresist layers.
[0007] Thirdly, an electronic product is provided, including the transistor device described in any embodiment of this application.
[0008] Compared with the prior art, the technical solution provided in this application has at least the following beneficial effects: In the transistor device provided in the above embodiments, a groove is formed between every two adjacent fins. The dielectric layer covers the fins and the grooves, and the gate metal extends through the dielectric layer along a first direction spanning the plurality of fins and the grooves. In a cross-section formed by a second direction and a third direction, outwardly extending portions are formed on both sides of the cross-sectional shape of the gate metal, and the edge of each extension portion includes at least two steps. The cross-sectional shape is the cross-sectional shape on the fins and in the grooves. Thus, the gate metal has two or more steps on each side edge, so that compared with the edge design of a vertical plane, the multi-level steps can effectively disperse the electric field concentrated at the edge, making the electric field distribution more gentle and reducing structural damage and leakage channels caused by the high electric field concentrated at the edge. On this basis, the semiconductor stack based on the spaced structure of fins and grooves further reduces leakage current, and together with the structural design of the gate metal, optimizes the electric field distribution, reduces leakage current, and thus improves device reliability. In addition, this structure maintains the ability of the fin gate, that is, improves the gate control capability of the device and suppresses the short-channel effect of the device, and does not increase the gate resistance while reducing the gate length to improve frequency characteristics. Moreover, compared to traditional fin gate structures, it reduces the impact of parasitic capacitance on the device.
[0009] The preparation method and electronic product provided in the above embodiments belong to the same concept as the corresponding transistor device embodiments, and thus have the same technical effects as the corresponding transistor device embodiments, which will not be repeated here. Attached Figure Description
[0010] Figure 1 This is a schematic diagram of the cross-sectional structure of a transistor device along the second and third directions in the related technology. Figure 2 This is a top view of a transistor device in one embodiment of this application; Figure 3 This is a schematic diagram of the semiconductor stacked structure of a transistor device in one embodiment of this application; Figure 4 This is a schematic diagram of the cross-sectional structure of the gate metal on the fin along the second direction and the third direction in one embodiment of this application; Figure 5 This is a schematic diagram of the cross-sectional structure of the gate metal on the groove along the second direction and the third direction in one embodiment of this application; Figure 6 This is a schematic diagram of the cross-sectional dimensions of the gate metal along the second direction and the third direction in one embodiment of this application; Figure 7 This is a schematic diagram of the cross-sectional structure of the gate metal along the second direction and the third direction in another embodiment of this application; Figure 8This is a schematic diagram of the cross-sectional structure of the gate metal along the first and second directions in one embodiment of this application.
[0011] Explanation of reference numerals in the attached figures 1. Substrate; 2. Semiconductor stack; 21. Source region; 22. Drain region; 23. Fin; 24. Groove; 25. Buffer layer; 26. Channel layer; 27. Barrier layer; 3. Dielectric layer; 31. Opening; 4. Gate metal; 41. Step; 411. First step; 412. Second step; 42. Extension; 5. Source metal; 6. Drain metal. Detailed Implementation
[0012] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that, in order to more clearly illustrate the present invention, the accompanying drawings are not to scale.
[0013] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description of this application will be provided in conjunction with the accompanying drawings. The described embodiments should not be considered as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0014] In the following description, the phrase "some embodiments" refers to a subset of all possible embodiments. It should be noted that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.
[0015] In the following description, the terms "first," "second," and "third" are used merely to distinguish similar objects and do not represent a specific ordering of the objects. It is understood that "first," "second," and "third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.
[0016] One embodiment of this application provides a transistor device, including: a substrate 1, a semiconductor stack 2, a dielectric layer 3, a gate metal 4, a source metal 5, and a drain metal 6; The semiconductor stack 2 is disposed on the substrate 1 and includes a source region 21, a drain region 22 and a plurality of fins 23. The fins 23 are connected between the source region 21 and the drain region 22. The source metal 5 is located on the source region 21 and the drain metal 6 is located on the drain region 22. A groove 24 is formed between every two adjacent fins 23, the dielectric layer 3 covers the fins 23 and the grooves 24, and the gate metal 4 extends through the dielectric layer 3 in a first direction across the plurality of fins 23 and the grooves 24; On the cross-section formed by the second direction and the third direction, the cross-sectional shape of the gate metal 4 forms an outwardly extending extension 42, and the edge of each extension 42 includes at least two steps 41; the cross-sectional shape is the cross-sectional shape of the gate metal 4 on the fin 23 and / or in the groove 24; the second direction is the direction in which the semiconductor stack 2 and the substrate 1 are stacked, and the third direction is the direction in which the length of the fin 23 extends, that is, the gate length direction, that is, the direction from the source region 21 to the drain region 22.
[0017] In one embodiment, the substrate 1 can be made of materials such as gallium nitride (GaN), silicon (Si), silicon carbide (SiC), or sapphire. The semiconductor stack 2 can include at least a nucleation layer, a buffer layer 25, a channel layer 26, and a barrier layer 27. The nucleation layer is located on the substrate 1, the buffer layer 25 is located on the nucleation layer, the channel layer 26 is located on the buffer layer 25, and the barrier layer 27 is located on the channel layer 26. A two-dimensional electron gas (2DEG) is formed between the channel layer 26 and the barrier layer 27.
[0018] The channel layer 26 is also called the electron transit layer. The channel layer 26 can be an unintentionally doped gallium nitride layer. Specifically, the channel layer 26 can be unintentionally doped aluminum gallium nitride (AlXGa1-XN (0≤X<1)). More specifically, for example, the channel layer 26 is unintentionally doped gallium nitride (GaN), and its thickness ranges from 200 to 640 nm. This significantly improves the breakdown voltage characteristics of the transistor device, enabling the transistor to be used in higher voltage applications and achieve greater output power and efficiency. A barrier layer 27 is disposed on the channel layer 26. The barrier layer 27 is also called the electron supply layer. The band gap of the barrier layer 27 is larger than that of the channel layer 26. The barrier layer 27 is, for example, unintentionally doped aluminum gallium nitride (AlYGa1-YN (0<Y≤1, X<Y)). The thickness of the barrier layer 27 is, for example, between 2 nm and 100 nm. The channel layer 26 and the barrier layer 27 form a heterojunction interface. A two-dimensional electron gas (2DEG) is formed at the heterojunction interface.
[0019] In one embodiment, an insertion layer may be included between the channel layer 26 and the barrier layer 27, for example, the material of the insertion layer may be aluminum nitride (AlN).
[0020] In one embodiment, the source region 21 and the drain region 22 are located on both sides of the gate, the fin 23 is a single strip structure, the source metal 5 is located on the source region 21 and contacts the source region 21 to form an ohmic contact, and the drain metal 6 is located on the drain region 22 and contacts the drain region 22 to form an ohmic contact.
[0021] In one embodiment, the plurality of fins 23 are strip-shaped structures arranged parallel to each other along a first direction. The plurality of fins 23 can be structures with equal widths, and a groove 24 is formed between two adjacent fins 23. The length and width of different grooves 24 can be equal. In some embodiments, the length and width of different grooves 24 can also be unequal. Along the first direction, gate metal 4 fills the groove 24 between adjacent fins 23 and is deposited on the fins 23, that is, gate metal 4 surrounds the fins 23 on the top and two sides. A two-dimensional electron gas is formed at the fins 23, but no two-dimensional electron gas is formed at the grooves.
[0022] In this context, the first direction is also the extension direction of the gate metal 4, and the second direction can be the direction in which the semiconductor stack 2 and the substrate 1 are stacked, i.e., the direction perpendicular to the plane of the substrate 1. The length extension direction of the fin 23 can be a third direction, and the source metal 5, gate metal 4, and drain metal 6 can be arranged along the third direction. The plane formed by the first direction and the third direction is a plane parallel to the substrate 1 and the semiconductor stack 2. The cross-section formed by the second direction and the third direction is perpendicular to the first direction. The length of the fin 23 and the groove 24 refers to the dimension in the third direction, and the width refers to the dimension in the first direction. The length of the gate metal 4 refers to the dimension in the first direction, and the width refers to the dimension in the third direction.
[0023] In one embodiment, a top view of the transistor device is as follows: Figure 2 As shown, a schematic diagram of semiconductor stack 2 in a transistor device is as follows. Figure 3 As shown, the first direction is direction A, the second direction is direction B, and the third direction is direction C.
[0024] In one embodiment, the transistor device described in any embodiment of this application is a GaN transistor device.
[0025] In one embodiment, the source metal 5, gate metal 4, and drain metal 6 are all made of metal. The source metal 5 and drain metal 6 are of the same material type, both being composite metal thin film structures, forming an ohmic contact with the semiconductor stack 2. The gate metal 4 is of a different material type than the source metal 5 / drain metal 6, also being a composite metal thin film structure, forming a Schottky contact with the semiconductor stack 2. The buffer layer 25 may be made of GaN, etc., the channel layer 26 may be made of GaN, etc., and the barrier layer 27 may be made of AlGaN, AlN, InAlGaN, or InAlN, etc. The dielectric layer 3 may be made of any one or more of silicon nitride (SiN), silicon dioxide (SiO2), AlN, and Al2O3.
[0026] In one embodiment, the thickness of the nucleation layer can be 10 nm to 50 nm, the thickness of the buffer layer 25 can be 100 nm to 1000 nm, the thickness of the channel layer 26 can be 100 nm to 300 nm, and the thickness of the barrier layer 27 can be 3 nm to 50 nm. Here, the thickness refers to the thickness along the second direction.
[0027] In one embodiment, the gate metal 4 is disposed on the fin 23 through the dielectric layer 3 and within the recess 24 through the dielectric layer 3. The term "disposed within the recess 24 through the dielectric layer 3" can refer to the dielectric layer 3 being disposed on the exposed portion of the etched semiconductor stack 2 within the recess 24 or on the exposed substrate 1 within the recess 24. The gate metal 4 on the fin 23 can be in contact with the fin 23, i.e., a Schottky contact; for example, the gate metal 4 forms a Schottky contact with the barrier layer 27.
[0028] The dielectric layer 3 covering the groove 24 can refer to the dielectric layer 3 covering the substrate 1 or semiconductor stack 2 exposed in the groove 24, for example, covering the buffer layer 25 exposed in the groove 24.
[0029] In one embodiment, the groove 24 may be a region formed by etching the semiconductor stack 2. The substrate 1 may be exposed by etching all of the semiconductor stack 2 within the groove 24, or a portion of the semiconductor stack 2 may be etched. For example, a buffer layer 25 may be exposed within the groove 24. The gate metal 4 may contact the buffer layer 25 within the groove 24.
[0030] In one embodiment, the depth of the groove 24 is 0.1 μm to 1 μm. Here, the depth refers to the depth along the second direction. The groove 24 is formed by etching the semiconductor stack 2, and the etching depth exceeds the interface between the barrier layer and the channel layer, so that the semiconductor stack below the groove 24 fails to form a two-dimensional electron gas.
[0031] In one embodiment, in a cross-section along the second direction of the stacking of the semiconductor stack 2 and the substrate 1, referring to the cross-section formed by the second direction and the third direction, the cross-sectional shape formed by the gate metal 4 in this cross-section includes at least two steps 41 (411, 412) on each of the two side edges. Here, "two side edges" refers to the side closer to the source metal 5 and the side closer to the drain metal 6.
[0032] In one embodiment, the dielectric layer 3 above the fin 23 may have an opening 31 through which the gate metal 4 contacts the semiconductor stack 2, for example, the barrier layer 27. The dielectric layer 3 covering the groove 24 is located on the semiconductor stack 2 exposed in the groove 24 and may also have an opening 31 through which the gate metal 4 contacts the semiconductor stack 2 exposed in the groove 24.
[0033] In one embodiment, the gate metal 4 may have the same cross-sectional shape on the fin 23 and the recess 24. For example, the cross-sectional shape may include a first portion located within the opening 31 on the dielectric layer 3 and a second portion located above the dielectric layer 3. The second portion may include two outwardly extending extensions 42. "Outwardly extending" means extending to both sides, with both sides referring to the side closer to the source metal 5 and the side closer to the drain metal 6. For example, the extensions 42 may include an extension 42 extending towards the source metal 5 relative to the first portion and an extension 42 extending towards the drain metal 6 relative to the first portion.
[0034] In one embodiment, on the cross section, based on the outwardly extending extension 42, the dimension of the second part along the third direction is greater than the dimension of the first part along the third direction, that is, the cross-sectional shape of the gate metal 4 is formed as a structure that is wider at the top and narrower at the bottom, with the upper part being above the substrate 1 and the semiconductor stack 2 in the stacking direction, and the lower part being below the substrate 1 and the semiconductor stack 2 in the stacking direction.
[0035] In one embodiment, the cross-sectional shape includes at least two steps 41 on each side edge, which may include a first step 411 and a second step 412. For example, the extension 42 on each side edge is formed as a first step 411 between itself and the dielectric layer 3, and the top edge of the extension 42 is formed as a second step 412.
[0036] In one embodiment, the second part may further include a connecting segment connecting the two extensions 42. The portion at the top where the two extensions 42 of the aforementioned cross-sectional shape meet via the connecting segment may be formed as a downwardly recessed shape. For example, there may be a height difference between the highest point of the extension 42 and the highest point on the central axis of the cross-sectional shape, meaning the height of the extension 42 in the second direction may be greater than the height of the connecting segment in the second direction. Here, the central axis refers to the central axis along the second direction, and the central axis of the aforementioned cross-sectional shape may coincide with the central axis of the connecting segment.
[0037] Thus, the gate metal 4 has two or more steps 41 on each of its two sides. Compared to the edge design of a vertical plane, the multi-step design can effectively disperse the electric field concentrated at the edge, making the electric field distribution more gradual and reducing structural damage and leakage paths caused by the high electric field concentrated at the edge. On this basis, the semiconductor stack 2 further reduces leakage current based on the spaced structure of the fins 23 and the grooves 24. Together with the structural design of the gate metal 4, it optimizes the electric field distribution, reduces leakage current, and thus improves device reliability.
[0038] In some embodiments, in a cross-section formed by the second direction and the third direction, the fin 23 includes at least a channel layer 26 and a barrier layer 27 disposed on the substrate 1. For example, the fin 23 includes a buffer layer 25 disposed on the substrate 1, a channel layer 26 disposed on the buffer layer 25, and a barrier layer 27 disposed on the channel layer 26.
[0039] An opening 31 is provided in the dielectric layer 3, and the opening 31 at the fin 23 extends to the barrier layer 27. The gate metal 4 contacts the barrier layer 27 through the opening 31 at the fin 23. Here, it can refer to the opening 31 on the dielectric layer 3 located on the fin 23 extending to the barrier layer 27.
[0040] In one embodiment, the opening 31 extends through the entire dielectric layer 3, allowing the gate metal 4 to contact the underlying semiconductor stack 2. The opening 31 may have an edge perpendicular to the semiconductor stack 2, for example, the side of the opening 31 in the dielectric layer 3 may be perpendicular to the barrier layer 27. The gate metal 4 fills the opening 31 and contacts the barrier layer 27, for example, a first portion of the gate metal 4 fills the interior of the opening 31.
[0041] In one embodiment, such as Figure 4 As shown, along Figure 2A cross-sectional diagram along the C1 direction, specifically the section formed by the second and third directions, shows the portion of the gate metal 4 located above the dielectric layer 3. This gate metal 4 can contact the upper surface of the dielectric layer 3 via a first step 411. For example, the first step 411 is located outside the side edge of the opening 31, thus forming a contact surface with the upper surface of the dielectric layer 3. Specifically, the first step 411 closer to the source metal 5 is closer to the source metal 5 than the edge of the opening 31 on that side; similarly, the first step 411 closer to the drain metal 6 is closer to the drain metal 6 than the edge of the opening 31 on that side. Here, the upper surface refers to the surface facing away from the substrate 1.
[0042] In one embodiment, the second step 412 may be located outside the first step 411 on the same side, that is, the second step 412 on the side closer to the source metal 5 is closer to the source metal 5 than the first step 411 on that side; the second step 412 on the side closer to the drain metal 6 is closer to the drain metal 6 than the first step 411 on that side.
[0043] In some embodiments, the semiconductor stack 2 below the groove 24 does not form a two-dimensional electron gas; in the cross section formed by the second direction and the third direction, the gate metal 4 is disposed within the opening 31 at the groove 24.
[0044] For example, such as Figure 5 As shown, along Figure 2 A cross-sectional view along the C2 direction shows that the groove 24 includes a buffer layer 25 disposed on the substrate 1; an opening 31 is provided on the dielectric layer 3, the opening 31 extends to the buffer layer 25, and the gate metal 4 contacts the buffer layer 25 through the opening 31.
[0045] In one embodiment, the opening 31 extends through the entire dielectric layer 3, allowing the gate metal 4 to contact the underlying semiconductor stack 2. The opening 31 may have edges perpendicular to the semiconductor stack 2; for example, the side of the opening 31 in the dielectric layer 3 may be perpendicular to the underlying buffer layer 25. The gate metal 4 fills the opening 31 and contacts the buffer layer 25; for example, a first portion of the gate metal 4 may fill the interior of the opening 31.
[0046] Thus, the gate metal 4 can span multiple fins 23 and grooves 24 in the fin structure, thereby increasing the control area of the gate metal 4 over the fins 23 (i.e., the channel) based on the grooves 24 above and on both sides of the fins 23, thereby maintaining the high linearity of the device.
[0047] In some embodiments, in a cross-section formed by the second direction and the third direction, the cross-sectional shape of the gate metal 4 includes at least a first step 411 formed on the dielectric layer 3 based on the opening 31 and a second step 412 formed on the edge of the extension 42 based on the extension 42.
[0048] Here, step 41 includes a first step 411 and a second step 412. The cross-sectional shape includes at least the first step 411 and the second step 412 on both the edge near the drain metal 6 and the edge near the source metal 5.
[0049] In one embodiment, in the third-party direction, the first step 411 is located between the edge of the opening 31 and the second step 412 on the same side as the first step 411. That is, on the same side edge of the aforementioned cross-sectional shape, the first step 411 is located outside the edge of the opening 31, and the second step 412 is located outside the first step 411. "Outside" refers to the side away from the opening 31 or away from the first portion.
[0050] In one embodiment, the distance between the second steps 412 on both sides is greater than the distance between the first steps 411 on both sides. The distance between the first steps 411 on both sides is greater than the distance between the two sides of the opening 31. Here, distance refers to the maximum distance along a third direction.
[0051] Thus, the gate metal 4 portion within the opening 31, based on the outwardly extending extension 42, not only forms multiple steps 41 at the side edge to disperse the electric field distribution and reduce gate leakage current, but also the outwardly extending extension 42 forms a gate metal 4 structure that is wider at the top and narrower at the bottom. Furthermore, the width of the first step 411 in the third direction is smaller than the width of the second step 412. The contact surface between the gate metal 4 and the dielectric layer 3 is defined only by the first step 411, thereby reducing parasitic capacitance based on a smaller overlapping area and further improving reliability.
[0052] In one embodiment, such as Figure 4 and 5 As shown, on the same side of the cross-sectional shape of the gate metal 4, the edge of the portion where the first step 411 and the second step 412 meet is arc-shaped, and the extensions 42 on both sides of the edge and the portion of the gate metal 4 located within the opening 31 form a Y-shape. Here, "the same side" refers to either the side closer to the source metal or the side closer to the drain metal. The portion of the gate metal 4 located within the opening 31 is the aforementioned first portion.
[0053] Here, the extensions 42 on both sides and the first part form a Y-shape, which means that the extensions 42 on both sides form a branch structure that extends obliquely upward on both sides of the Y-shape, and the first part can form a structure along the vertical direction in the Y-shape.
[0054] In one embodiment, the width of the second portion of the gate metal 4 located above the dielectric layer 3 is greater than the width of the first portion located within the opening 31; for example, the minimum width of the second portion is greater than the width of the first portion. Here, width refers to the dimension along a third direction. In the second portion, the first step 411 and the second step 412 located on the same side can be connected by an arc-shaped edge.
[0055] The second part may include two extensions 42 located on both sides and a connecting segment connecting the two extensions 42 together, wherein the central axis of the connecting segment may coincide with the central axis of the first part.
[0056] In one embodiment, when the gate metal 4 is Y-shaped, the angle α between the extension 42 and the plane containing the dielectric layer 3 is 30° to 80°. This angle α can be the angle between the axis of the extension 42 and the plane containing the dielectric layer 3, or it can be the angle between the tangent at the junction of the extension 42 and the dielectric layer 3 and the plane containing the dielectric layer 3, or it can be the angle between the line connecting the vertices of the two steps 41 on the extension 42 and the plane containing the dielectric layer 3, for example... Figure 6 As shown.
[0057] In one embodiment, the extensions 42 on both sides are mirror-symmetrical. The first steps 411 on both sides are mirror-symmetrical, and / or, the second steps 412 on both sides are mirror-symmetrical. For example, mirror symmetry refers to mirror symmetry based on the central axis of the portion of the gate metal 4 located within the opening 31.
[0058] Thus, based on the two steps 41 at the edge and the outward extension 42, a Y-shape extending obliquely upward is formed, thereby reducing the gate leakage current by dispersing the electric field distribution, reducing the overlapping area and thus reducing the parasitic capacitance, and further improving reliability.
[0059] In one embodiment, such as Figure 6 As shown, in the cross-section formed by the second direction and the third direction, the vertical distance L1 between the vertex of the first step 411 and the edge of the opening 31 on the same side is 50nm~200nm; the vertical distance is the distance along the length extension direction of the fin 23. The vertex of the first step 411 refers to the vertex of the angle formed by the first step 411, which is also the point farthest from the opening 31 or the first part on the interface between the extension 42 and the dielectric layer 3.
[0060] In this way, compared to the traditional planar structure where only the gate field plate on the upper side can optimize the electric field, the above structure not only optimizes the electric field on the upper side of the channel, but also the first step 411 on both sides of the channel acts as a gate field plate, which further improves the overall electric field optimization effect and reduces the electric field peak on the drain side of the gate.
[0061] Here, the direction of the length extension of the fin 23 is the aforementioned third direction.
[0062] In one embodiment, the value of L1 on the gate metal 4 can be different on different sides. For example, the L1 on the side closer to the drain region 22 can be greater than the L1 on the side closer to the source region 21, thereby ensuring the suppression effect of leakage current towards the drain region 22.
[0063] In one embodiment, on the cross-section formed by the second direction and the third direction, the vertical distance L2 between the vertex of the second step 412 and the edge of the opening 31 on the same side is 100nm~800nm; the vertical distance is the distance along the length extension direction of the fin 23. The vertex of the second step 412 refers to the vertex of the angle formed by the second step 412, which is also the point on the extension 42 farthest from the opening 31 or the first part.
[0064] In this way, the above structure forms the second step 412 on both sides of the channel as a gate field plate, which also plays a role in optimizing the electric field and further improves the electric field optimization effect to reduce the electric field peak on the drain side of the gate.
[0065] In one embodiment, the value of L2 on the gate metal 4 can be different on different sides. For example, the L2 on the side closer to the drain region 22 can be greater than the L2 on the side closer to the source region 21. As the length of L2 increases, the electric field peak on the drain side of the gate can be adjusted, thereby reducing the strong electric field on the gate-drain side and further suppressing the leakage current.
[0066] In one embodiment, the gate length L3 of the gate metal 4 is 50nm to 600nm, where L3 refers to the length of the first portion of the gate metal 4 within the opening 31 along the second direction, that is, the length between the two edges of the opening 31 along the second direction. Thus, the gate length can be adjusted according to the channel width, which is the width d1 of the fin 23 along the first direction. For example, the value of d1 can range from 80nm to 150nm. The gate length can vary positively with the channel width; the wider the channel width, the larger the gate length L3 can be. Therefore, based on a gate length that matches the dimensions for different channel widths, effective control of the two-dimensional electron gas within the channel can be achieved.
[0067] Here, the central axis of the opening 31 can also be the central axis of the first part of the gate metal 4 within the opening 31, or it can be the central axis of the gate metal 4. The central axis refers to the central axis along the second direction.
[0068] In some embodiments, such as Figure 7 As shown, the edge of the portion where the first step 411 and the second step 412 meet is straight, and the extension portion 42 on both sides and the portion of the gate metal 4 located in the opening 31 form a T-shape.
[0069] Here, the extensions 42 on both sides of the gate metal 4 and the portion of the gate metal 4 located within the opening 31 form a T-shape. This can refer to the extensions 42 on both sides of the gate and the portion between the extensions 42 forming a T-shape along the horizontal direction (i.e., the third direction), and the portion located within the opening 31 forming a T-shape along the vertical direction.
[0070] In one embodiment, the width of the second portion of the gate metal 4 above the dielectric layer 3 is greater than the width of the first portion located within the opening 31; for example, the minimum width of the second portion is greater than the width of the first portion. Here, width refers to the width along a third direction. In the second portion, the first step 411 and the second step 412 located on the same side can be connected by a straight edge.
[0071] The second part may include two extensions 42 located on both sides, and a connecting segment connecting the two extensions 42 together. The central axis of the connecting segment may coincide with the central axis of the first part. The second part may be formed into a trapezoidal shape that is narrower at the top and wider at the bottom.
[0072] In one embodiment, in the third direction, the second step 412 is located between the edge of the opening 31 on the same side as the first step 411 and the first step 411. That is, on the same side edge of the aforementioned cross-sectional shape, the second step 412 is located outside the edge of the opening 31, and the first step 411 is located outside the second step 412. "Outside" refers to the side away from the opening 31 or away from the first portion.
[0073] In one embodiment, the distance between the first steps 411 on both sides is greater than the distance between the second steps 412 on both sides. The distance between the second steps 412 on both sides is greater than the distance between the two sides of the opening 31. Here, distance refers to the maximum distance along a third direction.
[0074] In one embodiment, the height of the portion where the two extensions 42 meet on both sides can be lower than the height of the extensions 42, meaning there is a height difference between the highest point of the extension 42 and the highest point on the central axis of the cross-sectional shape. For example, the two extensions 42 of the aforementioned cross-sectional shape can be concave at their top junction. Height refers to the height along the second direction.
[0075] In one embodiment, such as Figure 8 As shown, along Figure 2 A cross-sectional view along direction A1, i.e., a cross-sectional view parallel to the plane formed by the first and second directions. In this view, the etched semiconductor stack 2 to a portion of the buffer layer 25 forms a groove 24.
[0076] In one embodiment, the width d1 of the fin 23 along the first direction is greater than 80 nm. For example, the value of d1 ranges from 80 nm to 500 nm.
[0077] Thus, d1 defines the channel width. The channel is formed through etching. When the channel width is too narrow, the etching process introduces damage and relaxation phenomena in the fin material 23, resulting in the absence of two-dimensional electron gas in the channel and device failure. Setting a width of not less than 80nm can effectively avoid the above situation. Furthermore, as the channel width increases, the gate metal 4's control over the two-dimensional electron gas in the channel weakens, which may lead to problems such as increased device leakage current.
[0078] In one embodiment, the channel width is no higher than 150 nm, resulting in low leakage current in the device. The channel width range forms a nanochannel design. By combining the above structure with the nanochannel design, leakage current can be further reduced, and the electric field distribution can be optimized together with the gate metal structure design.
[0079] In some embodiments, the gate metal 4 may be formed by: coating spaced first photoresist layers on the dielectric layer 3; forming an opening 31 on the dielectric layer 3 through the space between the first photoresist layers; coating spaced second photoresist layers above the first photoresist layers; depositing the gate metal 4 into the space between the first photoresist layers, the space between the second photoresist layers, and the opening; forming a first step 411 at the edge of the gate metal through the space between the first photoresist layers, and forming a second step 412 at the edge of the gate metal through the space between the second photoresist layers.
[0080] In one embodiment, the width of the groove 24 along the first direction is d2, and the value of d2 ranges from 3μm to 10μm.
[0081] Thus, the width d2 of the groove 24 defines the spacing between adjacent fins 23, i.e., the spacing between channels. Since the Y-shaped gate metal requires a thicker photoresist layer compared to traditional gate processes, this embodiment achieves this by coating two layers of photoresist and performing two photolithography steps. The total thickness of the photoresist layer exceeds 1 μm, and photoresist is coated on both sides of the channel. Setting a minimum spacing of 3 μm significantly reduces the complexity of the process. Furthermore, as the channel spacing increases, the device area increases, leading to increased costs. Setting the spacing to no more than 10 μm avoids excessive costs.
[0082] In one embodiment, the distance d3 between the edge of the groove 24 near the source region 21 and the source region 21 is in the range of 0.2μm to 2μm.
[0083] Thus, d3 defines the distance between the channel and the source metal 5. Since the source is the source of electrons, there is no nanochannel within the d3 distance, resulting in a larger two-dimensional electron gas. As the d3 distance increases, the concentration of the two-dimensional electron gas increases, providing more electrons. If the d3 value is too small, edge damage and relaxation of the fin 23 may occur due to etching or other reasons, reducing the concentration of the two-dimensional electron gas and leading to a low device saturation current. Therefore, a value not less than 0.2 μm is set to avoid the above situation. In addition, as the d3 distance increases, the gate-source spacing increases, the gate-source resistance increases, and the device transconductance decreases, leading to a degraded device performance. Therefore, a value not exceeding 2 μm is set to avoid the above situation.
[0084] In one embodiment, the distance d4 between the gate metal 4 covering the groove 24 and the edge of the groove 24 near the source region 21 ranges from 0.1 μm to 2 μm.
[0085] Thus, d4 defines the distance between the gate metal 4 and the edge of the nanochannel on one side of the source region 21. If the value of d4 is too small, it may cause edge damage and relaxation of the fin 23 due to etching or other reasons, reducing the concentration of the two-dimensional electron gas and resulting in a low device saturation current. Therefore, it is set to be no less than 0.1 μm to avoid the above situation. In addition, as the distance of d4 increases, the gate-source spacing increases, the gate-source resistance increases, and the device transconductance decreases, resulting in a decrease in device performance. Therefore, it is set to be no more than 2 μm to avoid the above situation.
[0086] In the above embodiments, d1, d2, d3, and d4 are as follows: Figure 2 The parameters marked in the document.
[0087] This application also provides a method for fabricating a transistor device, the method including: Provide substrate; A semiconductor stack is formed on the substrate; Fins and grooves are formed by etching the semiconductor stack; A medium layer is deposited on the fin and within the groove; A first photoresist layer with spacing is coated on the dielectric layer; An opening is formed on the dielectric layer through the spacing between the first photoresist layers; A second photoresist layer with spacing is coated above the first photoresist layer; Gate metal is deposited into the spacing between the first photoresist layers, the spacing between the second photoresist layers, and the opening; the spacing between the first photoresist layers forms a first step at the edge of the gate metal, and the spacing between the second photoresist layers forms a second step at the edge of the gate metal. Remove the first photoresist layer and the second photoresist layer.
[0088] In one embodiment, the above-described preparation method can produce the transistor device described in any embodiment of this application.
[0089] In one embodiment, coating the spaced first photoresist layer on the dielectric layer may include: coating the first photoresist layer on the dielectric layer and performing photolithography on the first photoresist layer by exposure and development to form the spaced first photoresist layer.
[0090] In one embodiment, forming an opening in the dielectric layer may include removing a portion of the dielectric layer to form an opening in the dielectric layer by adjusting at least one of the etching power, carrier gas, and flow rate.
[0091] In one embodiment, coating a spaced second photoresist layer over the first photoresist layer may include: coating a second photoresist layer over the first photoresist layer, and performing photolithography on the first photoresist layer by exposure and development to form the spaced second photoresist layer.
[0092] In one embodiment, removing the first photoresist layer and the second photoresist layer can be done by using an organic solvent.
[0093] In one embodiment, before coating a second photoresist layer spaced apart above the first photoresist layer, the method further includes: hardening the surface of the first photoresist layer using plasma. This hardening of the first photoresist layer surface facilitates the coating of the second photoresist layer onto the first photoresist layer.
[0094] Thus, the gate metal has two or more steps on each of its two edges. Compared to a vertical plane edge design, the multi-step approach effectively disperses the electric field concentrated at the edges, resulting in a smoother electric field distribution and reducing structural damage and leakage paths caused by high electric fields concentrated at the edges. Building on this, the semiconductor stack, with its spaced fin and groove structure combined with a nanoscale channel design, further reduces leakage current. Together with the gate metal's structural design, this optimizes the electric field distribution, reduces leakage current, and improves device reliability.
[0095] In other embodiments, after the semiconductor stack 2 is formed on the substrate, a passivation layer is also provided for protection. That is, when the fins 23 and the grooves 24 are formed by etching the semiconductor stack, the passivation layer protects the semiconductor stack 2. Viewed from the gate length direction, the gate root sides of the gate metal 4 at the fins 23 include a passivation layer and a dielectric layer 3, while the gate root sides of the gate metal 4 at the grooves 24 include a dielectric layer 3.
[0096] It should be noted that a dielectric layer 3 can be disposed below the gate root of the gate metal 4 at the groove 24.
[0097] This application also provides an electronic product, including the transistor device described in any one or more embodiments of this application, and / or including the transistor device prepared by the transistor device preparation method described in any one or more embodiments of this application.
[0098] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0099] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A transistor device, characterized in that, include: Substrate, semiconductor stack, dielectric layer, gate metal, source metal, and drain metal; The semiconductor stack is disposed on the substrate, and the semiconductor stack includes a source region, a drain region, and a plurality of fins, the fins being connected between the source region and the drain region; the source metal is located on the source region, and the drain metal is located on the drain region; A groove is formed between every two adjacent fins, the dielectric layer covers the fins and the grooves, and the gate metal extends through the dielectric layer in a first direction across the plurality of fins and the grooves; On the cross-section formed by the second direction and the third direction, outwardly extending portions are formed on both sides of the cross-sectional shape of the gate metal, and the edge of each extension portion includes at least two steps; wherein, the cross-sectional shape is the cross-sectional shape of the gate metal on the fin or in the groove; the second direction is the direction in which the semiconductor stack is stacked with the substrate, and the third direction is the direction in which the length of the fin extends.
2. The transistor device according to claim 1, characterized in that, In a cross section formed by the second direction and the third direction, the fin includes at least a channel layer disposed on the substrate and a barrier layer disposed on the channel layer; An opening is provided in the dielectric layer, and the opening at the fin extends to the barrier layer, and the gate metal contacts the barrier layer through the opening at the fin; The semiconductor stack beneath the groove did not form a two-dimensional electron gas; In the cross-section formed by the second direction and the third direction, the gate metal is disposed within the opening at the groove.
3. The transistor device according to claim 2, characterized in that, In the cross-section formed by the second direction and the third direction, the cross-sectional shape of the gate metal includes at least a first step formed at the dielectric layer based on the opening on each side edge, and a second step formed at the edge of the extension based on the extension.
4. The transistor device according to claim 3, characterized in that, The edge of the portion where the first step and the second step meet is arc-shaped, and the extension portion of the two side edges and the portion of the gate metal located in the opening form a Y-shape.
5. The transistor device according to claim 4, characterized in that, On the cross section formed by the second direction and the third direction, the vertical distance between the vertex of the first step and the edge of the opening on the same side is 50nm~200nm; the vertical distance is the distance along the length extension direction of the fin.
6. The transistor device according to claim 4, characterized in that, On the cross section formed by the second direction and the third direction, the vertical distance between the vertex of the second step and the edge of the opening on the same side is 100nm~800nm; the vertical distance is the distance along the length extension direction of the fin.
7. The transistor device according to claim 3, characterized in that, The edge of the portion where the first step and the second step meet is straight, and the extension portion of the two side edges and the portion of the gate metal located in the opening form a T-shape.
8. The transistor device according to claim 1, characterized in that, The groove has a width of 3μm to 10μm along the first direction; the fin has a width of more than 80nm along the first direction.
9. The transistor device according to claim 1, characterized in that, The distance between the edge of the groove near the source region and the source region is 0.2μm~2μm.
10. The transistor device according to claim 1, characterized in that, The distance between the gate metal covering the groove and the edge of the groove near the source region is 0.1 μm to 2 μm.
11. The transistor device according to claim 1, characterized in that, The transistor device is a GaN transistor device.
12. A method for fabricating a transistor device, characterized in that, The method includes: Provide substrate; A semiconductor stack is formed on the substrate; Fins and grooves are formed by etching the semiconductor stack; A medium layer is deposited on the fin and within the groove; A first photoresist layer with spacing is coated on the dielectric layer; An opening is formed on the dielectric layer through the spacing between the first photoresist layers; A second photoresist layer with spacing is coated above the first photoresist layer; Gate metal is deposited into the spacing between the first photoresist layers, the spacing between the second photoresist layers, and the opening; the spacing between the first photoresist layers forms a first step at the edge of the gate metal, and the spacing between the second photoresist layers forms a second step at the edge of the gate metal. Remove the first photoresist layer and the second photoresist layer.
13. An electronic product, characterized in that, The transistor device includes any one of claims 1 to 11.