MOSFET device and preparation method of MOSFET device

Abstract

The invention provides an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) device and a preparation method of the MOSFET device. The MOSFET device comprises a substrate, an epitaxial layer, a trench gate structure, a source electrode structure and a drain electrode structure, wherein the epitaxial layer is located on one side of the substrate; the trench gate structure is located in the epitaxial layer, the width of the trench gate structure is gradually increased in the direction from the substrate to the epitaxial layer, the trench gate structure comprises a polysilicon gate, a first gate dielectric layer, a second gate dielectric layer and a gate electrode, and the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer; the source electrode structure is located at one side, far away from the substrate, of the epitaxial layer and one side, far away from the substrate, of the trench gate structure; the drain structure is located on one side of the substrate away from the epitaxial layer. According to the MOSFET device provided by the invention, the performance of the MOSFET device can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a MOSFET device and a preparation method of the MOSFET device. BACKGROUND

[0002] At present, the MOSFET device is mainly applied in the fields of new energy vehicles and photovoltaic power generation. However, the gate oxide layer at the bottom of the trench bears a very high electric field and is easy to be damaged, which affects the long-term performance and stability of the device. In addition, the complex structure and process bring high cost, and at the same time, the energy consumption cannot be effectively reduced, which constitutes an obstacle to large-scale application.

[0003] To solve the above problems, the present application provides a MOSFET device.

[0004] The above information disclosed in the background section is only used to enhance the understanding of the background of the technology described herein, therefore, the background section can contain some information which is not known to those skilled in the art. SUMMARY

[0005] The main purpose of the present application is to provide a MOSFET device and a preparation method of the MOSFET device, so as to solve the problem of how to improve the performance of the MOSFET device in the prior art.

[0006] In order to achieve the above purpose, according to one aspect of the present application, a MOSFET device is provided, comprising: a substrate; an epitaxial layer located on one side of the substrate; a trench gate structure located in the epitaxial layer, the width of the trench gate structure gradually increases in the direction of the substrate pointing to the epitaxial layer, the trench gate structure comprises a polysilicon gate, a first gate dielectric layer, a second gate dielectric layer and a gate electrode, the second gate dielectric layer is located on the side of the first gate dielectric layer away from the substrate, the gate electrode is located on the side of the second gate dielectric layer away from the first gate dielectric layer, in the thickness direction perpendicular to the substrate, the polysilicon gate is located at the outer periphery of the second gate dielectric layer, the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer; a source structure located on the side of the epitaxial layer away from the substrate and the side of the trench gate structure away from the substrate; a drain structure located on the side of the substrate away from the epitaxial layer.

[0007] Optionally, the trench gate structure satisfies at least one of the following: the depth of the trench gate structure is 1-3 μm; the thickness of the first gate dielectric layer is 0.05-0.2 μm; the thickness of the second gate dielectric layer is 0.8-2.95 μm.

[0008] Optionally, the trench gate structure comprises a first level trench and a second level trench, the second level trench is located on a side of the first level trench away from the substrate, the first gate dielectric layer is located in the first level trench, the second gate dielectric layer is located in the first level trench and the second level trench, and the second level trench is located on a side of the first level trench away from the substrate.

[0009] Optionally, in a direction perpendicular to the thickness direction of the substrate, the width of the second level trench is 1.5:1-3:1 of the width of the first level trench.

[0010] Optionally, the trench gate structure satisfies at least one of the following: in a direction perpendicular to the thickness direction of the substrate, the width of the trench gate structure is 0.2-1.5 μm; in a direction perpendicular to the thickness direction of the substrate, the width of the polysilicon gate is 0.2-1 μm.

[0011] Optionally, the trench gate structure further comprises a third gate dielectric layer located on a side of the first gate dielectric layer close to the substrate and a side wall of the trench gate structure.

[0012] Optionally, the thickness of the third gate dielectric layer is 300-800 angstroms.

[0013] Optionally, the MOSFET device further comprises a first doped region, a second doped region and a third doped region, the first doped region, the second doped region and the third doped region are located in the epitaxial layer, the first doped region is located on a side of the second doped region and the third doped region close to the substrate, and in a direction perpendicular to the thickness of the substrate, the third doped region is located between the second doped region and the trench gate structure, wherein the doping type of the first doped region is the same as the doping type of the second doped region, and the doping type of the first doped region is different from the doping type of the third doped region.

[0014] Optionally, the MOSFET device further comprises an interlayer dielectric layer located between adjacent gate electrodes and source structures and on a side of the gate electrode away from the substrate; and an ohmic contact layer located between the source structure and the epitaxial layer.

[0015] In order to achieve the above object, according to one aspect of the present application, a preparation method of a MOSFET device is provided, comprising: providing a substrate, and forming a preliminary epitaxial layer on one side of the substrate; removing part of the preliminary epitaxial layer to form a trench, and the remaining preliminary epitaxial layer forms an epitaxial layer, wherein the width of the trench gradually increases in the direction from the bottom of the trench to the opening of the trench; sequentially forming a first gate dielectric layer, a polysilicon gate, a second gate dielectric layer and a gate electrode in the trench to obtain a trench gate structure, wherein the second gate dielectric layer is located on the side of the first gate dielectric layer away from the substrate, the gate electrode is located on the side of the second gate dielectric layer away from the first gate dielectric layer, the polysilicon gate is located on the outer periphery of the second gate dielectric layer in the direction perpendicular to the thickness of the substrate, and the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer; forming a source structure on the side of the epitaxial layer away from the substrate and the side of the trench gate structure away from the substrate; and forming a drain structure on the side of the substrate away from the epitaxial layer.

[0016] The technical scheme of the present application provides a MOSFET device, comprising: a substrate, an epitaxial layer, a trench gate structure, a source structure and a drain structure, the epitaxial layer is located on one side of the substrate; the trench gate structure is located in the epitaxial layer, and the width of the trench gate structure gradually increases in the direction from the substrate to the epitaxial layer, the trench gate structure comprises a polysilicon gate, a first gate dielectric layer, a second gate dielectric layer and a gate electrode, and the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer; the source structure is located on the side of the epitaxial layer away from the substrate and the side of the trench gate structure away from the substrate; and the drain structure is located on the side of the substrate away from the epitaxial layer. In the present scheme, first, the first gate dielectric layer with a larger dielectric constant is arranged at the bottom of the trench, which can attract more electric flux lines, thereby sharing and significantly reducing the electric field intensity at the corners above and below the trench, and enhancing the durability of the device; second, according to the formula for calculating capacitance, the capacitance value is proportional to the dielectric constant, that is, the smaller the dielectric constant, the smaller the capacitance value, that is, the second gate dielectric layer with a smaller dielectric constant can reduce the parasitic capacitance between the two adjacent polysilicon gates, and can improve the switching speed, thereby reducing the switching loss. By comprehensively using the above two methods, the performance of the MOSFET device can be comprehensively improved, and the technical problem of how to improve the performance of the MOSFET device is solved. BRIEF DESCRIPTION OF DRAWINGS

[0017] The drawings constituting a part of the specification of the present application are used to provide further understanding of the present application, the illustrative embodiments of the present application and the description thereof are used to explain the present application, and do not constitute improper limitations on the present application. In the drawings:

[0018] Figure 1Fig. 1 shows a structural schematic diagram of a MOSFET device according to an embodiment of the present application;

[0019] Figure 2 Fig. 2 shows a flow schematic diagram of a preparation method of a MOSFET device according to an embodiment of the present application;

[0020] Figs. 3(a)~(i) show structural schematic diagrams corresponding to specific flow of a preparation method of a MOSFET device according to an embodiment of the present application.

[0021] Among the above figures, the following reference signs are included:

[0022] 10, substrate; 11, epitaxial layer; 12, trench gate structure; 121, polysilicon gate; 122, first gate dielectric layer; 123, second gate dielectric layer; 124, gate electrode; 125, first level trench; 126, second level trench; 127, third gate dielectric layer; 13, source structure; 14, drain structure; 15, first doped region; 16, second doped region; 17, third doped region; 18, interlayer dielectric layer; 19, ohmic contact layer; 20, preliminary epitaxial layer; 21, trench. DETAILED DESCRIPTION

[0023] It should be noted that the following detailed description is merely exemplary in nature and is intended to provide further description of the application. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

[0024] It is also important to note that the use of the term "example" in the context of this application is not intended to mean that a particular feature is essential to the application, but rather, that the feature is an example. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0025] It should be noted that the terms "first", "second", and the like, as used in the description and the claims herein are intended to modify a particular feature or step of the application, but do not connote or imply that the features or steps are in any way prioritized, sequenced, or ordered, unless otherwise indicated by the context in which the terms are used. It is intended that the application as described herein can be carried out by any number of ways, components, means, and / or steps. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof.

[0026] It should be understood that when an element (such as a layer, film, region, or substrate) is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In addition, it should be understood that when an element is referred to as being "connected" to another element, it can be "directly connected" to the other element or "connected" to the other element through a third element.

[0027] As introduced in the background, the prior art MOSFET device is not ideal, to solve the above problems, the embodiment of the present application provides a MOSFET device and a preparation method of the MOSFET device.

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

[0029] Figure 1 is a structural schematic diagram of the MOSFET device according to the embodiment of the present application. As shown in Figure 1 , it comprises:

[0030] a substrate 10;

[0031] The material of the substrate 10 can be silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, sapphire, etc., and the resistivity of the substrate 10 can be 0.02±20% Ωcm.

[0032] an epitaxial layer 11 located on one side of the substrate 10;

[0033] In practical applications, the epitaxial layer 11 can be a single-layer structure or a multi-layer structure. The epitaxial layer 11 can be used as a drift layer and bear the main breakdown effect. The doping concentration of the epitaxial layer 11 can be 1E+15~1E+16 cm -3 The thickness of the epitaxial layer 11 can be set according to the size of the breakdown voltage of the MOS device, and the greater the voltage of the MOS device, the greater the thickness of the epitaxial layer 11.

[0034] The trench gate structure 12 is located in the epitaxial layer 11, and the width of the trench gate structure 12 gradually increases in the direction of the substrate 10 pointing to the epitaxial layer 11. The trench gate structure 12 includes a polysilicon gate 121, a first gate dielectric layer 122, a second gate dielectric layer 123, and a gate electrode 124. The second gate dielectric layer 123 is located on the side of the first gate dielectric layer 122 away from the substrate 10. The gate electrode 124 is located on the side of the second gate dielectric layer 123 away from the first gate dielectric layer 122. In the direction perpendicular to the thickness of the substrate 10, the polysilicon gate 121 is located at the outer periphery of the second gate dielectric layer 123. The dielectric constant of the first gate dielectric layer 122 is greater than that of the second gate dielectric layer 123.

[0035] In practical applications, the increase in the width of the trench of the trench gate structure 12 can be linear or non-linear, that is, the width difference of the trenches corresponding to adjacent levels can be the same or different. The material of the polysilicon gate 121 is polysilicon. The material of the first gate dielectric layer 122 can be at least one of HfO2, Si3N4, TiO2, Al2O3, and ZrO2. The material of the second gate dielectric layer 123 can be at least one of fluorosilicic acid glass, porous organic silicic acid glass, fluorine-containing polyimide, and benzocyclobutene. The dielectric constant, also known as the relative dielectric constant, is a physical quantity used to describe the charge storage capacity and dielectric properties of a material. It is one of the inherent properties of the material, indicating the proportion of the charge storage capacity of a certain material to the charge storage capacity in a vacuum state under the same electric field.

[0036] The core role of the first gate dielectric layer 122 at the bottom of the trench is electric field modulation. According to the continuity principle of electric displacement vector, the normal component of the electric displacement vector D is continuous at the interface of the two media, that is, D is the same. According to the formula D = K × ε0 × E, where K is the relative dielectric constant of the medium, ε0 is the vacuum dielectric constant, and E is the electric field strength. The larger K is, the smaller E is. In the blocking state, the trench bottom bears a lower electric field, which is more beneficial to the device. The first gate dielectric layer 122 is located at the lower part of the trench, close to the corner area of the trench bottom with the strongest electric field. From the substrate 10 to the gate oxide and then to the first gate dielectric layer 122, the electric field will undergo a redistribution. The first gate dielectric layer 122 can attract more electric flux lines, thereby sharing and significantly reducing the electric field strength of the gate oxide layer above and the corner below.

[0037] In the direction perpendicular to the thickness of the substrate 10, the second gate dielectric layer 123 is sandwiched between two adjacent polysilicon gates 121, forming a structure similar to a parallel plate capacitor. Its capacitance value is determined by the following formula: where K is the relative dielectric constant of the medium, ε0 is the vacuum permittivity, A is the area of the conductor relative, and d is the thickness of the medium. According to the above capacitance formula, the capacitance value C is proportional to K. Therefore, under the same area A and thickness d, using a material with a lower dielectric constant can directly and linearly reduce the parasitic capacitance between the two polysilicon gates 121. In the trench structure, the Miller capacitance (Cgd) is mainly the capacitance between the gate oxide / polysilicon and the drift region, that is, the larger capacitance formed by the polysilicon in the trench through the gate oxide and the drift region. By replacing the polysilicon at the bottom of the trench with the first gate dielectric layer 122, this part of the capacitance can be greatly weakened. In addition, the two polysilicon gates 121 and the first gate dielectric layer 122 form part of the gate-source capacitance (Cgs) and are also associated with the path of Cgd. Reducing this capacitance means that less charge needs to be charged and discharged during the switching process, thereby reducing the total gate charge (Qg) and the Miller charge (Qgd).

[0038] A source structure 13 is located on the side of the epitaxial layer 11 away from the substrate 10 and on the side of the trench gate structure 12 away from the substrate 10.

[0039] In practical applications, the source structure 13 can serve as the input end of current, and the material of the source structure 13 can be an alloy of one or more of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc.

[0040] A drain structure 14 is located on the side of the substrate 10 away from the epitaxial layer 11.

[0041] In practical applications, the drain structure 14 can serve as the output end of current, and the material of the drain structure 14 can be an alloy of one or more of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc.

[0042] The embodiment provides a MOSFET device, which comprises a substrate, an epitaxial layer, a trench gate structure, a source structure and a drain structure, the epitaxial layer is located on one side of the substrate; the trench gate structure is located in the epitaxial layer, and the width of the trench gate structure gradually increases in the direction of the substrate pointing to the epitaxial layer, the trench gate structure comprises a polysilicon gate, a first gate dielectric layer, a second gate dielectric layer and a gate electrode, the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer; the source structure is located on the side of the epitaxial layer away from the substrate and the side of the trench gate structure away from the substrate; and the drain structure is located on the side of the substrate away from the epitaxial layer. In the scheme, first, the first gate dielectric layer with a larger dielectric constant is arranged at the bottom of the trench, so that more electric flux lines can be attracted, thereby sharing and significantly reducing the electric field intensity borne by the corners above and below the trench, and the durability of the device is enhanced; second, according to the capacitance calculation formula, the capacitance value is proportional to the dielectric constant, that is, the smaller the dielectric constant, the smaller the capacitance value, that is, the second gate dielectric layer with a smaller dielectric constant can reduce the parasitic capacitance between the two adjacent polysilicon gates, and the switching speed can be improved, thereby reducing the switching loss. The above two methods can comprehensively improve the performance of the MOSFET device, and solve the technical problem of how to improve the performance of the MOSFET device.

[0043] In the implementation process, as shown in Figure 1 The depth of the trench gate structure 12 is 1-3 mu m; the thickness of the first gate dielectric layer 122 is 0.05-0.2 mu m; and the thickness of the second gate dielectric layer 123 is 0.8-2.95 mu m. The depth of the trench gate structure 12 in the above depth range can improve the breakdown voltage to a certain extent, and can also prevent the increase of heat dissipation difficulty caused by the over-deep trench gate structure 12. The thickness of the first gate dielectric layer 122 and the thickness of the second gate dielectric layer 123 are respectively in the above thickness range, so that the first gate dielectric layer 122 is only located in the trench closest to the substrate 10, and the second gate dielectric layer 123 is located in the plurality of grooves, which can not only ensure the reduction of the electric field intensity at the bottom of the trench, but also reduce the influence on the total gate charge and the Miller charge. In the implementation process, the depth of the trench gate structure 12 can be 1 mu m, 2 mu m, 3 mu m, or between any two of the above values. The thickness of the first gate dielectric layer 122 can be 0.05 mu m, 0.1 mu m, 0.15 mu m, 0.2 mu m, or between any two of the above values. The thickness of the second gate dielectric layer 123 is 0.8 mu m, 1 mu m, 1.4 mu m, 1.7 mu m, 2 mu m, 2.45 mu m, 2.95 mu m, or between any two of the above values.

[0044] In order to further reduce the difficulty of the manufacturing process of the MOSFET device, as shown in Figure 1 The trench gate structure 12 includes a first level trench 125 and a second level trench 126, the second level trench 126 is located on the side of the first level trench 125 away from the substrate 10, the first gate dielectric layer 122 is located in the first level trench 125, and the second gate dielectric layer 123 is located in the first level trench 125 and the second level trench 126.

[0045] In the implementation scheme, the first gate dielectric layer 122 is only located at the bottom of the side of the trench gate structure 12 close to the substrate 10, that is, only in the first level trench 125, and the second gate dielectric layer 123 is located in the first level trench 125 and the second level trench 126. In addition, the polysilicon gate 121 is located on the sidewall of the first gate dielectric layer 122 away from the substrate 10 in the first level trench 125, and on the bottom and sidewall of the second level trench 126.

[0046] As shown in Figure 1 In the thickness direction perpendicular to the substrate 10, the width ratio of the second level trench 126 to the first level trench 125 is 1.5:1~3:1. The width ratio of the second level trench 126 to the first level trench 125 within the range of the ratio can not only help to improve the electric field distribution of the MOSFET device, but also reduce the accuracy requirement of the etching process, thereby further improving the tolerance of the manufacturing process, further reducing the defective rate in the production process, and reducing the production cost.

[0047] That is, the width ratio of the second level trench 126 to the first level trench 125 can be any one of 1.5:1, 2:1, 2.5:1 and 3:1, or can be between any two of the above ratios.

[0048] As shown in Figure 1 In some embodiments, the trench gate structure 12 satisfies at least one of the following: in the thickness direction perpendicular to the substrate 10, the width of the trench gate structure 12 is 0.2~1.5μm; in the thickness direction perpendicular to the substrate 10, the width of the polysilicon gate 121 is 0.2~1μm. The width of the trench gate structure 12 within the above range can not only provide appropriate on-resistance, but also prevent excessive stress on the gate dielectric layer, which affects the performance of the MOSFET device. The width of the polysilicon gate 121 within the above range can not only ensure the good function of the gate, but also reduce the influence on the increase of the total gate charge and the Miller charge.

[0049] In the above implementation, the width of the trench gate structure 12 in the direction perpendicular to the thickness of the substrate 10 can be 0.2 μm, 0.5 μm, 0.7 μm, 1 μm, 1.2 μm, 1.5 μm, or any value between any two of the above values. The width of the polysilicon gate 121 in the direction perpendicular to the thickness of the substrate 10 can be 0.2 μm, 0.4 μm, 0.6 μm, 0.8 μm, 1 μm, or any value between any two of the above values.

[0050] To further improve the protection effect on the trench gate structure 12, in some other embodiments, as shown in Figure 1 the trench gate structure 12 further includes a third gate dielectric layer 127 located on the side of the first gate dielectric layer 122 close to the substrate 10 and on the sidewall of the trench gate structure 12.

[0051] The material of the third gate dielectric layer 127 can be an oxide, such as silicon oxide.

[0052] In some specific embodiments, the thickness of the third gate dielectric layer 127 is 300-800 angstroms. The thickness of the third gate dielectric layer 127 within the above range can provide good protection for the gate and prevent the breakdown voltage from decreasing and the electric field from being too concentrated.

[0053] The thickness of the third gate dielectric layer 127 can be 300 angstroms, 400 angstroms, 500 angstroms, 600 angstroms, 700 angstroms, or 800 angstroms. In actual applications, the width of the third gate dielectric layer 127 in the direction perpendicular to the thickness of the substrate 10 can also be 300-800 angstroms.

[0054] In some other embodiments, as shown in Figure 1 the MOSFET device further includes a first doped region 15, a second doped region 16, and a third doped region 17, the first doped region 15, the second doped region 16, and the third doped region 17 are located in the epitaxial layer 11, the first doped region 15 is located on the side of the second doped region 16 and the third doped region 17 close to the substrate 10, and in the direction perpendicular to the thickness of the substrate 10, the third doped region 17 is located between the second doped region 16 and the trench gate structure 12, wherein the doping type of the first doped region 15 is the same as that of the second doped region 16, and the doping type of the first doped region 15 is different from that of the third doped region 17.

[0055] In the above implementation, the doping concentration of the second doped region 16 is greater than the doping concentration of the first doped region 15. In the thickness direction perpendicular to the substrate 10, the average thickness of the first doped region 15 can be 0.7-0.8 μm. The doping concentration of the first doped region 15 can be 1E+17±50% cm -3 In the thickness direction perpendicular to the substrate 10, the average thickness of the second doped region 16 can be 0.2-0.3 μm, and the doping concentration of the second doped region 16 can be 1E+19±50% cm -3 The doping element of the first doped region 15 and the second doped region 16 can be B, Al, Ga, etc. In the thickness direction perpendicular to the substrate 10, the average thickness of the third doped region 17 can be 0.2-0.3 μm, and the doping concentration of the third doped region 17 can be 1E+19-1E+20 cm -3 .

[0056] In some embodiments, as shown in Figure 1 The MOSFET device further includes an interlayer dielectric layer 18 between the adjacent gate electrode 124 and the source structure 13 and on the side of the gate electrode 124 away from the substrate 10, and an ohmic contact layer 19 between the source structure 13 and the epitaxial layer 11.

[0057] The interlayer dielectric layer 18 is used to isolate the gate structure and the source structure 13. The material of the interlayer dielectric layer 18 can be silicon oxide, etc., and the thickness can be 600-1000 nm. The ohmic contact layer 19 can be formed of a metal material such as Ni or Ti.

[0058] The embodiments of the present application further provide a preparation method of a MOSFET device, and the method is used for preparing any one of the MOSFET devices, Figure 2 is a flowchart of the preparation method of the MOSFET device according to the embodiments of the present application. As shown in Figure 2 The method comprises the following steps:

[0059] In step S201, a substrate is provided, and a preliminary epitaxial layer is formed on one side of the substrate.

[0060] The material of the substrate can be silicon, silicon carbide, gallium nitride, diamond, gallium arsenide, sapphire, etc., and the resistivity of the substrate can be 0.02±20% Ωcm. The preliminary epitaxial layer can be a single-layer structure or a multi-layer structure. The preliminary epitaxial layer can be used as a drift layer and bear the main breakdown effect. The doping concentration of the preliminary epitaxial layer can be 1E+15-1E+16 cm -3 .

[0061] Step S202, removing part of the above-mentioned preliminary epitaxial layer to form a trench, and the remaining preliminary epitaxial layer forms an epitaxial layer, wherein the width of the trench gradually increases in the direction from the bottom of the trench to the opening of the trench;

[0062] The bottom of the trench refers to the side of the trench close to the substrate, and the opening of the trench refers to the side of the trench away from the substrate. In practical applications, the increase in the width of the trench can be linear or non-linear, that is, the width difference of the trenches corresponding to adjacent stages can be the same or different.

[0063] Step S203, sequentially forming a first gate dielectric layer, a polysilicon gate, a second gate dielectric layer and a gate electrode in the trench to obtain a trench gate structure, wherein the second gate dielectric layer is located on the side of the first gate dielectric layer away from the substrate, the gate electrode is located on the side of the second gate dielectric layer away from the first gate dielectric layer, the polysilicon gate is located on the outer periphery of the second gate dielectric layer in the direction perpendicular to the thickness of the substrate, and the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer;

[0064] The material of the polysilicon gate is polysilicon. The material of the first gate dielectric layer can be at least one of HfO2, Si3N4, TiO2, Al2O3 and ZrO2. The material of the second gate dielectric layer can be at least one of fluorosilicic acid glass, porous organic silicic acid glass, fluorine-containing polyimide and benzocyclobutene. The dielectric constant, also known as the relative dielectric constant, is a physical quantity used to describe the charge storage capacity and dielectric properties of a material. It is one of the inherent properties of the material, indicating the proportion of the charge storage capacity of a certain material to the charge storage capacity in a vacuum state under the action of the same electric field.

[0065] Step S204, forming a source structure on the side of the epitaxial layer away from the substrate and the side of the trench gate structure away from the substrate;

[0066] In practical applications, the source structure can serve as the input end of the current, and the material of the source structure can be an alloy of one or more of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru) and platinum (Pt).

[0067] Step S205, forming a drain structure on the side of the substrate away from the epitaxial layer.

[0068] In practical applications, the drain structure can be used as an output terminal of current, and the material of the drain structure can be an alloy of one or more of nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), and platinum (Pt).

[0069] By the embodiment, a preparation method of a MOSFET device is provided. First, a substrate is provided, and a preliminary epitaxial layer is formed on one side of the substrate. Then, part of the preliminary epitaxial layer is removed to form a trench, and the remaining preliminary epitaxial layer forms an epitaxial layer. The width of the trench gradually increases in a direction from the bottom of the trench to the opening of the trench. Then, a first gate dielectric layer, a polysilicon gate, a second gate dielectric layer, and a gate electrode are sequentially formed in the trench to obtain a trench gate structure. The second gate dielectric layer is located on the side of the first gate dielectric layer away from the substrate, and the gate electrode is located on the side of the second gate dielectric layer away from the first gate dielectric layer. In the thickness direction perpendicular to the substrate, the polysilicon gate is located on the outer periphery of the second gate dielectric layer, and the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer. Finally, a source structure is formed on the side of the epitaxial layer away from the substrate and on the side of the trench gate structure away from the substrate. A drain structure is formed on the side of the substrate away from the epitaxial layer. In this scheme, the first gate dielectric layer with a larger dielectric constant is arranged at the bottom of the trench to attract more electric flux lines, thereby sharing and significantly reducing the electric field intensity at the corners above and below the trench, enhancing the durability of the device. According to the capacitance calculation formula, the capacitance value is proportional to the dielectric constant, that is, the smaller the dielectric constant, the smaller the capacitance value. That is, the second gate dielectric layer with a smaller dielectric constant can reduce the parasitic capacitance between the two adjacent polysilicon gates, thereby improving the switching speed and reducing the switching loss. By combining the above two methods, the performance of the MOSFET device can be improved, and the technical problem of how to improve the performance of the MOSFET device is solved.

[0070] In order for those skilled in the art to more clearly understand the technical solutions of the present application, the implementation process of the preparation method of the MOSFET device of the present application will be described in detail below in conjunction with specific embodiments.

[0071] The present embodiment relates to a specific preparation method of a MOSFET device. In the preparation method, the structure obtained in each step is shown in FIGS. 3(a) to 3(i), and the preparation method includes the following steps:

[0072] Step S1: providing a substrate 10 and forming a preliminary epitaxial layer 20 on one side of the substrate 10 to obtain the structure shown in FIG. 3(a);

[0073] Step S2: processing the preliminary epitaxial layer 20 to form the second doped region 16, to obtain the structure as shown in Fig. 3(b);

[0074] Step S3: processing the preliminary epitaxial layer 20 to form the first doped region 15, to obtain the structure as shown in Fig. 3(c);

[0075] Step S4: processing the preliminary epitaxial layer 20 to form the third doped region 17, to obtain the structure as shown in Fig. 3(d);

[0076] Step S5: removing part of the preliminary epitaxial layer 20 to form the trench 21, and the remaining preliminary epitaxial layer 20 forms the epitaxial layer 11, wherein the width of the trench 21 gradually increases in the direction from the bottom of the trench 21 to the opening of the trench 21, to obtain the structure as shown in Fig. 3(e);

[0077] Step S6: forming the third gate dielectric layer 127 in the trench 21, to obtain the structure as shown in Fig. 3(f);

[0078] Step S7: sequentially forming the first gate dielectric layer 122, the polysilicon gate 121, the second gate dielectric layer 123 and the gate electrode 124 in the trench 21, to obtain the trench gate structure 12, wherein the second gate dielectric layer 123 is located on the side of the first gate dielectric layer 122 away from the substrate 10, the gate electrode 124 is located on the side of the second gate dielectric layer 123 away from the first gate dielectric layer 122, the polysilicon gate 121 is located on the outer periphery of the second gate dielectric layer 123 in the direction perpendicular to the thickness of the substrate 10, and the dielectric constant of the first gate dielectric layer 122 is greater than that of the second gate dielectric layer 123, to obtain the structure as shown in Fig. 3(g);

[0079] Step S8: forming the interlayer dielectric layer 18 on the side of the epitaxial layer 11 away from the substrate 10 and on the side of the gate electrode 124 away from the substrate 10, and forming the ohmic contact layer 19 on the side of the epitaxial layer 11 away from the substrate 10, to obtain the structure as shown in Fig. 3(h);

[0080] Step S9: forming the source structure 13 on the side of the epitaxial layer away from the substrate 10 and on the side of the trench gate structure 12 away from the substrate 10, to obtain the structure as shown in Fig. 3(i);

[0081] Step S10: forming the drain structure 14 on the side of the substrate 10 away from the epitaxial layer 11, to obtain the structure as shown in Fig. 3(j). Figure 1

[0082] From the above description, it can be seen that the above-mentioned embodiments of the present application achieve the following technical effects: ​

[0083] 1) The MOSFET device of the present application comprises a substrate, an epitaxial layer, a trench gate structure, a source structure and a drain structure, the epitaxial layer is located on one side of the substrate; the trench gate structure is located in the epitaxial layer, and the width of the trench gate structure gradually increases in the direction of the substrate pointing to the epitaxial layer, the trench gate structure comprises a polysilicon gate, a first gate dielectric layer, a second gate dielectric layer and a gate electrode, the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer; the source structure is located on the side of the epitaxial layer away from the substrate and the side of the trench gate structure away from the substrate; the drain structure is located on the side of the substrate away from the epitaxial layer. In the present application, first, the first gate dielectric layer with a larger dielectric constant is arranged at the bottom of the trench, which can attract more electric flux lines, thereby sharing and significantly reducing the electric field intensity borne by the corners above and below the trench, enhancing the durability of the device; second, according to the capacitance calculation formula, the capacitance value is proportional to the dielectric constant, that is, the smaller the dielectric constant, the smaller the capacitance value, that is, the use of the second gate dielectric layer with a smaller dielectric constant can reduce the parasitic capacitance between the two adjacent polysilicon gates, which can improve the switching speed and thus reduce the switching loss. The above two methods can comprehensively improve the performance of the MOSFET device and solve the technical problem of how to improve the performance of the MOSFET device.

[0084] 2) The preparation method of the MOSFET device of the application, first, a substrate is provided, and a preliminary epitaxial layer is formed on one side of the substrate; then, part of the preliminary epitaxial layer is removed to form a trench, and the remaining preliminary epitaxial layer forms an epitaxial layer, the width of the trench gradually increases in the direction from the bottom of the trench to the opening of the trench; then, a first gate dielectric layer, a polysilicon gate, a second gate dielectric layer and a gate electrode are sequentially formed in the trench to obtain a trench gate structure, wherein the second gate dielectric layer is located on the side of the first gate dielectric layer away from the substrate, the gate electrode is located on the side of the second gate dielectric layer away from the first gate dielectric layer, the polysilicon gate is located on the outer periphery of the second gate dielectric layer in the direction perpendicular to the thickness direction of the substrate, and the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer; finally, a source structure is formed on the side of the epitaxial layer away from the substrate and the side of the trench gate structure away from the substrate; and a drain structure is formed on the side of the substrate away from the epitaxial layer. In this scheme, first, the first gate dielectric layer with a larger dielectric constant is arranged at the bottom of the trench, which can attract more electric flux lines, thereby sharing and significantly reducing the electric field intensity at the corners above and below the trench, enhancing the durability of the device; second, according to the capacitance calculation formula, the capacitance value is proportional to the dielectric constant, that is, the smaller the dielectric constant, the smaller the capacitance value, that is, the use of the second gate dielectric layer with a smaller dielectric constant can reduce the parasitic capacitance between the two adjacent polysilicon gates, and can improve the switching speed, thereby reducing the switching loss. By combining the above two methods, the performance of the MOSFET device can be comprehensively improved, and the technical problem of how to improve the performance of the MOSFET device is solved.

[0085] The technical features of the above-mentioned embodiments can be combined in any way, in order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described, however, as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0086] The above-mentioned embodiments are only preferred embodiments of the present application and are not used to limit the present application. Those skilled in the art can make various modifications and changes to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A MOSFET device, characterized in that, include: Substrate; An epitaxial layer is located on one side of the substrate; A trench gate structure is located in the epitaxial layer. The width of the trench gate structure gradually increases in the direction from the substrate to the epitaxial layer. The trench gate structure includes a polysilicon gate, a first gate dielectric layer, a second gate dielectric layer, and a gate electrode. The second gate dielectric layer is located on the side of the first gate dielectric layer away from the substrate, and the gate electrode is located on the side of the second gate dielectric layer away from the first gate dielectric layer. In the thickness direction perpendicular to the substrate, the polysilicon gate is located on the outer periphery of the second gate dielectric layer. The dielectric constant of the first gate dielectric layer is greater than the dielectric constant of the second gate dielectric layer. The source structure is located on the side of the epitaxial layer away from the substrate and on the side of the trench gate structure away from the substrate; The drain structure is located on the side of the substrate away from the epitaxial layer.

2. The MOSFET device according to claim 1, characterized in that, The trench gate structure satisfies at least one of the following: The depth of the trench gate structure is 1~3μm; The thickness of the first gate dielectric layer is 0.05~0.2μm; The thickness of the second gate dielectric layer is 0.8~2.95μm.

3. The MOSFET device according to claim 1, characterized in that, The trench gate structure includes a first-level trench and a second-level trench. The second-level trench is located on the side of the first-level trench away from the substrate. The first gate dielectric layer is located in the first-level trench, and the second gate dielectric layer is located in both the first-level trench and the second-level trench.

4. The MOSFET device according to claim 3, characterized in that, In the direction perpendicular to the thickness of the substrate, the width ratio of the second-level trench to the width of the first-level trench is 1.5:1 to 3:

1.

5. The MOSFET device according to claim 1, characterized in that, The trench gate structure satisfies at least one of the following: The width of the trench gate structure is 0.2~1.5μm in the direction perpendicular to the thickness of the substrate; The width of the polysilicon gate is 0.2~1μm in the thickness direction perpendicular to the substrate.

6. The MOSFET device according to claim 1, characterized in that, The trench gate structure further includes: The third gate dielectric layer is located on the side of the first gate dielectric layer near the substrate and on the sidewall of the trench gate structure.

7. The MOSFET device according to claim 6, characterized in that, The thickness of the third gate dielectric layer is 300~800 angstroms.

8. The MOSFET device according to claim 1, characterized in that, The MOSFET device further includes a first doped region, a second doped region, and a third doped region, which are located in the epitaxial layer. The first doped region is located on the side of the second and third doped regions close to the substrate, and the third doped region is located between the second doped region and the trench gate structure in a direction perpendicular to the thickness of the substrate. The doping type of the first doped region is the same as that of the second doped region, and the doping type of the first doped region is different from that of the third doped region.

9. The MOSFET device according to claim 1, characterized in that, The MOSFET device further includes: An interlayer dielectric layer is located between adjacent gate electrodes and source structures, and on the side of the gate electrode away from the substrate; An ohmic contact layer is located between the source structure and the epitaxial layer.

10. A method for fabricating a MOSFET device, characterized in that, include: A substrate is provided, and a pre-epitaxial layer is formed on one side of the substrate; A portion of the prepared epitaxial layer is removed to form a trench, and the remaining prepared epitaxial layer forms an epitaxial layer, wherein the width of the trench gradually increases in the direction from the bottom of the trench to the opening of the trench. A first gate dielectric layer, a polysilicon gate, a second gate dielectric layer, and a gate electrode are sequentially formed in the trench to obtain a trench gate structure. The second gate dielectric layer is located on the side of the first gate dielectric layer away from the substrate, and the gate electrode is located on the side of the second gate dielectric layer away from the first gate dielectric layer. In the thickness direction perpendicular to the substrate, the polysilicon gate is located on the outer periphery of the second gate dielectric layer, and the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer. A source structure is formed on the side of the epitaxial layer away from the substrate and on the side of the trench gate structure away from the substrate; A drain structure is formed on the side of the substrate away from the epitaxial layer.

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