Laterally diffused metal oxide semiconductor device

Abstract

The invention relates to a laterally diffused metal oxide semiconductor device. The laterally diffused metal oxide semiconductor device comprises a substrate, wherein a drift region, a body region, a source region and a drain region are arranged in the substrate; the body regions and the drain regions are arranged in the drift region at intervals, and the source regions are arranged in the body regions; the grid electrode is arranged on the substrate, the orthographic projection of the grid electrode on the substrate is located between the source region and the drain region, and the grid electrode covers part of the body region; the split gate is arranged on the substrate and is positioned on one side, close to the drain region, of the gate; the split gate and the gate electrode are arranged in an insulated manner; the metal field plate is arranged on the substrate and is positioned on one side, close to the drain region, of the split gate; wherein the source region, the split gate and the metal field plate are electrically connected with a first potential. According to the invention, the gate-drain capacitance Cgd can be reduced, and the switching loss of the device is reduced.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a laterally diffused metal-oxide-semiconductor device. Background Technology

[0002] With the continuous development of semiconductor technology, Lateral Double-Diffuse Metal-Oxide-Semiconductor (LDMOS) devices are widely used in power supply chips. The switching state of LDMOS devices is adjusted to achieve power conversion between different levels. However, during the turn-on phase, the parasitic gate-drain capacitance of LDMOS devices increases losses. Therefore, reducing the gate-drain capacitance of LDMOS devices has become a key focus for designers. Summary of the Invention

[0003] Therefore, it is necessary to provide a laterally diffused metal-oxide-semiconductor device to address the above problems.

[0004] A laterally diffused metal-oxide-semiconductor device, comprising:

[0005] A substrate having a drift region, a body region, a source region, and a drain region therein; the body region and the drain region are arranged alternately within the drift region, and the source region is located within the body region;

[0006] A gate is disposed on the substrate, and the orthogonal projection of the gate on the substrate is located between the source region and the drain region, and covers a portion of the body region;

[0007] A split gate is disposed on the substrate and located on the side of the gate near the drain region; the split gate is insulated from the gate.

[0008] A metal field plate is disposed on the substrate and located on the side of the split gate near the drain region;

[0009] The source region, the split gate, and the metal field plate are all electrically connected to the first potential.

[0010] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes a field dielectric layer disposed between the split gate and the substrate, and between the metal field plate and the substrate.

[0011] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes a first dielectric layer, at least a portion of which is disposed between the metal field plate and the field dielectric layer.

[0012] In one embodiment, the dielectric constant of the first dielectric layer is greater than the dielectric constant of the field dielectric layer.

[0013] In one embodiment, the substrate has a first distance between its surface near the split gate and the split gate, and a second distance between its surface near the split gate and the metal field plate, the second distance being greater than the first distance.

[0014] In one embodiment, the first distance is between 200 angstroms and 800 angstroms;

[0015] And / or, the second distance is between 1000 angstroms and 5000 angstroms.

[0016] In one embodiment, the gate includes:

[0017] A gate dielectric layer is disposed on the substrate;

[0018] A gate conductive layer covers the side of the gate dielectric layer away from the substrate and a portion of the side of the field dielectric layer away from the substrate.

[0019] In one embodiment, the ratio of the size of the gate to the size of the split gate is between 0.25 and 4 along the direction in which the source region and the drain region are arranged.

[0020] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes a second dielectric layer disposed between the gate and the split gate.

[0021] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes:

[0022] A body lead-out area is provided within the body area;

[0023] A first conductive structure is disposed on the side of the substrate near the gate and is electrically connected to the source region, the body lead-out region, the split gate, and the metal field plate; the first conductive structure is used to connect to a first potential;

[0024] A second conductive structure is disposed on the side of the substrate near the gate and electrically connected to the drain region. The second conductive structure is used to access a second potential.

[0025] A third conductive structure is disposed on the side of the substrate near the gate and electrically connected to the gate. The third conductive structure is used to access a third potential.

[0026] The laterally diffused metal-oxide-semiconductor device provided in this application embodiment has a split gate between the gate and the drain region, and a metal field plate on the side of the split gate near the drain region, with the source region, split gate, and metal field plate all electrically connected to a first potential. In this way, the split gate and metal field plate not only shield the gate-drain capacitance Cgd between the drain region and the gate, but also convert the gate-drain capacitance Cgd into a source-drain capacitance Csd, thereby significantly reducing the gate-drain capacitance Cgd and consequently reducing the switching losses of the device. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic cross-sectional view of a laterally diffused metal-oxide-semiconductor device provided in one embodiment of this application.

[0029] Figure 2 This is a schematic cross-sectional view of another laterally diffused metal-oxide-semiconductor device provided in one embodiment of this application.

[0030] Figure 3 This is a schematic cross-sectional view of another laterally diffused metal-oxide-semiconductor device provided in one embodiment of this application.

[0031] Explanation of reference numerals in the attached figures:

[0032] 1. Laterally diffused metal-oxide-semiconductor device; 10. Substrate; 21. Drift region; 22. Body region; 23. Source region; 24. Drain region; 25. Body lead-out region; 30. Gate; 31. Gate dielectric layer; 32. Gate conductive layer; 40. Split gate; 50. Metal field plate; 60. Field dielectric layer; 70. First dielectric layer; 80. Second dielectric layer; 90. First conductive structure; 91. First contact metal; 92. First electrode; 93. Second electrode; 94. Third electrode; 100. Second conductive structure; 101. Second contact metal; 102. Fourth electrode. Detailed Implementation

[0033] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0035] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0036] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0037] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0038] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the application.

[0039] With the continuous development of semiconductor technology, Lateral Double-Diffuse Metal-Oxide-Semiconductor (LDMOS) devices are widely used in power supply chips. The switching state of LDMOS devices is adjusted to achieve power conversion between different levels. However, during the turn-on phase, the parasitic gate-drain capacitance of LDMOS devices increases losses. Therefore, reducing the gate-drain capacitance of LDMOS devices has become a key focus for designers.

[0040] To address the above issues, this application provides a laterally diffused metal-oxide-semiconductor (MOSFET) device capable of reducing gate-drain capacitance. This laterally diffused MOSFET device can be either an N-type or a P-type device.

[0041] Specifically, refer to Figure 1As shown, the laterally diffused metal-oxide-semiconductor device 1 includes a substrate 10, a gate 30, a split gate 40, and a metal field plate 50. The substrate 10 contains a drift region 21, a body region 22, a source region 23, and a drain region 24; the body region 22 and the drain region 24 are arranged alternately within the drift region 21, and the source region 23 is located within the body region 22. The gate 30 is disposed on the substrate 10, and its orthogonal projection onto the substrate 10 is located between the source region 23 and the drain region 24, covering a portion of the body region 22. The split gate 40 is disposed on the substrate 10 and located on the side of the gate 30 closest to the drain region 24; the split gate 40 is insulated from the gate 30. The metal field plate 50 is disposed on the substrate 10 and located on the side of the split gate 40 closest to the drain region 24; wherein the source region 23, the split gate 40, and the metal field plate 50 are all electrically connected to a first potential.

[0042] It is understood that the material of the substrate 10 may be monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low-temperature polycrystalline silicon (LTPS), or other materials known to those skilled in the art. The substrate 10 can provide a supporting foundation for the structural layers on the substrate 10.

[0043] In one embodiment, the substrate 10 is P-type doped, the drift region 21 is N-type doped, the body region 22 is P-type doped, the source region 23 is N-type doped, and the drain region 24 is N-type doped.

[0044] The laterally diffused metal-oxide-semiconductor device 1 provided in this application embodiment has a split gate 40 disposed between the gate 30 and the drain region 24 (drain end), and a metal field plate 50 disposed on the side of the split gate 40 near the drain region 24 (drain end), and the source region 23 (source end), the split gate 40, and the metal field plate 50 are all electrically connected to a first potential. In this way, the split gate 40 and the metal field plate 50 can not only shield the gate-drain capacitance Cgd between the drain region 24 (drain end) and the gate 30, but also convert the gate-drain capacitance Cgd into the source-drain capacitance Csd, thereby significantly reducing the gate-drain capacitance Cgd of the device, and thus reducing the switching loss of the device.

[0045] It should be noted that, compared to traditional devices without a split gate, adding a split gate 40 not only shields the gate-drain capacitance Cgd between the drain region 24 (drain terminal) and the gate 30, but also converts the gate-drain capacitance Cgd into a source-drain capacitance Csd. Furthermore, by placing a metal field plate 50 on the side of the split gate 40 near the drain region 24 (drain terminal), the metal field plate 50 can further shield the gate-drain capacitance Cgd between the drain region 24 (drain terminal) and the gate 30, and further convert the gate-drain capacitance Cgd into a source-drain capacitance Csd. Thus, the gate-drain capacitance Cgd of the device can be significantly reduced, thereby reducing the switching losses of the device.

[0046] In one embodiment, the laterally diffused metal-oxide-semiconductor device 1 further includes a field dielectric layer 60 disposed between the split gate 40 and the substrate 10, and between the metal field plate 50 and the substrate 10.

[0047] Thus, both the split gate 40 and the metal field plate 50 can assist in depleting the drift region 21. In the off-state, the multi-field plate structure formed by the split gate 40 and the metal field plate 50 optimizes the electric field of the drift region 21. Therefore, compared to devices with only the split gate 40, the embodiments of this application are advantageous in improving the breakdown voltage, or, compared to conventional devices without the split gate 40, in maintaining the breakdown voltage.

[0048] It should be noted that in conventional devices without a split gate 40, the gate 30 can act as a field plate to optimize the electric field of the drift region 21. Therefore, the size of the gate 30 is usually designed to be relatively large to improve the device breakdown voltage. Due to the limited size of the substrate 10, if a split gate 40 is provided, the device breakdown voltage will be reduced. However, by providing a metal field plate 50, the electric field of the drift region 21 can be optimized, thereby ensuring that the breakdown voltage of the device in this embodiment is not lower than that of conventional devices.

[0049] In one embodiment, the gate 30 includes a gate dielectric layer 31 and a gate conductive layer 32. The gate dielectric layer 31 is disposed on the substrate 10; the gate conductive layer 32 covers the side of the gate dielectric layer 31 away from the substrate 10 and a portion of the surface of the field dielectric layer 60 away from the substrate 10.

[0050] Specifically, the gate dielectric layer 31 is disposed on the surface of the substrate 10. The orthogonal projection of the gate dielectric layer 31 on the substrate 10 covers part of the drift region 21 and part of the body region 22 outside the body region 22.

[0051] In one embodiment, the thickness of the gate dielectric layer 31 is less than the thickness of the field dielectric layer 60.

[0052] For example, the gate dielectric layer 31 can be a gate oxide layer. The field dielectric layer 60 can be a field oxide layer.

[0053] In one embodiment, the gate conductive layer 32 and the split gate 40 are made of the same material. For example, both the gate conductive layer 32 and the split gate 40 are made of polysilicon. Thus, the gate conductive layer 32 and the split gate 40 can be fabricated in the same process, without requiring additional fabrication steps compared to conventional devices.

[0054] It is understood that the material of the split gate 40 can also be a metallic material. This application embodiment does not limit the material of the split gate 40.

[0055] In one embodiment, reference Figure 1 As shown, the laterally diffused metal-oxide-semiconductor device 1 further includes a first dielectric layer 70, at least a portion of which is disposed between the metal field plate 50 and the field dielectric layer 60. Specifically, the split gate 40 is disposed on the surface of the field dielectric layer 60 away from the substrate 10, and the first dielectric layer 70 is disposed between the metal field plate 50 and the field dielectric layer 60.

[0056] Thus, the metal field plate 50 and the split gate 40 together form a stepped field plate, which can better optimize the electric field of the drift region 21 and help improve the breakdown voltage of the device under off-state conditions.

[0057] In one embodiment, the dielectric constant of the first dielectric layer 70 is greater than that of the field dielectric layer 60. This effectively makes the dielectric layer structure between the metal field plate 50 and the substrate 10 a variable-K dielectric layer. Thus, the metal field plate 50 can better optimize the electric field of the drift region 21, which is beneficial for improving the breakdown voltage of the device under off-state conditions.

[0058] In one embodiment, reference Figure 1 As shown, the surface of the substrate 10 near the split gate 40 has a first distance L1 between it and the split gate 40, and the surface of the substrate 10 near the split gate 40 has a second distance L2 between it and the metal field plate 50. The second distance L2 is greater than the first distance L1.

[0059] Thus, the metal field plate 50 and the split gate 40 together form a stepped field plate, which can better optimize the electric field of the drift region 21 and help improve the breakdown voltage of the device under off-state conditions.

[0060] In one embodiment, the first distance L1 is between 200 angstroms and 800 angstroms, that is, the thickness of the field dielectric layer 60 below the split gate 40 is between 200 angstroms and 800 angstroms. For example, the first distance L1 can be 200 angstroms, 400 angstroms, 600 angstroms, 800 angstroms or between any two of the above values.

[0061] In one embodiment, the second distance L2 is between 1000 angstroms and 5000 angstroms, that is, the thickness of the first dielectric layer 70 below the metal field plate 50 is between 1000 angstroms and 5000 angstroms. For example, the second distance L2 can be 1000 angstroms, 1800 angstroms, 2900 angstroms, 4100 angstroms, 5000 angstroms or between any two of the above values.

[0062] By placing the first distance L1 and the second distance L2 within the aforementioned two ranges, it is beneficial for the metal field plate 50 and the split gate 40 to jointly form a stepped field plate, thereby better optimizing the electric field of the drift region 21 and improving the breakdown voltage of the device under off-state conditions.

[0063] In one embodiment, reference Figure 2 As shown, the metal field plate 50 can also be disposed on the surface of the field dielectric layer 60 away from the substrate 10.

[0064] In one embodiment, the ratio of the size of the gate 30 to the size of the split gate 40 along the direction in which the source region 23 and the drain region 24 are arranged is between 0.25 and 4. Figure 1 , Figure 2 and Figure 3 The horizontal direction in the diagram represents the arrangement of source region 23 and drain region 24.

[0065] For example, the ratio of the horizontal dimension of the gate 30 to the horizontal dimension of the split gate 40 can be 0.25, 1, 2, 3, 4 or between any two of the above values.

[0066] The above settings allow designers to adjust the dimensions of the gate 30 and the split gate 40 according to the actual improvement requirements of the gate-drain capacitance.

[0067] In one embodiment, the laterally diffused metal-oxide-semiconductor device 1 further includes a second dielectric layer 80 disposed between the gate 30 and the split gate 40. This facilitates insulation between the gate 30 and the split gate 40. It is understood that the second dielectric layer 80 comprises an insulating material.

[0068] It should be noted that the second dielectric layer 80 can be located on the surface of the field dielectric layer 60 away from the substrate 10, or on the surface of the gate dielectric layer 31 away from the substrate 10. When the second dielectric layer 80 is located on the surface of the field dielectric layer 60 away from the substrate 10, the horizontal dimension of the split gate 40 is smaller. When the second dielectric layer 80 is located on the surface of the gate dielectric layer 31 away from the substrate 10, the horizontal dimension of the split gate 40 is larger.

[0069] In one embodiment, the second dielectric layer 80 is located on the side of the gate dielectric layer 31 away from the substrate 10, and the orthographic projection of the second dielectric layer 80 onto the substrate 10 does not overlap with the body region 22. This prevents the second dielectric layer 80 from affecting the operating performance of the gate 30.

[0070] In one embodiment, the laterally diffused metal-oxide-semiconductor device 1 further includes a body lead-out region 25 disposed within the body region 22. Further, the body lead-out region 25 is connected to the same potential as the source region 23, and the doping type of the body lead-out region 25 is P-type.

[0071] In one embodiment, the laterally diffused metal-oxide-semiconductor device 1 further includes a first conductive structure 90, a second conductive structure 100, and a third conductive structure (not shown). The first conductive structure 90 is disposed on the side of the substrate 10 near the gate 30 and is electrically connected to the source region 23, the body lead-out region 25, the split gate 40, and the metal field plate 50; the first conductive structure 90 is used to connect to a first potential. The second conductive structure 100 is disposed on the side of the substrate 10 near the gate 30 and is electrically connected to the drain region 24; the second conductive structure 100 is used to connect to a second potential. The third conductive structure is disposed on the side of the substrate 10 near the gate 30 and is electrically connected to the gate 30; the third conductive structure is used to connect to a third potential. By providing the first conductive structure 90, the second conductive structure 100, and the third conductive structure, it is convenient for the device to connect to potentials.

[0072] In one embodiment, the first conductive structure 90 includes a first contact metal 91, a first electrode 92, a second electrode 93, and a third electrode 94. The first contact metal 91 is used for electrical connection to an external first potential. One end of the first electrode 92 is electrically connected to the body lead-out region 25, and the other end is electrically connected to the first contact metal 91. One end of the second electrode 93 is electrically connected to the source region 23, and the other end is electrically connected to the first contact metal 91. One end of the third electrode 94 is electrically connected to the split gate 40, and the other end is electrically connected to the first contact metal 91. The metal field plate 50 is directly electrically connected to the first contact metal 91.

[0073] It should be noted that the metal field plate 50, the first electrode 92, the second electrode 93, and the third electrode 94 can be made of the same material. In this way, the metal field plate 50, the first electrode 92, the second electrode 93, and the third electrode 94 can be manufactured in the same process, without the need for additional steps compared to traditional devices.

[0074] In one embodiment, the second conductive structure 100 includes a second contact metal 101 and a fourth electrode 102. The second contact metal 101 is used for electrical connection to a second external potential. One end of the fourth electrode 102 is electrically connected to the drain region 24, and the other end is electrically connected to the second contact metal 101.

[0075] It should be noted that the metal field plate 50, the first electrode 92, the second electrode 93, the third electrode 94, and the fourth electrode 102 can be made of the same material. In this way, the metal field plate 50, the first electrode 92, the second electrode 93, the third electrode 94, and the fourth electrode 102 can be manufactured in the same process, without the need for additional steps compared to traditional devices.

[0076] Furthermore, the second contact metal 101 and the first contact metal 91 can be made of the same material. In this way, the first contact metal 91 and the second contact metal 101 can be manufactured in the same process, without the need for additional steps compared to traditional devices.

[0077] In one embodiment, reference Figure 3 As shown, the split gate 40 can also be electrically connected to the metal field plate 50, and through the metal field plate 50, it can be electrically connected to the first contact metal 91.

[0078] In one embodiment, the first dielectric layer 70 further covers the surface of the gate 30, the surface of the split gate 40, and the exposed surface of the substrate 10. The first dielectric layer 70 is provided with a first via (not shown), a second via (not shown), a third via (not shown), and a fourth via (not shown). A first electrode 92 is disposed in the first via, a second electrode 93 is disposed in the second via, a third electrode 94 is disposed in the third via, and a fourth electrode 102 is disposed in the fourth via.

[0079] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0080] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0081] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A laterally diffused metal-oxide-semiconductor device, characterized in that, include: A substrate having a drift region, a body region, a source region, and a drain region therein; the body region and the drain region are arranged alternately within the drift region, and the source region is located within the body region; A gate is disposed on the substrate, and the orthogonal projection of the gate on the substrate is located between the source region and the drain region, and covers a portion of the body region; A split gate is disposed on the substrate and located on the side of the gate near the drain region; the split gate is insulated from the gate. A metal field plate is disposed on the substrate and located on the side of the split gate near the drain region; The source region, the split gate, and the metal field plate are all electrically connected to the first potential.

2. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The laterally diffused metal-oxide-semiconductor device further includes a field dielectric layer disposed between the split gate and the substrate, and between the metal field plate and the substrate.

3. The laterally diffused metal-oxide-semiconductor device according to claim 2, characterized in that, The laterally diffused metal-oxide-semiconductor device further includes a first dielectric layer, at least a portion of which is disposed between the metal field plate and the field dielectric layer.

4. The laterally diffused metal-oxide-semiconductor device according to claim 3, characterized in that, The dielectric constant of the first dielectric layer is greater than the dielectric constant of the field dielectric layer.

5. The laterally diffused metal-oxide-semiconductor device according to claim 2, characterized in that, The substrate has a first distance between its surface near the split gate and the split gate, and a second distance between its surface near the split gate and the metal field plate, the second distance being greater than the first distance.

6. The laterally diffused metal-oxide-semiconductor device according to claim 5, characterized in that, The first distance is between 200 angstroms and 800 angstroms; And / or, the second distance is between 1000 angstroms and 5000 angstroms.

7. The laterally diffused metal-oxide-semiconductor device according to claim 2, characterized in that, The gate includes: A gate dielectric layer is disposed on the substrate; A gate conductive layer covers the side of the gate dielectric layer away from the substrate and a portion of the side of the field dielectric layer away from the substrate.

8. The laterally diffused metal-oxide-semiconductor device according to any one of claims 1-7, characterized in that, Along the direction in which the source region and the drain region are arranged, the ratio of the size of the gate to the size of the split gate is between 0.25 and 4.

9. The laterally diffused metal-oxide-semiconductor device according to any one of claims 1-7, characterized in that, The laterally diffused metal-oxide-semiconductor device further includes a second dielectric layer disposed between the gate and the split gate.

10. The laterally diffused metal-oxide-semiconductor device according to any one of claims 1-7, characterized in that, The laterally diffused metal-oxide-semiconductor device further includes: A body lead-out area is provided within the body area; A first conductive structure is disposed on the side of the substrate near the gate and is electrically connected to the source region, the body lead-out region, the split gate, and the metal field plate; the first conductive structure is used to connect to a first potential; A second conductive structure is disposed on the side of the substrate near the gate and electrically connected to the drain region. The second conductive structure is used to access a second potential. A third conductive structure is disposed on the side of the substrate near the gate and electrically connected to the gate. The third conductive structure is used to access a third potential.

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