Laterally diffused metal oxide semiconductor device

Abstract

The invention relates to a laterally diffused metal oxide semiconductor device. The laterally diffused metal oxide semiconductor device comprises a substrate which is internally provided with a drift region, a body region, a source region and a drain region; the body region and the drain region are arranged in the drift region at intervals along a first direction, and the source region is arranged in the body region; the first direction is perpendicular to the thickness direction of the substrate; the grid electrode is arranged on the substrate, and the orthographic projection of the grid electrode on the substrate is located between the source region and the drain region and covers part of the body region; the grid electrode comprises a grid dielectric layer and a grid conducting layer which are stacked, a plurality of through holes which are distributed at intervals are formed in the grid conducting layer, and the through holes penetrate through the grid conducting layer in the thickness direction of the substrate; the plurality of split gates are correspondingly arranged in the plurality of through holes; the split gate is insulated from the gate conductive layer; the source region and the split gate are electrically connected with a first potential. According to the invention, the FOM value of the laterally diffused metal oxide semiconductor device can be reduced, and the performance of the device is improved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a laterally diffused metal-oxide-semiconductor device. Background Technology

[0002] With the continuous development of semiconductor technology, the application of Lateral Double-Diffuse Metal-Oxide-Semiconductor (LDMOS) devices is becoming increasingly widespread, while also placing higher demands on their performance. The Form-Off Value (FOM) is a key indicator of device performance; the smaller the FOM value, the better the device performance. FOM = Cgd * Rsp, determined by the LDMOS's Cgd capacitance and Rsp on-resistance. Reducing the FOM value has become a focus for designers. Summary of the Invention

[0003] Therefore, it is necessary to provide a laterally diffused metal-oxide-semiconductor device to address the above problems.

[0004] To achieve the above objectives, in a first aspect, this application provides a laterally diffused metal-oxide-semiconductor device, comprising:

[0005] A substrate having a drift region, a body region, a source region, and a drain region therein; the body region and the drain region are arranged at intervals along a first direction within the drift region, and the source region is located within the body region; the first direction is perpendicular to the thickness direction of the substrate;

[0006] A gate is disposed on the substrate, and the orthographic projection of the gate on the substrate is located between the source region and the drain region, and covers a portion of the body region; the gate includes a stacked gate dielectric layer and a gate conductive layer, and a plurality of vias are provided on the gate conductive layer at intervals, the vias penetrating the gate conductive layer along the thickness direction of the substrate;

[0007] Multiple split gates are correspondingly disposed within the multiple through holes; the split gates are insulated from the gate conductive layer;

[0008] The source region and the split gate are both electrically connected to the first potential.

[0009] In one embodiment, the plurality of through holes are arranged at intervals along the second direction;

[0010] The second direction intersects the first direction, and the second direction is perpendicular to the thickness direction of the substrate.

[0011] In one embodiment, the plurality of through holes are arranged at intervals along the first direction.

[0012] In one embodiment, the plurality of vias are arranged in rows along the first direction and in columns along a second direction intersecting the first direction; the second direction is perpendicular to the thickness direction of the substrate.

[0013] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes a field dielectric layer disposed on the side of the substrate near the gate, a portion of the gate conductive layer disposed on the side of the gate dielectric layer away from the substrate, and another portion of the gate conductive layer disposed on the side of the field dielectric layer away from the substrate.

[0014] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes a metal field plate disposed on the side of the field dielectric layer away from the substrate and on the side of the gate conductive layer near the drain region;

[0015] The metal field plate is electrically connected to the first potential and is insulated from the gate conductive layer.

[0016] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes a first dielectric layer, at least a portion of which is disposed between the metal field plate and the field dielectric layer.

[0017] In one embodiment, the dielectric constant of the first dielectric layer is greater than the dielectric constant of the field dielectric layer.

[0018] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes:

[0019] A body lead-out area is provided within the body area;

[0020] A first electrical connection structure is disposed on the side of the substrate near the gate and is electrically connected to the source region, the body lead-out region, the split gate, and the metal field plate; the first electrical connection structure is used to connect to a first potential;

[0021] A second electrical connection structure is disposed on the side of the substrate near the gate and electrically connected to the drain region. The second electrical connection structure is used to access a second potential.

[0022] A third electrical connection structure is disposed on the side of the substrate near the gate and electrically connected to the gate conductive layer. The third electrical connection structure is used to access a third potential.

[0023] In one embodiment, the laterally diffused metal-oxide-semiconductor device further includes a second dielectric layer disposed between the gate conductive layer and the split gate.

[0024] The laterally diffused metal-oxide-semiconductor device provided in this application embodiment has multiple vias on the gate conductive layer and multiple split gates correspondingly disposed within these vias, with both the source region and the split gates electrically connected to a first potential. Thus, on the one hand, the split gates not only shield the gate-drain capacitance Cgd between the drain region and the gate, but also convert the gate-drain capacitance Cgd into a source-drain capacitance Csd, thereby significantly reducing the gate-drain capacitance Cgd; on the other hand, by setting the gate conductive layer as a porous structure, it helps to increase the gate coverage area, thereby weakening the adverse effect of the split gates on the on-resistance, which in turn helps to reduce the FOM value of the device and improve device performance. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments or exemplary embodiments of this application, the drawings used in the description of the embodiments or exemplary embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the structure of a laterally diffused metal-oxide-semiconductor device provided in one embodiment of this application.

[0027] Figure 2 for Figure 1 The diagram shows a cross-sectional structure of a laterally diffused metal-oxide-semiconductor device.

[0028] Figure 3 This is a schematic cross-sectional view of another laterally diffused metal-oxide-semiconductor device provided in one embodiment of this application.

[0029] Explanation of reference numerals in the attached figures:

[0030] 1. Laterally diffused metal-oxide-semiconductor device; 10. Substrate; 21. Drift region; 22. Body region; 23. Source region; 24. Drain region; 25. Body lead-out region; 30. Gate; 31. Gate dielectric layer; 32. Gate conductive layer; 32a. Via; 40. Split gate; 50. Metal field plate; 60. Field dielectric layer; 70. First dielectric layer; 80. Second dielectric layer; 90. First conductive structure; 91. First contact metal; 92. First electrode; 93. Second electrode; 94. Third electrode; 100. Second conductive structure; 101. Second contact metal; 102. Fourth electrode. Detailed Implementation

[0031] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0033] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0034] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0035] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.

[0036] Embodiments of the application are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures), thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the application.

[0037] With the continuous development of semiconductor technology, the application of Lateral Double-Diffuse Metal-Oxide-Semiconductor (LDMOS) devices is becoming increasingly widespread, while also placing higher demands on their performance. The Form-Off Value (FOM) is a key indicator of device performance; the smaller the FOM value, the better the device performance. FOM = Cgd * Rsp, determined by the LDMOS's Cgd capacitance and Rsp on-resistance. Reducing the FOM value has become a focus for designers.

[0038] To address the above issues, this application provides a laterally diffused metal-oxide-semiconductor device capable of reducing the FOM value. This laterally diffused metal-oxide-semiconductor device can be either an N-type or a P-type device.

[0039] Specifically, refer to Figure 1 As shown, the laterally diffused metal-oxide-semiconductor device 1 includes a substrate 10, a gate 30, and a plurality of split gates 40. The substrate 10 contains a drift region 21, a body region 22, a source region 23, and a drain region 24. The body region 22 and the drain region 24 are spaced apart within the drift region 21 along a first direction X, and the source region 23 is located within the body region 22. The first direction X is perpendicular to the thickness direction of the substrate 10. The gate 30 is disposed on the substrate 10, and its orthogonal projection onto the substrate 10 is located between the source region 23 and the drain region 24, covering a portion of the body region 22. The gate 30 includes a stacked gate dielectric layer 31 and a gate conductive layer 32. A plurality of vias 32a are spaced apart on the gate conductive layer 32, penetrating the gate conductive layer 32 along the thickness direction of the substrate 10. The plurality of split gates 40 are correspondingly disposed within the plurality of vias 32a; the split gates 40 are insulated from the gate conductive layer 32. In this context, both the source region 23 and the split gate 40 are electrically connected to the first potential.

[0040] It should be noted that multiple split gates 40 can be provided within a single through-hole 32a. Alternatively, only one split gate 40 can be provided within a single through-hole 32a; that is, the multiple split gates 40 are provided in a one-to-one correspondence with the multiple through-holes 32a. The shape of the through-hole 32a can be rectangular, circular, polygonal, or irregular. In this embodiment, by providing multiple through-holes 32a on the gate conductive layer 32, the gate conductive layer 32 is effectively made into a porous structure.

[0041] It is understood that the material of the substrate 10 may be monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium silicon compound, silicon-on-insulator (SOI) or low-temperature polycrystalline silicon (LTPS), or other materials known to those skilled in the art. The substrate 10 can provide a supporting foundation for the structural layers on the substrate 10.

[0042] In one embodiment, the substrate 10 is P-type doped, the drift region 21 is N-type doped, the body region 22 is P-type doped, the source region 23 is N-type doped, and the drain region 24 is N-type doped.

[0043] The laterally diffused metal-oxide-semiconductor device 1 provided in this application embodiment has multiple vias 32a on the gate conductive layer 32, and multiple split gates 40 correspondingly disposed within the multiple vias 32a, with both the source region 23 and the split gates 40 electrically connected to a first potential. Thus, on the one hand, the split gates 40 can not only shield the gate-drain capacitance Cgd between the drain region 24 (drain terminal) and the gate 30, but also convert the gate-drain capacitance Cgd into a source-drain capacitance Csd, thereby significantly reducing the gate-drain capacitance Cgd; on the other hand, by setting the gate conductive layer 32 as a porous structure, the impact of the split gates 40 on the coverage area of ​​the gate conductive layer 32 is reduced, which helps to make the coverage area of ​​the gate conductive layer 32 larger, thereby making the coverage area of ​​the gate 30 larger, weakening the adverse effect of the split gates 40 on the on-resistance, and thus helping to reduce the FOM value of the device and improve device performance.

[0044] In one embodiment, reference Figure 1 and Figure 2 As shown, a plurality of vias 32a are arranged at intervals along a second direction Y. The second direction Y intersects the first direction X, and the second direction Y is perpendicular to the thickness direction of the substrate 10. Here, the second direction Y corresponds to the width direction of the laterally diffused metal-oxide-semiconductor device 1.

[0045] Since both the drain region 24 and the gate 30 extend along the second direction Y, arranging the split gate 40 along the second direction Y is beneficial for better shielding the gate-drain capacitance Cgd between the drain region 24 (drain end) and the gate 30, thereby minimizing the gate-drain capacitance Cgd.

[0046] In one embodiment, reference Figure 3 As shown, multiple vias 32a are arranged at intervals along the first direction X. Here, the first direction X corresponds to the length direction of the laterally diffused metal-oxide-semiconductor device 1. This allows designers to utilize the dimensions along the device's length, facilitating the setting based on the actual dimensions of the device.

[0047] In one embodiment, a plurality of vias 32a are arranged in a row along a first direction X and in a column along a second direction Y intersecting the first direction X; the second direction Y is perpendicular to the thickness direction of the substrate 10. That is, the plurality of vias 32a are arranged in an array.

[0048] In this way, on the one hand, designers can make full use of the dimensions in the length and width directions of the device, which makes it easier for designers to set according to the actual size of the device; on the other hand, it is beneficial to better shield the gate-drain capacitance Cgd between the drain region 24 (drain terminal) and the gate 30, thereby minimizing the gate-drain capacitance Cgd.

[0049] It should be noted that the multiple through holes 32a can also be arranged in an irregular manner.

[0050] It is understood that the multiple through holes 32a can be arranged at equal intervals or at unequal intervals. This application embodiment does not limit the arrangement of the through holes 32a; designers can design the arrangement of the through holes 32a according to actual needs.

[0051] In one embodiment, the gate conductive layer 32 and the split gate 40 are made of the same material. For example, both the gate conductive layer 32 and the split gate 40 are made of polysilicon. Thus, the gate conductive layer 32 and the split gate 40 can be fabricated in the same process, without requiring additional fabrication steps compared to conventional devices.

[0052] It is understood that the material of the split gate 40 can also be a metallic material. This application embodiment does not limit the material of the split gate 40.

[0053] In one embodiment, the laterally diffused metal-oxide semiconductor device 1 further includes a field dielectric layer 60, which is disposed on the side of the substrate 10 near the gate 30. A portion of the gate conductive layer 32 is disposed on the side of the gate dielectric layer 31 away from the substrate 10, and another portion of the gate conductive layer 32 is disposed on the side of the field dielectric layer 60 away from the substrate 10.

[0054] In one embodiment, the thickness of the gate dielectric layer 31 is less than the thickness of the field dielectric layer 60.

[0055] For example, the gate dielectric layer 31 can be a gate oxide layer. The field dielectric layer 60 can be a field oxide layer.

[0056] In one embodiment, the laterally diffused metal-oxide-semiconductor device 1 further includes a metal field plate 50, which is disposed on the side of the field dielectric layer 60 away from the substrate 10 and on the side of the gate conductive layer 32 near the drain region 24. The metal field plate 50 is electrically connected to a first potential and is insulated from the gate conductive layer 32.

[0057] Thus, on the one hand, the metal field plate 50 can further shield the gate-drain capacitance Cgd between the drain region 24 (drain terminal) and the gate 30, and further convert the gate-drain capacitance Cgd into the source-drain capacitance Csd, thereby significantly reducing the gate-drain capacitance Cgd of the device and thus reducing the switching loss of the device; on the other hand, both the split gate 40 and the metal field plate 50 can help deplete the drift region 21. Under the off-state condition, the multi-field plate structure formed by the split gate 40 and the metal field plate 50 optimizes the electric field of the drift region 21, which is beneficial to improving the breakdown voltage of the device.

[0058] In one embodiment, the laterally diffused metal-oxide-semiconductor device 1 further includes a first dielectric layer 70, at least partially disposed between the metal field plate 50 and the field dielectric layer 60. Specifically, a split gate 40 is disposed on the surface of the field dielectric layer 60 away from the substrate 10, and the first dielectric layer 70 is disposed between the metal field plate 50 and the field dielectric layer 60.

[0059] Thus, the metal field plate 50 and the split gate 40 together constitute a stepped field plate, which can better optimize the electric field of the drift region 21 and help improve the breakdown voltage of the device under off-state conditions.

[0060] In one embodiment, the dielectric constant of the first dielectric layer 70 is greater than that of the field dielectric layer 60. This effectively makes the dielectric layer structure between the metal field plate 50 and the substrate 10 a variable-K dielectric layer. Thus, the metal field plate 50 can better optimize the electric field of the drift region 21, which is beneficial for improving the breakdown voltage of the device under off-state conditions.

[0061] In one embodiment, the laterally diffused metal-oxide-semiconductor device 1 further includes a second dielectric layer 80 disposed between the gate conductive layer 32 and the split gate 40. This facilitates insulation between the gate conductive layer 32 and the split gate 40. It is understood that the second dielectric layer 80 comprises an insulating material.

[0062] The material of the second dielectric layer 80 can be insulating materials such as air or silicon dioxide.

[0063] It should be noted that the split gate 40 can be located on the side of the gate dielectric layer 31 away from the substrate 10. The orthographic projection of the split gate 40 on the substrate 10 does not overlap with the body region 22, and the orthographic projection of the second dielectric layer 80 on the substrate 10 does not overlap with the body region 22. In this way, the split gate 40 and the second dielectric layer 80 can be prevented from affecting the operating performance of the gate 30.

[0064] In one embodiment, the laterally diffused metal-oxide-semiconductor device 1 further includes a body lead-out region 25 disposed within the body region 22. Further, the body lead-out region 25 is connected to the same potential as the source region 23, and the doping type of the body lead-out region 25 is P-type.

[0065] In one embodiment, the laterally diffused metal-oxide-semiconductor device 1 further includes a first conductive structure 90, a second conductive structure 100, and a third conductive structure (not shown). The first conductive structure 90 is disposed on the side of the substrate 10 near the gate 30 and is electrically connected to the source region 23, the body lead-out region 25, the split gate 40, and the metal field plate 50; the first conductive structure 90 is used to connect to a first potential. The second conductive structure 100 is disposed on the side of the substrate 10 near the gate 30 and is electrically connected to the drain region 24; the second conductive structure 100 is used to connect to a second potential. The third conductive structure is disposed on the side of the substrate 10 near the gate 30 and is electrically connected to the gate 30; the third conductive structure is used to connect to a third potential. By providing the first conductive structure 90, the second conductive structure 100, and the third conductive structure, it is convenient for the device to connect to potentials.

[0066] In one embodiment, the first conductive structure 90 includes a first contact metal 91, a first electrode 92, a second electrode 93, and a third electrode 94. The first contact metal 91 is used for electrical connection to an external first potential. One end of the first electrode 92 is electrically connected to the body lead-out region 25, and the other end is electrically connected to the first contact metal 91. One end of the second electrode 93 is electrically connected to the source region 23, and the other end is electrically connected to the first contact metal 91. One end of the third electrode 94 is electrically connected to the split gate 40, and the other end is electrically connected to the first contact metal 91. The metal field plate 50 is directly electrically connected to the first contact metal 91.

[0067] It should be noted that the metal field plate 50, the first electrode 92, the second electrode 93, and the third electrode 94 can be made of the same material. In this way, the metal field plate 50, the first electrode 92, the second electrode 93, and the third electrode 94 can be manufactured in the same process, without the need for additional steps compared to traditional devices.

[0068] In one embodiment, the second conductive structure 100 includes a second contact metal 101 and a fourth electrode 102. The second contact metal 101 is used for electrical connection to a second external potential. One end of the fourth electrode 102 is electrically connected to the drain region 24, and the other end is electrically connected to the second contact metal 101.

[0069] It should be noted that the metal field plate 50, the first electrode 92, the second electrode 93, the third electrode 94, and the fourth electrode 102 can be made of the same material. In this way, the metal field plate 50, the first electrode 92, the second electrode 93, the third electrode 94, and the fourth electrode 102 can be manufactured in the same process, without the need for additional steps compared to traditional devices.

[0070] Furthermore, the second contact metal 101 and the first contact metal 91 can be made of the same material. In this way, the first contact metal 91 and the second contact metal 101 can be manufactured in the same process, without the need for additional steps compared to traditional devices.

[0071] It is understandable that the split gate 40 can also be electrically connected to the metal field plate 50 and to the first contact metal 91 through the metal field plate 50.

[0072] In one embodiment, the first dielectric layer 70 further covers the surface of the gate 30, the surface of the split gate 40, and the exposed surface of the substrate 10. The first dielectric layer 70 is provided with a first via (not shown), a second via (not shown), a third via (not shown), and a fourth via (not shown). A first electrode 92 is disposed in the first via, a second electrode 93 is disposed in the second via, a third electrode 94 is disposed in the third via, and a fourth electrode 102 is disposed in the fourth via.

[0073] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0074] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0075] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A laterally diffused metal-oxide-semiconductor device, characterized in that, include: A substrate having a drift region, a body region, a source region, and a drain region therein; the body region and the drain region are arranged at intervals along a first direction within the drift region, and the source region is located within the body region; the first direction is perpendicular to the thickness direction of the substrate; A gate is disposed on the substrate, and the orthographic projection of the gate on the substrate is located between the source region and the drain region, and covers a portion of the body region; the gate includes a stacked gate dielectric layer and a gate conductive layer, and a plurality of vias are provided on the gate conductive layer at intervals, the vias penetrating the gate conductive layer along the thickness direction of the substrate; Multiple split gates are correspondingly disposed within the multiple through holes; the split gates are insulated from the gate conductive layer; The source region and the split gate are both electrically connected to the first potential.

2. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The plurality of through holes are arranged at intervals along the second direction; The second direction intersects the first direction, and the second direction is perpendicular to the thickness direction of the substrate.

3. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The plurality of through holes are arranged at intervals along the first direction.

4. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The plurality of through holes are arranged in a row along the first direction and in a column along a second direction intersecting the first direction; the second direction is perpendicular to the thickness direction of the substrate.

5. The laterally diffused metal-oxide-semiconductor device according to claim 1, characterized in that, The laterally diffused metal-oxide-semiconductor device further includes a field dielectric layer, wherein the field dielectric layer is disposed on the side of the substrate near the gate, a portion of the gate conductive layer is disposed on the side of the gate dielectric layer away from the substrate, and another portion of the gate conductive layer is disposed on the side of the field dielectric layer away from the substrate.

6. The laterally diffused metal-oxide-semiconductor device according to claim 5, characterized in that, The laterally diffused metal-oxide-semiconductor device further includes a metal field plate, which is disposed on the side of the field dielectric layer away from the substrate and on the side of the gate conductive layer near the drain region. The metal field plate is electrically connected to the first potential and is insulated from the gate conductive layer.

7. The laterally diffused metal-oxide-semiconductor device according to claim 6, characterized in that, The laterally diffused metal-oxide-semiconductor device further includes a first dielectric layer, at least a portion of which is disposed between the metal field plate and the field dielectric layer.

8. The laterally diffused metal-oxide-semiconductor device according to claim 7, characterized in that, The dielectric constant of the first dielectric layer is greater than the dielectric constant of the field dielectric layer.

9. The laterally diffused metal-oxide-semiconductor device according to claim 6, characterized in that, The laterally diffused metal-oxide-semiconductor device further includes: A body lead-out area is provided within the body area; A first electrical connection structure is disposed on the side of the substrate near the gate and is electrically connected to the source region, the body lead-out region, the split gate, and the metal field plate; the first electrical connection structure is used to connect to a first potential; A second electrical connection structure is disposed on the side of the substrate near the gate and electrically connected to the drain region. The second electrical connection structure is used to access a second potential. A third electrical connection structure is disposed on the side of the substrate near the gate and electrically connected to the gate conductive layer. The third electrical connection structure is used to access a third potential.

10. The laterally diffused metal-oxide-semiconductor device according to any one of claims 1-9, characterized in that, The laterally diffused metal-oxide-semiconductor device further includes a second dielectric layer disposed between the gate conductive layer and the split gate.

Images