MOSFET power device and preparation method thereof

Abstract

The invention discloses a metal-oxide-semiconductor field effect transistor (MOSFET) power device and a preparation method thereof. The MOSFET power device comprises a shield grid and a first isolation dielectric layer which are located in the groove, the shield grid comprises a first part and a second part, the first part is located at the bottom of the groove, and the first isolation dielectric layer is located in the groove and the side, away from the substrate, of the first part; the grid electrodes are located on the two sides of the first isolation dielectric layer in the first direction, the width of the grid electrodes in the first direction is smaller than that of the shielding grid, and the first direction is perpendicular to the extending direction of the groove; the oxide layer is located in the groove, one part of the oxide layer wraps the shielding grid, the second part penetrates through the first isolation dielectric layer and the oxide layer and is in contact with the first part, and the other part of the oxide layer is located between the grid electrode and the side wall of the extension section. According to the invention, the problem that the MOSFET power device in the prior art is difficult to realize the balance between optimization of performances such as voltage endurance capability, gate-drain capacitance, switching speed and the like and reduction of manufacturing cost is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a MOSFET power device and a preparation method thereof. BACKGROUND

[0002] In the field of power semiconductor devices, especially in low-voltage MOSFET devices, Shielded-Gate Trench (SGT) MOSFETs exhibit superior performance to traditional MOSFETs due to their unique shielded gate structure, particularly in reducing switching loss and improving specific on-resistance. Traditional SGT MOSFETs are divided into left-right structure and up-down structure according to the position of the gate and shield field plate, although they exhibit their own advantages in some aspects, but the comprehensive performance still needs to be improved.

[0003] The left-right structure design can provide higher voltage resistance, but the shielding effect between the gate and the drain is insufficient, resulting in a high reverse capacitance C rss and limited switching speed. In addition, this structure has high requirements for manufacturing processes, increasing production costs, and reliability under extreme conditions.

[0004] The SGT MOSFET of the up-down structure design has low on-resistance and good process stability, suitable for low-voltage applications. However, this design performs poorly under high-voltage conditions, and it is difficult to significantly improve its voltage resistance through improvements, limiting its use in a wider range of applications.

[0005] In recent years, to optimize the performance of SGT MOSFETs, researchers have tried various process designs and material improvements, including using multi-layer epitaxial layer processes, changing shielded gate structures, and thickening the oxide layer around the trench bottom field plate. Although these methods can improve certain characteristics of the device to some extent, such as high-voltage resistance or uniformity of the electric field distribution, they also bring a series of new problems. For example, the design of non-uniform trench width increases the complexity of the process, making it difficult to etch the gate sharp corner, affecting the reliability and consistency of the device. In addition, these improvement schemes often come with a significant increase in manufacturing costs, which is not conducive to mass production and application.

[0006] Therefore, the SGT MOSFET power device and the preparation method thereof in the prior art have obvious limitations in voltage resistance, gate-drain capacitance control, switching speed optimization, and the balance of manufacturing costs, especially in high-voltage scenarios, the reliability and heat dissipation of the device, and the consistency of current sharing are still insufficient. Therefore, there is an urgent need for a power device and a preparation method thereof that can overcome the above problems. SUMMARY

[0007] The application provides a MOSFET power device and a preparation method thereof, to solve the problem that in the prior art, it is difficult to balance the performance of the MOSFET power device, such as the withstand voltage capability, gate-drain capacitance and switching speed, and the reduction of manufacturing cost.

[0008] According to an aspect of the application, a MOSFET power device is provided, comprising:

[0009] a substrate comprising a stacked substrate and an epitaxial layer, the epitaxial layer having a source region and a trench extending to the inside of the source region along a first surface, the first surface being a side surface of the epitaxial layer facing away from the substrate;

[0010] a shield gate and a first isolation dielectric layer located in the trench, the shield gate comprising a first part and a second part sequentially distributed in a direction away from the substrate, the first part being located at the bottom of the trench, and the first isolation dielectric layer being located in the trench and on a side of the first part away from the substrate;

[0011] a gate located on both sides of the first isolation dielectric layer in a first direction, and the width of the gate in the first direction being smaller than the width of the first part, the first direction being perpendicular to the extension direction of the trench;

[0012] an oxide layer located in the trench, and a part of the oxide layer wrapping the first part, the second part penetrating through the first isolation dielectric layer and the oxide layer and being in contact with the first part, and another part of the oxide layer being located between the gate and the sidewall of the extension section.

[0013] Optionally, the oxide layer comprises a field oxide layer, an isolation oxide layer and a gate oxide layer, the isolation oxide layer being located on a side of the field oxide layer away from the substrate, the field oxide layer and the isolation oxide layer collectively wrapping the first part and forming a shield gate structure with the second part, and the gate oxide layer being located outside the gate in the first direction; a normal projection of the gate on the shield gate structure is a first normal projection, and at least part of the first normal projection falls into the surface of the shield gate structure.

[0014] Optionally, the first part has a second surface close to the bottom surface of the trench, and the oxide layer has a third surface in contact with the bottom surface of the trench, the second surface and the third surface being arc surfaces protruding towards the substrate.

[0015] Optionally, the material of the first isolation dielectric layer is a low dielectric constant material.

[0016] Optionally, the source region includes: a first inversion region located in the epitaxial layer, wherein the first inversion region is a region formed by ion implantation of a portion of the first surface; a second inversion region located in the epitaxial layer and at least one side of the first inversion region, wherein the first inversion region is a region formed by ion implantation of a portion of the first surface, and the first inversion region and the second inversion region have the same doping type; and an implantation region located in a portion of the second inversion region, wherein the implantation region is a region formed by ion implantation of the surface of the second inversion region.

[0017] Optionally, the MOSFET power device further includes: a source, located on the side of the epitaxial layer away from the substrate and in contact with the source region; a second isolation dielectric layer and an ohmic contact metal layer, located between the epitaxial layer and the source, wherein the second isolation dielectric layer isolates the source from the gate, and the ohmic contact metal layer contacts the source and the source region respectively; and a drain, located on the side of the substrate away from the epitaxial layer.

[0018] Optionally, the second isolation dielectric layer isolates the source electrode from the second portion; or one end of the second portion opposite to the first portion penetrates the second isolation dielectric layer and contacts the source electrode.

[0019] According to one aspect of this application, a method for fabricating a MOSFET power device is provided, the method comprising the following steps:

[0020] A substrate is provided, the substrate comprising a stacked substrate and an epitaxial layer;

[0021] The epitaxial layer has a source region and a trench extending along a first surface into the source region, the trench having a bottom and an extension communicating with the bottom, the first surface being the side surface of the epitaxial layer facing away from the substrate.

[0022] A shielding gate, a first isolation dielectric layer, a gate, and an oxide layer are formed in the trench. The shielding gate includes a first portion and a second portion sequentially distributed along a direction away from the substrate. The first portion is located at the bottom. The first isolation dielectric layer is located on the side of the first portion away from the substrate. The gate is located on both sides of the first isolation dielectric layer along a first direction, and the width of the gate in the first direction is smaller than the width of the first portion. A portion of the oxide layer covers the first portion, and another portion of the oxide layer is located between the gate and the sidewall of the extension. The second portion penetrates the first isolation dielectric layer and the oxide layer and contacts the first portion. The first direction is perpendicular to the extension direction of the trench.

[0023] Optionally, the step of forming the shielding gate, the oxide layer, the gate, and the first isolation dielectric layer in the trench includes: covering the inner wall of the trench with a field oxide pre-layer; forming a first portion at the bottom, wherein a portion of the field oxide pre-layer is located between the bottom surface of the trench and the first portion, and removing the field oxide pre-layer located in the extension, the remaining field oxide pre-layer constituting the field oxide layer; forming an isolation oxide layer on the surface of the first portion, and forming a gate oxide layer on the sidewall of the extension, the isolation oxide layer, the gate oxide layer, and the isolation oxide layer constituting the oxide layer; forming a gate pre-layer in the trench, removing a portion of the gate pre-layer to expose a portion of the surface of the isolation oxide layer, the remaining gate pre-layer covering the sidewall of the even-numbered extensions, and forming the first isolation dielectric layer in the area where the gate pre-layer was removed; forming a second portion in the trench penetrating the first isolation dielectric layer and the oxide layer, such that the second portion contacts the first portion.

[0024] Optionally, the step of forming the source region includes: performing ion implantation on a portion of the first surface to form a first inversion region; performing ion implantation on a portion of the first surface to form a second inversion region located on at least one side of the first inversion region, wherein the first inversion region and the second inversion region have the same doping type; performing ion implantation on the surface of the second inversion region to form an implantation region located in a portion of the second inversion region; the step of forming the trench includes: sequentially forming a mask layer and a photoresist layer on the surface of the source region; etching the photoresist layer to form a first groove, wherein the bottom surface of the first groove is an arc surface; etching the mask layer through the first groove to form a second groove connecting the photoresist layer and the mask layer; etching the epitaxial layer through the second groove to form the trench penetrating the source region, wherein the bottom surface of the trench is an arc surface protruding toward the substrate.

[0025] In this application, an active region and a trench extending from a first surface into the source region are formed within the epitaxial layer of a MOSFET power device. A shielding gate is located in the trench and includes a first portion and a second portion sequentially distributed along a direction away from the substrate. The first portion is located at the bottom of the trench. A first isolation dielectric layer is located in the trench and on the side of the first portion away from the substrate. The gate is located on both sides of the first isolation dielectric layer along a first direction, and the width of the gate in the first direction is smaller than the width of the first portion. This results in a larger width for the first portion located at the bottom of the trench, which not only provides stronger shielding and more effectively shields the electric field between the gate and drain, but also effectively reduces the electric field coupling between the gate and drain when the device is subjected to high voltage, preventing electrical breakdown and improving withstand voltage performance. Furthermore, it effectively reduces the face-to-face area between the gate and drain, thereby significantly reducing the reverse capacitance C. rrsMeanwhile, the gate is disposed on both sides of the first isolation dielectric layer and its width is smaller than that of the first part, effectively reducing the gate volume, thereby reducing the gate charge, improving the switching speed, and reducing switching losses. Furthermore, the trench structure in the MOSFET power device of this application can be formed in one step, which simplifies the process flow and reduces the frequency of costly steps such as masking, photolithography, etching, and cleaning, thereby significantly reducing the overall manufacturing cost. This allows the MOSFET power device of this application to reduce manufacturing costs while improving withstand voltage, reducing gate-drain capacitance, and accelerating switching speed, thus solving the problem in related technologies where it is difficult to achieve a balance between optimizing withstand voltage, gate-drain capacitance, switching speed, and other performance characteristics and reducing manufacturing costs in MOSFET power devices. Attached Figure Description

[0026] The accompanying drawings, which form part of this application, are used to provide a further understanding of this application. The illustrative embodiments and descriptions of this application are used to explain this application and do not constitute an undue limitation of this application. In the drawings:

[0027] Figure 1 This is a cross-sectional schematic diagram of a MOSFET power device according to an embodiment of this application;

[0028] Figure 2 This is a cross-sectional schematic diagram of another MOSFET power device provided according to an embodiment of this application;

[0029] Figure 3 This is a schematic flowchart of a method for fabricating a MOSFET power device according to an embodiment of this application;

[0030] Figure 4 This illustration shows a cross-sectional view of the substrate provided in a method for fabricating a MOSFET power device according to an embodiment of this application.

[0031] Figure 5 It shows in Figure 4 A cross-sectional schematic diagram of the matrix after the formation of the first inversion region in the epitaxial layer;

[0032] Figure 6 It shows in Figure 5 A schematic cross-sectional view of the matrix after the formation of the second inversion region in the epitaxial layer;

[0033] Figure 7 It shows in Figure 6 A cross-sectional schematic diagram of the matrix after the injection region is formed in the second inversion region;

[0034] Figure 8 It shows in Figure 7 A cross-sectional schematic diagram of the substrate after a mask layer and a photoresist layer are sequentially formed on the epitaxial layer;

[0035] Figure 9 It shows in Figure 8 A cross-sectional schematic diagram of the substrate after the first groove is formed in the photoresist layer;

[0036] Figure 10 It shows in Figure 9 A cross-sectional schematic diagram of the substrate after the second groove is formed in the mask layer and photoresist layer;

[0037] Figure 11 It shows the formation of through Figure 10 A cross-sectional schematic diagram of the substrate behind the trench in the source region;

[0038] Figure 12 It shows in Figure 11 A cross-sectional schematic diagram of the substrate after the inner wall of the trench is covered with an oxygen pre-coating layer;

[0039] Figure 13 It shows in Figure 12 A cross-sectional view of the substrate after the bottom of the trench forms the first part of the shielding grid and the partial field oxygen pre-layer is removed to form the field oxygen layer;

[0040] Figure 14 It shows in Figure 13 A cross-sectional schematic diagram of the substrate after an isolation oxide layer is formed on the surface of the first part of the shielding grid;

[0041] Figure 15 It shows in Figure 14 A cross-sectional schematic diagram of the substrate after the gate oxide layer is formed on the sidewall of the extended section of the trench;

[0042] Figure 16 It shows in Figure 15 A cross-sectional schematic diagram of the substrate after the gate preparation layer is formed in the trench;

[0043] Figure 17 It shows the removal Figure 16 A cross-sectional view of the substrate after a partial gate preparation layer is formed to form the gate and a first isolation dielectric layer is formed in the area where the gate preparation layer is removed;

[0044] Figure 18 It shows in Figure 17 A cross-sectional schematic diagram of the substrate after the second part of the shielding grid, which penetrates the first isolation medium layer and the oxide layer, is formed in the trench;

[0045] Figure 19 It shows in Figure 18 A cross-sectional schematic diagram of the substrate after the second isolation dielectric layer and the ohmic contact metal layer are formed on the epitaxial layer.

[0046] The above figures include the following reference numerals:

[0047] 10. Substrate; 100. Second isolation dielectric layer; 110. Substrate; 120. Epitaxial layer; 121. First surface; 130. Drain; 140. Ohmic contact metal layer; 150. Mask layer; 160. Photoresist layer; 171. First trench; 172. Second trench; 20. Source region; 210. First inversion region; 220. Second inversion region; 230. Implantation region; 30. Trench; 40. First portion; 401. Second surface; 50. First isolation dielectric layer; 60. Gate; 610. Gate preparation layer; 70. Oxide layer; 701. Third surface; 710. Field oxide layer; 711. Field oxide preparation layer; 720. Isolation oxide layer; 730. Gate oxide layer; 80. Second portion; 90. Source. Detailed Implementation

[0048] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0050] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0051] As described in the background section, existing SGT MOSFET power devices and their fabrication methods have significant limitations in balancing voltage withstand capability, gate-drain capacitance control, switching speed optimization, and manufacturing cost. Especially in high-voltage scenarios, the device's reliability, heat dissipation, and current sharing consistency remain insufficient. To address the challenge of achieving a balance between optimizing voltage withstand capability, gate-drain capacitance, and switching speed while reducing manufacturing costs in related MOSFET power devices, embodiments of this application provide a MOSFET power device and its fabrication method.

[0052] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0053] According to one embodiment of this application, a MOSFET power device is provided, such as... Figure 1 and Figure 2 As shown, it includes:

[0054] The substrate 10 includes a stacked substrate 110 and an epitaxial layer 120. An active region 20 is formed inside the epitaxial layer 120 and a trench 30 extending along a first surface 121 into the source region 20. The trench 30 has a bottom and an extension segment communicating with the bottom. The first surface 121 is the side surface of the epitaxial layer 120 facing away from the substrate 110.

[0055] The shielding gate and the first isolation dielectric layer 50 are located in the trench 30. The shielding gate includes a first portion 40 and a second portion 80 sequentially distributed in a direction away from the substrate 110. The first portion 40 is located at the bottom of the trench 30, and the first isolation dielectric layer 50 is located in the trench 30 and on the side of the first portion 40 away from the substrate 110.

[0056] Gate 60 is located on both sides of the first isolation dielectric layer 50 along the first direction, and the width of gate 60 in the first direction is smaller than the width of the first portion 40, and the first direction is perpendicular to the extension direction of trench 30.

[0057] An oxide layer 70 is located in the trench 30, and a portion of the oxide layer 70 covers the first portion 40. The second portion 80 penetrates the first isolation dielectric layer 50 and the oxide layer 70 and contacts the first portion 40. Another portion of the oxide layer 70 is located between the gate 60 and the sidewall of the extension.

[0058] In this embodiment, an active region 20 and a trench 30 extending from the first surface 121 into the source region 20 are formed inside the epitaxial layer 120 of the MOSFET power device. A shielding gate is located in the trench 30 and includes a first portion 40 and a second portion 80 sequentially distributed along a direction away from the substrate 110. The first portion 40 is located at the bottom of the trench 30. A first isolation dielectric layer 50 is located in the trench 30 and on the side of the first portion 40 away from the substrate 110. A gate 60 is located on both sides of the first isolation dielectric layer 50 along a first direction, and the width of the gate 60 in the first direction is smaller than the width of the first portion 40. This results in a larger width for the first portion 40 located at the bottom of the trench 30, which not only provides stronger shielding but also more effectively shields the electric field between the gate and the drain 130. Especially when the device is subjected to high voltage, it can effectively reduce the electric field coupling between the gate and the drain, prevent electrical breakdown, and improve the withstand voltage performance. It can also effectively reduce the facing area between the gate 60 and the drain 130, thereby significantly reducing the reverse capacitance C. rrs Meanwhile, the gate 60 is disposed on both sides of the first isolation dielectric layer 50, and its width is smaller than that of the first portion 40. The volume of the gate 60 is effectively reduced, thereby reducing the charge on the gate 60, improving the switching speed, and reducing switching losses. Furthermore, the trench structure in the MOSFET power device of this application can be formed in one step, which simplifies the process flow and reduces the frequency of costly steps such as masking, photolithography, etching, and cleaning, thereby significantly reducing the overall manufacturing cost. This allows the MOSFET power device of this application to reduce manufacturing costs while improving withstand voltage, reducing gate-drain capacitance, and accelerating switching speed. It solves the problem in related technologies where it is difficult to achieve a balance between optimizing withstand voltage, gate-drain capacitance, switching speed, and other performance characteristics and reducing manufacturing costs in MOSFET power devices.

[0059] In this embodiment, the substrate 10 can be made of silicon carbide, which allows the device to have high thermal conductivity and high breakdown field strength, making it suitable for manufacturing high-performance devices that can operate under high temperature and high pressure environments. Figure 1 and Figure 2 As shown, the substrate 10 includes a substrate 110 and an epitaxial layer 120. The doping concentration of the substrate 110 is higher than that of the epitaxial layer 120. The higher doping concentration of the substrate 110 can increase the depth of the depletion layer, thereby increasing the reverse breakdown voltage and reducing the risk of device breakdown. Furthermore, the substrate 110 can absorb charge carriers from the epitaxial layer 120, further reducing the on-resistance. The lower doping concentration of the epitaxial layer 120 can provide greater carrier mobility when the device is turned on, thereby reducing the on-resistance.

[0060] In this embodiment, the main function of the shield gate is to provide additional electric field shielding between the gate 60 and the drain 130 to optimize the switching performance and withstand voltage of the device. The material of the shield gate can be the same as that of the gate 60. The materials of the shield gate and the gate 60 can be independently selected from polysilicon and / or metals, and this embodiment does not make specific limitations.

[0061] In this embodiment, the first isolation dielectric layer 50 is located in the trench 30 and on the side of the first portion 40 of the shielding gate facing away from the substrate 110. Its main purpose is to form an insulating barrier between the polysilicon of the gate 60 and the source / drain region 130, reducing the capacitive coupling between the gate 60 and the source / drain, while protecting the oxide layer 70 of the gate 60 from the effects of subsequent process steps. The material of the first isolation dielectric layer 50 may include a low-k dielectric material. The application of such materials can reduce the parasitic capacitance between the gate 60 and the source metal, thereby reducing the switching losses of the device and improving the overall energy efficiency.

[0062] It should be noted that the material of the first insulating dielectric layer 50 is not limited to the low dielectric constant material mentioned above, but can also be other insulating materials, such as silicon dioxide (SiO2), silicon carbide oxide (SiCOH), silicon carbide (SiC), silicon fluoride glass (SiOF), silicon carbide nitrogen (SiCN), silicon oxynitride (SiON), silicon carbide oxynitride (SiCON), etc.

[0063] In some alternative implementations, such as Figure 1 and Figure 2 As shown, the oxide layer 70 includes a field oxide layer 710, an isolation oxide layer 720, and a gate oxide layer 730. The isolation oxide layer 720 is located on the side of the field oxide layer 710 away from the substrate 110. The field oxide layer 710 and the isolation oxide layer 720 together enclose the first portion 40 and form a shielding gate structure with the second portion 80. The gate oxide layer 730 is located on the outside of the gate 60 along the first direction. The orthographic projection of the gate 60 on the shielding gate structure is the first orthographic projection, and at least part of the first orthographic projection falls into the surface of the shielding gate structure.

[0064] In the above optional embodiments, the materials of the field oxide layer 710, the isolation oxide layer 720 and the gate oxide layer 730 can be the same or different. For example, the materials of the field oxide layer 710, the isolation oxide layer 720 and the gate oxide layer 730 are all silicon dioxide (SiO2).

[0065] Specifically, the field oxide layer 70 and the isolation oxide layer 720 tightly cover the first portion 40 of the shielding gate located at the bottom of the trench 30, while the gate oxide layer 70 is located on the outer side of the gate 60 along the first direction. The optimized structural design ensures that the orthogonal projection of the gate 60 onto the shielding gate structure falls into the surface of the first portion 40, thereby effectively reducing the overall volume of the gate 60, thus reducing the charge on the gate 60 and significantly enhancing the switching speed of the device. At the same time, by designing the first portion 40 in the trench 30 and the gate 60 as an upper and lower structure, the gate 60 is completely separated from the drain 130, effectively reducing the gate-drain capacitance and improving the high-frequency performance and energy conversion efficiency of the device.

[0066] In some alternative embodiments, the first portion 40 in the shielding grid has a second surface 401 near the bottom surface of the trench 30, and the oxide layer 70 has a third surface 701 in contact with the bottom surface of the trench 30. The second surface 401 and the third surface 701 are arcuate surfaces protruding toward the substrate 110.

[0067] In the above optional embodiments, the surface of the first portion 40 of the shielding gate near the bottom of the trench 30 (second surface 401) and the surface of the oxide layer 70 in contact with the bottom of the trench 30 (third surface 701) are designed as arc surfaces protruding towards the substrate 110. This arc surface design aims to improve the uniformity of the electric field distribution of the device, effectively dispersing the electric field concentration at the bottom of the trench 30 and avoiding reliability problems caused by charge concentration at the sharp corners of the gate 60. Simultaneously, the contact interface between the first portion 40 of the arc surface in the shielding gate and the oxide layer 70 at the bottom of the trench 30 is continuous. This not only enhances the shielding effect of the shielding gate on the electric field of the drain 130 but also optimizes the heat dissipation performance and the consistency of current distribution of the device. For example, both the second surface 401 and the third surface 701 are hemispherical surfaces.

[0068] Specifically, the field oxide layer 70 and the isolation oxide layer 720 tightly cover the first part 40 of the shielding gate located at the bottom of the trench 30, forming a shielding gate structure. Under high voltage, the shielding gate structure has an arc surface protruding towards the substrate 110 (which can also be understood as the shielding gate structure being inverted mushroom-shaped), which can more effectively control the electric field distribution, reduce the electric field peak, and thus improve the device's withstand voltage and operational reliability.

[0069] In this embodiment, the source region 20 may include: a first inversion region 210 located in the epitaxial layer 120, wherein the first inversion region 210 is a region formed by ion implantation of a portion of the first surface 121; a second inversion region 220 located in the epitaxial layer 120 and at least one side of the first inversion region 210, wherein the first inversion region 210 is a region formed by ion implantation of a portion of the first surface 121, and the first inversion region 210 and the second inversion region 220 have the same doping type; and an implantation region 230 located in a portion of the second inversion region 220, wherein the implantation region 230 is a region formed by ion implantation of the surface of the second inversion region 220.

[0070] Specifically, the structure of the source region 20 may include a first inversion region 210, a second inversion region 220, and an implantation region 230. The first inversion region 210 is formed in the epitaxial layer 120, adjacent to the first surface 121. The second inversion region 220 is formed on the side of the first inversion region 210, also located inside the epitaxial layer 120, and its doping type is the same as that of the first inversion region 210. The implantation region 230 is disposed in a part of the second inversion region 220 and is completed through further ion implantation. The first inversion region 210, the second inversion region 220, and the implantation region 230 are implanted in layers. The synergistic effect of the first inversion region 210 and the second inversion region 220 enhances the switching capability and current carrying capacity of the device, while the high concentration of charge carriers in the implantation region 230 ensures good ohmic contact and reduces source resistance.

[0071] In the above embodiments, the first inversion region 210 and the second inversion region 220 can be first-type doped regions, having N-type doping or P-type doping, and the implantation region 230 can be a second-type doped region, having P-type doping or N-type doping. For example, the first doped region has N-type doping and the second doped region has P-type doping, or the first doped region has P-type doping and the second doped region has N-type doping. The N-type doping element can be any one of pentavalent elements, including phosphorus (P), arsenic (As), and antimony (Sb), and the P-type doping element can be any one of trivalent elements, including boron (B), aluminum (Al), and gallium (Ga). The embodiments of this application do not specifically limit the doping element.

[0072] In this embodiment, the MOSFET power device may further include: a source 90 located on the side of the epitaxial layer 120 away from the substrate 110 and in contact with the source region 20; a second isolation dielectric layer 100 and an ohmic contact metal layer 140 located between the epitaxial layer 120 and the source 90, wherein the second isolation dielectric layer 100 isolates the source 90 from the gate 60, and the ohmic contact metal layer 140 is in contact with the source 90 and the source region 20 respectively; and a drain 130 located on the side of the substrate 110 away from the epitaxial layer 120.

[0073] Specifically, the source 90 is disposed on the side of the epitaxial layer 120 away from the substrate 110 and directly contacts the source region 20, ensuring good conductivity between the source 90 and the active region 20. A second isolation dielectric layer 100 is located between the epitaxial layer 120 and the source 90, effectively isolating the source 90 from the gate 60 and avoiding parasitic capacitance between them, thereby further optimizing the device's switching performance. A drain 130 is disposed on the side of the substrate 110 away from the epitaxial layer 120, ensuring continuity between the drain 130 and the substrate 110 and providing a stable current path for the device.

[0074] In the above embodiments, the source electrode 90 and the drain electrode 130 are made of metals and / or metal compounds, such as nickel (Ni), titanium (Ti), aluminum (Al), molybdenum (Mo), tungsten (W), iridium (Ir), ruthenium (Ru), platinum (Pt), etc., and metal compounds such as TiSi2 (titanium silicide), CoSi2 (cobalt silicide), etc. The embodiments of this application do not specifically limit the materials.

[0075] In the above embodiments, the thickness of the second isolation dielectric layer 100 can be between 1.0 and 2.5 μm. The material of the second isolation dielectric layer 100 can be a low dielectric constant material such as fluorinated silica (SiOF), tetraethoxysilane (TEOS), silylquinone (MSQ), borosilicate glass (BPSG), or a combination thereof. For example, in the embodiments of this application, the material of the second isolation dielectric layer 100 is a composition of BPSG and tetraethoxysilane deposited silica (TEOSD).

[0076] In the embodiments of this application, such as Figure 1 As shown, the second isolation dielectric layer 100 can completely isolate the source 90 from the second portion 80 in the shielding gate, but it is not limited to the above-described arrangement. In some alternative embodiments, such as... Figure 2 As shown, one end of the first part 40 in the second part 80, which is away from the shielding grid, penetrates the second isolation medium layer 100 and contacts the source electrode 90.

[0077] Specifically, traditional device designs connect the shielding gate to the source metal at the chip terminal. During avalanche, the rapid change in high electric field leads to significant heat dissipation and current sharing at the terminal and the active region 20, further accelerating device failure. In this embodiment, the second part 80 of the shielding gate, facing away from the first part 40, penetrates the second isolation dielectric layer 100 and contacts the source 90. This design ensures electrical insulation between the source 90 and the second part 80. Simultaneously, the direct connection of the first part 40 to the active region 20 metal not only optimizes the electric field distribution but also effectively disperses heat, enhances current sharing consistency, improves the device's avalanche resistance, and reduces reliability issues caused by localized overheating or current concentration. Compared to traditional structures, the power device of this application exhibits higher withstand voltage, lower conduction losses, and more stable performance.

[0078] According to embodiments of this application, a method for fabricating a MOSFET power device is provided, used to fabricate the MOSFET power device described in the above embodiments, such as... Figure 3 As shown, the preparation method includes:

[0079] Step S1, providing a substrate, the substrate comprising a stacked substrate and an epitaxial layer;

[0080] Step S2: The epitaxial layer has a source region and a trench extending along the first surface into the source region. The trench has a bottom and an extension segment communicating with the bottom. The first surface is the side surface of the epitaxial layer facing away from the substrate.

[0081] Step S3: A shielding gate, a first isolation dielectric layer, a gate, and an oxide layer are formed in the trench. The shielding gate includes a first portion and a second portion sequentially distributed along a direction away from the substrate. The first portion is located at the bottom, the first isolation dielectric layer is located on the side of the first portion away from the substrate, and the gate is located on both sides of the first isolation dielectric layer along a first direction. The width of the gate in the first direction is smaller than the width of the first portion. A portion of the oxide layer covers the first portion, and another portion of the oxide layer is located between the gate and the sidewall of the extension section. The second portion penetrates the first isolation dielectric layer and the oxide layer and contacts the first portion. The first direction is perpendicular to the extension direction of the trench.

[0082] In this embodiment, a source region and a trench extending along the first surface into the source region are formed inside the epitaxial layer. A first portion of a shielding gate is formed at the bottom of the trench. A first isolation dielectric layer is then formed in the trench and on the side of the first portion facing away from the substrate. Gates are then formed on both sides of the first isolation dielectric layer along a first direction. The width of the gate in the first direction is smaller than the width of the first portion, thus giving the first portion at the bottom of the trench a larger width. This not only provides stronger shielding capability and more effectively shields the electric field between the gate and drain, but also effectively reduces the electric field coupling between the gate and drain when the device is subjected to high voltage, preventing electrical breakdown and improving withstand voltage performance. Furthermore, it effectively reduces the facing area between the gate and drain, thereby significantly reducing the reverse capacitance C. rrs Meanwhile, the gate is disposed on both sides of the first isolation dielectric layer and its width is smaller than that of the first part, effectively reducing the gate volume, thereby reducing the gate charge, improving the switching speed, and reducing switching losses. Furthermore, the trench structure in the MOSFET power device of this application can be formed in one step, which simplifies the process flow and reduces the frequency of costly steps such as masking, photolithography, etching, and cleaning, thereby significantly reducing the overall manufacturing cost. This allows the MOSFET power device of this application to reduce manufacturing costs while improving withstand voltage, reducing gate-drain capacitance, and accelerating switching speed, thus solving the problem in related technologies where it is difficult to achieve a balance between optimizing withstand voltage, gate-drain capacitance, switching speed, and other performance characteristics and reducing manufacturing costs in MOSFET power devices.

[0083] Exemplary embodiments of the method for fabricating a MOSFET power device according to embodiments of this application will now be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments may be implemented in many different forms and should be construed as being limited to the embodiments set forth herein. It should be understood that these embodiments are provided so that the disclosure of this application is thorough and complete, and that the concept of these exemplary embodiments is fully conveyed to those skilled in the art.

[0084] First, proceed to step S1: as follows Figure 4 As shown, a substrate 10 is provided, which includes a stacked substrate 110 and an epitaxial layer 120.

[0085] In some optional embodiments, this application further includes the step of forming the substrate 10 described above: providing a substrate 110 and forming an epitaxial layer 120 on the substrate 110 using an epitaxial process. Specifically, the material of the epitaxial layer 120 includes silicon carbide, and the material of the substrate 110 includes, but is not limited to, semiconductor materials such as silicon, silicon carbide, and gallium nitride, etc., which are not specifically limited in this application.

[0086] In the above optional embodiments, the doping type of the substrate 110 and the epitaxial layer 120 is not specifically limited in this application embodiment. Specifically, the above-mentioned SGT MOSFET can be a silicon carbide (SiC) MOSFET, and the substrate 110 and the epitaxial layer 120 in the silicon carbide device can have the same doping type. For example, the substrate 110 is a highly doped N-type MOSFET. + Silicon carbide material, with epitaxial layer 120 being lightly doped N. - Silicon carbide material. For example, the thickness of the epitaxial layer 120 is between 9 and 14 μm, and the carrier concentration of the epitaxial layer 120 is between 1e⁻¹. 15 -1e 17 cm -3 between.

[0087] After providing the substrate 10, which includes the substrate 110 and the epitaxial layer 120, step S2 is performed: as follows Figures 5 to 11 As shown, the epitaxial layer 120 has a source region 20 and a trench 30 extending along a first surface 121 into the source region 20. The trench 30 has a bottom and an extension communicating with the bottom. The first surface 121 is the side surface of the epitaxial layer 120 facing away from the substrate 110.

[0088] In some alternative implementations, the step of forming source region 20 includes: as follows Figure 5 As shown, a portion of the first surface 121 is ion implanted to form a first inversion region 210; as Figure 6 As shown, a portion of the first surface 121 is ion implanted to form a second inversion region 220 located on at least one side of the first inversion region 210, and the first inversion region 210 and the second inversion region 220 have the same doping type; as Figure 7 As shown, ion implantation is performed on the surface of the second inversion region 220 to form an implantation region 230 located in a portion of the second inversion region 220. The main function of the inversion region is to further optimize the electric field distribution of the device through high-concentration ion implantation, reduce contact resistance, and suppress the turn-on of the bulk transistor.

[0089] For example, a first type of carrier is injected into the epitaxial layer 120 to form a first inversion region 210, the concentration of the first inversion region 210 being 1e 16 -1e 18 cm 3 Between, a high concentration of a second trans region 220 is implanted into the first trans region 210, the ion implantation concentration of the second trans region 220 being 1e 17 -1e 19 cm 3Between; the first inversion region 210 and the second inversion region 220 have the same carrier type, and the concentration of the second inversion region 220 is greater than that of the first inversion region 210; a high concentration of second-type carriers with the opposite conductivity type is injected into the first inversion region 210 to form an injection region 230, and the ion implantation concentration of the injection region 230 is 1e 19 -1e 22 cm 3 Between them, the conductivity type of the injection region 230 is the same as the carrier conductivity type of the epitaxial layer 120.

[0090] In the above example, both the first inversion region 210 and the second inversion region 220 are formed by injecting a first type of charge carrier into the epitaxial layer 120. The first type of charge carrier is an N-type charge carrier or a P-type charge carrier, so that the first inversion region 210 and the second inversion region 220 are N-type doped or P-type doped. The injection region 230 is formed by injecting a second type of charge carrier into the second inversion region 220. The second type of charge carrier is a P-type charge carrier or an N-type charge carrier, so that the injection region 230 is P-type doped or N-type doped. For example, the first inversion region 210 and the second inversion region 220 are N-type doped and the injection region 230 is P-type doped, or the first inversion region 210 and the second inversion region 220 are P-type doped and the injection region 230 is N-type doped. The injected N-type charge carriers are pentavalent elements, including any one of phosphorus (P), arsenic (As), and antimony (Sb), and the injected P-type charge carriers are trivalent elements, including any one of boron (B), aluminum (Al), and gallium (Ga). The injection of N / P type charge carriers can be done once or in multiple injections, and the energy and dose of each injection can be the same or different. This application does not make specific limitations on the embodiments.

[0091] In some alternative embodiments, after the step of forming the source region 20, the surface of the substrate 10 is cleaned and a C film is deposited on the surface of the substrate 10. Then, it is annealed at a high temperature to activate the implanted ions and repair lattice damage during the implantation process. The annealing temperature can be between 900°C and 1100°C and the time can be between 30 and 60 minutes.

[0092] In some alternative implementations, the step of forming the trench 30 includes: as follows Figure 8 As shown, a mask layer 150 and a photoresist layer 160 are sequentially formed on the surface of the source region 20; as Figure 9 As shown, the photoresist layer 160 is etched to form a first groove 171, the bottom surface of which is an arc surface; as Figure 10 As shown, the mask layer 150 is etched through the first groove 171 to form a second groove 172 connecting the photoresist layer 160 and the mask layer 150; as Figure 11As shown, the epitaxial layer 120 is etched through the second groove 172 to form a trench 30 that penetrates the source region 20. The bottom surface of the trench 30 is an arc surface that protrudes toward the substrate 110.

[0093] Specifically, after forming the source region 20, the process of fabricating the arc-shaped bottom trench 30 is carried out: First, a mask layer 150 and a photoresist layer 160 are deposited on the surface of the epitaxial layer 120, and the photoresist layer 160 is photolithographically etched. By adjusting the center focus of the light source, the arc-shaped photoresist layer 160 is fabricated. Then, the mask layer 150 is etched. By adjusting the center focus of the light source, the arc-shaped mask layer 150 is fabricated. The above two steps are the key processes for realizing the arc-shaped trench 30 type SGT MOSFET. Then, the trench 30 is etched. First, the photoresist layer 160 is removed, and then the mask layer 150 is used as a mask to etch the epitaxial layer 120, thereby transferring the arc-shaped pattern into the epitaxial layer 120 and completing the etching of the arc-shaped trench 30.

[0094] For example, the central angle of the arc-shaped bottom surface of the groove 30 is 120~180°, preferably 180°; the width of the groove 30 is 1.3~1.9μm, preferably 1.6μm; the depth of the groove 30 grid is 5~9μm, preferably 7μm; and the spacing between the left and right grooves 30 is 1.2~1.6μm, preferably 1.4μm.

[0095] In the above-mentioned optional embodiments, the arc-shaped design of the trench 30 optimizes the electric field distribution and reduces the tip effect, thereby improving the device's withstand voltage and reliability. Furthermore, by forming the trench 30 in one step and adopting an arc-bottom structure, the manufacturing process is simplified, and the process cost is reduced, especially demonstrating significant advantages in mass production, achieving a balance between high performance and low cost.

[0096] After forming the trench 30 within the epitaxial layer 120, proceed to step S3: as follows Figures 12 to 18 As shown, a shielding gate, an oxide layer 70, a gate 60 and an oxide layer 70 are formed in the trench 30. The first portion 40 of the shielding gate is located at the bottom. The first isolation dielectric layer 50 is located on the side of the first portion 40 away from the substrate 110. The gate 60 is located on both sides of the first isolation dielectric layer 50 along the first direction, and the width of the gate 60 in the first direction is smaller than the width of the first portion 40. A portion of the oxide layer 70 covers the first portion 40, and another portion of the oxide layer 70 is located between the gate 60 and the sidewall of the extension section. The second portion 80 of the shielding gate penetrates the first isolation dielectric layer 50 and the oxide layer 70 and contacts the first portion 40. The first direction is perpendicular to the extension direction of the trench 30.

[0097] In some alternative embodiments, the step of forming a shielding gate, oxide layer 70, gate 60, and first isolation dielectric layer 50 in trench 30 includes: as followsFigure 12 As shown, a field oxygen preparatory layer 711 is applied to the inner wall of trench 30; as Figure 13 As shown, a first portion 40 forming a shielding grid at the bottom, a portion of the field oxygen preparation layer 711 is located between the bottom surface of the trench 30 and the first portion 40, and the field oxygen preparation layer 711 located in the extension section is removed; as Figure 14 and Figure 15 As shown, the remaining field oxide preparatory layer 711 constitutes the field oxide layer 710, an isolation oxide layer 720 is formed on the surface of the first portion 40, and a gate oxide layer 730 is formed on the sidewall of the extension section. The isolation oxide layer 720, the gate oxide layer 730, and the isolation oxide layer 720 constitute the oxide layer 70; as shown Figure 16 and Figure 17 As shown, a gate preparation layer 610 is formed in trench 30. A portion of the gate preparation layer 610 is removed to expose a portion of the surface of the isolation oxide layer 720. The remaining gate preparation layer 610 covers the sidewalls of the even-numbered extensions, and a first isolation dielectric layer 50 is formed in the area where the gate preparation layer 610 was removed. The remaining gate preparation layer constitutes the gate 60. Figure 18 As shown, a second portion 80 is formed that penetrates the first insulating medium layer 50 and the oxide layer 70, so that the second portion 80 contacts the first portion 40 to form a shielding gate.

[0098] For example, after etching the trench 30, a field oxide layer 710 is deposited, with a thickness between 3000 Å and 6000 Å, preferably 4500 Å. After forming the field oxide layer 710, polysilicon material is deposited in the trench 30, filling the arc-shaped trench 30. Then, an etch-back process is performed, simultaneously removing excess field oxide layer 710 material. The etch-back depth can be between 4 and 5 μm, forming a bottom arc-shaped shield. Gate); then a secondary oxide layer 70 is deposited, with a thickness between 0.8 and 1.6 μm, to form an isolation oxide layer 720; after the isolation oxide layer 720 is formed, a gate oxide layer 730 is formed, preferably using a dry thermal oxidation process, with a thickness of 400 to 800 Å; after the gate oxide layer 730 is formed, polysilicon is filled into the trench 30 to form a gate preparation layer 610; then the polysilicon of the gate 60 is etched back, etching the middle region, with a width of 0.8 to 1.2 μm and a depth of 1.5 to 3 μm, and a first isolation dielectric layer 50 (such as a low-k dielectric layer) is deposited, and the first isolation dielectric layer 50 is etched to penetrate to the bottom first portion 40, and then polysilicon is deposited to form the complete second portion 80.

[0099] In the optional embodiments described above, during the fabrication of the trench 30 type SGT MOSFET power device, a preliminary field oxide layer 70 is covered on the inner wall of the trench 30, and then a first portion 40 of the shielding gate is formed at the bottom of the trench 30. Part of the preliminary field oxide layer 70 remains between the bottom surface of the trench 30 and the first portion 40, while the preliminary field oxide layer 70 located in the extension section is removed. The remaining preliminary field oxide layer 70 constitutes the final field oxide layer 70. Subsequently, an isolation oxide layer 720 is formed on the surface of the first portion 40, and a gate oxide layer 70 is formed on the sidewall of the extension section. These oxide layers 70 together constitute the complete oxide layer 70 structure. A gate preparation layer 610 is deposited in the trench 30, and subsequent partial removal exposes the surface of the isolation oxide layer 720. The remaining gate preparation layer 610 covers the sidewall of the extension section, and an isolation dielectric layer is formed in the exposed area. Finally, by forming a second part 80 of the shielding gate that penetrates the isolation dielectric layer and the oxide layer 70 in the trench 30, the second part 80 is made to directly contact the first part 40 to form a shielding gate, thereby optimizing the device structure. This not only simplifies the production process and reduces processing costs, but also significantly improves the device's withstand voltage performance and reduces the gate leakage capacitance, thus improving the overall operating efficiency and reliability of the device.

[0100] After forming the shielding gate, the first isolation dielectric layer 50, the gate 60, and the oxide layer 70 as described above, embodiments of this application may further include the following steps: Figure 19 As shown, a second insulating dielectric layer 100 and an ohmic contact metal layer 140 are formed on the epitaxial layer 120, and; as Figure 1 and Figure 2 As shown, a source 90 is formed on the second isolation dielectric layer 100 and the ohmic contact metal layer 140. The second isolation dielectric layer 100 isolates the source 90 from the gate 60, and a drain 130 is formed on the side of the substrate 110 away from the epitaxial layer 120.

[0101] Specifically, the source 90 is disposed on the side of the epitaxial layer 120 away from the substrate 110 and directly contacts the source region 20, ensuring good conductivity between the source 90 and the active region 20. A second isolation dielectric layer 100 is located between the epitaxial layer 120 and the source 90, effectively isolating the source 90 from the gate 60 and avoiding parasitic capacitance between them, thereby further optimizing the device's switching performance. A drain 130 is disposed on the side of the substrate 110 away from the epitaxial layer 120, ensuring continuity between the drain 130 and the substrate 110 and providing a stable current path for the device.

[0102] In the embodiments of this application, such as Figure 1As shown, the second isolation dielectric layer 100 can completely isolate the source electrode 90 from the second portion 80 of the shielding gate, but it is not limited to the above-described arrangement. In some optional embodiments, one end of the second portion 80 facing away from the first portion 40 penetrates the second isolation dielectric layer 100 and contacts the source electrode 90. In this case, the step of forming the second portion 80 may further include: after forming the second isolation dielectric layer 100, forming a through-hole in the second isolation dielectric layer 100, and further filling the through-hole with the material of the second portion 80, so that the formed second portion 80 has an end that penetrates the second isolation dielectric layer 100 and contacts the source electrode 90, such as... Figure 2 As shown.

[0103] It should be noted that the process steps and sequence in the above method for fabricating a MOSFET power device in the embodiments of this application are not fixed and can be adjusted according to the actual process. The formation of each layer structure requires one or more semiconductor processes such as masking, photolithography, etching, and cleaning, which will not be described in detail in the embodiments of this application.

[0104] The diode power device and its fabrication method provided in this application will be described in detail below with reference to specific embodiments.

[0105] Example 1

[0106] The method for fabricating the diode power device provided in this embodiment is as follows: Figures 1 to 19 As shown, the process includes the following:

[0107] A silicon wafer is used as the substrate 110, and an epitaxial layer 120 is grown on it. The thickness of the epitaxial layer 120 is between 9 and 1 μm, and the carrier concentration of the epitaxial layer 120 is between 1 e^(-1 / 2)e ... 15 -1e 17 cm -3 between;

[0108] Carriers are injected into the epitaxial layer 120 to form a first inversion region 210, the concentration of which is 1e 16 -1e 18 cm 3 Between these two layers, a high concentration of a second inversion region 220 is implanted into the first inversion layer, wherein the ion implantation concentration of the second inversion region 220 is 1e. 17 -1e 19 cm 3 Between the two regions, the first inversion region 210 and the second inversion region 220 have the same carrier type, and the concentration of the second inversion region 220 is greater than that of the first inversion region 210.

[0109] A high concentration of carriers with the opposite conductivity type is injected into the first inversion region 210 to form an injection region 230, wherein the ion implantation concentration of the injection region 230 is 1e. 19 -1e22 cm 3 Between them, the conductivity type of the injection region 230 is the same as the carrier conductivity type of the epitaxial layer 120;

[0110] After completing all the above processes, clean the surface of substrate 10, deposit a C film on the surface of substrate 10, and then perform annealing at a high temperature between 900℃ and 1100℃ for 30 to 60 minutes.

[0111] A mask layer 150 and a photoresist layer 160 are deposited on the surface of the epitaxial layer 120. The photoresist layer 160 is photolithographically etched. The arc-shaped photoresist layer 160 is fabricated by adjusting the center focus of the light source. The mask layer 150 is etched. The arc-shaped mask layer 150 is fabricated by adjusting the center focus of the light source.

[0112] First, the photoresist layer 160 is removed. Then, the epitaxial layer 120 is etched using the mask layer 150 as a mask, thereby transferring the arc-shaped pattern into the epitaxial layer 120 to form a trench 30 with an arc-shaped bottom surface. The central angle of the bottom arc-shaped cross-section is 120-180°, the width of the trench 30 is 1.3~1.9μm, the depth of the trench 30 gate is 5~9μm, and the spacing between the left and right trenches 30 is 1.2~1.6μm.

[0113] After completing the etching of trench 30, a field oxide layer 710 is deposited with a thickness between 3000 Å and 6000 Å.

[0114] After forming the field oxide layer 710, polysilicon is deposited in the trench 30. The polysilicon fills the arc-shaped trench 30, and then the etching is performed to remove excess field oxide layer 710 material. The etching depth is between 4 and 5 μm, forming the first part 40 of the shielding gate with an arc bottom.

[0115] Subsequently, a secondary oxide layer 70 is deposited with a thickness between 0.8 and 1.6 μm to form an isolation oxide layer 720;

[0116] After the isolation oxide layer 720 is formed, the gate oxide layer 730 is formed using a dry thermal oxidation process, and the thickness of the gate oxide layer 730 is 400~800 Å.

[0117] After the gate oxide layer 730 is formed, the gate 60 is formed by filling the trench 30 with polysilicon to form the gate preparation layer 610.

[0118] Subsequently, polysilicon etch-back is performed to etch the intermediate region, with a width of 0.8~1.2μm and a depth of 1.5~3μm, and a first isolation dielectric layer 50 is deposited using a low-k dielectric material;

[0119] The low-K dielectric material is etched to the bottom of the trench 30 in the first part 40, and then polysilicon is deposited to form the second part 80 of the shielding gate.

[0120] After the shielding barrier is formed, a second isolation dielectric layer 100 is deposited. The thickness of the second isolation dielectric layer 100 is between 1.0 and 2.5 μm, and the material includes a combination of BPSG and TEOSD.

[0121] After the second isolation dielectric layer 100 is formed, the ohmic contact metal layer 140 is deposited and etched.

[0122] After the ohmic contact metal layer 140 is formed, the upper metal layer is deposited to form the source electrode. The thickness of the metal layer is between 4 and 8 μm. After the source electrode is formed, the chip is flipped to deposit the back metal to form the drain electrode 130. The thickness of the metal layer is between 1 and 3 μm.

[0123] Example 2

[0124] The difference between the method for fabricating the diode power device provided in this embodiment and that in Embodiment 1 is:

[0125] After the second isolation dielectric layer 100 is deposited, a via is formed in the second isolation dielectric layer 100, and the via is further filled with the material of the second portion 80 of the shielding gate, so that the formed second portion 80 has an end that penetrates the second isolation dielectric layer 100. After the source electrode 90 is formed, this end contacts the source electrode 90, such as... Figure 2 As shown.

[0126] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0127] The above are merely embodiments of this application and are not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A MOSFET power device, characterized in that, include: The substrate includes a stacked substrate and an epitaxial layer, the epitaxial layer having a source region and a trench extending along a first surface into the source region, the trench having a bottom and an extension communicating with the bottom, the first surface being the side surface of the epitaxial layer facing away from the substrate. A shielding gate and a first isolation dielectric layer are located in the trench. The shielding gate includes a first portion and a second portion sequentially distributed in a direction away from the substrate. The first portion is located at the bottom of the trench, and the first isolation dielectric layer is located in the trench and on the side of the first portion away from the substrate. A gate is located on both sides of the first isolation dielectric layer along a first direction, and the width of the gate in the first direction is smaller than the width of the first portion, the first direction being perpendicular to the extension direction of the trench; An oxide layer is located in the trench, and a portion of the oxide layer covers the first portion, the second portion penetrates the first isolation dielectric layer and contacts the first portion, and another portion of the oxide layer is located between the gate and the sidewall of the extension.

2. The MOSFET power device according to claim 1, characterized in that, The oxide layer includes a field oxide layer, an isolation oxide layer, and a gate oxide layer. The isolation oxide layer is located on the side of the field oxide layer away from the substrate. The field oxide layer and the isolation oxide layer together enclose the first portion and form a shielding gate structure with the second portion. The gate oxide layer is located on the outside of the gate along the first direction. The orthographic projection of the gate onto the shielding gate structure is a first orthographic projection, and at least a portion of the first orthographic projection falls into the surface of the shielding gate structure.

3. The MOSFET power device according to claim 1, characterized in that, The first portion has a second surface close to the bottom of the trench, and the oxide layer has a third surface in contact with the bottom of the trench. The second surface and the third surface are arc surfaces protruding toward the substrate.

4. The MOSFET power device according to claim 1, characterized in that, The material of the first isolation dielectric layer is a low dielectric constant material.

5. The MOSFET power device according to any one of claims 1 to 4, characterized in that, The source region includes: The first inversion region is located in the epitaxial layer, and the first inversion region is a region formed by ion implantation of a portion of the first surface; The second inversion region is located in the epitaxial layer and at least one side of the first inversion region. The first inversion region is a region formed by ion implantation of a portion of the first surface, and the first inversion region and the second inversion region have the same doping type. An implantation region is located within a portion of the second inversion region, and the implantation region is a region formed by ion implantation onto the surface of the second inversion region.

6. The MOSFET power device according to any one of claims 1 to 4, characterized in that, Also includes: The source electrode is located on the side of the epitaxial layer opposite to the substrate and is in contact with the source region; A second isolation dielectric layer and an ohmic contact metal layer are located between the epitaxial layer and the source electrode. The second isolation dielectric layer isolates the source electrode from the gate electrode, and the ohmic contact metal layer contacts the source electrode and the source region, respectively. The drain is located on the side of the substrate away from the epitaxial layer.

7. The MOSFET power device according to claim 6, characterized in that, The second isolation dielectric layer isolates the source electrode from the second portion; or The end of the second part that is opposite to the first part penetrates the second isolation dielectric layer and contacts the source electrode.

8. A method for fabricating a MOSFET power device, characterized in that, The method for fabricating the MOSFET power device according to any one of claims 1 to 7 comprises the following steps: A substrate is provided, the substrate comprising a stacked substrate and an epitaxial layer; A source region and a trench extending along a first surface into the source region are formed in the epitaxial layer. The trench has a bottom and an extension communicating with the bottom. The first surface is the side surface of the epitaxial layer facing away from the substrate. A shielding gate, a first isolation dielectric layer, a gate, and an oxide layer are formed in the trench. The shielding gate includes a first portion and a second portion sequentially distributed along a direction away from the substrate. The first portion is located at the bottom. The first isolation dielectric layer is located on the side of the first portion away from the substrate. The gate is located on both sides of the first isolation dielectric layer along a first direction, and the width of the gate in the first direction is smaller than the width of the first portion. A portion of the oxide layer covers the first portion, and another portion of the oxide layer is located between the gate and the sidewall of the extension. The second portion penetrates the first isolation dielectric layer and the oxide layer and contacts the first portion. The first direction is perpendicular to the extension direction of the trench.

9. The preparation method according to claim 8, characterized in that, The step of forming the shielding gate, the oxide layer, the gate electrode, and the first isolation dielectric layer in the trench includes: An oxygen pre-coating layer is applied to the inner wall of the trench; The first portion is formed at the bottom, a portion of the field oxygen preparation layer is located between the bottom surface of the trench and the first portion, and the field oxygen preparation layer located in the extension is removed, the remaining field oxygen preparation layer constitutes the field oxygen layer; An isolation oxide layer is formed on the surface of the first portion, and a gate oxide layer is formed on the sidewall of the extension, wherein the isolation oxide layer, the gate oxide layer, and the isolation oxide layer constitute the oxide layer; A gate preparation layer is formed in the trench, a portion of the gate preparation layer is removed to expose a portion of the surface of the isolation oxide layer, the remaining gate preparation layer covers the sidewalls of the even-numbered extensions, and the first isolation dielectric layer is formed in the area where the gate preparation layer is removed. A second portion is formed in the trench, penetrating the first insulating medium layer and the oxide layer, so that the second portion contacts the first portion.

10. The preparation method according to claim 8, characterized in that, The steps for forming the source region include: Ion implantation is performed on a portion of the first surface to form a first inversion region; Ion implantation is performed on a portion of the first surface to form a second inversion region located on at least one side of the first inversion region, wherein the first inversion region and the second inversion region have the same doping type; Ion implantation is performed on the surface of the second inversion region to form an implantation region located in a portion of the second inversion region; The steps for forming the trench include: A mask layer and a photoresist layer are sequentially formed on the surface of the source region; The photoresist layer is etched to form a first groove, the bottom surface of which is an arc surface; The mask layer is etched through the first groove to form a second groove connecting the photoresist layer and the mask layer; The epitaxial layer is etched by the second groove to form the trench penetrating the source region, the bottom surface of the trench being an arc surface protruding toward the substrate.

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