Super junction device

Abstract

The invention discloses a super junction device, which is characterized in that a super junction structure is at least formed in an active region, device unit structures are formed in the active region, each device unit structure comprises a gate unit structure, and each gate unit structure forms a two-dimensional mesh gate structure. The two-dimensional mesh gate structure comprises a plurality of first gate strips which extend in a first direction and are arranged in parallel, and a first gate spacer region is arranged between every two adjacent first gate strips. A plurality of second gate segments and grid regions located between the second gate segments are formed in each first gate spacer region, and a forming region of each device unit structure comprises a corresponding grid region; and each second grid section is also connected with the first grid strips on the two sides, and grid connection nodes are formed at the connection positions. According to the invention, the gate parasitic capacitance such as the gate source capacitance and the gate drain capacitance can be improved, and the synchronization level of each device unit structure, namely the primitive cell, can be improved at the same time, so that the voltage and current overshoot can be inhibited, and the EMI can be reduced.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit device, and more particularly to a super junction device. Background Technology

[0002] The core innovation of superjunction MOSFETs lies in replacing the single-doped drift region of traditional VDMOS with alternating P-type and N-type semiconductor pillars. When the device is in the off state (cut-off), adjacent P-type and N-type pillars deplete each other, forming a lateral electric field that almost completely depletes the drift region, thus maintaining a high breakdown voltage. When the device is on, the N-type pillars provide a low-resistance current path. Since the doping concentration of the N-type pillars can be much higher than that of the drift region in traditional VDMOS, the on-resistance is significantly reduced. This charge-balancing mechanism achieves a fundamental breakthrough in the relationship between on-resistance and breakdown voltage, reducing the relationship between Rsp and BV from the 2.5th power to approximately the 1.3th power. While the chip area of ​​the superjunction MOSFET is significantly reduced, its capacitance is also drastically reduced.

[0003] like FIG. 1A The diagram shown is a layout of the gate structure of an existing superjunction device. FIG. 1B This is a schematic diagram of the cross-sectional structure of an existing superjunction device along line AA'; FIG. 1A The upper right corner also displays a magnified view of a local area of ​​the gate structure layout diagram, with line AA' in... FIG. 1A It is marked in the enlarged image in the upper right corner. Taking an N-type superjunction MOSFET as an example, in existing superjunction devices, a superjunction structure is formed in at least the active region 101, and the superjunction structure is formed in the first N-type doped epitaxial layer 1-2.

[0004] The device unit structure of the superjunction device is formed in the active region 101.

[0005] The device cell structure includes a trench gate, which comprises a gate dielectric layer 6, such as a gate oxide layer, and a polysilicon gate 7 formed in the gate trench. FIG. 1A As shown, the polysilicon gate 7 has a strip-shaped structure.

[0006] A terminal region 103 surrounds the active region 101, and a transition region 102 is also included between the terminal region 103 and the active region 101. FIG. 1A In this context, transition region 102 is also represented by region 1, and terminal region 103 is also represented by region 2. Superjunction structures are also formed in transition region 102 and terminal region 103.

[0007] like FIG. 1B As shown, the superjunction structure includes alternating N-type pillars and P-type pillars 4; the N-type pillars are composed of a first epitaxial layer 1-2 located between the P-type pillars 4.

[0008] The extension direction of the N-type pillars and the P-type pillars 4 is the same as the extension direction of the strip structure of each polysilicon gate 7.

[0009] Each polysilicon gate 7 is located on the top of the corresponding N-type pillar.

[0010] Each device cell structure includes a P-type doped channel region 8 formed in the surface region of the super junction structure on both sides of the polysilicon gate 7.

[0011] An N-type heavily doped source region 9 is formed on the surface of the channel region 8, and the side surface of the source region 9 is aligned with the polysilicon gate 7.

[0012] The source region 9 is connected to a source electrode composed of a front metal layer 13 through a first contact hole 11 passing through the interlayer film on the top of the source region 9.

[0013] Each first contact hole 11 is also connected to the channel region 8. Please refer to FIG. 14 It can be seen that the first contact hole 11 also has a strip structure.

[0014] As shown in FIG. 1A A gate bus 15 is wrapped around the side of the gate structure. The gate bus 15 can be composed of polysilicon. FIG. 1A It can be seen that the gate bus 15 is located in the transition region 102.

[0015] Both ends of the polysilicon gate 7 are connected to the gate bus 15, and the gate bus 15 is connected to a gate pad 16 composed of a front metal layer 13.

[0016] An N-type heavily doped drain region 1-1 is formed on the back of the first epitaxial layer 1-2. Generally, the drain region 1-1 is composed of a thinned semiconductor substrate.

[0017] A drain electrode composed of a back metal layer 14 is formed on the back of the drain region 1-1.

[0018] The super junction MOSFET has extremely low switching loss and extremely fast switching speed, but it also brings high voltage change rate (dv / dt), which in turn causes electromagnetic interference (EMI) problems. Because the switching speed of the super junction MOSFET is extremely fast, during the switching process, especially during the off state, the sharp change of the drain-source voltage VDS will be coupled to the gate through the gate-drain capacitance Cgd, also known as the Miller capacitance, causing the ringing of the gate voltage, and even leading to the false opening of the device, i.e. the Miller conduction. This ringing and false opening not only increases the switching loss, but also generates strong electromagnetic noise, which seriously interferes with other sensitive circuits in the same system.

[0019] The conventional solution includes adding a resistor in the external gate drive circuit to slow down the switching speed, but this will sacrifice the inherent low switching loss advantage of the super-junction MOSFET. Another existing method is to integrate a small gate resistor inside the device package, but this will also increase the loss and lack flexibility. SUMMARY

[0020] The technical problem to be solved by the present application is to provide a super-junction device that can improve the gate parasitic capacitance such as gate-source capacitance and gate-drain capacitance, and at the same time improve the synchronization level of each device cell structure, i.e. the primitive cell, so as to suppress voltage and current overshoot and reduce EMI.

[0021] To solve the above technical problem, the super-junction device provided by the present application is characterized in that at least a super-junction structure is formed in the active region, and the super-junction structure is formed in a first epitaxial layer doped with a first conductivity type.

[0022] The device cell structure of the super-junction device is formed in the active region, and each device cell structure includes a gate cell structure, and the gate cell structures of each device cell structure together form a two-dimensional mesh gate structure.

[0023] The two-dimensional mesh gate structure includes a plurality of first gate strips extending in a first direction, and each first gate strip is arranged in parallel and has a first gate interval between adjacent first gate strips.

[0024] A plurality of second gate segments and a mesh region between each second gate segment are formed in each first gate interval, and the formation region of each device cell structure includes a corresponding mesh region; each second gate segment is connected to the first gate strips on both sides and forms a gate connection node at the connection position.

[0025] Each second gate segment is used to increase the gate parasitic capacitance of the super-junction device, and each gate connection node is used to synchronize the switching of the device cell structures on the periphery and achieve the switching synchronization of each device cell structure in the entire super-junction device.

[0026] Further improvement is that the lengths of each mesh region in the same first gate interval in the first direction are equal.

[0027] Further improvement is that the lengths of all mesh regions are equal.

[0028] Further improvement is that in a second direction perpendicular to the first direction, each second gate segment is aligned and forms a second gate strip.

[0029] Alternatively, in a second direction perpendicular to the first direction, the second gate segments in adjacent first gate spacers are staggered; the second gate segments in two first gate spacers spaced by one first gate spacer are aligned.

[0030] Further improvement is, further comprising: a gate bus encircling the periphery of the two-dimensional mesh gate structure.

[0031] Two ends of the first gate strip are connected to the gate bus respectively, and the gate bus is connected to a gate pad composed of a front metal layer.

[0032] Further improvement is, the super-junction structure comprises first-conductivity-type columns and second-conductivity-type columns arranged alternately; the first-conductivity-type columns are composed of the first epitaxial layer located between the second-conductivity-type columns.

[0033] The first-conductivity-type columns and the second-conductivity-type columns both extend along the first direction.

[0034] Further improvement is, the second-conductivity-type columns comprise a second-conductivity-type doped second epitaxial layer filled in super-junction trenches.

[0035] Further improvement is, the first gate strip is located on top of the corresponding first-conductivity-type column.

[0036] Further improvement is, each of the device cell structures comprises a second-conductivity-type doped channel region formed in a surface region of the super-junction structure of the mesh region.

[0037] A first-conductivity-type heavily doped source region is formed on the surface of the channel region, and the source region is aligned with the side surface of the first gate strip.

[0038] A source electrode composed of the front metal layer is connected to the source region through a first contact hole passing through an interlayer film on top of the source region.

[0039] Each of the first contact holes is also connected to the channel region.

[0040] Each of the first contact holes is located in the corresponding mesh region, and the first contact holes in each adjacent mesh region have a spacing.

[0041] Further improvement is, the two-dimensional mesh gate structure is a trench gate.

[0042] Each of the trench gates longitudinally passes through the channel region, and the surface of the channel region covered by the side surface of the first gate strip in the trench gate is used to form a conductive channel.

[0043] Further improvement is that the two-dimensional net-shaped gate structure is a planar gate, and the channel region also extends to the bottom of the planar gate, and the surface of the channel region covered by the first gate strip in the planar gate is used for forming a conductive channel.

[0044] Further improvement is that a first conductive type heavily doped drain region is formed on the back surface of the first epitaxial layer.

[0045] A drain electrode composed of a back surface metal layer is formed on the back surface of the drain region.

[0046] Further improvement is that a terminal region is surrounded on the peripheral side of the active region, and a transition region is also included between the terminal region and the active region.

[0047] The super junction structure is also formed in the transition region and the terminal region.

[0048] Further improvement is that it also includes a dielectric film protective layer, which covers the front surface of the super junction device formed with the front metal layer and opens the gate lead-out region and the source lead-out region.

[0049] Or, it also includes a passivation layer and a polyimide protective layer, which cover the front surface of the super junction device formed with the front metal layer and open the gate lead-out region and the source lead-out region.

[0050] Further improvement is that the super junction device is an N-type device, the first conductive type is N-type, and the second conductive type is P-type; or, the super junction device is a P-type device, the first conductive type is P-type, and the second conductive type is N-type.

[0051] The application makes special settings to the whole gate structure of the super junction device. On the basis of the first gate strip arranged in parallel, a second gate segment connecting two adjacent first gate strips is added in the first gate interval between the first gate strips, so that the gate structure is a two-dimensional mesh gate structure. The added second gate segment can first increase the area of the gate structure, so as to increase the gate parasitic capacitance, including the gate-source capacitance and the gate-drain capacitance. The increase of the gate parasitic capacitance can produce a buffering effect on the switching process of the device. The second gate segment can also be connected with the first gate strip and form a gate connection node. The gate connection node can make the device unit structures on the side of the gate connection node switch synchronously. Since the two-dimensional mesh gate structure includes multiple gate connection nodes, the switching of the device unit structures in the whole super junction device can be synchronized. The switching of the device unit structures can smooth the overall switching waveform. Therefore, the application can improve the gate parasitic capacitance and the synchronization level of the device unit structures at the same time. Under the synergistic effect of the double optimization mechanisms, the application can fundamentally realize a cleaner and smoother turn-on and turn-off process, and can significantly reduce the switching loss and the EMI noise emission level. Therefore, the application can effectively suppress voltage overshoot and current ringing by reducing the mutation rate of voltage and current from the source of the device, so as to reduce electromagnetic interference (EMI).

[0052] In addition, the application does not need an external series gate resistor. Unlike the method of connecting an external series gate resistor, since the application smoothes the switching waveform through the capacitive effect, rather than simply limiting the movement of carriers, the application can effectively suppress EMI while relatively small increase in switching loss, and better maintain the advantages of high efficiency of the super junction MOSFET.

[0053] In addition, the application only needs to improve the pattern of the gate structure to achieve the two-dimensional mesh gate structure, which can be realized by completely compatible steps with the existing standard planar gate process and trench gate process, without the need for additional photolithography or process steps, and has good process feasibility and low cost advantage. BRIEF DESCRIPTION OF DRAWINGS

[0054] The application will be further described in detail below in combination with the drawings and specific embodiments: FIG. 1A is a gate structure layout of the existing super junction device; FIG. 1B is a cross-sectional structure schematic diagram of the existing super junction device along the line AA'; FIG. 2A is a gate structure layout of the super junction device of the first embodiment of the application; FIG. 2B is a cross-sectional structure schematic diagram of the super junction device of the first embodiment of the application along the line AA'; FIG. 2C This is a schematic cross-sectional view of the superjunction device along line BB' in the first embodiment of the present invention; FIG. 3A These are turn-off waveform curves of the superjunction device according to the first embodiment of the present invention and a conventional superjunction device; FIG. 3B These are turn-on waveform curves of the superjunction device according to the first embodiment of the present invention and a conventional superjunction device; FIG. 4A This is a layout diagram of the gate structure of the superjunction device according to the second embodiment of the present invention; FIG. 4B This is a schematic cross-sectional view of the superjunction device along line CC' according to the second embodiment of the present invention; FIG. 5 - FIG. 11B This is a schematic diagram of the device structure in each step of the method for manufacturing the superjunction device according to the first embodiment of the present invention; FIG. 12 - FIG. 14 This is a schematic diagram of the three-dimensional structure of the device in the corresponding steps of manufacturing existing superjunction devices. Detailed Implementation

[0055] like FIG. 2A The diagram shown is a layout of the gate structure of the superjunction device according to the first embodiment of the present invention; as shown... FIG. 2B The diagram shown is a cross-sectional view of the superjunction device along line AA' according to the first embodiment of the present invention; as shown... FIG. 2C The diagram shown is a cross-sectional view of the superjunction device along line BB' in the first embodiment of the present invention. FIG. 2A The upper right corner also shows a magnified view of a local area of ​​the gate structure layout, with lines AA' and BB' in... FIG. 2A The image is shown in the upper right corner of the enlarged view. In the superjunction device of the first embodiment of the present invention, a superjunction structure is formed at least in the active region 101, and the superjunction structure is formed in the first epitaxial layer 1-2 doped with a first conductivity type.

[0056] The device unit structure of the superjunction device is formed in the active region 101. Each device unit structure includes a gate unit structure, and the gate unit structures of each device unit structure together form a two-dimensional mesh gate structure.

[0057] In the first embodiment of the present invention, a terminal region 103 is surrounded around the active region 101, and a transition region 102 is also included between the terminal region 103 and the active region 101. FIG. 2A In this context, transition region 102 is also represented by region 1, and terminal region 103 is also represented by region 2. Superjunction structures are also formed in transition region 102 and terminal region 103.

[0058] The two-dimensional mesh gate structure includes a plurality of first gate strips 7a extending in a first direction, each first gate strip 7a being arranged in parallel and having a first gate spacing region between each adjacent first gate strip 7a.

[0059] Multiple second gate segments 7b and a grid region located between each second gate segment 7b are formed in each first gate spacing region. The forming area of ​​each device unit structure includes a corresponding grid region. Each second gate segment 7b is also connected to the first gate strips 7a on both sides and forms a gate connection node 17a at the connection position.

[0060] Each second gate segment 7b is used to increase the gate parasitic capacitance of the superjunction device, and each gate connection node 17a is used to synchronize the switching of the peripheral device cell structure and realize the switching synchronization of all device cell structures within the entire superjunction device. The gate connection node 17a has the fastest potential response speed, driving the surrounding cells to respond faster.

[0061] In the first embodiment of the present invention, the lengths of each grid region in the same first grid spacing region along the first direction are equal. Furthermore, the lengths of all grid regions are equal.

[0062] In a second direction perpendicular to the first direction, each of the second gate segments 7b is aligned and forms a second gate strip.

[0063] like FIG. 2B As shown, the superjunction structure includes alternating first conductivity type pillars and second conductivity type pillars 4; the first conductivity type pillars are composed of first epitaxial layers 1-2 located between the second conductivity type pillars 4.

[0064] Both the first conductive type column and the second conductive type column 4 extend along the first direction.

[0065] In the first embodiment of the present invention, the second conductivity type pillar 4 includes a second epitaxial layer doped with the second conductivity type and filled in the superjunction trench. In other embodiments, the second conductivity type pillar 4 may also be formed by stacking multiple ion implantation regions of the second conductivity type, and the first epitaxial layer 1-2 may be formed by stacking epitaxial sublayers formed by multiple epitaxial processes.

[0066] In the first embodiment of the present invention, the first gate bar 7a is located at the top of the corresponding first conductivity type pillar.

[0067] Each device unit structure includes a channel region 8 doped with a second conductivity type in the surface region of the superjunction structure formed in the grid region.

[0068] A source region 9 of a first conductivity type is formed on the surface of the channel region 8, and the source region 9 is aligned with the side of the first gate strip 7a.

[0069] The source region 9 is connected to the source electrode, which is composed of the front metal layer 13, through the first contact hole 11 that passes through the interlayer membrane at the top of the source region 9.

[0070] Each first contact hole 11 is also connected to the channel area 8.

[0071] Each first contact hole 11 is located in a corresponding grid region, and the first contact holes 11 in each adjacent grid region have a spacing. The structure with a spacing between the first contact holes 11 is shown in FIG. 11B .

[0072] In the first embodiment of the present application, the two-dimensional mesh gate structure is a trench gate. Each trench gate longitudinally passes through the channel region 8, and the surface of the channel region 8 covered by the first gate strip 7a in the trench gate is used to form a conductive channel.

[0073] In the first embodiment of the present application, the trench gate includes a gate dielectric layer 6 such as a gate oxide layer and a polysilicon gate formed in the gate trench. Both the first gate strip 7a and the second gate segment 7b are polysilicon gates.

[0074] In other embodiments, the two-dimensional mesh gate structure can also be a planar gate, and the channel region 8 also extends to the bottom of the planar gate, and the surface of the channel region 8 covered by the first gate strip 7a in the planar gate is used to form a conductive channel.

[0075] As shown in FIG. 2A , it further includes a gate bus 15 surrounding the periphery of the two-dimensional mesh gate structure. The gate bus 15 can be composed of polysilicon, and the gate bus 15 is connected to the gate pad 16 composed of the front metal layer 13. FIG. 2A As can be seen, the gate bus 15 is located in the transition region 102.

[0076] The two ends of the first gate strip 7a are respectively connected to the gate bus 15, and the gate bus 15 is connected to the gate pad 16 composed of the front metal layer 13.

[0077] In the first embodiment of the present application, the super-junction device is a super-junction MOSFET, and a drain region 1-1 of a first conductivity type is formed on the back surface of the first epitaxial layer 1-2. Generally, the drain region 1-1 is composed of a thinned semiconductor substrate, and the first epitaxial layer 1-2 is formed on the top surface of the semiconductor substrate. The drain region 1-1 can also be formed by further back surface implantation of a first conductivity type heavy doping in the thinned semiconductor substrate.

[0078] A drain electrode composed of a back metal layer 14 is formed on the back surface of the drain region 1-1.

[0079] In some embodiments, it further includes a dielectric film protective layer covering the front surface of the super-junction device on which the front metal layer 13 is formed, and opening the gate lead-out region and the source lead-out region.

[0080] In some embodiments, it can also include a passivation layer and a polyimide protective layer covering the front surface of the super-junction device on which the front metal layer 13 is formed, and opening the gate lead-out region and the source lead-out region.

[0081] In the first embodiment of the present application, the super-junction device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type. In other embodiments, the super-junction device can be a P-type device, the first conductivity type can be P-type, and the second conductivity type can be N-type.

[0082] In the first embodiment of the present application, the gate structure of the entire super-junction device is specially configured. On the basis of the first gate strips 7a arranged in parallel, which are commonly used in the prior art, a second gate segment 7b connecting two adjacent first gate strips 7a is added in the first gate interval between the first gate strips 7a. The gate structure is a two-dimensional mesh gate structure. The second gate segment 7b can first increase the area of the gate structure, thereby increasing the gate parasitic capacitance, including the gate-source capacitance and the gate-drain capacitance. The increase in the gate parasitic capacitance can buffer the switching process of the device. The second gate segment 7b can also be connected with the first gate strips 7a to form a gate connection node. The gate connection node can synchronize the switching of the device unit structures on the side of the gate connection node. Since the two-dimensional mesh gate structure includes multiple gate connection nodes, the switching of the device unit structures in the entire super-junction device can be synchronized. The synchronization of the switching of the device unit structures can smooth the overall switching waveform. Therefore, the first embodiment of the present application can improve the gate parasitic capacitance and the synchronization level of the device unit structures. Under the synergistic effect of the double optimization mechanisms, the opening and closing processes can be fundamentally cleaner and smoother, the switching loss and the EMI noise emission level can be significantly reduced. Therefore, the first embodiment of the present application can effectively suppress voltage overshoot and current ringing by reducing the mutation rate of voltage and current from the source of the device, thereby reducing electromagnetic interference (EMI).

[0083] In addition, the first embodiment of the present application does not need an external gate resistor in series. Unlike the method of using an external gate resistor in series, the first embodiment of the present application can effectively suppress EMI while relatively small increasing the switching loss, thereby better maintaining the high efficiency advantage of the super-junction MOSFET, since the first embodiment of the present application smoothes the switching waveform through the capacitive effect, rather than simply limiting the movement of carriers.

[0084] In addition, the first embodiment of the present application can be implemented only by improving the pattern of the gate structure. The two-dimensional mesh gate structure of the first embodiment of the present application can be implemented using steps completely compatible with the existing standard planar gate process and trench gate process, without the need for additional photolithography or process steps, thereby having good process feasibility and low cost advantage.

[0085] As FIG. 3AAs shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly.

[0086] As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly. FIG. 3B As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly.

[0087] FIG. 3A As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly. FIG. 3B As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly.

[0088] The super junction device of the second embodiment of the present application is as shown in the figure: As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly. FIG. 4A As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly. FIG. 4B As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly. FIG. 4A As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly. FIG. 2B As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly. As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly. FIG. 4A As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly. FIG. 2C As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly. FIG. 4B As shown in the figure, it is the off waveform curve diagram of the super junction device of the first embodiment of the present application and the prior art super junction device; wherein curve 201 is the off waveform curve of the prior art super junction device, and curve 202 is the off waveform curve of the super junction device of the first embodiment of the present application, both are simulation waveform curves, and it can be seen that the waveform of curve 201 is steep and ringing is serious, and the waveform of curve 202 changes more rapidly and smoothly.

[0089] FIG. 4A ​In the middle, there are 3 grid areas around the connection node 17b, which is more than FIG. 2A The number of the four grid regions surrounding the central connecting node 17a is even smaller, therefore FIG. 4A The structure shown provides better synchronization of the switching of each device unit. FIG. 4A In this case, it has a more uniform potential distribution and more connection nodes 17b.

[0090] To address the high dv / dt and EMI issues caused by excessively fast switching speeds in existing superjunction MOSFETs, embodiments of the present invention, such as superjunction MOSFET structures, fundamentally increase their parasitic capacitance by redesigning the layout of the gate in the active region, thus gently mitigating switching edges, suppressing voltage and current overshoot, and reducing EMI.

[0091] In this embodiment of the invention, the core improvement in the layout of the gate of the active region lies in that the planar layout of the gate structure is a mesh structure covering the entire active region, i.e., a two-dimensional mesh gate structure. The mesh structure extends and connects to each other in at least two directions, such as the mutually perpendicular X and Y directions. The mesh gate can connect multiple units (cells) in the active region of the device that were originally separated by strip gates into a whole network at the gate level.

[0092] Because a low-resistance, high-speed-response gate potential distribution network is formed in the active region, compared with the existing conventional strip gate, in this embodiment of the invention, the potential response speed is fastest at the gate junction, i.e., the gate connection node. This allows the cells adjacent to the junction to be turned on preferentially and turned off later, and promotes the synchronization of the cell switching behavior throughout the active region, thereby smoothing the overall switching waveform.

[0093] The gate is isolated from the semiconductor layer (i.e., the channel region and the first epitaxial layer) by the gate oxide layer. The significant increase in gate area directly leads to a synchronous increase in the gate-source capacitance Cgs and the gate-drain capacitance Cgd. This produces a natural buffering effect during switching, gently mitigating the edges of the switching waveform. This effectively suppresses voltage overshoot and ringing, and reduces dv / dt and EMI.

[0094] The superjunction device of the present invention will be further described below with reference to the manufacturing method: like FIG. 5 to FIG. 11B The diagram shown is a schematic representation of the device structure in each step of the method for manufacturing the superjunction device according to the first embodiment of the present invention. Taking an N-type superjunction MOSFET as an example, the method for manufacturing the superjunction device according to the first embodiment of the present invention includes: Step 1, such as FIG. 5As shown, on the semiconductor substrate corresponding to the N-type substrate with low resistivity, such as less than 0.003 ohm.cm, i.e. the drain region 1-1, a layer of N-type epitaxial layer 1-2 with high resistivity, such as 0.5-5 ohm.cm, i.e. the first epitaxial layer 1-2, is grown, and the thickness of the first epitaxial layer 1-2 is 45-50 µm. The design of the epitaxial resistivity and the subsequent P-type column 4, i.e. the second conductive type column 4, and the N-type column are associated with the step-by-step simulation, which can be designed by computer-aided software.

[0095] Step two, as shown in FIG. 5 , a dielectric film is deposited on the surface of the epitaxial layer 1-2 as a hard mask 2 for deep trench etching, i.e. super-junction trench etching. The hard mask 2 can be a three-layer superposition structure formed by 500-1000 Å of SiO2, 300-1500 Å of SiN and 2-5 microns of SiO2. Then, through photoetching, glue coating and developing, a photoresist pattern 3 is formed.

[0096] Step three, as shown in FIG. 6 , then the hard mask 2 and the epitaxial layer 1-2 are etched in sequence by dry etching to form a deep trench with an upper opening in the epitaxial layer 1-2, and the width and depth of the trench are set according to the requirements of the device BVDSS. Then, the top SiO2 and SiN of the hard mask 2 are completely removed, and the bottom SiO2 is kept as a protective layer for the Si surface. Then, the upper opening deep trench is completely filled by P-type epitaxial deposition, and then the surface Si is completely removed by chemical mechanical polishing. The alternating P-type column 4 and N-type column are formed.

[0097] Step four, as shown in FIG. 7A , a dielectric film 5 is deposited on the surface of the epitaxial layer 1-2 with super-junction structure as a dielectric film for trench gate etching. The dielectric film 5 is generally a SiO2 film.

[0098] Then, as shown in FIG. 7B , on the basis of the existing method, by redesigning the layout of the active area gate, after photoetching, glue coating and developing, a photoresist 5 defined mesh gate pattern is formed.

[0099] As shown in FIG. 12 , as a comparison, in the existing method, after photoetching, glue coating and developing, the photoresist 5 will form FIG. 12 a strip-shaped gate pattern.

[0100] As shown in FIG. 8A , then dry etching is performed to form a shallow trench, i.e. a gate trench, and the width of the gate trench is set to 0.6-1.5 µm, and the depth is set to 2-4 µm.

[0101] Then, a gate oxide film, i.e. a gate dielectric layer 6, is deposited, and the gate dielectric layer 6 is generally SiO2 with a thickness of 500 Å-2000 Å.

[0102] Then, polysilicon is deposited and etched to form a polysilicon gate. FIG. 8A The first gate bar 7a is shown in the image. FIG. 8B The corresponding 3D diagram also shows a second gate segment 7b.

[0103] like FIG. 13 As shown, in contrast, in existing methods, the polysilicon gate 7 is a strip structure. Therefore, the embodiments of the present invention form a mesh gate structure.

[0104] Step 5, as follows FIG. 9 As shown, a P-type well 8, i.e., the channel region 8, is formed through photolithography and ion implantation. Here, ion implantation of the P-type well 8 typically involves boron (B), with implantation energy generally between 30 keV and 130 keV. The implantation dose is designed according to the device threshold voltage requirements. This ion implantation can also be achieved using two or more B implantations at different energies, thus constructing different P-type wells and adjusting device performance parameters, including threshold voltage and EAS. After the P-type well ion implantation is formed, a high-temperature annealing process can be performed, such as annealing at 1100℃ for 30 minutes or at higher temperatures and for longer durations. This pushes the P-type well to the desired position and repairs any damage caused during ion implantation. Alternatively, high-temperature TRA (transient ion transfer) can be used to activate the implanted B ions, while simultaneously reducing the interdiffusion between the P-type and N-type pillars, effectively lowering the specific on-resistance.

[0105] Step Six, as FIG. 10 As shown, source region 9 is formed by photolithography and ion implantation of N-type impurities. The N-type impurity in source region 9 can be phosphorus (P) or arsenic (As), for example, As at 60 keV and 1-5E15 atoms / cm². 2 After ion implantation, there can be an activation process below 950°C, such as 900°C for 30 minutes, or RTA activation can be used.

[0106] Step 7, as follows FIG. 11A As shown, a dielectric film 10 is deposited, for example, first depositing 2000 angstroms of undoped SiO2, then depositing 8000-10000 angstroms of BPSG to form the dielectric film 10, and then forming contact holes 11 by photolithography etching. FIG. 11A The contact hole 11 shown is the first contact hole 11 at the top of the source region 9, all denoted by the symbol 11. The first contact hole 11 can penetrate 100 Å to 4000 Å into the silicon material of the first epitaxial layer 1-2 at the bottom. A P-type region 12 can be formed at the bottom of the first contact hole 11 by implanting B or BF2. For example, B can be 30-60 keV, 5E14-1E15 / cm 2, which better guarantees the ohmic contact of the subsequent metal and the contact hole Si and reduces the contact resistance. Then, the barrier layer is deposited, which can be a combination of Ti and TIN, one setting being 300-500Å of Ti and 500-1000Å of TiN. Then, the metal tungsten (W) is deposited to fill the contact hole, and the process of filling the contact hole with metal tungsten is to grow along the side wall of the contact hole and contact the center area of the contact hole. The part of the contact hole can have some gaps or no gaps. The tungsten can completely fill the contact hole or not completely fill the contact hole, as long as the subsequent metal can well realize the coverage of the hole.

[0107] As shown in FIG. 11B , the layout of the contact hole 11 is redesigned in the embodiment of the application, and the contact hole 11 of the active region, i.e., the first contact hole 11, is discontinuous and small, avoiding the short circuit between the source and the gate.

[0108] As shown in FIG. 14 , as a comparison, in the prior art, the contact hole 11 is a continuous strip structure.

[0109] Step eight, as shown in FIG. 2A , the front metal layer 13 is deposited again, the material of the front metal layer 13 includes AlCu, the deposition temperature is 250-450°C, and the thickness can be set to 2-6µm. Then, the metal AlCu, the W under the metal AlCu, and the barrier layer film are all removed through metal photolithography and dry etching, so as to realize the patterning of the front metal layer 13.

[0110] Then, the entire silicon wafer, i.e., the substrate corresponding to the drain region 1-1, is thinned to 60-200 microns through back thinning, and then the back metal layer 14 is formed on the back, and the material of the back metal layer 14 can be TiNiAg, and the thickness can be Ti 1000Å, Ni 2000Å, and Ag 10000Å.

[0111] The above process can realize the manufacture of a super-junction MOSFET and form the division of the active region 101, the transition region 102, and the terminal region 103 bearing the lateral voltage. The electrode of the source region is led out through the front metal layer 13. The gate is connected and led out through the contact hole between the metal and the end of the trench gate through the layout design of the trench gate. The drain is the back metal.

[0112] In some embodiment methods, the following processes can be added after step eight is completed to improve the performance and reliability of the product, including: After depositing a 1-2 micron dielectric film protective layer, the material can be SiON, SiO2, SiN, silicon oxide film rich in Si, or their combination, then through photolithography and dry etching to open the electrode lead-out area of the gate, the source lead-out area, and protect other areas including the terminal area subjected to lateral electric field, so as to improve the reliability of the product.

[0113] Further, after the completion of step eight, a passivation layer and a protective layer are deposited on the surface of the silicon wafer. The passivation layer can be dense silicon oxide or silicon nitride, and the protective layer can be a polyimide film. Through photolithography and development, the electrode lead-out area of the gate is opened, the source lead-out area is opened, and other areas including the terminal area subjected to lateral electric field are protected, so as to improve the reliability of the product. After the completion of the photolithography and development of the polyimide film, baking at 300-400℃ (30-90min) can be performed, and the thickness of the polyimide after baking is 4-15 microns.

[0114] The embodiment of the present application realizes a cleaner and smoother turn-on and turn-off process by the passive buffer of "capacitance increase" and the active equalization of "potential synchronization", and significantly reduces the switching loss and EMI noise emission level. By reducing the mutation rate of voltage and current from the source of the device, the present application can effectively suppress voltage overshoot and current ringing, thereby reducing electromagnetic interference (EMI).

[0115] Unlike the method of externally connecting a gate resistor, the embodiment of the present application smoothes the switching waveform through the capacitive effect, rather than simply limiting the movement of carriers. Therefore, it effectively suppresses EMI while relatively small increases in switching loss, and better maintains the advantages of high efficiency of super-junction MOSFET.

[0116] The mesh gate structure can be realized through steps fully compatible with existing standard planar gate process and trench gate process, without the need to add additional photolithography or process steps, and has good process feasibility and low cost advantage.

[0117] The above has been described in detail through specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can also make many modifications and improvements without departing from the principles of the present application, and these should also be considered as falling within the scope of protection of the present application.

Claims

1. A superjunction device, characterized in that: A superjunction structure is formed at least in the active region, the superjunction structure being formed in a first epitaxial layer doped with a first conductivity type; The device unit structure of the superjunction device is formed in the active region, and each device unit structure includes a gate unit structure and the gate unit structures of each device unit structure together form a two-dimensional mesh gate structure. The two-dimensional mesh gate structure includes a plurality of first gate strips extending in a first direction, each of the first gate strips being arranged in parallel and having a first gate spacing region between each adjacent first gate strip; A plurality of second gate segments and a grid region located between each of the first gate spacing regions are formed therein, and the forming region of each device unit structure includes a corresponding grid region; each of the second gate segments is also connected to the first gate strips on both sides and forms a gate connection node at the connection position; Each of the second gate segments is used to increase the gate parasitic capacitance of the superjunction device, and each of the gate connection nodes is used to synchronize the switching of the device unit structures on the periphery and realize the switching synchronization of each device unit structure in the entire superjunction device.

2. The superjunction device as described in claim 1, characterized in that: The lengths of each of the grid regions in the same first grid spacing region along the first direction are equal.

3. The superjunction device as described in claim 2, characterized in that: All of the grid regions are of equal length.

4. The superjunction device as described in claim 3, characterized in that: In a second direction perpendicular to the first direction, each of the second gate segments is aligned and forms a second gate strip; Alternatively, in a second direction perpendicular to the first direction, the second gate segments in adjacent first gate spacing regions are staggered; the second gate segments in two first gate spacing regions separated by one first gate spacing region are aligned.

5. The superjunction device as described in claim 1, characterized in that, Also includes: Gate bus surrounding the periphery of the two-dimensional mesh gate structure; The two ends of the first gate strip are respectively connected to the gate bus, and the gate bus is connected to the gate pad composed of a front metal layer.

6. The superjunction device as described in claim 5, characterized in that: The superjunction structure includes alternating first conductivity type pillars and second conductivity type pillars; the first conductivity type pillars are composed of the first epitaxial layer located between the second conductivity type pillars; Both the first conductive type post and the second conductive type post extend along the first direction.

7. The superjunction device as described in claim 6, characterized in that: The second conductivity type pillar includes a second epitaxial layer doped with the second conductivity type and filled in a superjunction trench.

8. The superjunction device as described in claim 6, characterized in that: The first gate bar is located on top of the corresponding first conductivity type pillar.

9. The superjunction device as described in claim 8, characterized in that: Each of the device unit structures includes a channel region doped with a second conductivity type formed in the surface region of the superjunction structure in the grid region; A source region of a first conductivity type is formed on the surface of the channel region, and the source region is aligned with the side of the first gate strip. The source region is connected to the source electrode, which is composed of the front metal layer, through a first contact hole passing through the interlayer membrane at the top of the source region. Each of the first contact holes is also connected to the channel area; Each of the first contact holes is located within the corresponding grid area, and the first contact holes in adjacent grid areas are spaced apart.

10. The superjunction device as described in claim 9, characterized in that: The two-dimensional mesh gate structure is a trench gate; Each of the trench gates extends longitudinally through the channel region, and the surface of the channel region covered by the first gate strip sidewall in the trench gate is used to form a conductive channel.

11. The superjunction device as described in claim 9, characterized in that: The two-dimensional mesh gate structure is a planar gate, and the channel region extends to the bottom of the planar gate. The surface of the channel region, which is covered by the first gate strip side in the planar gate, is used to form a conductive channel.

12. The superjunction device as described in claim 9, characterized in that: A heavily doped drain region of the first conductivity type is formed on the back side of the first epitaxial layer; A drain electrode composed of a back metal layer is formed on the back side of the drain region.

13. The superjunction device as described in claim 12, characterized in that: A terminal region surrounds the active region, and a transition region is also included between the terminal region and the active region. The superjunction structure is also formed in the transition region and the terminal region.

14. The superjunction device as described in claim 13, characterized in that, Also includes: A dielectric protective layer covers the front side of the superjunction device on which the front metal layer is formed and opens the gate lead-out region and the source lead-out region; Alternatively, it may also include: a passivation layer and a polyimide protective layer, the passivation layer and the polyimide protective layer covering the front side of the superjunction device on which the front metal layer is formed and opening the gate lead-out region and the source lead-out region.

15. The superjunction device according to any one of claims 1 to 14, characterized in that: The superjunction device is an N-type device with an N-type first conductivity type and a P-type second conductivity type; or, the superjunction device is a P-type device with a P-type first conductivity type and an N-type second conductivity type.

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