A transistor with low parasitic capacitance and a method of manufacturing the same
By forming a high-resistivity insulating region in the drain region of GaN devices and setting an intermediate metal layer or air bridge structure, the problem of large parasitic capacitance is solved, radio frequency performance is improved, and R&D costs and time are saved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- INNOGRATION SUZHOU
- Filing Date
- 2021-04-25
- Publication Date
- 2026-07-24
AI Technical Summary
Existing GaN devices have large parasitic drain-source capacitance, which affects RF performance. Furthermore, existing methods for reducing this capacitance are prone to introducing other problems and involve long development costs and cycles.
A high-resistivity insulating region is formed in a part of the drain region. The insulating region is formed by doping with ion implantation and an intermediate metal layer or air bridge structure may be set to reduce the area of the two-dimensional electron gas in the drain region and reduce the source-drain parasitic capacitance.
It significantly reduces source-drain parasitic capacitance, improves RF performance, and saves R&D costs and time, while the metal current capacity and lifespan are unaffected.
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Figure CN115249742B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a low parasitic capacitance transistor and its fabrication method, which is particularly suitable for GaN HEMT devices. Background Technology
[0002] When a transistor operates normally, its source and drain junctions are reverse-biased. When the voltage between the source and drain changes, the capacitors charge or discharge. When the transistor operates at a high frequency, the charging and discharging of parasitic capacitances will affect the transistor's high-frequency characteristics. Simultaneously, noise from the substrate will be transmitted to the transistor along the parasitic capacitances. Noise can also be transmitted to various branches of the circuit through the loops formed by the substrate and the various parasitic capacitances, severely impacting circuit performance.
[0003] The following explanation uses GaN devices as an example. The cross-section of existing GaN devices is as follows: Figure 1 As shown, the device includes a GaN wafer with a grounded backside metal layer 08, a substrate 01, and an epitaxial layer. The epitaxial layer includes a GaN buffer layer 02 and an AlGaN carrier supply layer 03. A two-dimensional electron gas structure is formed between the buffer layer 02 and the carrier supply layer 03 due to heterojunction polarization. The device also includes an electrode layer disposed on the epitaxial layer, comprising a gate 05, a field plate 06, a source ohmic contact metal layer 041, a source upper metal layer 071, a drain ohmic contact metal layer 042, and a drain upper metal layer 072. Under the influence of electric fields and thermal stress, metal migration occurs in semiconductor devices, leading to a decrease in the effective lifetime of the device. Often, a certain width of metal is designed in the device design to meet certain lifetime requirements. At the same time, the current capacity of a certain thickness of metal is also limited. To meet the requirements of power output per unit size and lifetime, the lateral width of the drain region of GaN devices is relatively large, such as... Figure 2 As shown, the larger the drain region, the larger the vertical parasitic drain-source capacitance Cds_Y of the GaN device will be. The overall parasitic drain-source capacitance of the GaN device, which is the lateral parasitic drain-source capacitance Cds_X + Cds_Y, will also increase accordingly. This is the main reason affecting the RF performance of the device.
[0004] Existing methods for reducing parasitic drain-source capacitance mostly involve modifying wafer epitaxial design and adjusting some chip surface processes. However, these adjustments can easily introduce other problems, and the research and development costs and cycles are relatively long. Summary of the Invention
[0005] To address the aforementioned technical problems, the present invention aims to provide a low parasitic capacitance transistor and its fabrication method, which forms a high-resistivity insulating region in a portion of the drain region, significantly reducing source-drain parasitic capacitance and improving the radio frequency performance of the radio frequency device.
[0006] To address these problems in the prior art, the technical solution provided by this invention is as follows:
[0007] A low parasitic capacitance transistor includes a substrate, a ground metal layer disposed on a second surface of the substrate, an epitaxial layer disposed on a first surface of the substrate, and an electrode layer disposed on the epitaxial layer. The epitaxial layer includes a gate region, a source region, and a drain region. The electrode layers of the source region and the drain region include an ohmic contact layer and an upper metal layer disposed on the ohmic contact layer. A portion of the drain region is doped to epitaxially form an insulating region in that region.
[0008] In the preferred technical solution, doping is achieved using ion implantation.
[0009] In a preferred embodiment, the ion implantation region is a certain width region below the middle of the ohmic contact layer of the drain region.
[0010] In a preferred embodiment, at least one intermediate metal layer is provided between the ohmic contact layer and the upper metal layer.
[0011] In a preferred embodiment, an insulating layer is provided between the insulating region and the ohmic contact layer.
[0012] In a preferred embodiment, the ohmic contact layer above the insulating region is disconnected;
[0013] In a preferred embodiment, the ohmic contact layer and the intermediate metal layer above the insulating region are disconnected.
[0014] In a preferred embodiment, a cavity is provided below the upper metal layer of the drain region at the location corresponding to the insulating region, so that the upper metal layer of the drain region forms an air bridge structure.
[0015] This invention also discloses a method for fabricating a transistor with low parasitic capacitance, comprising the following steps:
[0016] S01: A grounded metal layer is formed on the second surface of the substrate;
[0017] S02: An epitaxial layer is grown on the first surface of a substrate, and an electrode layer is disposed on the epitaxial layer. The epitaxial layer includes a gate region, a source region, and a drain region. The electrode layers of the source region and the drain region include an ohmic contact layer and an upper metal layer disposed on the ohmic contact layer.
[0018] S03: A portion of the drain region is doped to create an epitaxial insulating region.
[0019] In a preferred embodiment, at least one intermediate metal layer is provided between the ohmic contact layer and the upper metal layer.
[0020] In a preferred embodiment, the ohmic contact layer above the insulating region is disconnected, and a cavity is provided below the upper metal layer of the drain region at the position corresponding to the insulating region, so that the upper metal layer of the drain region forms an air bridge structure.
[0021] In a preferred embodiment, the ohmic contact layer and the intermediate metal layer above the insulating region are disconnected, and a cavity is provided below the upper metal layer of the drain region at the position corresponding to the insulating region, so that the upper metal layer of the drain region forms an air bridge structure.
[0022] Compared with existing solutions, the advantages of this invention are:
[0023] This invention utilizes existing epitaxial wafers and processes, significantly reducing R&D costs and time. Doping a portion of the area below the drain region creates a high-resistivity insulating region, reducing the area of the two-dimensional electron gas in the drain region. Raising or disconnecting the ohmic contact metal of the insulating region reduces the parasitic capacitance between the drain region and the back-side grounded metal, lowering the overall source-drain parasitic capacitance of the device and improving its RF performance without affecting metal current capacity or lifespan. Attached Figure Description
[0024] The present invention will be further described below with reference to the accompanying drawings and embodiments:
[0025] Figure 1 This is a schematic diagram of the cross-sectional structure of an existing GaN device;
[0026] Figure 2 A schematic diagram of the parasitic source and leakage capacitances of a cross-sectional structure of an existing GaN device;
[0027] Figure 3 This is a schematic cross-sectional view of a transistor with low parasitic capacitance according to one embodiment.
[0028] Figure 4 A schematic cross-sectional view of a transistor with low parasitic capacitance according to another embodiment;
[0029] Figure 5 This is a schematic cross-sectional view of a transistor with low parasitic capacitance according to another embodiment.
[0030] Figure 6 This is a flowchart illustrating the fabrication method of the low parasitic capacitance transistor of the present invention. Detailed Implementation
[0031] The above-described solution will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. The implementation conditions used in the embodiments may be further adjusted according to the conditions of specific manufacturers, and the implementation conditions not specified are generally those in routine experiments.
[0032] This invention is mainly used for GaN HEMT devices, but can also be used for GaAs FETs and LDMOS, etc. The following description uses GaNHEMT devices as an example. Other transistor structures also have similar structures.
[0033] Example 1:
[0034] like Figure 3 As shown, a low parasitic capacitance transistor includes a substrate 11, a ground metal layer 18 disposed on a second surface 111 (lower surface) of the substrate 11, an epitaxial layer disposed on a first surface 112 (upper surface) of the substrate 11, and an electrode layer disposed on the epitaxial layer. The epitaxial layer includes a GaN buffer layer 12 and an AlGaN carrier supply layer 13. A two-dimensional electron gas is formed between the buffer layer 12 and the carrier supply layer 13 due to the heterojunction polarization effect.
[0035] An ohmic contact layer 14 is disposed on the AlGaN carrier supply layer 13, and an upper metal layer 15 is disposed on the ohmic contact layer 14. The epitaxial layer includes a gate region, a source region, and a drain region. The electrode layer includes an electrode layer for the gate region, an electrode layer for the source region, and an electrode layer for the drain region. The electrode layer for the gate region includes a gate 21 and a field plate 22. The electrode layer for the source region includes an upper metal layer 31 for the source and an ohmic contact layer 32 for the source. The electrode layer for the drain region includes an upper metal layer 41 for the drain and an ohmic contact layer 42 for the drain. That is, the upper metal layer 15 includes an upper metal layer 41 for the drain and an upper metal layer 31 for the source, and the ohmic contact layer 14 includes an ohmic contact layer 32 for the source and an ohmic contact layer 42 for the drain.
[0036] A portion of the drain region is doped to epitaxially form an insulating region 50, disrupting the two-dimensional electron gas and lattice structure. The insulating region 50 extends toward the substrate 11.
[0037] The substrate 11 can be a SiC substrate, a Si substrate, or a sapphire substrate.
[0038] Doping methods include epitaxy, ion implantation, thermal diffusion, etc. In a specific implementation, ion implantation is used to achieve doping, specifically high-energy ion implantation. This disrupts the two-dimensional electron gas and crystal lattice structure, causing the epitaxial formation of a high-resistivity insulating region 50 in that area.
[0039] The ions implanted can be N + O + Ar+ Kr + Fe + B + or Zn + One or more of the following. Of course, other feasible ions can also be used, as long as they can disrupt the two-dimensional electron gas and crystal lattice structure to form an insulating region 50.
[0040] Ion implantation is performed below the ohmic contact layer in the drain region, that is, ion implantation is performed in a certain width area below the middle of the ohmic contact layer 42 of the drain. This certain width can be 1 / 3 of the total width of the ohmic contact layer 42 of the drain, or it can be other widths, which are not limited here.
[0041] The upper metal layer 15 typically uses two metal layers, resulting in a thicker overall thickness compared to a single-layer metal layer. This allows for greater metal current capacity and a longer lifespan. A high-resistance insulating region is positioned at the center of the drain ohmic contact, without affecting the device's conductive path, turn-on resistance, or saturation current. Simultaneously, two-thirds of the ohmic contact area is retained to ensure the drain metal and conductive path remain unaffected, reducing Cds_Y.
[0042] Example 2:
[0043] like Figure 4 As shown, the structure of the low parasitic capacitance transistor in this embodiment is basically the same as that in Embodiment 1, except that at least one intermediate metal layer 16 is provided between the ohmic contact layer 14 and the upper metal layer 15, for example, one, two, or more layers. An insulating layer 51 is provided between the insulating region 50 and the ohmic contact layer 14. The insulating layer 51 can be a nitride or an oxide. The insulating layer 51 serves to raise the upper metal layer 41 of the drain region and the back-side grounding metal layer 18, so that there is no direct metal contact above the high-resistivity insulating region, and no Schottky diode effect is generated. This can further reduce the source-drain parasitic capacitance, that is, the overall parasitic capacitance of the drain region and the back-side grounding metal.
[0044] In a preferred embodiment, two intermediate metal layers are used, namely a first metal layer and a second metal layer, and an upper metal layer is used as a third metal layer, with the thickness of the three metal layers increasing sequentially.
[0045] Alternatively, the intermediate metal layer 16 can be omitted, and an insulating layer 51 can be placed directly between the insulating area 50 and the ohmic contact layer 14 to achieve the same effect.
[0046] Example 3:
[0047] like Figure 5As shown, the structure of the low parasitic capacitance transistor in this embodiment is basically the same as that in Embodiment 1, except that at least one intermediate metal layer 16 is provided between the ohmic contact layer 14 and the upper metal layer 15, for example, one, two, or more layers. The ohmic contact layer 14 and the intermediate metal layer 16 above the insulating region 50 are disconnected. Alternatively, in Embodiment 1, only the ohmic contact layer above the insulating region 50 can be disconnected. This ensures that there is no direct metal contact above the high-resistivity insulating region, preventing the Schottky diode effect and further reducing source-drain parasitic capacitance.
[0048] To further reduce source-drain parasitic capacitance, in a preferred embodiment, a cavity 60 is provided below the upper metal layer 41 of the drain region at a position corresponding to the insulating region 50, thereby forming an air bridge structure in the upper metal layer 41 of the drain region. The air bridge structure can be implemented using an air bridge process. The ohmic contact layers 42 of the drain on both sides of the air bridge structure and the intermediate metal layer 16 serve as the piers of the air bridge structure. Additionally, bridge pillars of a certain height are formed on both sides below the air bridge structure. This further reduces source-drain parasitic capacitance without affecting the metal current capacity and lifespan.
[0049] Alternatively, the intermediate metal layer 16 can be omitted, and only the ohmic contact layer above the insulation region 50 can be disconnected. An air bridge structure can be made in the upper metal layer 41 of the drain region to achieve the same effect.
[0050] Example 4:
[0051] like Figure 6 As shown, the present invention also discloses a method for fabricating a transistor with low parasitic capacitance, comprising the following steps:
[0052] S01: A grounded metal layer is formed on the second surface of the substrate;
[0053] S02: An epitaxial layer is grown on the first surface of a substrate, and an electrode layer is disposed on the epitaxial layer. The epitaxial layer includes a gate region, a source region, and a drain region. The electrode layers of the source region and the drain region include an ohmic contact layer and an upper metal layer disposed on the ohmic contact layer.
[0054] S03: A portion of the drain region is doped to create an epitaxial insulating region.
[0055] The ions implanted can be N + O + Ar + Kr + Fe + B + or Zn +One or more of the following. Of course, other feasible ions can also be used, as long as they can disrupt the two-dimensional electron gas and crystal lattice structure to form an insulating region 50.
[0056] In a preferred embodiment, step S02 further includes providing at least one intermediate metal layer between the ohmic contact layer and the upper metal layer, and providing an insulating layer 51 between the insulating region 50 and the ohmic contact layer 14. The insulating layer 51 can be a nitride or an oxide. The insulating layer 51 serves to raise the upper metal layer 41 of the drain region and the back-side grounded metal layer 18, so that there is no direct metal contact above the high-resistivity insulating region, and no Schottky diode effect is generated. This can further reduce the source-drain parasitic capacitance, that is, the parasitic capacitance of the drain region as a whole and the back-side grounded metal.
[0057] In a preferred embodiment, the method further includes the following steps: forming at least one intermediate metal layer between the ohmic contact layer and the upper metal layer; disconnecting the ohmic contact layer 41 and the intermediate metal layer above the insulating region; and forming a cavity below the upper metal layer of the drain region at a location corresponding to the insulating region using an air-bridge process, thereby forming an air-bridge structure in the upper metal layer 41 of the drain region. This further reduces source-drain parasitic capacitance without affecting the metal current capacity and lifespan.
[0058] This invention utilizes existing epitaxial wafers and processes, significantly reducing R&D costs and time.
[0059] It should be understood that the specific embodiments described above are merely illustrative or explanatory of the principles of the invention and do not constitute a limitation thereof. Therefore, any modifications, equivalent substitutions, improvements, etc., made without departing from the spirit and scope of the invention should be included within the protection scope of the invention. Furthermore, the appended claims are intended to cover all variations and modifications falling within the scope and boundaries of the appended claims, or equivalent forms of such scope and boundaries.
Claims
1. A low parasitic capacitance transistor, comprising a substrate, a ground metal layer disposed on a second surface of the substrate, an epitaxial layer disposed on a first surface of the substrate, and an electrode layer disposed on the epitaxial layer, wherein the epitaxial layer comprises a gate region, a source region, and a drain region, characterized in that, The electrode layer of the source region and the electrode layer of the drain region include an ohmic contact layer and an upper metal layer disposed on the ohmic contact layer; at least one intermediate metal layer is disposed between the ohmic contact layer and the upper metal layer; Doping is performed only in a localized area in the middle of the ohmic contact layer of the drain region, with the width of the localized area being 1 / 3 of the total width of the ohmic contact layer of the drain region. This is done to disrupt the two-dimensional electron gas and lattice structure of the localized area, forming an insulating region extending toward the substrate, and retaining ohmic contact regions on both sides of the insulating region. The ohmic contact layer and the intermediate metal layer above the insulating area are both disconnected, so that there is no direct metal contact above the insulating area. The upper metal layer of the drain region is not broken above the insulating region, and a cavity is provided below it at the position corresponding to the insulating region, so that the upper metal layer of the drain region spans the cavity and forms an air bridge structure, and the ohmic contact layer and the middle metal layer of the drain region on both sides of the air bridge structure serve as the piers of the air bridge structure.
2. The low parasitic capacitance transistor according to claim 1, characterized in that, Doping is achieved using ion implantation.
3. The low parasitic capacitance transistor according to claim 1, characterized in that, An insulating layer is provided between the insulating region and the ohmic contact layer.
4. A method for fabricating a transistor with low parasitic capacitance, characterized in that, Includes the following steps: S01: A grounded metal layer is formed on the second surface of the substrate; S02: An epitaxial layer is grown on a first surface of a substrate, and an electrode layer is disposed on the epitaxial layer. The epitaxial layer includes a gate region, a source region, and a drain region. The electrode layers of the source region and the drain region include an ohmic contact layer and an upper metal layer disposed on the ohmic contact layer. At least one intermediate metal layer is disposed between the ohmic contact layer and the upper metal layer. S03: Doping is performed only in the middle local region of the ohmic contact layer in the width direction of the drain region. The width of the middle local region is 1 / 3 of the total width of the ohmic contact layer of the drain region, so as to destroy the two-dimensional electron gas and lattice structure of the middle local region, form an insulating region extending towards the substrate, and retain ohmic contact regions on both sides of the insulating region. S04: Remove the ohmic contact layer and intermediate metal layer above the insulating area so that there is no direct metal contact above the insulating area; S05: An upper metal layer of the drain region is formed on the intermediate metal layer. The upper metal layer of the drain region is not broken above the insulating region, and a cavity is provided below it at the position corresponding to the insulating region, so that the upper metal layer of the drain region spans above the cavity and forms an air bridge structure. The ohmic contact layer of the drain region and the intermediate metal layer on both sides of the air bridge structure serve as the piers of the air bridge structure.