Integrated circuit package including high thermal conductivity materials in three-dimensional die stack

Abstract

The invention relates to an integrated circuit package including a high thermal conductivity material in a three-dimensional die stack. Microelectronic assemblies, related devices and methods are disclosed herein. In some embodiments, a microelectronic assembly may include: a first die having a surface; a second die and a third die, the second die and the third die having a first surface and an opposing second surface, where the first surfaces of the second die and the third die are electrically coupled to the surface of the first die; a first material on a surface of the first die and around and between the second die and the third die, the first material having a non-planar surface; and a layer on the non-planar surface of the first material and in physical contact with the non-planar surface of the first material and with the second surfaces of the second and third dies, the layer comprising a second material having a thermal conductivity equal to or greater than 10 watts per meter-Kelvin (W / m-K).

Description

Background Technology

[0001] Electronic circuits, when typically fabricated on wafers of semiconductor materials such as silicon, are called ICs. Wafers containing such ICs are usually diced into many individual dies. These dies can be packaged into IC packages as three-dimensional (3D) die stacks, which contain one or more dies along with other electronic components such as resistors, capacitors, and inductors. IC packages can be integrated into electronic systems such as consumer electronics systems. Attached Figure Description

[0002] The embodiments will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. For ease of this description, the same reference numerals designate the same structural elements. In the accompanying figures, the embodiments are illustrated by way of example rather than limitation.

[0003] Figure 1 A is a schematic cross-sectional view of an example microelectronic assembly according to some embodiments of the present disclosure.

[0004] Figure 1 B is Figure 1 A schematic cross-sectional view of a portion of an example microelectronic assembly.

[0005] Figures 2A-2D This is a schematic cross-sectional view of other example microelectronic assemblies according to some embodiments of the present disclosure.

[0006] Figures 3A-3F It is for manufacturing according to some embodiments of this disclosure. Figure 1 A schematic cross-sectional view of different stages of an example process for a microelectronic assembly of A.

[0007] Figures 4A-4C This is a schematic cross-sectional view of other example microelectronic assemblies according to some embodiments of the present disclosure.

[0008] Figure 4D yes Figure 4C A schematic cross-sectional view of a portion of an example microelectronic assembly.

[0009] Figure 4E and Figure 4F This is a schematic cross-sectional view of other example microelectronic assemblies according to some embodiments of the present disclosure.

[0010] Figures 5A-5D This is a schematic cross-sectional view of other example microelectronic assemblies according to some embodiments of the present disclosure.

[0011] Figures 6A-6DThis is a schematic cross-sectional view of other example microelectronic assemblies according to some embodiments of the present disclosure.

[0012] Figure 7A and 7B This is a schematic cross-sectional view of yet another example microelectronic assembly according to some embodiments of the present disclosure.

[0013] Figures 8A-8C This is a schematic cross-sectional view of other example microelectronic assemblies according to some embodiments of the present disclosure.

[0014] Figure 8D It is for manufacturing according to some embodiments of this disclosure. Figure 8C A schematic cross-sectional view of a stage in an example process of microelectronic assembly.

[0015] Figure 9 This is a cross-sectional view of a device package including one or more microelectronic assemblies according to any embodiment of the embodiments disclosed herein.

[0016] Figure 10 It is a cross-sectional side view of a device assembly including one or more microelectronic assemblies according to any embodiment of the embodiments disclosed herein.

[0017] Figure 11 This is a block diagram of an example computing device including one or more microelectronic assemblies, according to any embodiment of the embodiments disclosed herein. Detailed Implementation

[0018] In today's 3D stacking architectures, chiplets (also referred to herein as dies) are typically bonded to a base wafer (e.g., monolithic or depolymerized dies) with through-the-substrate vias (TSVs), and the gaps between the chiplets are then filled with a dielectric material (e.g., silicon oxide); this process is referred to as gap filling. High-density interconnects are used to couple the chiplets to the base wafer; these high-density interconnects are also referred to herein as hybrid bonding. As used herein, "high-density interconnects" include die-to-die (DTD) interconnects with a pitch of less than 10 micrometers. As used herein, the pitch is measured center-to-center (e.g., from the center of the interconnect to the center of the adjacent interconnect). 3D stacking architectures can also be combined to allow top-packaged chips to communicate vertically with other dies using through-the-dielectric vias (TDVs), also referred to herein as "conductive vias," which are typically larger than the TSVs. Deposition of the gap filling material continues to a few micrometers above the top of the chiplets. Some of this additional thickness is then removed using a planarization process such as chemical mechanical polishing (CMP). However, due to the different CMP removal rates of the interstitial fill material relative to adjacent silicon, completely removing the interstitial fill material from above the chiplet will leave a certain morphology in the interstitial fill region between them (e.g., producing an irregular morphology 111, such as...). Figure 1As shown in Figure 8, this degrades or prevents subsequent bonding of the structured silicon wafer. As a result, after planarization (e.g., as shown in Figure 8), a finite thickness of interstitial filler (e.g., typically between 1 and 3 micrometers) is left over the dielet as a bonding layer to the structured silicon. One challenge of this approach is that this bonding layer exhibits high thermal resistance and reduces heat transfer due to the low thermal conductivity of typical interstitial fillers (e.g., silicon oxide has a thermal conductivity of approximately 1 watt per meter-Kelvin (W / mK), less than 1 / 100th the thermal conductivity of silicon). Another challenge is that the interstitial filler is typically filled vertically and horizontally, and an interface seam is formed at an angle between the horizontal surface of the base wafer and the sidewalls of the dielet, which can introduce additional thermal resistance from the interstitial filler. Furthermore, plasma-enhanced chemical vapor deposition (PECVD) processes are typically used to deposit the interstitial filler, which generates high stress in the interstitial filler on the sidewalls of the dielet due to the aspect ratio involved in the deposition process and the conformal nature of the interstitial filler, leading to cracking. Once cracks begin to form, they tend to propagate through the gap filler material and / or dielets, where additional mechanical and / or thermal stresses increase the severity of crack propagation. In particular, thermal cycling of IC packages during manufacturing and operation can promote crack propagation. Crack formation and propagation compromise the structural integrity of IC packages and make them particularly vulnerable to failure over time. Crack formation can further lead to the formation of voids between the gap filler material and the structural silicon cap, reducing heat dissipation.

[0019] Embodiments of this disclosure relate to various techniques and related apparatus and methods for mitigating (e.g., alleviating or reducing) high thermal resistance in bonding layers and high stress in gap-filling materials. One aspect of this disclosure includes planarizing the gap-filling layer after deposition to fully expose the die-off, and then depositing a high thermal conductivity (HTC) material (e.g., having a thermal conductivity equal to or greater than 10 W / mK) to correct for inconsistent morphology of the planarized gap-filling material (e.g., as shown in the image). Figure 1 A, Figures 2A-2D and Figures 3A-3F (As shown in the diagram). A thin pad (e.g., a diffusion barrier layer) can be deposited between the gap filler material and the HTC material to prevent the HTC material from diffusing into the die or into the gap filler material. A bonding material layer can be deposited on the HTC material to enable bonding to a structured wafer, which may have its own thin bonding material layer. This approach can reduce the thermal resistance of the gap filler material to less than 1 / 10, which minimizes the total thermal resistance to remove heat from the die, and enables higher power and improved system performance during operation.

[0020] Another aspect of this disclosure also includes adding an HTC material layer (e.g., such as...) to an IC package having stacked dies. Figures 4A-4F As shown in the diagram, the HTC material layer serves as a heat spreader to prevent localized high temperatures, also known as "hot spots," which can exceed temperature limits and degrade package performance. The heat spreader is currently integrated into the package cover, where a thermal interface material (TIM) is applied to contact the back side of the die. This may be insufficient for 3D heterogeneous integration of entirely different chiplets into a multilayer die composite, where heat spreaders may be needed at different chiplet locations or layers within the stack. A thin bonding material layer (e.g., titanium) deposited on the HTC material allows HTC material layers of any thickness to be fabricated on a separate substrate and integrated into a 3D die composite as needed to serve as a heat spreader. Such heat spreader fabrication is not constrained by the process limitations (such as thermal budget or film stress) of monolithic fabrication on the die in the assembly, as they can be fabricated and bonded externally during assembly. In some embodiments of such heat spreaders, the HTC material can be a high thermal conductivity material with a thermal conductivity equal to or greater than 150 W / mK.

[0021] Another aspect of this disclosure includes adding a substrate with microchannels for allowing cooling fluid to flow to an IC package having stacked dies, the IC package having an HTC material layer (e.g., such as...). Figures 5A-5D As shown in the diagram. As described above, an IC package with stacked dies can include a substrate (i.e., a structural silicon cap) bonded on top of the chiplet. In this respect, the substrate includes microchannels with cooling fluid to form a substrate-based microchannel cooler. For example, thermal stress at the interface can be reduced by integrating a substrate-based microchannel cooler compared to using a metal-based microchannel embedded integrated heat sink (IHS) because there is no coefficient of thermal expansion (CTE) mismatch between the chiplet and the substrate. Furthermore, the substrate-based microchannel cooler is thermally superior compared to conventional cold plates (with TIM1 and TIM2) or microchannel embedded IHS because it eliminates excessive thermal resistance interfaces (TIMs) from the stack.

[0022] Another aspect of this disclosure also includes adding a dummy die to an IC package having stacked dies, wherein the dummy die is electrically coupled to the base wafer and to an HTC material layer (e.g., as shown in the image). Figures 6A-6D(As shown in the diagram). In today's 3D stacked architectures, virtual or non-functional (NF) structured dielets are typically bonded to a base wafer (e.g., a monolithic or depolymerized base wafer) to meet system thermomechanical requirements. Such virtual dies are typically bonded to the base wafer using dielectric fusion bonding or metal-dielectric hybrid bonding for better thermal interface resistance, and are bonded to a structural silicon cap at the top of the 3D die composite using dielectric bonding layers (such as silicon oxide, silicon nitride, or silicon nitride carbon). The challenge of this approach is that such bonding layers at both surfaces of the virtual die have high thermal resistance due to the low thermal conductivity of the dielectric materials typically used for bonding (e.g., silicon oxide has a thermal conductivity of about 1 W / mK, which is less than 1 / 100th the thermal conductivity of silicon), creating a thermal bottleneck for removing heat from the base die during operating conditions. Conductively coupling the virtual die to both surfaces reduces assembly costs because precise alignment is not required compared to hybrid bonding, and heat dissipation of the base wafer can be increased by reducing the interface temperature of the coefficient resistance (TCR) (e.g., metal relative to dielectric layers). By utilizing materials with higher thermal conductivity than silicon, heat dissipation can be further improved, so that the interface does not dominate the overall thermal conductivity.

[0023] Another aspect of this disclosure includes adding a die comprising a circuit module for power delivery, and adding a substrate having a redistribution layer (RDL) to an IC package having stacked dies, the IC package having an HTC material layer (e.g., such as...). Figure 7A (as shown) or having a bonding material layer (e.g., as shown) Figure 7B (As shown in the diagram). With the increasing demand for faster microchips, power requirements also increase. Power delivery in IC packages with stacked dies is challenging due to the increased power density (which results in fewer resources for power delivery and limits the performance of such architectures). One of the biggest challenges involves addressing die-to-die interfaces. New technologies have expanded the physical size of interfaces to improve input / output (I / O) capabilities; however, this is not the case for power delivery. Conventional power delivery methods follow a hierarchical flow based on the system's lithographic density, where high-voltage power enters through the circuit board, is routed to the package substrate, and ultimately to the die with its fine features. Newer approaches have focused on reducing these paths by vertically integrating power delivery paths through voltage regulators on the top or bottom of the die. Direct metal-to-metal bonding creates a better thermal interface, also serves as a power delivery path, and facilitates the formation of line contacts and / or planar contacts instead of point contacts. This document discloses power delivery structures that use thin bonding layers and lines and / or planes in an RDL, or use HTC material layers, thin bonding layers and lines and / or planes in an RDL as power delivery paths.

[0024] Another aspect of this disclosure includes reducing or eliminating interface seams between small chips in an IC package having stacked dies, and mitigating stress in the gap-fill material during deposition (e.g., by increasing the roughness of the sidewall surface areas, by depositing a protective coating material, or by using electrostatic effects during gap-fill deposition). Figures 8A-8C (As shown in the diagram). The increased surface roughness reduces the adhesion of the gap filler to the sidewalls and results in more horizontal directional filling during the PECVD process. The protective coating material may include materials that reduce precursor absorption of the gap filler to the sidewalls during the PECVD process due to their hydrophobicity. Electrostatic effects during deposition may preferentially deposit the gap filler for more horizontal directional filling during the PECVD process. With reduced adhesion to the sidewalls, the gap filler follows a more bottom-up filling pattern, resulting in seamless filling, less breakage, and a void-free bond between the gap filler and the structured silicon cap.

[0025] Different aspects of this disclosure can be detected when any structure described herein is examined using images from suitable characterization tools, such as scanning electron microscopy (SEM) images and transmission electron microscopy (TEM) images. Different compositions of the materials in the structures described herein can be detected using, for example, energy-dispersive X-ray spectroscopy (EDS). Surface roughness can be determined using, for example, atomic force microscopy (AFM).

[0026] Each of the structures, assemblies, packages, methods, apparatuses, and systems disclosed herein may have several innovative aspects, none of which individually is responsible for all the desired properties disclosed herein. Details of one or more implementations of the subject matter described herein are set forth in the following description and accompanying drawings.

[0027] In the following detailed description, various aspects of the illustrative implementation may be described using terms commonly used by those skilled in the art to convey the substance of the work to others skilled in the art.

[0028] The terms “circuit” and “circuit module” refer to one or more passive and / or active electrical and / or electronic components arranged to cooperate with each other to provide a desired function. The terms also refer to analog circuit modules, digital circuit modules, hardwired circuit modules, programmable circuit modules, microcontroller circuit modules, and / or any other type of physical hardware electrical and / or electronic components.

[0029] The term "integrated circuit" refers to a circuit that is integrated into a single semiconductor or similar material.

[0030] In some embodiments, the IC dies disclosed herein may include a substantially single-crystal semiconductor, such as silicon or germanium, as a base material (e.g., substrate, body), on which integrated circuits are fabricated using conventional semiconductor processing methods. The semiconductor base material may include, for example, N-type or P-type materials. The die may include, for example, a crystalline base material formed using bulk silicon (or other bulk semiconductor materials) or a silicon-on-insulator (SOI) structure. In some other embodiments, the base material of one or more dies in the IC die may include alternative materials, which may or may not be combined with silicon. These alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of III-N, III-V, II-VI, or IV group materials. In still other embodiments, the base material may include, for example, a compound semiconductor having a first sublattice of at least one element from group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from group V of the periodic table (e.g., P, As, Sb). In other embodiments, the base material may include intrinsic IV or III-V semiconductor materials or alloys that are not intentionally doped with any electroactive impurities; in alternative embodiments, a nominal level of impurity dopant may be present. In still other embodiments, the die may include an amorphous material such as a polymer; for example, the base material may include epoxy resin filled with silicon dioxide. In other embodiments, the base material may include high-mobility oxide semiconductor materials such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Typically, the base material may include one or more of the following: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium. While several examples of materials for dies are described herein, any material or structure that can be used as the basis (e.g., base material) upon which IC circuits and structures as described herein can be built is within the spirit and scope of this disclosure.

[0031] Unless otherwise stated, the IC dies described herein include one or more IC structures (or simply "ICs") that implement (i.e., are configured to perform) a certain function. In one such example, the term "memory die" may be used to describe a die that includes one or more ICs implementing memory circuitry modules (e.g., ICs implementing one or more memory devices, memory arrays, control logic configured to control memory devices and arrays, etc.). In another such example, the term "computing die" may be used to describe a die that includes one or more ICs implementing logic / computing circuitry modules (e.g., ICs implementing one or more I / O functions, arithmetic operations, data pipeline operations, etc.).

[0032] In another example, the terms “package” and “IC package” are synonymous, as are the terms “die” and “IC die”. Note that the terms “chiplet,” “chip,” “die,” and “IC die” are used interchangeably in this document.

[0033] Unless otherwise stated, the term "insulation" means "electrical insulation" and the term "conduction" means "electrical conduction". In relation to optical signals and / or devices, components, and elements that operate on or use optical signals, the term "conduction" may also mean "optical conduction".

[0034] The terms “oxide,” “carbide,” and “nitride” refer to compounds that contain oxygen, carbon, nitrogen, etc., respectively.

[0035] The term "high-k dielectric" refers to a material with a higher dielectric constant than silicon oxide, while the term "low-k dielectric" refers to a material with a lower dielectric constant than silicon oxide.

[0036] The term "insulating material" or "insulator" (also referred to herein as "dielectric material" or "dielectric") means a solid material that is substantially non-conductive (and / or a liquid material that solidifies after processing as described herein). These can include (by way of example and not limitation) organic polymers and plastics, as well as inorganic materials such as ionic crystals, ceramics, glass, silicon, silicon oxide, silicon carbide, silicon carbonitride, silicon nitride, and alumina, or combinations thereof. They can include dielectric materials, high-polarizability materials, and / or piezoelectric materials. Dielectric materials can include any suitable dielectric material commonly used in semiconductor manufacturing, such as silicon and one or more of oxygen, nitrogen, hydrogen, and carbon (e.g., in the form of silicon oxide, silicon nitride, silicon oxynitride, or silicon carbonitride); polyimide materials; or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, porous dielectrics, organic polymer dielectrics, photoimageable dielectrics, and / or benzocyclobutene-based polymers). They can be transparent or opaque without departing from the scope of this disclosure. Another example of insulating materials is the material of the mold or similar mold used in encapsulation applications and the underfill, including, for example, materials used in organic interlayers, encapsulation supports and other such components.

[0037] In various embodiments, the components associated with the IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. In various embodiments, the components associated with the IC may include those monolithically integrated within the IC, those mounted on the IC, or those connected to the IC. Depending on the components associated with the IC, the ICs described herein may be analog or digital and can be used in many applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc. The ICs described herein may be used in a single IC die or as part of a chipset to perform one or more related functions in a computer.

[0038] In various embodiments of this disclosure, the transistors described herein may be field-effect transistors (FETs), such as MOSFETs. In many embodiments, an FET is a four-terminal device. In silicon-on-insulator, nanoribbon, or gate-around-all (GAA) FETs, an FET is a three-terminal device that includes source, drain, and gate terminals and uses an electric field to control the current flowing through the device. An FET typically includes a channel material, source and drain regions provided in and / or on the channel material, and a gate stack including a gate electrode material (alternatively referred to as a "work function" material) provided on a portion of the channel material between the source and drain regions ("channel portion") and optionally also including a gate dielectric material between the gate electrode material and the channel material.

[0039] In a general sense, “interconnection” refers to any element that provides a physical connection between two other elements. For example, an electrical interconnect provides electrical connectivity between two electrical components, facilitating the transmission of electrical signals between them; an optical interconnect provides optical connectivity between two optical components, facilitating the transmission of optical signals between them. As used herein, both electrical interconnects and optical interconnects are included in the term “interconnection.” The nature of the described interconnection is understood herein with reference to the associated signal medium. Therefore, when used in relation to electronic devices, such as ICs that operate using electrical signals, the term “interconnection” describes any element formed of a conductive material that provides electrical connectivity to one or more elements associated with the IC and / or electrical connectivity between various such elements. In this context, the term “interconnection” can refer to both electrical traces (sometimes also referred to as “lines,” “wires,” “metallic wires,” or “trenches”) and conductive vias (sometimes also referred to as “vias” or “metallic vias”). Sometimes, conductive traces and vias may be referred to as “conductive traces” and “conductive vias,” respectively, to emphasize the fact that these elements comprise conductive materials such as metals. Similarly, when used in relation to devices that also operate on optical signals, such as photonic ICs (PICs), "interconnect" can also describe any element formed of optically conductive material that provides optical connectivity to one or more elements associated with the PIC. In this case, the term "interconnect" can refer to optical waveguides, including optical fibers, beam splitters, optical combiners, optical couplers, and optical vias.

[0040] The term "waveguide" refers to any structure that functions to guide the propagation of light from one location, typically through a substrate material such as silicon or glass, to another location. In various examples, waveguides can be formed from silicon, doped silicon, silicon nitride, glass such as silica (e.g., silicon dioxide or SiO2), borosilicates (e.g., 70-80 wt% SiO2, 7-13 wt% B2O3, 4-8 wt% Na2O or K2O, and 2-8 wt% Al2O3), and so on. Various techniques can be used to form waveguides, including but not limited to in-situ waveguide formation. For example, in some embodiments, waveguides can be formed in-situ in glass using low-temperature glass-to-glass bonding or by laser direct writing. In-situ formed waveguides can have lower loss characteristics.

[0041] The term "conductive trace" can be used to describe conductive elements isolated by insulating materials. Within an IC die, such insulating materials include interlayer low-k dielectrics provided within the IC die. Within packaging substrates and printed circuit boards (PCBs), such insulating materials include organic materials such as Ajinomoto laminate (ABF), polyimide, or epoxy resin. These traces are typically arranged in several levels or layers of metallized stacks.

[0042] The term "conductive via" can be used to describe a conductive element that interconnects two or more conductors at different levels of a metallization stack. For this purpose, vias can be provided that are substantially perpendicular to a plane of the IC die / chip or support structure, on which the IC structure is provided, and the vias can interconnect two conductors in adjacent levels or two conductors in non-adjacent levels.

[0043] The term "packaging substrate" can be used to describe any substrate material that facilitates the packaging of any assembly of semiconductor dies and / or other electrical components such as passive electrical components. As used herein, packaging substrates can be formed of any material, including but not limited to insulating materials such as resin-impregnated glass fibers (e.g., PCBs or printed wiring boards (PWB)), glass, ceramics, silicon, silicon carbide, etc. Additionally, as used herein, packaging substrate can refer to a substrate comprising stacked layers (e.g., ABF layers).

[0044] The term "metallization stack" can be used to refer to one or more interconnect stacks used to provide connectivity to different circuit components to IC dies / chips and / or package substrates.

[0045] As used in this article, the term "spacing" for interconnect refers to the center-to-center distance between adjacent interconnects.

[0046] In the context of stacked dies coupled to each other, or in the context of dies coupled to a package substrate, the term "interconnect" can also refer to DTD interconnects and die-to-package substrate (DTPS) interconnects, respectively. DTD interconnects can also be referred to as first-level interconnects (FLI). DTPS interconnects can also be referred to as second-level interconnects (SLI).

[0047] Although not specifically shown in all figures in this illustration to avoid confusion, when describing a DTD or DTPS interconnect, the surface of the first die may include a first set of conductive contacts, and the surface of the second die or package substrate may include a second set of conductive contacts. One or more conductive contacts in the first set can then be electrically and mechanically coupled to some conductive contacts in the second set via the DTD or DTPS interconnect.

[0048] In some embodiments, the spacing of the DTD interconnects may differ from the spacing of the DTPS interconnects, although in other embodiments these spacings may be substantially the same.

[0049] The DTPS interconnects disclosed herein can take any suitable form. In some embodiments, a set of DTPS interconnects may include solder (e.g., solder bumps or solder balls formed by heat reflow to create the DTPS interconnect). DTPS interconnects including solder may include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, a set of DTPS interconnects may include anisotropic conductive materials, such as anisotropic conductive films or anisotropic conductive pastes. Anisotropic conductive materials may include conductive materials dispersed within non-conductive materials. In some embodiments, anisotropic conductive materials may include microscopic conductive particles embedded in an adhesive or thermosetting adhesive film (e.g., thermosetting biphenyl-based epoxy resins or acrylic-based materials). In some embodiments, conductive particles may include polymers and / or one or more metals (e.g., nickel or gold). For example, conductive particles may include nickel-coated gold or silver-coated copper sequentially coated with a polymer. In another example, the conductive particles may include nickel. When the anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other. However, when the anisotropic conductive material is sufficiently compressed (e.g., through conductive contacts on either side of the anisotropic conductive material), the conductive material near the compressed region can come into contact with each other to form a conductive path from one side of the film to the other in the compressed region. In some embodiments, the interconnects 150 disclosed herein may have a spacing between approximately 18 micrometers and 75 micrometers.

[0050] The DTD interconnects disclosed herein can take any suitable form. In some embodiments, some or all of the DTD interconnects in a microelectronic assembly or IC package as described herein may be metal-to-metal interconnects (e.g., copper-to-copper interconnects or plated interconnects). In such embodiments, conductive contacts on either side of the DTD interconnect may be joined together (e.g., under elevated pressure and / or temperature) without the use of intervening solder or anisotropic conductive materials. In some metal-to-metal interconnects, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide) may be present between the joined metals (e.g., between copper pads or copper pillars providing associated conductive contacts). In some embodiments, one side of the DTD interconnect may include a metal pillar (e.g., a copper pillar), and the other side of the DTD interconnect may include a metal contact (e.g., a copper contact) recessed in a dielectric. In some embodiments, metal-to-metal interconnects (e.g., copper-to-copper interconnects) may include noble metals (e.g., gold) or their oxides that are conductive (e.g., silver). In some embodiments, metal-to-metal interconnects may include metal nanostructures (e.g., nanorods) that may have a reduced melting point. Metal-to-metal interconnects may be able to reliably conduct higher currents compared to other types of interconnects; for example, some solder interconnects may form brittle intermetallic compounds when current flows, and the maximum current provided by such interconnects may be limited to mitigate mechanical failure.

[0051] In some embodiments, the die on either side of a set of DTD interconnects may be a bare (e.g., unpackaged) die.

[0052] In some embodiments, DTD interconnects may include solder. For example, a DTD interconnect may include conductive bumps or pillars (e.g., copper bumps or copper pillars) attached to corresponding conductive contacts by solder. In some embodiments, a thin solder cap may be used in the metal-to-metal interconnect to accommodate planarity, and the solder may become an intermetallic compound during processing. In some embodiments, the solder used in some or all of the DTD interconnects may have a higher melting point than the solder included in some or all of the DTPS interconnects. For example, when forming DTD interconnects in an IC package prior to forming DTPS interconnects, solder-based DTD interconnects may use solder with a higher temperature (e.g., a melting point above 200 degrees Celsius), while DTPS interconnects may use solder with a lower temperature (e.g., a melting point below 200 degrees Celsius). In some embodiments, the higher-temperature solder may include tin; tin and gold; or tin, silver, and copper (e.g., 96.5% tin, 3% silver, and 0.5% copper). In some embodiments, the low-temperature solder may include tin and bismuth (e.g., eutectic tin-bismuth), tin, silver, bismuth, indium, indium and tin, or gallium.

[0053] In some embodiments, a set of DTD interconnects may include anisotropic conductive materials, such as any of the materials discussed above for DTPS interconnects. In some embodiments, DTD interconnects may be used as data transmission channels, while DTPS interconnects may be used as power lines and ground lines, etc.

[0054] In microelectronic assemblies or IC packages as described herein, some or all of the DTD interconnects can have finer pitch than DTPS interconnects. In some embodiments, depending on the type of DTD interconnect, the DTPS interconnects disclosed herein can have a pitch between about 80 micrometers and 300 micrometers, while the DTD interconnects disclosed herein can have a pitch between about 0.5 micrometers and 100 micrometers. Some DTD interconnect densities provide examples of silicon-level interconnect densities. In some embodiments, DTD interconnects may have a pitch too fine to be directly coupled to the package substrate (e.g., too fine to be used as DTPS interconnects). DTD interconnects can have a smaller pitch than DTPS interconnects because the materials in different dies on either side of a set of DTD interconnects are more similar than the materials between the die and the package substrate on either side of a set of DTPS interconnects. In particular, differences in the material composition of the die and the package substrate can cause different expansion and contraction of the die and the package substrate due to heat generated during operation (and heat applied during various manufacturing operations). To mitigate damage caused by these different expansions and contractions (e.g., cracking, solder bridging, etc.), any DTPS interconnect in a microelectronic assembly or IC package as described herein can be formed larger and more widely spaced than a DTD interconnect. Due to the greater material similarity of the die pairs on either side of the DTD interconnect, the DTD interconnect may experience less thermal stress.

[0055] It will be appreciated that one or more levels of underfill (e.g., organic polymer materials such as benzotriazole, imidazole, polyimide, or epoxy resin) can be provided in the IC packages described herein and may be left unlabeled to avoid confusing the figures. In various embodiments, each level of underfill may comprise the same or different insulating materials. In some embodiments, each level of underfill may comprise a thermosetting epoxy resin with silica particles; in some embodiments, each level of underfill may comprise any suitable material capable of performing underfill functions, such as supporting the die and reducing thermal stress on interconnects. In some embodiments, the selection of underfill material may be based on design considerations such as shape factor, size, stress, operating conditions, etc.; in other embodiments, the selection of underfill material may be based on material properties and processing conditions such as curing temperature, glass transition temperature, viscosity, and chemical resistance, among other factors; in some embodiments, the selection of underfill material may be based on both design and processing considerations.

[0056] In some embodiments, one or more levels of solder resist (e.g., epoxy liquid, liquid photoimageable polymer, dry film photoimageable polymer, acrylic resin, solvent) may be provided in the IC package described herein, and the one or more levels of solder resist may not be labeled or shown to avoid cluttering the diagram. The solder resist may be a liquid or dry film material comprising a photoimageable polymer. In some embodiments, the solder resist may be non-photoimageable.

[0057] The terms “substantially,” “near,” “approximately,” “near,” and “about” generally refer to a target value within + / -20% (e.g., within + / -5% or 10% of the target value) based on the context of a particular value as described herein or as known in the art.

[0058] Terms indicating the orientation of various elements (such as "coplanar", "perpendicular", "orthogonal", "parallel" or any other angle between elements) generally refer to the target value within + / - 5% to 20% based on the context of a particular value as described herein or as known in the art.

[0059] The term “connected” refers to a direct connection (which may be one or more of mechanical, electrical and / or thermal connections) between connected things without any intermediate means, while the term “coupled” refers to either a direct connection between connected things or an indirect connection through one or more passive or active intermediate means.

[0060] The description uses the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments.

[0061] Furthermore, the terms “comprising,” “including,” “having,” etc., as used in relation to embodiments of this disclosure are synonymous.

[0062] The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate discussion and are not intended to limit the application of the disclosed embodiments.

[0063] As used herein, the terms “above,” “below,” “between,” “at,” “adjacent,” and “on” refer to the relative position of a material layer or component with respect to other layers or components. For example, a layer placed above or below another layer may be in direct contact with the other layer or may have one or more intervening layers. Furthermore, a layer placed between two layers may be in direct contact with one or both of the two layers or may have one or more intervening layers. For example, a first solder material layer may be described as being in contact with a second solder material layer below, although one or more layers of other materials, such as intermetallic compounds, may be formed or present at the interface between the two solder material layers. Another example is an interface oxide layer or dielectric layer, etc., that appears between two contacting metal layers. Thus, as used herein, two structures such as two material layers may still be referred to as being in contact by being above, below, between, at, or adjacent, regardless of whether there are other structures between the two layers, such as one or more interface layers or other intermediate or intervening layers. Conversely, a first layer described as being “above” a second layer refers to the layer in direct contact with that second layer. Similarly, unless otherwise explicitly stated, a feature placed between two features may be in direct contact with the adjacent feature or may have one or more intervening layers.

[0064] As used herein, the term “setup” refers to placement, positioning, arrangement and / or arrangement, and not to any particular method of formation.

[0065] When used in relation to measurement range, the term "between" includes the endpoints of the measurement range.

[0066] For the purposes of this disclosure, the phrase "A and / or B" refers to (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" refers to (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). When used herein, the symbol "A / B / C" refers to (A), (B), and / or (C).

[0067] While certain elements may be referred to in the singular form herein, such elements may include multiple sub-elements. For example, "conductive material" may include one or more conductive materials. In another example, "dielectric material" may include one or more dielectric materials.

[0068] Unless otherwise stated, the use of ordinal adjectives such as “first,” “second,” and “third” to describe common objects merely indicates that different instances of similar objects are being mentioned and is not intended to imply that the objects described must be in a given sequence, either temporally, spatially, hierarchically, or in any other way.

[0069] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, and embodiments that may be practiced are illustrated by way of example in the drawings. It should be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be construed as limiting.

[0070] The accompanying drawings are not necessarily drawn to scale.

[0071] In the figures, the same reference numerals indicate the same or similar elements / materials, such that, unless otherwise stated, the interpretation of an element / material with a given reference numeral provided in the context of one of the figures applies to other figures in which elements / materials with the same reference numerals may be illustrated. Furthermore, the singular and plural forms of the reference numerals may be used together with the reference numerals to respectively denote single and multiple elements of the same or similar type, kind, or category.

[0072] Furthermore, the figures may include schematic illustrations of example structures of the various devices and assemblies described herein, using precise right angles and straight lines. However, it should be understood that such schematic illustrations may not reflect real-world manufacturing limitations, which may cause features to appear less than "ideal" when examined using images from suitable characterization tools, such as scanning electron microscopy (SEM) images, transmission electron microscopy (TEM) images, or non-contact profilometers. Possible processing and / or surface defects may also be visible in such images of real structures, such as surface roughness; curvature or profile deviations; pits or scratches; imperfectly straight edges of material; tapered through-holes or other openings; unintentional rounding of corners or variations in the thickness of different material layers; accidental spirals, edge or combination dislocations within (one or more) crystalline regions; and / or accidental dislocation defects of individual atoms or clusters of atoms. Other defects not listed herein but common in the field of device fabrication and / or packaging may also be present.

[0073] Note that in the figures, various components (e.g., interconnects) are shown aligned (e.g., at corresponding interfaces) merely for illustrative purposes; in reality, some or all of them may be misaligned. Additionally, other components present in the assembly, such as bonding pads, landing pads, metallization, etc., are not shown in the figures to avoid clutter. Furthermore, the figures are used to illustrate the relative arrangement of components within their assemblies, and typically, such assemblies may include other components not shown (e.g., various other components or interface layers related to optical functionality, electrical connectivity, or thermal mitigation). For example, in some other embodiments, the assemblies shown may include additional dies along with other electrical components. Additionally, while some components of the assembly are illustrated as planar rectangles or formed by cuboids in the figures, this is merely for illustrative purposes, and embodiments of these assemblies may be curved, circular, or otherwise irregularly shaped, as prescribed and sometimes unavoidable by the manufacturing processes used to produce the various components.

[0074] The figures show a specific number and arrangement of structures and components for illustrative purposes, and any desired number or arrangement of such structures and components may be shown in various embodiments.

[0075] Furthermore, unless otherwise stated, the structures shown in the figures may take any suitable form or shape depending on the material properties, manufacturing process, and operating conditions.

[0076] For convenience, if a collection of graphs is named with different letters (e.g.) Figures 2A-2D If a set of figures with different numbers or letters exists, such a set may be referred to in this document without the letter (e.g., as “Figure 2”). Similarly, if a set of figures with different numbers or letters exists (e.g., 104-1, 104-2, 104-3), such a set may be referred to in this document without the number or letter (e.g., as “104”).

[0077] Various operations can be described sequentially as a plurality of discrete actions or operations in a manner most conducive to understanding the claimed subject matter. However, the order of description should not be construed as implying that these operations must be sequentially related. In particular, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0078] Figure 1A is a schematic cross-sectional view of an example microelectronic assembly 100 according to some embodiments of the present disclosure. The microelectronic assembly 100 includes a plurality of layers 102 (e.g., 102-1, 102-2, and 102-3) and stacked dies 104 (e.g., 104-1, 104-2, and 104-3). Specifically, the microelectronic assembly 100 includes a first die 104-1 in a first layer 102-1; a second die 104-2 and a third die 104-3 in a second layer 102-2, the second die 104-2 and the third die 104-3 being surrounded by a dielectric material 108 and an HTC material 105 on the dielectric material 108 and on the second die 104-2 and the third die 104-3, the dielectric material 108 also referred to herein as a “gap filler material” having an inconsistent morphology 111 (e.g., a non-planar surface); and a substrate 112 in the third layer 102-3, also referred to herein as a “structural silicon cap”. The HTC material 105 may be formed into a planar surface for bonding to the substrate 112. The substrate 112 may include a structurally rigid and thermally conductive substrate, such as silicon, which may provide mechanical support and stability for the microelectronic assembly 100.

[0079] HTC material 105 may comprise any suitable material having a thermal conductivity equal to or greater than 10 W / mK, such as copper, aluminum, aluminum and nitrogen (e.g., in the form of aluminum nitride), diamond, silicon and carbon (e.g., in the form of silicon carbide), boron and nitrogen (e.g., in the form of boron nitride), and boron and arsenic (e.g., in the form of boron arsenide). HTC material 105 may have any suitable dimensions; for example, the thickness (e.g., z-dimensional) of HTC material 105 on the top surfaces of the second die 104-2 and the third die 1043 may be between 1 micrometer and 2 micrometers. Due to the inconsistent morphology 111, HTC material 105 may have a greater thickness on dielectric material 108, wherein dielectric material 108 may have one or more pits (e.g., voids or depressions) having a depth (e.g., z-dimensional) between 20 nanometers and 500 nanometers. The dielectric material 108 may include any suitable material, such as silicon and nitrogen (e.g., in the form of silicon nitride), silicon and oxygen (e.g., in the form of silicon oxide), or silicon, carbon, and nitrogen (e.g., in the form of silicon carbon nitride); polymeric materials (e.g., epoxy resin or polyimide); mold materials; or low-k or ultra-low-k dielectrics. The dielectric material 108 may be formed using any suitable process, including chemical vapor deposition (CVD), physical vapor deposition (PVD), lamination, or slot coating and curing.

[0080] The microelectronic assembly 100 may further include a bonding layer 107 for bonding the substrate 112 of the third layer 102-3 to the HTC material 105 of the second layer 102-2. The bonding layer 107 may comprise any suitable material; for example, the material of the bonding layer 107 may include one or more of titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, and silicon, carbon, and nitrogen. The bonding layer 107 may have any suitable dimensions; for example, the thickness of the bonding layer 107 (e.g., z-dimension) may be between 0.2 nanometers and 100 nanometers. Bonding materials may be deposited on the bonding surfaces of the substrate 112 and the HTC material 105, and then bonded together to form the bonding layer 107, as described below with reference to FIG3.

[0081] The microelectronic assembly 100 may further include pads 103-1 between the dielectric material 108 and the top surfaces of the IC dies 104-2 and 104-3, and between the dielectric material 108 and the HTC material 105. The microelectronic assembly may also include pads 103-2 between the bonding layer 107 and the substrate 112. Pads 103-1 may serve as diffusion barrier layers to prevent the HTC material 105 from migrating into the dielectric material 108 and into the materials of the second die 104-2 and the third die 104-3. Pads 103-2 may serve as diffusion barrier layers to prevent the material of the bonding layer 107 from migrating into the material of the substrate 112. Pads 103 (e.g., pads 103-1, 103-2) may include any suitable material, including, for example, one or more of titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, ruthenium, and tungsten. The pad 103 can have any suitable size; for example, the pad 103 can have a thickness between 1 nanometer and 50 nanometers.

[0082] The first die 104-1 may include a first surface 170-1 (e.g., a bottom surface) and an opposing second surface 170-2 (e.g., a top surface). The second die 104-2 and the third die 104-3 may be coupled to the second surface 170-2 of the first die 104-1 via interconnects 106. In various embodiments, the interconnects 106 may have a spacing of less than 10 micrometers between adjacent interconnects. In some embodiments, examples of interconnects 106 are hybrid bonding, including metal-metal and dielectric-dielectric bonding.

[0083] Figure 1B is a schematic cross-sectional view showing details of a specific interconnect in interconnect 106 of the microelectronic assembly 100. Note that although only interconnect 106 is shown, the same structure and description may be applied to any other such interconnect in the microelectronic assembly 100 that includes hybrid bonding, where applicable. In a general sense, at the interface 130 between layers 102-1 and 102-2, interconnect 106 may include a metal-metal bond between bonding pads 132 of layer 102-1 and bonding pads 134 of layer 102-2, and a dielectric-dielectric bond (e.g., oxide-oxide bond) in the dielectric materials 109 of layers 102-1 and 102-2. Bonding pads 132 of layer 102-1 may bond to bonding pads 134 of layer 102-2. Dielectric materials 109 in layers 102-1 and 102-2 (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.) may bond to each other. In some embodiments, dielectric material 109 may be the same material as dielectric material 108. The bonded metal and dielectric materials form interconnects 106, including hybrid bonding, thereby providing electrical and mechanical coupling between layers 102-1 and 102-2. In various embodiments, interconnects 106 may have linear dimensions of less than 5 micrometers and spacing of less than 10 micrometers between adjacent interconnects.

[0084] Return to Figure 1A. The die 104 disclosed herein may include an insulating material (e.g., a dielectric material formed in multiple layers as known in the art) and multiple conductive pathways (not shown) formed through the insulating material. In some embodiments, the insulating material of the die 104 may include a dielectric material such as silicon oxide, silicon nitride, oxide oxynitride, polyimide material, glass-reinforced epoxy matrix material, or low-k or ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, organic polymer dielectric, photo-imaging dielectric, and / or benzocyclobutene-based polymer). In some embodiments, the insulating material of the die 104 may include a semiconductor material (such as silicon, germanium, or group III-V materials (e.g., gallium nitride)) and one or more additional materials. For example, the insulating material may include silicon oxide or silicon nitride. The conductive pathways in the die 104 may include conductive traces, conductive vias, and / or TSVs, and may connect any conductive contacts in the conductive contacts of the die 104 in any suitable manner (e.g., connecting multiple conductive contacts on the same or different surfaces of the die 104). Conductive pathways in die 104 may be bounded by padding materials, such as suitable adhesive pads and / or barrier pads. In some embodiments, the first die 104-1 is a wafer. In some embodiments, die 104 is a monolithic silicon, fan-out or fan-in packaged die, or die stack (e.g., wafer stack, die stack, or multilayer die stack). In various embodiments, die 104 may include one or more of, or a portion of, one or more of, the following: a central processing unit (CPU), a memory device (e.g., a high-bandwidth memory device), logic circuitry, an input / output circuit module, a transceiver such as a field-programmable gate array transceiver, gate array logic such as field-programmable gate array logic in a power delivery circuit module, a III-V or III-N device such as a III-N or III-N amplifier (e.g., a GaN amplifier), a fast peripheral component interconnect (PCIe) circuit module, a double data rate (DDR) transmission circuit module, or other electronic components known in the art. In some embodiments, the second die 104-2 and the third die 104-3 may include different functionalities. As used herein, the term "functionality" with respect to a die refers to one or more functions (e.g., capabilities, tasks, operations, actions, instruction execution, etc.) that the die in question can perform. In other embodiments, the second die 104-2 and the third die 104-3 may include the same or similar functionalities. In some embodiments, the first die 104-1 may be configured to carry power, signal, and / or ground connections between the package substrate 118 and the second die 104-2 and the third die 104-3.In various embodiments, one or more dies 104 in the microelectronic assembly 100 may include different kinds of conductive traces, such as conductive traces configured to carry power and conductive traces configured to carry signals, which have different dimensions (e.g., conductive traces configured to carry power may typically be larger (e.g., thicker, wider) than conductive traces configured to carry signals).

[0085] In some embodiments, the microelectronic assembly 100 may include a second die 104-2 and a third die 104-3, wherein the sidewalls have increased surface roughness and / or a scallop surface 802 or a protective coating material 804, as referenced below. Figure 8A and Figure 8B As stated above.

[0086] The microelectronic assembly 100 may further include a packaging substrate 118 having conductive pathways (not shown) through a dielectric material. The conductive pathways may include conductive traces coupled by conductive vias. The packaging substrate 118 may also include bonding pads, redistribution layers, substrate dies, passive components, and other components not shown for illustrative purposes only and not as a limitation. The packaging substrate 118 may be coupled to a first surface 170-1 of a first die 104-1 via interconnects 142 (e.g., DTPS interconnects, such as flip-chip solder bonding). In various embodiments, the interconnects 142 may have a spacing greater than 10 micrometers between adjacent interconnects. An underfill material 127 may be disposed around the interconnects 142. The underfill process may include dispensing the underfill material in liquid form to allow material flow and fill the gaps around the interconnects 142, and subjecting the assembly to a curing process such as baking to cure the material.

[0087] Figure 2A This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 1 Configuration A. The configuration of the microelectronic assembly 100 as described herein also includes patterned HTC material 105, rather than a blanket of HTC material 105 (e.g., as shown in the image). Figure 1(As shown in Figure A). Patterned HTC material 105 may be present on the top surfaces of the second die 104-2 and the third die 104-3, and may extend partially beyond the top surfaces of the second die 104-2 and the third die 104-3. Patterned HTC material allows for electrical coupling between components (e.g., as described below with reference to Figure 7) and allows for easier separation. If multiple assemblies are manufactured together and separation is required, separation between the second die 104-2 and the third die 104-3 is more easily performed using dielectric material 108 without having to cut through HTC material 105, which may increase stress and potentially lead to delamination in the microelectronic assembly. If the microelectronic assembly 100 includes a pad 103-1, the pad 103-1 may also be patterned.

[0088] Figure 2B This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 1Configuration A. The configuration of the microelectronic assembly 100 as described herein includes four layers (e.g., 102-1, 102-2, 102-3, 102-4), with a bonding layer 107A between the second layer 102-2 and the third layer 102-3, and a bonding layer 107B between the third layer 102-3 and the fourth layer 102-4. Specifically, the third layer 102-3 includes a fourth die 104-4 and a fifth die 104-5 surrounded by a dielectric material 108 having an inconsistent morphology 111 (e.g., a non-planar surface), and an HTC material 105 on the dielectric material 108 and on the fourth die 104-4 and the fifth die 104-5. The conductive contact 224 on the top surface of the second die 104-2 can be electrically coupled to the conductive contact 226 on the bottom surface of the fourth die 104-4 through the conductive via 110, and the conductive contact 224 on the top surface of the third die 104-3 can be electrically coupled to the conductive contact 226 on the bottom surface of the fifth die 104-5 through the conductive via 110. The conductive via 110 can extend through the HTC material 105 and the bonding layer 107A, and through the pad 103 (not shown) if the pad 103 is included in the microelectronic assembly 100. The conductive via 110 can be formed of any suitable conductive material, such as, for example, copper, silver, nickel, gold, aluminum, or other metals or alloys. In some embodiments, the conductive via 110 can be bounded by an insulating material, such as an inorganic dielectric comprising silicon, oxygen, nitrogen, and / or carbon, which isolates the conductive material of the conductive via 110 from the HTC material 105, the bonding layer 107A, and / or the pad 103. The microelectronic assembly 100 may further include a fourth layer 102-4 on top of the third layer 102-3, and the fourth layer 102-4 includes a substrate 112 of HTC material 105 coupled to the third layer 102-3 via a bonding layer 107. The materials of the bonding layers 107A and 107B may include any suitable materials, including those referenced above. Figure 1 The material described in bonding layer 107 of A.

[0089] Figure 2C This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 1Configuration A. The configuration of the microelectronic assembly 100 as described herein also includes a conductive via 210 through a dielectric material 108. The conductive via 210 may be formed of any suitable conductive material, such as, for example, copper, silver, nickel, gold, aluminum, or other metals or alloys, and may be formed of the same material as HTC material 105. A first end of the conductive via 210 may be electrically coupled to a conductive contact 228 at a second surface 170-2 of the first die 104-1, and the opposite second end of the conductive via 210 may be electrically coupled to HTC material 105. The conductive via 210 may provide another heat transfer path in the microelectronic assembly 100. In some embodiments, the conductive via 210 has a spacing between 10 micrometers and 500 micrometers.

[0090] Figure 2D This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 1 Configuration A. The configuration of the microelectronic assembly 100 as described herein also includes a plurality of first dies 104-1 in a first layer 102-1, and further includes a conductive via 210 extending through a dielectric material 108 between a package substrate 118 and an HTC material 105. Specifically, a first end of the conductive via 210 may be electrically coupled to the package substrate 118 via an interconnect 142, and a opposite second end of the conductive via 210 may be electrically coupled to the HTC material 105.

[0091] Any suitable technology can be used to manufacture the microelectronic assembly 100 disclosed herein. For example, Figures 3A-3F It is for manufacturing according to various embodiments Figure 1 Side cross-sectional views of various stages in an example process of microelectronic assembly 100 of A. Although illustrated in a specific order, see below for reference. Figures 3A-3F The operations discussed herein (and other figures in the accompanying drawings representing the manufacturing process) are subject to these descriptions, but may be performed in any suitable order. Furthermore, additional operations not shown may be performed without departing from the scope of this disclosure. Moreover, modifications may be made to the descriptions herein based on this disclosure. Figures 3A-3F The various operations discussed are used to create other things from the microelectronic assembly 100 disclosed herein.

[0092] Figure 3AThe illustration shows an assembly after the second die 104-2 and the third die 104-3 are electrically coupled to the first die 104-1 by forming an interconnect 106, depositing dielectric material 108 on and around the second die 104-2 and the third die 104-3, and planarizing the top surface of the assembly to remove the dielectric material above the IC die. The second die 104-2 and the third die 104-3 can be positioned using any suitable method, such as automated pick-and-place. Figure 3A The assembly can undergo appropriate bonding processes to form interconnects 106. For example, the bonding process may include applying appropriate pressure and heating to a suitable temperature (e.g., to a moderately high temperature) for a period of time. The dielectric material 108 can be deposited using any suitable technique, such as CVD, PVD, or PECVD. The top surface of the assembly can be planarized to remove the dielectric 108 using any suitable technique, such as grinding or etching, followed by chemical mechanical polishing (CMP). The planarization process can expose the top surfaces of the second die 104-2 and the third die 104-3 and can form an inconsistent morphology 111 on the top surface of the dielectric material 108. In some embodiments, the inconsistent morphology 111 on the top surface of the dielectric material 108 may include voids with depth (e.g., z-dimensional), as referenced above. Figure 1 As described in A. In some embodiments, the first die 104-1 may include a plurality of first dies on a carrier (not shown), and the second die 104-2 and the third die 104-3 are electrically coupled via interconnect 106 to form a structure similar to Figure 2D After the microelectronic assembly, dielectric material 108 can be deposited on and around multiple first dies.

[0093] Figure 3B The illustration shows that in Figure 3A The liner 103-1 is deposited on the top surface of the assembly after the assembly is assembled. The liner 103-1 may include any suitable material, as referenced above. Figure 1 As described above, and can be formed using any suitable process, including PVD, atomic layer deposition (ALD), or CVD. The pad 103-1 can have any suitable dimensions, as referenced above. Figure 1 As described in A. In some embodiments, a through-hole opening may be formed through the dielectric material 108 to expose conductive contacts (e.g., conductive contacts 228, such as) on the surface of the first die 104-1 prior to the deposition pad 103-1. Figure 2C (As shown in the diagram). Any suitable technique, such as laser drilling or etching, can be used to form the via opening. Pad 103-1 can be deposited on the dielectric material 108 and in the via opening, and then a conductive material can be deposited in the via opening to form a conductive via (e.g., conductive via 210, as shown in the diagram). Figure 2C and / or Figure 2D (As shown in the image). The conductive material can be deposited using any suitable technique, such as electroplating, PVD, or CVD, and can include any suitable material as referenced above. Figure 1 As described in A. In some embodiments, conductive vias 210 may be formed when HTC material 105 is deposited to fill via openings and cover the top surface of the assembly.

[0094] Figure 3C The illustration shows that in Figure 3B The assembly is formed by depositing HTC material 105 on the top surface of the assembly. HTC material 105 may include any suitable material, as referenced above. Figure 1 As described in A, and can be formed using any suitable process, including electroplating, PVD, or CVD. HTC material 105 can be deposited to have a greater thickness (e.g., between 2 and 5 micrometers) and can be planarized to a thickness between 1 and 2 micrometers above the top surfaces of the second die 104-2 and the third die 104-3. Any suitable technique can be used to remove HTC material 105, such as grinding and / or CMP. Pad 103 and HTC material 105 can be deposited to completely cover the top surface of the assembly (e.g., full-surface overlay deposition), and then, using any suitable technique (e.g., etching), pad 103 and HTC material 105 can be selectively removed to form a pattern (e.g., as shown in the image). Figure 2A (as shown in the image).

[0095] Figure 3D The illustration shows that in Figure 3C The bonding layer 107-1 is formed on the top surface of the assembly after the assembly is assembled. The bonding layer 107-1 can be deposited using any suitable technique, such as electroplating, PVD, or CVD, and can include any suitable material, as referenced above. Figure 1 As described in A, the bonding layer 107-1 can be deposited to have any suitable size, including, for example, a thickness between 0.1 nanometers and 50 nanometers. In some embodiments, for example, when manufacturing... Figure 2B When constructing the microelectronic assembly 100, via openings can be formed through the bonding layer 107-1, HTC material 105, and pad 103 (if included) to expose conductive contacts 224 on the top surfaces of the second die 104-2 and the third die 104-3. Insulating material can be deposited in the via openings, and subsequently, conductive material can be deposited in the via openings to form a conductive via 110. A fourth die 104-4 and a fifth die 104-5 can be attached to the bonding layer 107-1, and conductive contacts 226 on the bottom surfaces of the fourth die 104-4 and the fifth die 104-5 can be electrically coupled to the conductive via 110. As described above... Figure 3AAs described in the reference to the dielectric material 108 surrounding the second die 104-2 and the third die 104-3, the dielectric material 108 may be deposited on and around the fourth die 104-4 and the fifth die 104-5 and planarized.

[0096] Figure 3E The diagram illustrates the formation of a bonding layer 107-2 on a substrate 112 and the bonding layer 107-2 on the substrate 112 with... Figure 3D The bonding layer 107-1 of the assembly is aligned with the subsequent assembly. The bonding layer 107-2 can be deposited using any suitable technique, such as electroplating, PVD, CVD, ALD, or ion beam deposition (IBD), and can include any suitable material as referenced above. Figure 1 As described in A. Substrate 112 may include any suitable material for providing mechanical stability during manufacturing operations and use, and in some embodiments, may include silicon. Bonding layer 107-2 may be deposited to have any suitable size, including, for example, a thickness between 0.1 nanometers and 50 nanometers. In some embodiments, pad 103-2 may be deposited on substrate 112 prior to depositing bonding layer 107-2. Pad 103-2 may use materials including those referenced above. Figure 3B Any suitable technique described above for deposition, and may include the above references. Figure 1 Any suitable material as described in A.

[0097] Figure 3F The illustration shows an assembly after a substrate 112 is attached to HTC material 105 by coupling bonding layers 107-1 and 107-2 together to form bonding layer 107. Bonding layers 107-1 and 107-2 can be bonded together using any suitable technique, such as by heating, atmospheric bonding, surface activation bonding, diffusion bonding, or thermocompression bonding. If multiple assemblies are manufactured together, the assemblies can be divided. As shown in the figure, Figure 3F The assembly itself can be a microelectronic assembly 100. It can be used for... Figure 3F The microelectronic assembly 100 undergoes further manufacturing operations to form other microelectronic assemblies 100; for example, similar to Figure 1 In the microelectronic assembly 100 of A, solder can be applied to conductive contacts on the bottom surface of the first die 104-1 and used to connect via interconnect 142. Figure 3F The microelectronic assembly 100 is coupled to the packaging substrate 118.

[0098] Figure 4A This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 1Configuration A. The configuration of the microelectronic assembly 100 as described herein includes four layers (e.g., 102-1, 102-2, 102-3, 102-4), with a bonding layer 107A between the second layer 102-2 and the third layer 102-3, and a bonding layer 107B between the third layer 102-3 and the fourth layer 102-4. Specifically, the third layer 102-3 includes a second HTC material 105-2, which can be used as a heat sink. The second HTC material 105-2 of the third layer 102-3 can be bonded to the first HTC material 105-1 of the second layer 102-2 via the bonding layer 107A. The first HTC material 105-1 may include any suitable material and may have any suitable dimensions, as referenced above. Figure 1 The HTC material 105 described in A. The second HTC material 105-2 may comprise any suitable material and may have any suitable size. In some embodiments, the second HTC material 105-2 may comprise any suitable material having a thermal conductivity equal to or greater than 150 W / mK, such as copper, aluminum, aluminum and nitrogen (e.g., in the form of aluminum nitride), diamond, silicon and carbon (e.g., in the form of silicon carbide), boron and nitrogen (e.g., in the form of boron nitride), boron and arsenic (e.g., in the form of boron arsenide), silver, or gold, and may have a thickness between 1 micrometer and 200 micrometers (e.g., z-dimensionality). In some embodiments, the second HTC material 105-2 may be a single-crystal layer epitaxially grown on a carrier such as a silicon wafer and subsequently attached to the first HTC material 105-1 via a bonding layer 107A. In some such embodiments, the second HTC material 105-2 can be deposited on a silicon wafer using any high deposition temperature technique (such as PECVD or low-pressure chemical vapor deposition (LPCVD)) at a temperature range between 500°C and 1000°C, and epitaxially grown to have a crystal structure matching the 111 crystal structure of the silicon material on the wafer. The microelectronic assembly 100 may also include a fourth layer 102-4 on top of the third layer 1023, and the fourth layer 102-4 may include a substrate 112 of the second HTC material 105-2 coupled to the third layer 102-3 via a bonding layer 107B. The materials of the bonding layers 107A, 107B may include any suitable materials, including those referenced above. Figure 1 The bonding layer 107 in A describes the material. In some embodiments, for example, when the second HTC material 105-2 is epitaxially grown on the silicon substrate 112, the bonding layer 107B and the pad 103 between the second HTC material 105-2 and the substrate 112 may be omitted (e.g., as shown in Figure 107). Figure 4F (as shown in the image).

[0099] Figure 4BThis is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 2B The configuration of the microelectronic assembly 100 as described herein includes six layers (e.g., 102-1, 102-2, 102-3, 102-4, 102-5, 102-6), a bonding layer 107A between the second layer 102-2 and the third layer 102-3, a bonding layer 107B between the third layer 102-3 and the fourth layer 102-4, a bonding layer 107C between the fourth layer 102-4 and the fifth layer 102-5, and a bonding layer 107D between the fifth layer 102-5 and the sixth layer 102-6. Specifically, the fourth layer 102-4 includes a fourth die 104-4 and a fifth die 104-5 surrounded by a dielectric material 108 having an inconsistent morphology 111, a pad 103, and a first HTC material 105-1, and the third layer 102-3 and the fifth layer 102-5 include a second HTC material 105-2 that can be used as a heat sink. Conductive contacts 224 on the top surface of the second die 104-2 can be electrically coupled to conductive contacts 226 on the bottom surface of the fourth die 104-4 through conductive vias 110, and conductive contacts 224 on the top surface of the third die 104-3 can be electrically coupled to conductive contacts 226 on the bottom surface of the fifth die 104-5 through conductive vias 110. The conductive vias 110 can extend through the first HTC material 105-1, bonding layer 107A, the second HTC material 105-2, and bonding layer 107B. The conductive via 110 can be formed of any suitable conductive material, such as, for example, copper, silver, nickel, gold, aluminum, or other metals or alloys. The conductive via 110 can be bounded by an insulating material to isolate it from the pad 103, the first HTC material 105-1 and the second HTC material 105-2, and the bonding layers 107A and 107B. The insulating material can include any suitable material, for example, as referenced above. Figure 2B As described above, the microelectronic assembly 100 may further include a sixth layer 102-6 on the fifth layer 102-5, and the sixth layer 102-6 may include a substrate 112 of a second HTC material 105-2 coupled to the fifth layer 102-5 via a bonding layer 107D. The materials of the bonding layers 107A, 107B, 107C, and 107D may include any suitable materials, including those referenced above. Figure 1 The material described in bonding layer 107 of A.

[0100] Figure 4C This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 4AThe configuration of the microelectronic assembly 100 as described herein includes five layers (e.g., 102-1, 102-2, 102-3, 102-4, 102-5), with a bonding layer 107A between the second layer 102-2 and the third layer 102-3, a bonding layer 107B between the third layer 102-3 and the fourth layer 102-4, and a bonding layer 107C between the fourth layer 102-4 and the fifth layer 102-5. Specifically, the second layer 102-2 includes a second die 104-2, and the third layer 102-3 includes a patterned second HTC material 105-2, which is bonded over the second die 104-2 to a first HTC material 105-1 in the second layer 102-2 via the bonding layer 107A. Bonding layer 107A may include a first bonding layer 107A-1 on the top surface of a first HTC material 105-1 bonded together, and a second bonding layer 107A-2 on the bottom surface of a second HTC material 105-2 bonded together. The patterned second HTC material 105-2 may be surrounded by a dielectric material 108 having an inconsistent morphology 111. Third layer 102-3 may also include the first HTC material 105-1 on a pad 103 (if included) and on the first dielectric material 108. A fourth layer 102-4 including the second HTC material 105-2 may be bonded to the first HTC material 105-1 of the third layer 102-3 via bonding layer 107B. The patterned second HTC material 105-2 in the third layer 102-3 and the second HTC material 105-2 in the fourth layer can be used as a heat sink. The patterned HTC material 105-2 can be used to transfer heat from the second die 104-2 in the second layer 102-2, which can be a high-power die that generates a high level of heat. The second HTC material 105-2 can be patterned using any suitable technique, including those referenced above. Figure 3C The described technology. In some embodiments, the second HTC material 105-2 may be reconstructed and patterned on a carrier and subsequently attached to the second layer 102-2 via bonding layer 107A. The second HTC material 105-2 may be attached to the carrier and released for bonding via an infrared (IR) release film. The microelectronic assembly 100 may also include a fourth layer 102-4 and a fifth layer 102-5, the fourth layer 102-4 having a second HTC material 105-2 bonded to the first HTC material 105-1 of the third layer 102-3 via bonding layer 107B, and the fifth layer 102-5 having a substrate 112 bonded to the second HTC material 105-2 of the fourth layer 102-4 via bonding layer 107C. The materials of bonding layers 107A, 107B, and 107C may include any suitable materials, including those referenced above. Figure 1 The material described in bonding layer 107 of A.

[0101] Figure 4D The image includes an enlarged portion of the patterned second HTC material 105-2 in the third layer 102-3, showing the second HTC material 105-2 having a surface roughness 123 greater than or equal to 5 nanometers (e.g., between 5 nanometers and 150 nanometers) and a planarization material 125 between the second HTC material 105-2 and the bonding layer 107A. The planarization material 125 may include any suitable material, such as copper or aluminum, used to planarize the surface of the second HTC material 105-2 for forming the bonding layer 107A-2 on the bottom surface of the second HTC material 105-2.

[0102] Figure 4E This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 4C The configuration of the microelectronic assembly 100 as described herein includes five layers (e.g., 102-1, 102-2, 102-3, 102-4, 102-5), with a bonding layer 107A between the second layer 102-2 and the third layer 102-3, a bonding layer 107B between the third layer 102-3 and the fourth layer 102-4, and a bonding layer 107C between the fourth layer 102-4 and the fifth layer 102-5. Specifically, the third layer 102-3 also includes a fourth die 104-4, which is adjacent to a patterned second HTC material 105-2 surrounded by a dielectric material 108 and electrically coupled to the first die 104-1 through a conductive via 410. The conductive via 410 may extend through the dielectric material 108 of the second layer 102-2, the first HTC material 105-1, and the bonding layer 107A, and may be electrically coupled to conductive contacts 426 on the bottom surface of the fourth die 104-4 and conductive contacts 428 on the top surface of the first die 104-1. The conductive via 410 may be formed of any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys. The conductive via 410 may be bounded by an insulating material to isolate it from the pad 103, the first HTC material 105-1, and the bonding layer 107A. The insulating material may include, for example, as referenced above. Figure 2B Any suitable material as described.

[0103] Figure 4F This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 4CThe configuration of the microelectronic assembly 100 as described herein includes four layers (e.g., 102-1, 102-2, 102-3, 102-4), with a bonding layer 107A between the second layer 102-2 and the third layer 102-3, and a bonding layer 107B between the third layer 102-3 and the fourth layer 102-4. Specifically, the second layer 102-2 may include a second die 104-2 as a high-heat-generating die and a third die 104-3 as a low-heat-generating die, and the third layer 102-3 may include a second HTC material 105-2 patterned on the second die 104-2 but not on the third die 104-3. The second HTC material 105-2 can be used as a heat sink to transfer the heat generated by the second die 104-2. The fourth layer 102-4 may include a substrate 112 and a second HTC material 105-2, the second HTC material 105-2 being epitaxially grown on the substrate 112 (e.g., as referenced above). Figure 4A (as described), and then attached to the third layer 102-3 via bonding layer 107B.

[0104] Figure 5A This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 1Configuration A. The configuration of the microelectronic assembly 100 as described herein also includes microchannels 524 through the substrate 112 for transferring heat away from the second die 104-2 and the third die 104-3 in the second layer 102-2. The microelectronic assembly 100 may also include a system for circulating fluid (also referred to herein as “cooling fluid”) through the microchannels 524. The microchannels 524 may include inlets and outlets 523 for circulating the fluid. The fluid may be circulated through the fluid passage 541 using a pump or fan 542, which may be a stand-alone device (e.g., as shown) or may be part of a cooling device 543. The microelectronic assembly 100 may also include conduits or connections to a heat exchanger, cooler, or other means (not shown) for cooling the fluid before returning it to the microchannels 524 of the substrate 112. The fluid can be any suitable liquid, gas, or liquid / gas mixture, such as a coolant (e.g., water, fluorinated liquid, silicone oil, water glycol, polyalphaolefin, or silicate) or a vapor of a liquid coolant (including water and fluorocarbons), which can typically be circulated by a pump to dissipate heat more efficiently from the second wick 104-2 and / or the third wick 104-3. The fluid may also include additives to prevent corrosion of different components or to allow operation at higher / lower temperatures (e.g., additives for water to lower its freezing point or raise its boiling point). The coolant used may depend on its properties, including viscosity and heat capacity, circulation rate, and temperature rise during device operation. In some embodiments, the fluid can be an electronic coolant liquid or a dielectric fluid that is electrically insulating, highly thermally stable, non-toxic, chemically inert, non-corrosive, and has high thermal conductivity. Dielectric fluids may include dielectric materials in a liquid state. For example, the fluid may be an ultra-low viscosity dielectric heat transfer fluid comprising synthetic hydrocarbon oils. In some embodiments, the fluid may not contain sulfur. In some embodiments, the fluid may include transformer oil, perfluoroalkane, and purified water.

[0105] Figure 5B This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 1Configuration A. The microelectronic assembly 100, as described herein, comprises four layers (e.g., 102-1, 102-2, 102-3, 102-4), with a bonding layer 107A between the second layer 102-2 and the third layer 102-3, and a bonding layer 107B between the third layer 102-3 and the fourth layer 102-4. Specifically, the fourth layer 102-4 includes a second substrate 112B having microchannels 524 for transferring heat away from the second die 104-2 and the third die 104-3 in the second layer 102-2, the fourth layer 102-4 being bonded to the first substrate 112A in the third layer via the bonding layer 107B. The substrate 112 with microchannels 524 may also include the above-referenced... Figure 5A Any element described.

[0106] Figure 5C This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 5A The configuration of the microelectronic assembly 100 described herein includes three layers (e.g., 102-1, 102-2, 102-3), with a bonding layer 107 between the second layer 102-2 and the third layer 102-3. Specifically, the third layer 102-3 includes a substrate 112C with microchannels 524 located only above the second die 104-2, the microchannels 524 being used to transfer heat away from the second die 104-2. The substrate 112C with microchannels 524 may also include the components referenced above. Figure 5A Any element described.

[0107] Figure 5D This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 2B The configuration of the microelectronic assembly 100 described herein includes five layers (e.g., 102-1, 102-2, 102-3, 102-4, 102-5), with a bonding layer 107A between the second layer 102-2 and the third layer 102-3, a bonding layer 107B between the third layer 102-3 and the fourth layer 102-4, and a bonding layer 107C between the fourth layer 102-4 and the fifth layer 102-5. Specifically, the third layer 102-3 includes a substrate 112A having microchannels 524 for transferring heat away from the second die 104-2 and the third die 104-3. The substrate 112B having microchannels 524 may also include the above-referenced... Figure 5AAny element described herein. In some embodiments, the substrate 112A having microchannel 524 may include inputs and outputs 523 extending at least partially through the first die 104-1 to a side surface, as shown. In some embodiments, the inputs and outputs 523 may extend through the first die 104-1 to a bottom surface (not shown). Conductive contacts 224 on the top surface of the second die 104-2 may be electrically coupled to conductive contacts 226 on the bottom surface of the fourth die 104-4 via conductive vias 110, and conductive contacts 224 on the top surface of the third die 104-3 may be electrically coupled to conductive contacts 226 on the bottom surface of the fifth die 104-5 via conductive vias 110. Conductive vias 110 may extend through the pad 103 (if included) and the HTC material 105, bonding layer 107A, first substrate 112A, and bonding layer 107B in the second layer 102-2. The conductive via 110 can be formed of any suitable conductive material, such as, for example, copper, silver, nickel, gold, aluminum, or other metals or alloys. The conductive via 110 can be bounded by an insulating material, such as the one referenced above. Figure 2B As described, the insulating material isolates the conductive material of the conductive via 110 from the HTC material 105, bonding layers 107A, 107B, and the first substrate 112A. The microelectronic assembly 100 may also include a fifth layer 102-5 on top of the fourth layer 102-4, and the fifth layer 102-5 may include the substrate 112B of the HTC material 105 coupled to the fourth layer 102-4 via bonding layer 107C. The materials of bonding layers 107A, 107B, and 107C may include any suitable materials, including those referenced above. Figure 1 The material described in bonding layer 107 of A.

[0108] Figure 6A This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 1Configuration A. The configuration of the microelectronic assembly 100 as described herein also includes virtual dies 114-1, 114-2 adjacent to the second die 104-2 and the third die 104-3 in the second layer 102-2. Specifically, the bottom surfaces of the virtual dies 114-1, 114-2 can be electrically coupled to the first die 104-1 via bonding layer 107A, and the top surfaces of the virtual dies 114-1, 114-2 can be electrically coupled to HTC material 105 and pad 103 (if included). As used herein, the terms "virtual die," "virtual silicon," or "non-functional die" refer to a structure that is similar in size and shape to a die but does not have an active integrated circuit module (unlike a die). For non-limiting examples, virtual dies may have some features found on dies, such as bonding pads (e.g., for forming interconnect 106, as shown). Figure 6D (as shown in the diagram), but does not include transistor circuit modules capable of being energized or processing signals. The virtual die 114 may include any suitable structurally rigid bulk material that can provide mechanical support and stability to the microelectronic assembly 100. The virtual die 114 may include thermally conductive materials such as silicon, silicon and carbon (e.g., in the form of silicon carbide), gallium and nitrogen (e.g., in the form of gallium nitride), boron and nitrogen (e.g., in the form of hexagonal boron nitride), or diamond, which can enhance heat transfer in the microelectronic assembly 100. Figure 6A As shown, the virtual die 114 can be electrically coupled to the first die 104-1 via a cross-interface metal-to-metal bond (e.g., using a bonding layer 107). The bonding layer 107 can be achieved by bonding a layer (e.g., similar to...) on the top surface of the first die 104-1. Figure 3E The bonding layers on the bottom surfaces of the bonding layer 107-1 in the middle and the virtual dies 114-1, 114-2 (e.g., similar to the bonding layers on the bottom surfaces of the bonding layer 107-1 in the middle and the bonding layers on the bottom surfaces of the virtual dies 114-1, 114-2) Figure 3E The virtual die 114 is formed by coupling with a bonding layer 107-2. In some embodiments, the virtual die 114 may include a silicon wafer diced to be mounted adjacent to the second die 104-2 and the third die 104-3 along the edge or perimeter of the first die 104-1. The virtual die 114 may have any suitable size. In some embodiments, the virtual die 114, as well as the second die 104-2 and the third die 104-3, may have the same total thickness (e.g., z-dimension 193). In some embodiments, the virtual die 114 may have a surface area between 1 mm x 1 mm and 26 mm x 33 mm (e.g., xy-dimension).

[0109] Figure 6B This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 6A The configuration of the microelectronic assembly 100 as described herein includes virtual dies 114-1, 114-2 electrically coupled to the first die 104-1 via bonding layers 107A on the bottom surfaces of virtual dies 114-1, 114-2 to conductive contacts 146 on the top surface of the first die 104-1. Specifically, the conductive contacts 146 on the top surface of the first die 104-1 may have different densities. For example, the conductive contacts 146-1 may have a defined spacing and may cover a surface area substantially the same as the surface area of ​​the virtual die 114-1, with spacing between the individual conductive contacts 146-1. For example, in some embodiments, the conductive contacts 146-1 may have a spacing between 10 micrometers and 500 micrometers. The conductive contacts 146-1 provide increased thermal connectivity, which allows for improved heat transfer from the first die 104-1 through the virtual die 114-1 to the HTC material 105. Conductive contact 146-2 may comprise a conductive material having a surface area (e.g., xy-dimensional) substantially identical to the surface area of ​​dummy die 114-2. Conductive contact 146-2 provides optimal thermal connectivity, allowing for improved heat transfer from first die 104-1 through dummy die 114-2 to HTC material 105. Furthermore, precise alignment of conductive contact 146-2 is not required during attachment of dummy die 114-2 to first die 104-1. The material of conductive contact 146-2 may comprise any suitable conductive material, such as copper, silver, nickel, gold, aluminum, or other metals or alloys.

[0110] Figure 6C This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 6B The configuration of the microelectronic assembly 100 as described herein includes virtual dies 114-1 and 114-2, which are electrically coupled to the first die 104-1 via a bonding layer 107A on the bottom surface of the virtual dies 114-1 and 114-2 to a hybrid bonding region on the top surface of the first die 104-1. Figure 1 As shown in Figure B, the hybrid bonding region may include bonding pads 132 in the dielectric material 109. Bonding layers 107A on the bottom surfaces of the virtual dies 114-1 and 114-2 are electrically coupled to bonding pads 132 in the hybrid bonding region on the top surface of the first die 104-1. The configuration shown in the figures allows for greater thermal connectivity and does not require precise alignment during attachment.

[0111] Figure 6DThis is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 6C The configuration of the microelectronic assembly 100 as described herein includes a second die 104-2, a third die 104-3, and dummy dies 114-1 and 114-2 hybridly bonded to the first die 104-1, wherein a bonding layer 107A is located between hybrid bonding regions beneath the dummy dies 114-1 and 114-2. Specifically, the bonding layer (e.g., similar to...) on the hybrid bonding regions at the bottom surfaces of the second die 104-2, the third die 104-3, and the dummy dies 114-1 and 114-2... Figure 3E The bonding layer 107-2 in the middle can be electrically coupled to the bonding layer on the mixed bonding region at the top surface of the first die 104-1 (e.g., similar to the bonding layer on the top surface of the first die 104-1). Figure 3E The bonding layer 107-1 in the middle is used to form the bonding layer 107A. For example... Figure 1 As shown in Figure B, the hybrid bonding region of the first die 104-1 may include bonding pads 132 in the dielectric material 109, and the hybrid bonding regions of the second die 104-2, the third die 104-3, and the virtual dies 114-1, 114-2 may include bonding pads 134 in the dielectric material 109. Bonding layer 107A can facilitate bonding, wherein bonding layer 107A acts as a conductor when in contact with a conductive material, and as an insulator when in contact with an insulating material. The configuration shown in the figures allows for greater thermal connectivity and does not require precise alignment during attachment.

[0112] Figure 7A This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 2AThe configuration of the microelectronic assembly 100 as described herein includes four layers (e.g., 102-1, 102-2, 102-3, 102-4), with a bonding layer 107A between the first layer 102-1 and the second layer 102-2, and a bonding layer 107B between the second layer 102-2 and the third layer 102-3. The configuration of the embodiment shown in the figures may be part of a top-side power delivery network (PDN), wherein the package substrate 118 includes a power supply 701, the third die 104-3 includes a voltage regulator (VR) circuit module 702, the second layer 102-2 includes a conductive via 710 (e.g., also referred to herein as “TDV”) through a dielectric material 108, and the third layer 102-3 includes a redistribution layer (RDL) 148 having conductive contacts 726 at a bottom surface and conductive pathways 196 through the dielectric. Conductive pathways 196 in RDL 148 may include one or more conductive lines and / or conductive planes for power delivery. In some embodiments, RDL 148 may include an array of conductive lines and / or planes, wherein some of the conductive lines and / or planes are coupled to a positive supply voltage (e.g., also referred to herein as “Vcc”), and some of the conductive lines and / or planes are coupled to ground or zero-voltage connection points (e.g., also referred to herein as “Vss”). In some embodiments, the array of conductive lines and / or planes may include alternating rows of Vcc and Vss connections. As shown, conductive pathway 196 may also include conductive vias. RDL 148 may be formed on substrate 112 and subsequently attached to third layers 102-3 via bonding layer 107B. RDL may be formed using any suitable technique, such as a semi-additive process.

[0113] The first die 104-1 may also include a conductive via 712 (e.g., also referred to herein as a "TSV"). Specifically, the first die 104-1 may include a first TSV 712-1 electrically coupled to the third die via interconnect 106 and a second TSV 712-2 electrically coupled to the TDV 710 via interconnect 156. Interconnect 156 may be one of a plurality of interconnects having a spacing between 10 micrometers and 100 micrometers. Interconnects 106 and 156 may include a bonding layer 107A. The bonding layer 107A may be formed by bonding layers on a mixed bonding layer (e.g., similar to...). Figure 3E The bonding layer on the mixed bonding layer (e.g., similar to the bonding layer 107-1 in the bonding layer) and the conductive contact 722 on the top surface of the first die 104-1, and the bonding layer on the bottom surface of the second die 104-2 and the third die 104-3 (e.g., similar to the bonding layer on the bonding layer 107-1 in the bonding layer) and the bonding layer on the bottom surface of the second die 104-2 and the Figure 3EThe bonding layer 107-2 in the middle is coupled to form it. The materials of TSV 712, TDV 710, conductive contacts 722, 726 and conductive passage 196 may include any suitable conductive material, such as, for example, copper, silver, nickel, gold, aluminum or other metals or alloys.

[0114] The configuration of the embodiments shown in the accompanying drawings can provide a co-stacked power delivery assembly and a power consumption die. In some embodiments, the second die 104-2 is a power consumption die. In such embodiments, power can be delivered directly from a power source through a first TSV 712-1 to a third die 104-3 having a VR circuit module 702, to a conductive plane (e.g., conductive path 196) in the RDL 148, and to the second die 104-2. In another such example embodiment, power can be delivered directly from a power source through a second TSV 712-2 and a TDV 710 to a conductive plane (e.g., conductive path 196) in the RDL 148, and to the second die 104-2. In yet another such example embodiment, power can be delivered directly from a power source (not shown) attached to a conductive plane (e.g., conductive path 196) in the RDL 148 to the second die 104-2. In some embodiments, the first die 104-1 is a power consumption die. In such embodiments, power can be delivered directly from the power source via the second TSV 712-2 and TDV 710 to the conductive plane in RDL 148 (e.g., conductive path 196), to the third die 104-3 with VR circuit module 702, and to the first die 104-1. Due to lower resistance and increased thermal interface, the bonding layers 107A and 107B can provide improved power delivery via PDN.

[0115] Figure 7B This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 7AThe configuration of the microelectronic assembly 100 as described herein may include a dielectric material 108 surrounding the second die 104-2 and the third die 104-3, and may not include HTC material 105 or pad 103. The microelectronic assembly 100 may also include a third die having a passive component 704, such as a capacitor (e.g., a deep trench or metal-insulator-metal (MIM) capacitor) and / or an inductor, which may have non-conductive interconnects for heat conduction. Conductive paths 196 in RDL 148 may be electrically coupled to the second die 104-2, the third die 104-3, and TDV 710 via interconnect 158, and interconnect 158 ​​may include a bonding layer 107B. Interconnect 158 ​​may have a spacing between 10 micrometers and 100 micrometers. The third die 104-3 may be electrically coupled to the first die 104-1 via interconnect 156, and interconnect 156 may include a bonding layer 107A.

[0116] Figures 8A-8C This is a schematic cross-sectional view of other example microelectronic assemblies according to some embodiments of the present disclosure. Figure 8A This is a schematic cross-sectional view of an example microelectronic assembly 100 according to some embodiments of the present disclosure. The microelectronic assembly 100 includes three layers 102 (e.g., 102-1, 102-2, 102-3). Specifically, the microelectronic assembly 100 includes a first die 104-1 in the first layer 102-1, a second die 104-2 and a third die 104-3 in a second layer 102-2 surrounded by a dielectric material 108 (wherein the sidewalls of the second die 104-2 and the third die 104-3 have increased surface roughness and / or are scalloped 802), and a substrate 112 in the third layer 102-3. As used herein, the term "scalloped" refers to having edges or sides marked with semicircles. In some embodiments, the dimensions (e.g., y-dimensions) of a single scallop are between 10 nanometers and 500 nanometers. The increased surface roughness and / or scalloped 802 sidewalls of the second die 104-2 and the third die 104-3 can be formed using any suitable technique, such as by varying the frequency of gas switching during a plasma dicing process, which includes cyclic isotropic etching followed by protective film deposition. The increased surface roughness and / or scalloped 802 sidewalls reduce adhesion of the dielectric material 108 to the sidewalls of the second die 104-2 and the third die 104-3 during deposition, resulting in more horizontal directional filling and eliminating interface seams in the dielectric material 108.

[0117] Figure 8B This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 8A The configuration of the embodiment shown in the figures may include a protective coating material 804 on the sidewalls of the second die 104-2 and the third die 104-3, and may not have increased surface roughness and / or a scalloped shape. Due to its hydrophobicity, the protective coating material 804 can reduce precursor adhesion to the sidewalls during the deposition of the dielectric material 108. With fewer nucleation sites on the sidewalls, the dielectric material 108 can have a more horizontally oriented filling during deposition, and interface seams in the dielectric material 108 can be eliminated. The protective coating material 804 can have any suitable size; for example, the protective coating material 804 can have a width (e.g., y-dimensionality) between 1 nanometer and 5 nanometers. The protective coating material 804 may include any suitable material, such as self-assembled monolayer (SAM) materials, including: alkyl and fluoroalkyl silanes (e.g., octadecylsilane (ODS) and perfluorodecyltrichlorosilane (FDTS)), thiols (e.g., hexadecylthiol), phosphonic acids (e.g., octadecyl and perfluorooctanephosphonic acids), alkyl acids (e.g., heptadecanonical acid); or non-SAM polymer films, including: siloxanes (e.g., polydimethylsiloxane (PDMS) and its derivatives, and hexamethyldisiloxane (HMDSO)), silazanes (e.g., hexamethyldisilazane (HMDS)), polyolefins (e.g., polypropylene (PP)), or fluorinated polymers (e.g., polytetrafluoroethylene (PTFE), perfluoropolyether (PFPE), perfluorodecanoic acid (PFDA), or perfluorocyclobutane (C4F8) (e.g., as a plasma-deposited polymer film)). The protective coating material 804 can be selectively deposited on the sidewalls or deposited on all surfaces and subsequently removed from the top surfaces of the first die 104-1, the second die 104-2 and the third die 104-3.

[0118] Figure 8C This is a schematic cross-sectional view of another example microelectronic assembly according to some embodiments of the present disclosure. Apart from the differences as further described, the configuration of the embodiments shown in the figures is similar. Figure 8B The configuration of the illustrated embodiment may exclude the protective coating material on the sidewalls of the second die 104-2 and the third die 104-3. The configuration of the illustrated embodiment may also exclude the interface seams in the dielectric material 108. Figure 8C The microelectronic assembly 100 can be manufactured using electrostatic effects to preferentially deposit dielectric material 108 in a horizontally oriented fill and eliminate interface seams in the dielectric material 108.

[0119] Figure 8D It is for manufacturing according to some embodiments of this disclosure. Figure 8C A schematic cross-sectional view of a stage in an example process of microelectronic assembly. (See attached image.) Figure 8DAs shown, the first die 104-1 can be placed on an electrostatic chuck 801 having a positive region 803-1 and a negative region 803-2, where the positive region 803-1 and the negative region 803-2 attract and repel the deposition of dielectric material 108 in their respective regions, or vice versa. In such embodiments, a PECVD process can be used to deposit the dielectric material 108. The electrostatic chuck 801 can generate an electrostatic effect to preferentially deposit the dielectric material 108 in the bottom-up fill 805 using a preferred horizontal deposition assembly, and eliminate interface seams in the dielectric material 108.

[0120] The packages disclosed herein (such as any microelectronic assembly 100 described herein or any further embodiments) can be included in any suitable electronic component. Figures 9-11 The illustrations show various examples of packages, assemblies, and devices that can be used with or may include any of the IC packages disclosed herein.

[0121] Figure 9 This is a side cross-sectional view of an example IC package 2200 that may include an IC package, according to any embodiment of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a SiP (System-in-Package).

[0122] As shown in the figure, the encapsulation substrate 2252 can be formed of an insulator (e.g., ceramic, deposited film, epoxy resin film containing filler particles, etc.) and can have conductive pathways extending through the insulator between the first surface 2272 and the second surface 2274, or extending between different locations on the first surface 2272, and / or between different locations on the second surface 2274. These conductive pathways can take the form of any interconnect structure including wires and / or vias.

[0123] The packaging substrate 2252 may include conductive contacts 2263 coupled to conductive pathways 2262 through the packaging substrate 2252, allowing circuit modules within the die 2256 and / or interposer 2257 to be electrically coupled to individual conductive contacts in the conductive contacts 2264 (or electrically coupled to other devices included in the packaging substrate 2252, not shown).

[0124] IC package 2200 may include an interposer 2257 coupled to package substrate 2252 via conductive contacts 2261 of interposer 2257, first-level interconnects 2265, and conductive contacts 2263 of package substrate 2252. The first-level interconnect 2265 illustrated is a solder bump, but any suitable first-level interconnect 2265, such as a solder bump, solder pillar, or bonding wire, can be used.

[0125] IC package 2200 may include one or more dies 2256 coupled to interposer 2257 via conductive contacts 2254 of die 2256, first-level interconnects 2258, and conductive contacts 2260 of interposer 2257. Conductive contacts 2260 may be coupled to conductive paths (not shown) through interposer 2257, allowing circuit modules within die 2256 to be electrically coupled to individual conductive contacts in conductive contacts 2261 (or electrically coupled to other devices included in interposer 2257, not shown). The first-level interconnect 2258 illustrated is a solder bump, but any suitable first-level interconnect 2258, such as a solder bump, solder post, or bonding wire, may be used. As used herein, "conductive contact" may refer to a portion of conductive material (e.g., metal) used as an interface between different components; conductive contacts may be recessed into, flush with, or extend away from the surface of a component and may take any suitable form (e.g., conductive pad or socket).

[0126] In some embodiments, an underfill material 2266 may be provided around a first-level interconnect 2265 between a package substrate 2252 and an interposer 2257, and a die 2268 may be provided around a die 2256 and an interposer 2257, with the die 2268 contacting the package substrate 2252. In some embodiments, the underfill material 2266 may be the same as the die 2268. An example material that can be used for the underfill material 2266 and the die 2268 is a suitable epoxy resin. A second-level interconnect 2270 may be coupled to a conductive contact 2264. The second-level interconnect 2270 illustrated in the figure is a solder ball (e.g., for a ball grid array (BGA) arrangement), but any suitable second-level interconnect 2270 may be used (e.g., pins in a pin grid array arrangement or packages in a land grid array arrangement). The second-level interconnect 2270 may be used to couple the IC package 2200 to as known in the art and as referenced below. Figure 10 The components under discussion include circuit boards (e.g., motherboards), interposers, or other IC packages.

[0127] In various embodiments, any die of 2256 may be a microelectronic assembly 100 as described herein. In embodiments where IC package 2200 includes a plurality of dies 2256, IC package 2200 may be referred to as a multi-chip package (MCP). Dies 2256 may include circuit modules for performing any desired functionality. For example, in addition to one or more of dies 2256 being a microelectronic assembly 100 as described herein, one or more of dies 2256 may also be logic dies (e.g., silicon-based dies), one or more of dies 2256 may also be memory dies (e.g., HBM), etc. In some embodiments, any die of 2256 may be implemented as discussed with reference to any of the figures in the preceding figures. In some embodiments, at least some of dies 2256 may not include the implementations described herein.

[0128] Although the IC package 2200 illustrated is a flip-chip package, other package architectures can be used. For example, IC package 2200 can be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, IC package 2200 can be a wafer-level chip-scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are illustrated in IC package 2200, IC package 2200 can include any desired number of dies 2256. IC package 2200 can include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first side 2272 or the second side 2274 of the package substrate 2252 or on either side of the interposer 2257. More generally, IC package 2200 can include any other active or passive components known in the art.

[0129] In some embodiments, the interposer 2257 may not be included in the IC package 2200; instead, the die 2256 may be directly coupled to the conductive contact 2263 at the first surface 2272 via the first interconnect 2265.

[0130] Figure 10This is a cross-sectional side view of an IC device assembly 2300 that may include components having one or more microelectronic assemblies 100, according to any embodiment of the embodiments disclosed herein. The IC device assembly 2300 includes a plurality of components disposed on a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed on a first surface 2340 of the circuit board 2302 and an opposing second surface 2342 of the circuit board 2302; typically, components may be disposed on one or both of surfaces 2340 and 2342. In particular, according to any embodiment of the embodiments disclosed herein, any suitable component of the IC device assembly 2300 may include any microelectronic assembly from one or more microelectronic assemblies 100; for example, any IC package discussed below with reference to the IC device assembly 2300 may adopt the above-referenced... Figure 9 Any embodiment of the IC package 2200 discussed herein.

[0131] In some embodiments, circuit board 2302 may be a PCB comprising multiple metal layers separated from each other by layers of insulators and interconnected by conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 2302 (optionally in combination with other metal layers). In other embodiments, circuit board 2302 may be a non-PCB package substrate.

[0132] As illustrated in the figures, in some embodiments, the IC device assembly 2300 may include an interposer-on-intermediate package (IPC) structure 2336 coupled to a first side 2340 of a circuit board 2302 via a coupling assembly 2316. The coupling assembly 2316 may electrically and mechanically couple the IPC structure 2336 to the circuit board 2302 and may include solder balls (as shown), raised and recessed portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0133] The interposer-on-package structure 2336 may include an IC package 2320 coupled to the interposer 2304 via a coupling component 2318. The coupling component 2318 may take any suitable form, such as those discussed above with reference to coupling component 2316, depending on the desired functionality. In some embodiments, such as those mentioned above with reference to... Figure 9 As described, IC package 2320 may be or may include IC package 2200. In some embodiments, IC package 2320 may include at least one microelectronic assembly 100 as described herein. To avoid cluttering the figures, microelectronic assembly 100 is not specifically shown in the figures.

[0134] Although a single IC package 2320 is shown in the figure, multiple IC packages can be coupled to the interposer 2304; in fact, additional interposers can be coupled to the interposer 2304. The interposer 2304 can provide an intermediate package substrate for bridging the circuit board 2302 and the IC package 2320. Typically, the interposer 2304 can redistribute connections to a wider pitch or reroute connections to different connections. For example, the interposer 2304 can couple the IC package 2320 to the BGA of the coupling assembly 2316 for coupling to the circuit board 2302.

[0135] In the embodiment illustrated in the figure, the IC package 2320 and the circuit board 2302 are attached to opposite sides of the interposer 2304. In other embodiments, the IC package 2320 and the circuit board 2302 may be attached to the same side of the interposer 2304. In some embodiments, three or more components may be interconnected via the interposer 2304.

[0136] Interposer 2304 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic materials, or polymeric materials such as polyimide. In some implementations, interposer 2304 may be formed of alternative rigid or flexible materials, which may include the same materials described above for semiconductor substrates, such as silicon, germanium, and other group III-V and IV materials. Interposer 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSVs 2306. Interposer 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, ESD devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on interposer 2304. The interposer-on-intermediate (IPI) structure 2336 can take the form of any IPI structure known in the art.

[0137] In some embodiments, the IC device assembly 2300 may include an IC package 2324 coupled to a first side 2340 of the circuit board 2302 via a coupling component 2322. The coupling component 2322 may take the form of any embodiment discussed above with reference to coupling component 2316, and the IC package 2324 may take the form of any embodiment discussed above with reference to IC package 2320.

[0138] In some embodiments, the IC device assembly 2300 may include a package-on-package structure 2334 coupled to a second side 2342 of a circuit board 2302 via a coupling component 2328. The package-on-package structure 2334 may include IC packages 2326 and 2332 coupled together via a coupling component 2330, such that IC package 2326 is positioned between the circuit board 2302 and IC package 2332. The coupling components 2328 and 2330 may take the form of any embodiment of the coupling component 2316 discussed above, and IC packages 2326 and / or 2332 may take the form of any embodiment of the IC package 2320 discussed above. The package-on-package structure 2334 may be configured according to any package-on-package structure known in the art.

[0139] Figure 11 This is a block diagram of an example computing device 2400 that may include one or more components having one or more IC packages, according to any embodiment of the embodiments disclosed herein. For example, any suitable component of computing device 2400 may include a microelectronic assembly (e.g., 100) according to any embodiment of the embodiments disclosed herein. In another example, any one or more components of computing device 2400 may include any embodiment of IC package 2200 (e.g., such as...). Figure 9 (As shown in the image). In another example, any one or more components of computing device 2400 may include IC device assembly 2300 (e.g., as shown in the image). Figure 10 (As shown in the image).

[0140] Multiple components are illustrated as being included in computing device 2400, but any one or more of these components may be omitted or copied as appropriate for an application. In some embodiments, some or all of the components included in computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single SoC die.

[0141] Additionally, in various embodiments, computing device 2400 may not include one or more of the components illustrated in the figures, but computing device 2400 may include interface circuit modules for coupling to one or more components. For example, computing device 2400 may not include display device 2406, but may include display device interface circuit modules (e.g., connector and driver circuit modules) to which display device 2406 can be coupled. In another set of examples, computing device 2400 may not include audio input device 2418 or audio output device 2408, but may include audio input or output device interface circuit modules (e.g., connector and support circuit modules) to which audio input device 2418 or audio output device 2408 can be coupled.

[0142] Computing device 2400 may include processing device 2402 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any means or part of a means of processing electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory. Processing device 2402 may include one or more DSPs, ASICs, CPUs, GPUs, cryptographic processors (dedicated processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing means. Computing device 2400 may include memory 2404, which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, memory 2404 may include memory that shares a die with processing device 2402. Such memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0143] In some embodiments, computing device 2400 may include communication chip 2412 (e.g., one or more communication chips). For example, communication chip 2412 may be configured to manage wireless communication for transmitting data to and from computing device 2400. The term "wireless" and its derivatives can be used to describe circuits, apparatus, systems, methods, techniques, communication channels, etc., that can transmit data through a non-solid medium using modulated electromagnetic radiation. The term does not imply that the associated apparatus does not contain any wires, although in some embodiments they may not contain any wires.

[0144] The 2412 communication chip can implement any of a variety of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, such as Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), and LTE projects along with any modifications, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). Broadband Wireless Access (BWA) networks compliant with IEEE 802.16 are often referred to as WiMAX networks. WiMAX is an acronym for Global Interoperability for Microwave Access, and it is a certification mark for products that have passed conformance and interoperability testing of the IEEE 802.16 standard. The 2412 communication chip can operate according to Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication chip 2412 may operate according to GSM Evolution Enhanced Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chip 2412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolved Data Optimization (EV-DO), and its derivatives, as well as any other wireless protocol designated as 3G, 4G, 5G, and above. In other embodiments, communication chip 2412 may operate according to other wireless protocols. Computing device 2400 may include antenna 2422 to facilitate wireless communication and / or receiving other wireless communications (such as AM or FM radio transmissions).

[0145] In some embodiments, the communication chip 2412 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As described above, the communication chip 2412 may include multiple communication chips. For example, a first communication chip 2412 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communication chip 2412 may be dedicated to wireless communications, and the second communication chip 2412 may be dedicated to wired communications.

[0146] The computing device 2400 may include a battery / power circuit module 2414. The battery / power circuit module 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuit modules for coupling components of the computing device 2400 to an energy source (e.g., AC line power) separate from the computing device 2400.

[0147] The computing device 2400 may include a display device 2406 (or a corresponding interface circuit module, as discussed above). For example, the display device 2406 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0148] The computing device 2400 may include an audio output device 2408 (or a corresponding interface circuit module, as discussed above). For example, the audio output device 2408 may include any device that generates audible indicators, such as a speaker, headphones, or earphones.

[0149] The computing device 2400 may include an audio input device 2418 (or a corresponding interface circuit module, as discussed above). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital musical instrument (e.g., a musical instrument with a Musical Instrument Digital Interface (MIDI) output).

[0150] The computing device 2400 may include a GPS device 2416 (or a corresponding interface circuit module, as discussed above). As is known in the art, the GPS device 2416 can communicate with a satellite-based system and can receive the location of the computing device 2400.

[0151] The computing device 2400 may include other output devices 2410 (or corresponding interface circuit modules, as discussed above). Examples of other output devices 2410 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0152] The computing device 2400 may include other input devices 2420 (or corresponding interface circuit modules, as discussed above). Examples of other input devices 2420 may include accelerometers; gyroscopes; compasses; image capture devices; keyboards; cursor control devices such as mice, pens, and touchpads; barcode readers; quick-response (QR) code readers; any sensors; or radio frequency identification (RFID) readers.

[0153] The computing device 2400 can have any desired form factor, such as a handheld or mobile computing device (e.g., a cellular phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), super mobile personal computer, etc.), desktop computing device, server or other networked computing component, printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable computing device. In some embodiments, the computing device 2400 can be any other electronic device that processes data.

[0154] The above description of the disclosed illustrated implementation (including those described in the abstract) is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. While specific implementations and examples of the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as will be appreciated by those skilled in the art.

[0155] Example 1 provides a microelectronic assembly comprising: a first die having a surface; a second die and a third die having a first surface and opposing second surfaces, wherein the first surfaces of the second die and the third die are electrically coupled to the surface of the first die; a first material having a non-planar surface on the surface of the first die and around and between the second die and the third die; and a layer on the non-planar surface of the first material and in physical contact with the non-planar surface of the first material and with the second surfaces of the second die and the third die, the layer comprising a second material having a thermal conductivity equal to or greater than 10 watts per meter-Kelvin (W / mK).

[0156] Example 2 provides a microelectronic assembly according to Example 1, wherein the first material comprises silicon and nitrogen, silicon and oxygen, or silicon, nitrogen, and carbon; a polymer material; a mold material; or a low-k or ultra-low-k dielectric.

[0157] Example 3 provides a microelectronic assembly according to Example 1 or 2, wherein the second material comprises one or more of copper, aluminum, aluminum and nitrogen, diamond, silicon and carbon, boron and nitrogen, and boron and arsenic.

[0158] Example 4 provides a microelectronic assembly according to any one of Examples 1-3, wherein the thickness of the second material on the second surface of the second die and the third die is between 1 micrometer and 2 micrometers.

[0159] Example 5 provides a microelectronic assembly according to any one of Examples 1-4, wherein the layer further comprises a third material between the non-planar surface of the second material and the first material and the second surface of the second die and the third die, the third material comprising one or more of titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, ruthenium, and tungsten.

[0160] Example 6 provides a microelectronic assembly according to Example 5, wherein the third material has a thickness between 1 nanometer and 50 nanometers.

[0161] Example 7 provides a microelectronic assembly according to any one of Examples 1-6, further comprising a substrate coupled to the layer.

[0162] Example 8 provides a microelectronic assembly according to Example 7, wherein the substrate is made of silicon.

[0163] Example 9 provides a microelectronic assembly according to Example 7 or 8, further comprising a fourth material between the layer and the substrate, wherein the fourth material comprises one or more of titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, and silicon, carbon and nitrogen.

[0164] Example 10 provides a microelectronic assembly according to Example 9, wherein the fourth material has a thickness between 0.2 nanometers and 100 nanometers.

[0165] Example 11 provides a microelectronic assembly according to Example 9 or 10, further comprising a fifth material between the substrate and the fourth material, the fifth material comprising titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, ruthenium, or tungsten.

[0166] Example 12 provides a microelectronic assembly according to Example 11, wherein the fifth material has a thickness between 1 nanometer and 50 nanometers.

[0167] Example 13 provides a microelectronic assembly according to any one of Examples 1-12, further comprising a through-hole through the first material, the through-hole comprising a conductive material and electrically coupled to the first die and the second material.

[0168] Example 14 provides a microelectronic assembly according to Example 13, wherein the via is one of a plurality of vias.

[0169] Example 15 provides a microelectronic assembly according to any one of Examples 1-14, wherein the surface of the first die is a second surface, and the first die further includes a first surface opposite to the second surface, and the microelectronic assembly further includes a packaging substrate electrically coupled to the first surface of the first die via solder interconnects.

[0170] Example 16 provides a microelectronic assembly comprising: a first die having a surface; a second die having a first surface and an opposing second surface, the first surface of the second die being electrically coupled to the surface of the first die; a first material on the surface of the first die and around and between the second die, the first material having a non-planar surface and comprising silicon and nitrogen, silicon and oxygen, or silicon, nitrogen and carbon; a second material on the non-planar surface of the first material and the second surface of the second die, the second material comprising titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, ruthenium, or tungsten; a third material on the second material, the third material comprising one or more of copper, aluminum, aluminum and nitrogen, diamond, silicon and carbon, boron and nitrogen, and boron and arsenic; a fourth material on the third material, the fourth material comprising one or more of titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, and silicon, carbon and nitrogen; and a substrate on the fourth material, wherein the substrate is made of silicon.

[0171] Example 17 provides a microelectronic assembly according to Example 16, wherein the second material has a thickness between 1 nanometer and 50 nanometers.

[0172] Example 18 provides a microelectronic assembly according to Example 16 or 17, wherein the thickness of the third material on the second surface of the second die is between 1 micrometer and 2 micrometers.

[0173] Example 19 provides a microelectronic assembly according to any one of Examples 16-18, wherein the fourth material has a thickness between 0.2 nanometers and 100 nanometers.

[0174] Example 20 provides a microelectronic assembly according to any one of Examples 16-19, further comprising a fifth material between the substrate and the fourth material, the fifth material comprising titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, ruthenium, or tungsten.

[0175] Example 21 provides a microelectronic assembly according to Example 20, wherein the fifth material has a thickness between 1 nanometer and 50 nanometers.

[0176] Example 22 provides a microelectronic assembly comprising: a first layer including a first die; a second layer on the first layer, the second layer including two or more second dies and a dielectric material around and between the two or more second dies, wherein the first die is electrically coupled to the two or more second dies by interconnects having a spacing of less than 10 micrometers between adjacent interconnects, and wherein the surface of the dielectric material has an inconsistent morphology; a third layer on the second layer, the third layer including a high thermal conductivity material on and between the two or more second dies and at least a portion of the dielectric material, and wherein the thickness of the high thermal conductivity material on the two or more second dies is between 1 micrometer and 2 micrometers; and a substrate on the third layer.

[0177] Example 23 provides a microelectronic assembly according to Example 22, wherein the dielectric material comprises silicon and nitrogen, silicon and oxygen, or silicon, nitrogen and carbon; a polymer material; a mold material; or a low-k or ultra-low-k dielectric.

[0178] Example 24 provides a microelectronic assembly according to Example 22 or 23, wherein the high thermal conductivity material includes one or more of copper, aluminum, aluminum and nitrogen, diamond, silicon and carbon, boron and nitrogen, and boron and arsenic.

[0179] Example 25 provides a microelectronic assembly according to any one of Examples 22-24, wherein the substrate is made of silicon.

[0180] Example 26 provides a microelectronic assembly according to any one of Examples 22-25, wherein the third layer further includes a pad located between the second layer and the high thermal conductivity material, wherein the material of the pad includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, ruthenium, or tungsten.

[0181] Example 27 provides a microelectronic assembly according to Example 26, wherein the pad has a thickness between 1 nanometer and 50 nanometers.

[0182] Example 28 provides a microelectronic assembly according to any one of Examples 22-27, wherein the substrate is coupled to the third layer by a bonding material comprising one or more of titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, and silicon, carbon and nitrogen.

[0183] Example 29 provides a microelectronic assembly according to Example 28, wherein the bonding material has a thickness between 0.2 nanometers and 100 nanometers.

[0184] Example 30 provides a microelectronic assembly according to Example 28 or 29, further comprising a pad between the substrate and the bonding material, wherein the material of the pad includes titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, ruthenium, or tungsten.

[0185] Example 31 provides a microelectronic assembly according to Example 30, wherein the pad has a thickness between 1 nanometer and 50 nanometers.

[0186] Example 32 provides a microelectronic assembly according to any one of Examples 22-31, wherein the first die is one of a plurality of first dies, and wherein each of the two or more second dies is electrically coupled to each of the plurality of first dies.

[0187] Example 33 provides a microelectronic assembly according to any one of Examples 22-32, further comprising a packaging substrate electrically coupled to the first layer at a surface opposite the second layer via solder interconnects.

Claims

1. A microelectronic assembly, comprising: a first die having a surface; a second die and a third die having first surfaces and opposing second surfaces, wherein the first surfaces of the second and third dies are electrically coupled to the surface of the first die; a first material on the surface of the first die and around and between the second and third dies, the first material having a non-planar surface; and a layer on and in physical contact with the non-planar surface of the first material and with the second surfaces of the second and third dies, the layer comprising a second material having a thermal conductivity equal to or greater than 10 Watts per meter-Kelvin (W / m-K).

2. The microelectronic assembly of claim 1, wherein, the first material comprises silicon and nitrogen, silicon and oxygen, or silicon, nitrogen, and carbon; a polymeric material; a mold material; or a low-k or ultra-low-k dielectric.

3. The microelectronic assembly of claim 1, wherein, the second material comprises one or more of copper, aluminum, aluminum and nitrogen, diamond, silicon and carbon, boron and nitrogen, and boron and arsenic.

4. The microelectronic assembly of claim 1, wherein, a thickness of the second material on the second surfaces of the second and third dies is between 1 micron and 2 microns.

5. The microelectronic assembly of any of claims 1-4, wherein, the layer further comprises: a third material between the second material and the non-planar surface of the first material and the second surfaces of the second and third dies, the third material comprising one or more of titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, ruthenium, and tungsten.

6. The microelectronic assembly of claim 5, wherein, the third material has a thickness between 1 nanometer and 50 nanometers.

7. The microelectronic assembly of any of claims 1-4, further comprising: a substrate coupled to the layer.

8. The microelectronic assembly of claim 7, wherein, a material of the substrate comprises silicon.

9. The microelectronic assembly of claim 7, further comprising: a fourth material between the layer and the substrate, wherein the fourth material comprises one or more of titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, and silicon, carbon and nitrogen.

10. The microelectronic assembly of claim 9, wherein, the fourth material has a thickness between 0.2 nanometers and 100 nanometers.

11. The microelectronic assembly of any of claims 1-4, further comprising: a via through the first material, the via comprising a conductive material and electrically conductively coupled to the first die and the second material.

12. An integrated circuit (IC) package, comprising: a first die having a surface; a second die having a first surface and an opposing second surface, the first surface of the second die electrically coupled to the surface of the first die; a first material on the surface of the first die and around and between the second die, the first material having a non-planar surface and comprising silicon and nitrogen, silicon and oxygen, or silicon, nitrogen and carbon; a second material on the non-planar surface of the first material and the second surface of the second die, the second material comprising titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, ruthenium, or tungsten; a third material on the second material, the third material comprising one or more of copper, aluminum, aluminum and nitrogen, diamond, silicon and carbon, boron and nitrogen, and boron and arsenic; a fourth material on the third material, the fourth material comprising one or more of titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, and silicon, carbon and nitrogen; and a substrate on the fourth material, wherein a material of the substrate comprises silicon.

13. The IC package of claim 12, wherein, the second material has a thickness between 1 nanometer and 50 nanometers.

14. The IC package of claim 12, wherein, a thickness of the third material on the second surface of the second die is between 1 micrometer and 2 micrometers.

15. The IC package of claim 12, wherein, a thickness of the fourth material is between 0.2 nanometers and 100 nanometers.

16. The IC package of any of claims 12-15, further comprising: a fifth material between the substrate and the fourth material, the fifth material comprising titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, ruthenium, or tungsten.

17. The IC package of claim 16, wherein, a thickness of the fifth material is between 1 nanometer and 50 nanometers.

18. A computing system, comprising: a first layer comprising a first die; a second layer on the first layer, the second layer comprising two or more second dies and a dielectric material around and between the two or more second dies, wherein the first die is electrically coupled to the two or more second dies by interconnects having a pitch between adjacent interconnects of less than 10 micrometers, and wherein a surface of the dielectric material has an inconsistent topography; a third layer on the second layer, the third layer comprising a high thermal conductivity material on the two or more second dies and on at least a portion of the dielectric material between the two or more second dies, and wherein a thickness of the high thermal conductivity material on the two or more second dies is between 1 micrometer and 2 micrometers; and a substrate on the third layer.

19. The computing system of claim 18, wherein, the high thermal conductivity material comprises one or more of copper, aluminum, aluminum and nitrogen, diamond, silicon and carbon, boron and nitrogen, and boron and arsenic.

20. The computing system of claim 18, wherein, the dielectric material comprises silicon and nitrogen, silicon and oxygen, or silicon, nitrogen and carbon; a polymeric material; a mold material; or a low-k or ultra-low-k dielectric.

21. The computing system of claim 18, wherein, a material of the substrate comprises silicon.

22. The computing system of any of claims 18-21, wherein, the third layer further comprises a liner between the second layer and the high thermal conductivity material, wherein a material of the liner comprises titanium, titanium and nitrogen, tantalum, tantalum and nitrogen, ruthenium, or tungsten.

23. The computing system of claim 22, wherein, the liner has a thickness between 1 nanometer and 50 nanometers.

24. The computing system of any of claims 18-21, wherein, the substrate is coupled to the third layer by a bonding material comprising one or more of titanium, tantalum, gold, ruthenium, silver, aluminum and nitrogen, silicon and oxygen, silicon and nitrogen, and silicon, carbon and nitrogen.

25. The computing system of claim 24, wherein, the bonding material has a thickness between 0.2 nanometers and 100 nanometers.

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