Integrated circuit package assembly

Abstract

An integrated circuit package assembly is provided. One form of an integrated circuit package assembly includes a package substrate. The bare chip is assembled on the packaging substrate. A layer of a graphite thermal interface material (TIM) is located on the die, and the layer of the graphite thermal interface material (TIM) is located on the die. A spacer frame is on the die and disposed along a plurality of sidewalls of the layer of graphite thermal interface material. A layer of adhesive thermal interface material is on the die and disposed along an outer sidewall of the spacer frame. And the metal cover is positioned on the graphite thermal interface material layer. The spacer frame separates the adhesive thermal interface material layer from the graphite thermal interface material layer.

Description

Technical Field

[0001] This utility model relates to a semiconductor technology, and more particularly to an integrated circuit packaging component. Background Technology

[0002] The electronics industry's demand for smaller and faster electronic devices, capable of supporting a greater number of increasingly complex and sophisticated functions, is constantly growing. To meet these demands, the integrated circuit (IC) industry continues its trend towards low-cost, high-efficiency, and low-power ICs. To date, these goals have been largely achieved by shrinking IC dimensions (e.g., miniaturizing IC feature units), thereby increasing production efficiency and reducing associated costs. However, this miniaturization also increases the complexity of IC manufacturing processes. Therefore, continued advancements in IC manufacturing processes and technologies are needed to achieve further progress in IC devices and their performance.

[0003] The demand for higher power and more compact die space (e.g., in high-performance computing (HPC) and artificial intelligence (AI) applications) necessitates proportional advancements in thermal management. For example, advanced thermal interface materials (TIMs), such as graphite TIMs, are used to enhance thermal coupling between integrated circuit (IC) dies and heat sinks. Graphite TIMs have a vertically stacked structure, which facilitates good thermal conductivity in the vertical direction. Furthermore, graphite TIMs inherently possess high thermal conductivity and high compressibility. Since graphite TIMs are typically non-adhesive, adhesive TIMs are used as an adjunct to promote better adhesion. However, defects can occur at the interface between these two heterogeneous materials. These defects can penetrate deep into the interior of the graphite TIM, thereby worsening its contact resistance. Furthermore, if too much pressure is applied to the graphite thermal interface material (TIM), excessive compression will damage the graphite material itself, thereby reducing thermal efficiency.

[0004] Therefore, although existing graphite thermal interface materials (TIMs) in integrated circuit (IC) packaging are generally sufficient to meet their intended purpose, they are not entirely satisfactory in every respect. Utility Model Content

[0005] The purpose of this invention is to provide an integrated circuit packaging component to solve at least one of the above-mentioned problems.

[0006] In some embodiments, an integrated circuit packaging assembly is provided, comprising: a packaging substrate; a die assembled on the packaging substrate; a graphite thermal interface material layer located on the die; a spacer frame located on the die and disposed along a plurality of sidewalls of the graphite thermal interface material layer; an adhesive thermal interface material layer located on the die and disposed along a plurality of outer sidewalls of the spacer frame; and a metal cover located on the graphite thermal interface material layer. The spacer frame separates the adhesive thermal interface material layer from the graphite thermal interface material layer.

[0007] According to one embodiment of the present invention, it further includes: a matrix adhesive located on a peripheral frame of the encapsulation substrate, wherein the metal cover is fixed to the peripheral frame by the matrix adhesive, and wherein the metal cover is fixed to the bare die by the adhesive thermal interface material layer.

[0008] According to one embodiment of the present invention, the metal cover rests directly on the graphite thermal interface material layer and the spacer frame.

[0009] According to one embodiment of the present invention, the spacer frame completely surrounds the graphite thermal interface material layer, except for the multiple corners of the graphite thermal interface material layer.

[0010] According to one embodiment of the present invention, the spacer frame includes: a first ring that completely surrounds the graphite thermal interface material layer; and a second ring that completely surrounds the first ring, wherein the first ring and the second ring maintain a distance from each other.

[0011] In some embodiments, an integrated circuit packaging assembly is provided, comprising: a packaging substrate; a first die assembled on the packaging substrate; a first thermal interface material (TIM) layer disposed on a central portion of the first die; a spacer frame disposed on a plurality of peripheral portions of the first die and along a plurality of sidewalls of the first TIM layer; a second die assembled on the packaging substrate; a second TIM layer disposed on a central portion of the second die; and a metal cover disposed on the first TIM layer and the second TIM layer. The first TIM layer and the second TIM layer comprise different materials.

[0012] According to one embodiment of the present invention, it further includes: an adhesive disposed on the first bare sheet and along a plurality of outer side walls of a spacer frame, wherein the spacer frame separates the adhesive from the first thermal interface material layer, and wherein the adhesive bonds the metal cover to the first bare sheet.

[0013] According to one embodiment of the present invention, the spacer frame completely surrounds the first thermal interface material layer.

[0014] According to one embodiment of the present invention, the partition frame includes a plurality of corner portions extending diagonally from the plurality of corner portions of the partition frame.

[0015] According to one embodiment of the present invention, the spacer frame only partially surrounds the first thermal interface material layer. Attached Figure Description

[0016] Figure 1 An integrated circuit (IC) package assembly according to an embodiment of the present invention is shown, having a spacer frame integrated with a graphite thermal interface material (TIM) layer.

[0017] Figure 2A , Figure 2B and Figure 2C A perspective view, a plan view, and a cross-sectional view of a spacer frame integrated with a graphite thermal interface material (TIM) layer according to an embodiment of the present invention are shown respectively.

[0018] Figure 3 The following are flowcharts illustrating methods for forming integrated circuit (IC) package components according to embodiments of the present invention. The integrated circuit (IC) package components have spacer frames that are partially or completely integrated with a graphite thermal interface material (TIM) layer.

[0019] Figure 4 The illustration shows process details for forming a spacer frame on a bare die according to an embodiment of the present invention. Figure 3 Some of the methods in [the text].

[0020] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5F Various structural configurations of the spacer frame surrounding the graphite thermal interface material (TIM) layer according to different embodiments of the present invention are shown.

[0021] Figure 6 A cross-sectional schematic diagram of a spacer frame integrated with a graphite thermal interface material (TIM) layer according to an embodiment of the present invention is shown.

[0022] Figure 7 The diagram shows a cross-sectional view of an integrated circuit (IC) package assembly according to an embodiment of the present invention, the integrated circuit (IC) package assembly having a heat sink placed on a spacer frame integrated with a graphite thermal interface material (TIM) layer.

[0023] The attached figures are labeled as follows:

[0024] 100: Integrated Circuit (IC) Packaging Components

[0025] 102: Packaging substrate

[0026] 104, 204: Nude films

[0027] 106: Graphite thermal interface material (TIM) layer

[0028] 106c: Top corner

[0029] 111: Packaged components

[0030] 112: Peripheral framework

[0031] 113: Adhesive / Matrix Adhesive

[0032] 116: Adhesive Thermal Interface Materials (TIM)

[0033] 120: Spacing Frame

[0034] 120a: First spacer ring

[0035] 120b: Second spacer ring

[0036] 206: Viscous thermal interface material (TIM) layer

[0037] 300: Method

[0038] 302, 304, 306, 308, 310: Operating Procedures

[0039] 702: Cover / Metal Cover / Heat Dissipation Cover

[0040] D1: Distance

[0041] H, H1, H2, H G : high

[0042] L: Inner length

[0043] L G : length

[0044] T: Thickness

[0045] W: Inner width

[0046] W G Width Detailed Implementation

[0047] The following disclosure provides many different embodiments or examples to implement different features of this utility model. The following disclosure provides specific examples of the various components and their arrangements to simplify this utility model. Of course, these are merely illustrative examples and are not intended to define this utility model. For example, if the following disclosure describes a first feature being formed above or on a second feature, it indicates that it includes embodiments where the first and second feature are in direct contact, and also includes embodiments where additional feature components may be formed between the first and second feature components, so that the first and second feature components may not be in direct contact. Furthermore, reference numerals and / or text are repeated in various examples of this utility model. This repetition is for simplification and clarity, and not to specify the relationships between the various embodiments and / or configurations discussed.

[0048] Furthermore, spatial terms such as "below," "below," "below," "down," "above," "above," "upper," etc., are used here to readily express the relationship between the device or feature shown in the accompanying drawings and other devices or feature. These spatial terms cover not only the orientation shown in the drawings but also different orientations of the device during use or operation. The device may have different orientations (rotated 90 degrees or other orientations), and the spatial symbols used herein also have corresponding explanations.

[0049] Furthermore, when a numerical value or range is described using terms such as "approximately" or "around," the term includes a value within a reasonable range that takes into account variations inherent during manufacturing, as understood by one of skill in the art. For example, based on known manufacturing tolerances for a feature part having a numerically related characteristic, the size or range of the value includes a reasonable range of said value, such as within + / -10% of said value. For example, a material layer with a thickness of "approximately 5 nm" can cover a size range from 4.5 nm to 5.5 nm, where a manufacturing tolerance associated with the deposited material layer is known to one of skill in the art to be + / -10%. And when comparing the size or dimensions of one feature part with another feature part, terms such as "substantially identical," "basically the same," or "similar in size" can be understood as within + / -10% of the compared feature parts. Furthermore, the disclosed dimensions of different feature parts may implicitly disclose size ratios between different features.

[0050] This invention relates to an integrated circuit (IC) packaging assembly incorporating a graphite thermal interface material (TIM) layer to improve heat transfer between a heat source (e.g., an IC chip or die) and a heat sink. Graphite thermal interface materials (TIMs) offer advantages over other types of thermal interface materials (TIMs) due to their excellent thermal conductivity, high compressibility (i.e., elasticity), and high heat resistance. Furthermore, their vertically stacked structure enhances heat transfer in the vertical direction. Graphite thermal interface materials (TIMs) are flexible and malleable; therefore, combining them with adhesive thermal interface materials (TIMs) enhances the adhesion of the graphite thermal interface materials (TIMs) and provides better structural support. For example, the adhesive thermal interface material (TIM), upon curing, physically holds the graphite thermal interface material (TIM) in place and prevents warping of the package. However, as mentioned earlier, defects may occur at the interface between the graphite thermal interface material (TIM) and the adhesive thermal interface material (TIM). These defects may penetrate deep into the interior of the graphite thermal interface material (TIM), thereby worsening the contact resistance of the TIM. Furthermore, although the graphite thermal interface material (TIM) is highly compressible and has good thermal conductivity in the vertical direction, excessive compression due to excessive pressure will damage the graphite material itself, thus reducing thermal efficiency.

[0051] This invention describes a spacer frame used in conjunction with a graphite thermal interface material (TIM) layer. The spacer frame can be used with an adhesive thermal interface material (TIM). However, in some embodiments, a spacer frame is provided that does not require an adhesive thermal interface material (TIM). Nevertheless, while still using an adhesive thermal interface material (TIM), the spacer frame separates the graphite thermal interface material (TIM) layer from the adhesive thermal interface material (TIM), thereby avoiding interface defect problems between dissimilar materials. Furthermore, the spacer frame comprises a high-modulus material to protect the graphite thermal interface material (TIM) from over-compression. Therefore, the spacer frame can control the degree of compression of the graphite thermal interface material (TIM), which provides greater flexibility in the design of the graphite thermal interface material (TIM) thickness. Different designs of the spacer frame can also be customized for different needs. For example, the specific placement and / or number of spacers can be adjusted to achieve a balance between preventing package warping, supporting the graphite thermal interface material (TIM) from over-compression, and allowing space for the adhesive thermal interface material (TIM).

[0052] Figure 1An integrated circuit (IC) package assembly 100 according to an embodiment of the present invention is shown, having a spacer frame 120 integrated with a graphite thermal interface material (TIM) layer 106. The IC package assembly 100 includes a package substrate 102, a die 104 mounted on the package substrate 102, a graphite thermal interface material (TIM) layer 106 located on the die 104, a spacer frame 120 located on the die and disposed along the sidewalls of the graphite thermal interface material (TIM) layer 106, and a cover 702 disposed on the graphite thermal interface material (TIM) layer 106. In the illustrated embodiment, the IC package assembly 100 further includes a die 204 mounted on the package substrate 102 and an adhesive thermal interface material (TIM) layer 206 located on the die 204. Note that the cover 702 is also disposed on the adhesive thermal interface material (TIM) layer 206. The cover 702 covers the integrated circuit (IC) package assembly 100 by attaching it to the peripheral frame 112 of the package substrate 102. These different features will be described in detail below.

[0053] Package substrate 102 generally refers to a wafer or semiconductor structure that serves as a carrier substrate for an integrated circuit (IC) package. This carrier substrate may also be referred to as a substrate base, substrate underlayer, etc. In one embodiment, package substrate 102 includes a semiconductor substrate formed of silicon, silicon germanium, silicon carbon, or the like. Package substrate 102 may have various package components assembled thereon, such as die 104, die 204, or other active or passive die devices. Package substrate 102 also includes other package components 111, such as silicon interlayers, dielectric substrates, or the like. For example, package component 111 may include a redistribution layer and / or interlayer for routing signals from the die component to a printed circuit board (PCB). In the illustrated embodiment, package substrate 102 also includes a peripheral frame 112 defining the periphery of package substrate 102. Peripheral frame 112 may be part of package substrate 102 or a separate structure formed on the upper surface of package substrate 102. In one embodiment, the peripheral frame 112 is formed on a semiconductor or dielectric material constituting the package substrate 102. In any case, the cover 702 is secured to the peripheral frame 112 to cover the integrated circuit (IC) package assembly 100. In one embodiment, the peripheral frame 112 comprises a thermally conductive material, such as aluminum, copper, cobalt, or other metals. In another embodiment, the peripheral frame 112 comprises a material similar to the cover 702.

[0054] Although not shown, the integrated circuit (IC) package assembly 100 may be part of a larger integrated circuit (IC) structure. For example, the integrated circuit (IC) package assembly 100 may be mounted onto a printed circuit board (PCB). In this case, the package substrate 102 may include a ball-grid array (BGA) structure on its back side. The ball-grid array (BGA) structure includes solder contacts that can bond one or more integrated circuit (IC) package assemblies 100 to the larger printed circuit board (PCB). The printed circuit board (PCB) may include multiple other integrated circuit (IC) components mounted thereon to form processors, controllers, memory cells, or other electronic modules.

[0055] Please refer to Figure 1 The integrated circuit (IC) package assembly 100 includes dies 104 and 204. Dies 104 and 204 are assembled on a package substrate 102. Each of dies 104 and 204 may include various active and passive devices (e.g., transistor devices, resistors, capacitors, carrier substrates, etc.). In the illustrated embodiment, dies 104 and 204 are arranged adjacent to each other in the lateral direction. In another embodiment, dies 104 and / or 204 may be stacked on top of each other in the vertical direction. In yet another embodiment, dies 104 and / or 204 may be arranged adjacent to each other and may also be stacked on top of each other to form various integrated 3DIC stack structures.

[0056] Dies 104 and 204 can be assembled onto package substrate 102 via a controlled collapse chip connection (C4) layer. The controlled collapse chip connection (C4) layer includes internal connection bumps, such as solder bumps or copper pillar (CuP) bumps. Solder bumps may include tin, lead, and / or silver, and copper pillar (CuP) bumps may include copper pillars with solder caps at their ends. The solder caps may be made of tin, lead, and / or silver. The internal connection bumps serve as means for connecting a chip / die to another chip / die (when there are vertically stacked dies) or to package substrate 102, which is part of integrated circuit (IC) package assembly 100. In one embodiment, the controlled collapse chip connection (C4) layer is disposed on the back surface of the back-side internal connection structure of dies 104 and 204. For example, the internal connection bumps are disposed on aluminum bonding pads of the back-side internal connection structure. The aluminum bonding pads may be part of an aluminum pad layer. The aluminum pad can be part of a redistribution layer (RDL) structure. The RDL structure can contain redistributed wiring embedded within one or more passivation sheaths.

[0057] Each of dies 104 and 204 may include a device layer sandwiched between various integrated circuit (IC) layers and components (e.g., sandwiched between a front-side interconnect structure and a back-side interconnect structure). The device layer is where device-level features (e.g., transistor devices) are formed. Transistor devices may be logic devices, memory devices, or similar devices. Each transistor device includes a channel region between source / drain (S / D) regions and a gate stack above the channel region. The device layer may also include other device-level features, such as source / drain (S / D) contacts, source / drain (S / D) vias, gate contacts, and / or gate vias, each of which electrically connects the source / drain (S / D) regions and / or gate stacks to higher or lower material layers of the die (e.g., front-side and / or back-side interconnect structures). Dies 104 and 204 may include a front-side interconnect structure above the device layer and a back-side interconnect structure below the device layer. The front and back internal interconnect structures may include metal lines and vias embedded in an intermetallic dielectric (IMD) layer, which route signal wiring to and from transistor devices within the device layer. In one embodiment, a bonding layer, which is part of (or separate from) dies 104 and 204, is disposed above the front internal interconnect structure, and a carrier substrate is disposed above the bonding layer. For example, the bonding layer and the carrier substrate (e.g., made of silicon) are formed to provide structural support when the back internal interconnect structure is formed.

[0058] In the illustrated embodiment, the difference between die 104 and die 204 lies in the type of thermal interface material (TIM) used. For example, die 104 uses a graphite thermal interface material (TIM) layer 106, while die 204 uses a viscous thermal interface material (TIM) layer 206. In one embodiment, die 104 performs a more computationally intensive task than die 204 and requires better thermal control. In one embodiment, die 104 uses a graphite thermal interface material (TIM) for better thermal efficiency, while die 204 uses a viscous thermal interface material (TIM). In one embodiment, die 104 includes a high-power or high-speed logic or memory device, and die 204 includes a low-power or low-speed logic or memory device. In one embodiment, die 204 is a DRAM device.

[0059] Please refer to Figure 1 The integrated circuit (IC) package assembly 100 includes a thermal interface material (TIM) layer disposed above the die 104 and 204. Specifically, a graphite thermal interface material (TIM) layer 106 is disposed above the center portion of the die 104. Figure 1A bare die 104 is shown (but there may be more), and a viscous thermal interface material (TIM) layer 206 is disposed above the central portion of the bare die 204. In embodiments with multiple stacked bare dies, corresponding thermal interface material (TIM) layers may be disposed between the stacked dies. In any case, the corresponding thermal interface material (TIM) layers are disposed on the upper surfaces of the uppermost bare die 104 and the uppermost bare die 204. The graphite thermal interface material (TIM) layer 106 and the viscous thermal interface material (TIM) layer 206 serve as heat conductors and distributors on the front side of the corresponding bare dies. The corresponding thermal interface material (TIM) layers can be used to uniformly and efficiently guide heat from the corresponding bare dies 104 and 204 to the cover 702.

[0060] The graphite thermal interface material (TIM) layer 106 may include graphite filler embedded in the substrate, wherein the graphite filler has a vertically stacked structure (the filler direction extends vertically). As described herein, the vertically stacked structure improves heat distribution in the vertical direction. In other embodiments, the graphite filler has a horizontally stacked structure (the filler direction extends horizontally). For example, because vertically stacked structures may be more sensitive to downward pressure than horizontally stacked structures, horizontally stacked structures are used in some cases for applications that are more sensitive to force. The substrate material of the graphite thermal interface material (TIM) layer 106 may be a polymer, resin, or other suitable material. The graphite thermal interface material (TIM) layer 106 is non-adhesive and is held in place between the bare sheet 104 and the cap 702 by compressive force and / or by an adhesive thermal interface material (TIM) material (e.g., the adhesive thermal interface material (TIM) 116 described later).

[0061] The adhesive thermal interface material (TIM) layer 206 may also include a matrix material and a filler. However, the adhesive thermal interface material (TIM) layer 206 does not include graphite. The matrix material of the adhesive thermal interface material (TIM) layer 206 may include silicone, polyolefin, resin, or epoxy resin. The filler of the adhesive thermal interface material (TIM) layer 206 may be a dielectric filler, such as alumina, magnesium oxide, aluminum nitride, boron nitride, and / or diamond powder. Alternatively, the filler of the adhesive thermal interface material (TIM) layer 206 may be a metallic filler, such as silver, copper, aluminum, or the like. The adhesive thermal interface material (TIM) layer 206 may be a thermal adhesive or thermal gel, which cures under a curing process and becomes structurally rigid. In this way, the adhesive thermal interface material (TIM) layer 206 serves not only as a heat distributor but also as an adhesive film to bond between the bare sheet 204 and the cover 702.

[0062] Please refer to Figure 1The integrated circuit (IC) package assembly 100 also includes a cover 702 disposed on the upper surfaces of a graphite thermal interface material (TIM) layer 106 and an adhesive thermal interface material (TIM) layer 206. The cover 702 is secured to a peripheral frame 112, for example, via a matrix adhesive 113 on the upper surface of the peripheral frame 112. The matrix adhesive 113 can be made of any suitable material (e.g., epoxy resin, tape, etc.). In this way, the cover 702 is directly assembled to the peripheral frame 112 of the package substrate 102 via the matrix adhesive 113. Alternatively, the cover 702 can also be bonded to the die 204 via the adhesive thermal interface material (TIM) layer 206. In some embodiments, and as described in more detail below, an adhesive thermal interface material (TIM) 116 can also be disposed on the die 104, and the cover 702 is also adhesively bonded to the die 104 via the adhesive thermal interface material (TIM) 116.

[0063] Cover 702 (or metal cover 702) may be a metal cap serving as a cover for integrated circuit (IC) package assembly 100. In addition to serving as a cover, cover 702 also functions as a heat sink and heat absorber to absorb any heat dissipated from components of die 104 and 204. Cover 702 absorbs heat from die 104 and 204 through corresponding graphite thermal interface material (TIM) layer 106 and adhesive thermal interface material (TIM) layer 206. In embodiments with adhesive thermal interface material (TIM) 116, cover 702 also absorbs heat from die 104 from adhesive thermal interface material (TIM) 116. Cover 702 is formed of a metal or metal alloy having high thermal conductivity, for example, above about 100 W / m / K. For example, cover 702 may be formed of a metal or metal alloy selected from Al, Cu, Ni, Co, stainless steel, and alloys thereof. In one embodiment, cover 702 comprises a material similar to the peripheral frame 112. In another embodiment, the cover 702 and the peripheral frame 112 are part of a single cover structure, and the peripheral frame portion of the single cover structure is bonded to the encapsulation substrate 102 by a matrix adhesive 113.

[0064] Please refer to Figure 1The integrated circuit (IC) package assembly 100 also includes spacer frames 120 disposed along the sidewalls of the graphite thermal interface material (TIM) layer 106. If multiple graphite thermal interface material (TIM) layers 106 are present (e.g., multiple dies 104 are present on the package substrate 102), the multiple spacer frames 120 correspond to each of the multiple graphite thermal interface material (TIM) layers 106. However, the die 204 does not have a corresponding spacer frame 120. This is because the spacer frames 120 are designed as a specific conjugate solution for the graphite thermal interface material (TIM) layer 106, and this solution is not suitable for viscous thermal interface material (TIM) layers 206. For example, the spacer frames 120 have a larger elastic modulus than the graphite thermal interface material (TIM) layer 106, protecting the graphite thermal interface material (TIM) layer 106 from excessive compression. In one embodiment, the spacer frame 120 is a rigid material with an elastic modulus greater than approximately 3000 MPa. In this way, when the cover 702 presses down too forcefully, the cover 702 will stop compressing the graphite thermal interface material (TIM) layer 106 when it lands on the spacer frame 120. In other words, the graphite thermal interface material (TIM) layer 106 will only be pressed down (at most) until the cover 702 lands on the spacer frame 120. This allows the amount of compression of the graphite thermal interface material (TIM) to be designed according to the height of the spacer frame 120. Furthermore, the amount of compression can be designed to hold the graphite thermal interface material (TIM) layer 106 in place without the need for additional adhesive thermal interface material (TIM) 116 between the bare sheet 104 and the cover 702. In one embodiment, the spacer frame 120 comprises a material similar to the previously described peripheral frame 112.

[0065] Figures 2A-2C The diagrams show a perspective view, a plan view, and a cross-sectional view of a spacer frame integrated with a graphite thermal interface material (TIM) layer according to an embodiment of the present invention. Please refer to... Figure 2A A graphite thermal interface material (TIM) layer 106 is disposed above the central portion of the bare die 104. The graphite thermal interface material (TIM) layer 106 has a width W along the x-direction. G Length L along the y-direction G and the height H along the z-direction G Width W G and length L GThe exposed portion of the bare sheet 104 is smaller than its width and length. Therefore, the exposed portion of the bare sheet 104 extends along its periphery. These exposed portions provide a peripheral spacing for the spacer frame 120, allowing the spacer frame 120 to be placed on the bare sheet 104 along the sidewalls of the graphite thermal interface material (TIM) layer 106. The peripheral spacing can be defined by the area between the edge of the graphite thermal interface material (TIM) layer 106 and the edge of the bare sheet 104. In one embodiment, the graphite thermal interface material (TIM) layer 106 has a width W. G and length L G The graphite thermal interface material (TIM) layer 106 covers at least 90% of the area of ​​the bare die 104. However, the present invention is not limited to this. For example, as long as the graphite thermal interface material (TIM) layer 106 completely covers the hot spot area above the bare die 104, the graphite thermal interface material (TIM) layer 106 can cover a smaller area of ​​the bare die 104.

[0066] Please refer to this as well. Figure 2A and Figure 2B Note that the distance D1 between the edge of the graphite thermal interface material (TIM) layer 106 and the edge of the bare die 104 is at least greater than the thickness T of the spacer frame in the lateral directions (x and y). This provides sufficient space for placing the spacer frame 120 and the optional adhesive thermal interface material (TIM) 116. In one embodiment, the thickness T is designed to be as thin as possible (e.g., T < 1 mm) to avoid affecting the heat dissipation of the graphite thermal interface material (TIM) layer 106. The spacer frame 120 has a height H in the z-direction, a thickness T in the x and y directions, and encloses a region with an inner length L and an inner width W. The inner width W can be equal to or greater than the width WG of the graphite thermal interface material (TIM) layer 106. In other words, the spacer frame 120 can directly contact the sidewall of the graphite thermal interface material (TIM) layer 106 (i.e., L = L). G and / or W=W G Alternatively, there can be a certain gap between the spacer frame 120 and the graphite thermal interface material (TIM) layer 106 (i.e., L>L). G and / or W>W G In the illustrated embodiment, the spacer frame 120 completely surrounds the sidewalls of the graphite thermal interface material (TIM) layer 106 and includes corner portions extending diagonally from the corners of the spacer frame 120. This and other designs of the spacer frame 120 will be discussed in conjunction with… Figures 5A-5F Further details.

[0067] Please refer to Figure 2C The formed graphite thermal interface material (TIM) layer 106 can have a high H GThe formed spacer frame 120 can have a height H, and the height H is less than or equal to the height H. G (that is, H and H) G The ratio is less than or equal to 1. Height H should not be greater than height H. G Otherwise, when fixing the cover 702, the cover 702 can only rest on the spacer frame 120 and will not contact the graphite thermal interface material (TIM) layer 106. In other words, the spacer frame 120 is designed to prevent compression. Therefore, if H is greater than H G The spacer frame 120 will prevent the cover 702 from contacting the graphite thermal interface material (TIM) layer 106. In some embodiments, the graphite thermal interface material (TIM) layer 106 needs to be compressed to a certain extent (i.e., H and H). G The ratio must be less than 1. This compression improves surface contact and heat flow between the bare die 104 and the cover 702. To promote compression, the height H should be less than the height H'. G In this way, when the fixed cover 702 is in place, the graphite thermal interface material (TIM) layer 106 can be compressed downwards until it reaches height H. Therefore, height H cannot be too small. In one embodiment, the compression amount should not exceed height H. G This is because if the compression exceeds 50%, the graphite thermal interface material (TIM) layer 106 may be damaged. In this case, the height H should be at least greater than the height H. G Half of (i.e., H and H) G The ratio is greater than or equal to 0.5. In one embodiment, the height H of the spacer frame 120 is 0.5. H G ≤H≤H G In one embodiment, the height H of the spacer frame 120 is 0.5. H G ≤H <H G .

[0068] Figure 3 A flowchart of a method 300 for forming an integrated circuit (IC) package assembly 100 according to an embodiment of the present invention is shown. The IC package assembly 100 has a spacer frame 120 partially or completely integrated with a graphite thermal interface material (TIM) layer 106. Method 300 is configured to... Figure 4 To explain, Figure 4 illustrate Figure 3 This is part of method 300, including other process details for forming the spacer frame 120 on the die 104. Other operational steps may also be performed before, during, and after method 300, and for other embodiments of method 300, certain operational steps may be moved, replaced, or cancelled. It should be noted that in method 300, reference can be made to previous steps... Figure 1 and Figures 2A-2C The described feature components.

[0069] In step 302 of method 300, a bare die 104 is formed on the package substrate 102. It should be noted that more than one bare die 104 may be formed on the package substrate 102, and other bare dies 204 may also be formed on the package substrate 102. The bare dies 104 and 204 can be bonded on the package substrate 102 via controlled collapse chip interconnects (C4) as described above.

[0070] In step 304 of method 300, a graphite thermal interface material (TIM) layer 106 is formed on the bare die 104. The formed graphite thermal interface material (TIM) layer 106 has a height H G It should be noted that during this operation, method 300 can also form a viscous thermal interface material (TIM) layer 206 on the bare die 104. The corresponding thermal interface material (TIM) layer can be formed by any suitable deposition or coating process.

[0071] In step 306 of method 300, a spacer frame 120 is formed on the bare wafer and disposed along the sidewall of the graphite thermal interface material (TIM) layer 106. For the reasons previously described, the height H of the spacer frame 120 is equal to or less than the height H... G For further details regarding this procedure, please refer to [link / reference]. Figure 4As shown in the figure, operation step 306 includes placing the spacer frame 120 so that it at least partially surrounds the sidewalls of the graphite thermal interface material (TIM) layer 106. In the illustrated embodiment, the spacer frame 120 completely surrounds the graphite thermal interface material (TIM) layer 106. When placed, the spacer frame 120 may or may not contact the side surface of the graphite thermal interface material (TIM) layer 106, depending on the inner width W and inner length L of the spacer frame 120. In this embodiment, operation step 306 may also include applying an adhesive thermal interface material (TIM) 116 to the peripheral portion of the bare sheet 104 adjacent to the spacer frame 120. The adhesive thermal interface material (TIM) 116 may include a material similar to the adhesive thermal interface material (TIM) layer 206, and the adhesive thermal interface material (TIM) 116 facilitates the adhesion of the graphite thermal interface material (TIM) layer 106. For example, physical compression may not be sufficient to hold the graphite thermal interface material (TIM) layer 106 in place. The adhesive thermal interface material (TIM) 116 increases adhesion, resulting in better surface contact. The adhesive thermal interface material (TIM) 116 also provides additional structural support, preventing warping issues after curing. However, as previously mentioned, directly mixing the adhesive thermal interface material (TIM) 116 with the graphite thermal interface material (TIM) layer 106 may lead to defects due to the heterogeneous interface; therefore, the spacer frame 120 can provide appropriate isolation between the thermal interface materials (TIMs). In some embodiments, the adhesive thermal interface material (TIM) 116 is not required, and step 306 only involves placing the spacer frame 120.

[0072] In operation step 308 of method 300, a metal cover 702 is secured to the packaging substrate 102. The metal cover 702 can be secured to the packaging substrate 102 by adhesive bonding to the peripheral frame 112, by fastening to the peripheral frame 112, or by other securing methods. The metal cover 702 can also be bonded to the die 204 via an adhesive thermal interface material (TIM) layer 206, and / or via an adhesive thermal interface material (TIM) 116 (if present). In any case, operation step 308 includes securing the metal cover 702 so that the cover rests directly on the adhesive thermal interface material (TIM) layer 206, the graphite thermal interface material (TIM) layer 106, and / or the adhesive thermal interface material (TIM) 116. In one embodiment, operation step 308 includes compressing the graphite thermal interface material (TIM) layer 106 until the metal cover 702 presses against the upper surface of the spacer frame 120. In this embodiment, after the metal cover 702 is fixed, due to compression, the height H... GThe height H is such that the upper surfaces of the graphite thermal interface material (TIM) layer 106 and the spacer frame 120 are substantially coplanar. In other embodiments, the spacer frame 120 is designed as a safety feature to determine the maximum compression point. In these embodiments, the graphite thermal interface material (TIM) layer 106 does not need to be compressed to the maximum compression point. Therefore, the height H G It may still be greater than the height H after the fixed metal cover 702 is installed.

[0073] In operation step 310 of method 300, further operations are performed to form integrated circuit (IC) package assembly 100. For example, a heat sink structure is formed on a metal cover 702. In one embodiment, the heat sink structure may also be fixed to the package substrate 102. For example, another thermal interface material (TIM) layer may be formed between the metal cover and the heat sink structure. As part of operation step 310, integrated circuit (IC) package assembly 100 may be formed on a larger printed circuit board (PCB). In one embodiment, the heat sink structure may be fixed to the printed circuit board (PCB).

[0074] Figures 5A-5F Various configurations of the spacer frame 120 surrounding the graphite thermal interface material (TIM) layer 106 according to various embodiments of the present invention are shown. Figure 5A , Figure 5B and Figure 5D At least one spacer frame 120 is shown completely surrounding the sidewalls of the graphite thermal interface material (TIM) layer 106. These designs ensure maximum support for the graphite thermal interface material (TIM) to prevent over-compression. For example, in the event of any uneven distribution of compression, the portion of the spacer frame 120 always prevents over-compression. Figure 5C , Figure 5E and Figure 5F The spacer frames 120 are shown partially surrounding the sidewalls of the graphite thermal interface material (TIM) layer 106. These designs free up more space on the bare die 104 and allow for strategic placement of spacers and adhesive thermal interface material (TIM) 116 to target hot spots or compression points. In one embodiment, the adhesive thermal interface material (TIM) 116 (if present) is placed only in the spacers adjacent to the spacer frames 120. That is, there is no adjacent adhesive thermal interface material (TIM) 116 on the exposed sidewalls of the graphite thermal interface material (TIM) layer 106.

[0075] Please refer to now. Figure 5AThe spacer frame 120 also includes corner portions extending diagonally from the corners of the spacer frame 120. The corner portions may extend substantially at a 45-degree angle, and they provide additional contact support between the bare sheet 104 and the cover 702. This additional contact support prevents the bare sheet 104 and / or the cover 702 from bending or warping when thermal or physical stress is applied. Please now refer to... Figure 5B In some embodiments, the spacer frame 120 does not include corners.

[0076] Please refer to Figure 5C and Figure 5F As shown, the corners of the graphite thermal interface material (TIM) layer 106 are surrounded by spacer frames 120, while at least some sides are exposed. Please refer to... Figure 5C The exposed side can be one or more gaps in the spacer frame 120. Now please refer to Figure 5F The exposed side can be larger than Figure 5C Longer in some cases, for example, spanning almost the entire length or width of the thermal interface material (TIM) sidewall. Similar to Figure 5A , Figure 5F A spacer frame 120 with corner portions is shown, extending from the corners of the spacer frame 120. In the illustrated embodiment, the corner portions extend substantially at a 90-degree angle and provide additional contact support between the bare sheet 104 and the cover 702. Please refer to... Figure 5E Except for the corners of the graphite thermal interface material (TIM) layer 106, the spacer frame 120 completely surrounds the graphite thermal interface material (TIM) layer 106.

[0077] Please refer to now. Figure 5D The spacer frame 120 includes a first spacer ring 120a and a second spacer ring 120b. The first spacer ring 120a is similar to... Figure 5B The spacer frame 120 is used in the process. A first spacer ring 120a completely surrounds the sidewalls of the graphite thermal interface material (TIM) layer 106 and can directly contact the sidewalls of the TIM layer 106. A second spacer ring 120b completely surrounds the first spacer ring 120a, wherein the first spacer ring 120a and the second spacer ring 120b are spaced apart from each other. The advantage of these two rings is that they both support the graphite thermal interface material (TIM) layer 106 to prevent excessive compression (via the first spacer ring 120a) and provide overall contact support to prevent warping problems (via the second spacer ring 120b), while also reserving space for the adhesive thermal interface material (TIM) 116.

[0078] Figure 6 This diagram shows a cross-sectional view of a spacer frame 120 integrated with a graphite thermal interface material (TIM) layer 106 according to an embodiment of the present invention. Specifically, Figure 6 and Figure 5D The spacer frame configuration corresponds to the first spacer ring 120a and the second spacer ring 120b. In this configuration, the first spacer ring 120a has a height H1, while the second spacer ring 120b has a height H2, and the height H2 is greater than or equal to the height H1. The height H2 may be greater than the height H1 because the edges of the bare sheet 104 will warp more when the cover 702 is fixed to the graphite thermal interface material (TIM) layer 106. For example, the upper surface of the second spacer ring 120b will be subjected to greater physical and thermal stress than the upper surface of the first spacer ring 120a. Therefore, the second spacer ring 120b can be designed to have a higher height H2 for cushioning purposes, while the first spacer ring 120a only needs sufficient height to prevent excessive compression of the graphite thermal interface material (TIM) layer 106. In one embodiment, the spacer frame 120 has H1 and H2 such that 0.5 H G ≤ H1≤H2≤ H G It should be noted that in this embodiment, the height H G This refers to the height of the graphite thermal interface material (TIM) layer 106 before compression (i.e., before the cover 702 is fixed). After compression, the height H... G It can descend to heights H, H1, or H2.

[0079] Figure 7 Showing integrated circuit (IC) package components (e.g.) Figure 1 A cross-sectional schematic diagram of an integrated circuit (IC) package assembly 100 in the middle portion, the IC package assembly having a heat sink 702 placed on a spacer frame 120 of an integrated graphite thermal interface material (TIM) layer 106. As shown, after the sink 702 is fixed to the graphite thermal interface material (TIM) layer 106, the graphite thermal interface material (TIM) layer 106 can be opened from a height H. G Compressed to the height H, H1, or H2 described herein. It should be noted that in some embodiments, such as... Figure 7 As shown, due to the compression of the graphite thermal interface material (TIM) layer 106, the upper corner 106c of the TIM layer 106 may be compressed and extend laterally to the upper surface of the spacer frame 120. In other embodiments (not shown), the upper corner 106c is avoided by leaving more space between the sidewall of the spacer frame 120 and the sidewall of the TIM layer 106. The additional space can be used to accommodate possible lateral diffusion of the TIM layer 106 after the heat sink cover 702 is secured to the TIM layer 106.

[0080] While not limited to these features, this invention offers advantages for integrated circuit (IC) packaging components. One example of this advantage is the use of spacer frames to mitigate the weaknesses of graphite as a thermal interface material (TIM). Another example is surrounding the graphite TIM with spacer frames to control its thickness (or height) and prevent over-compression. Yet another example is combining spacer frames with adhesive TIM to improve adhesion and help control package warpage. Another example is using spacer frames to separate graphite TIM from adhesive TIM to avoid interface defects between dissimilar materials. A further advantage is the availability of various spacer frame configurations to meet design requirements.

[0081] One aspect of this utility model relates to an integrated circuit (IC) packaging assembly. The IC packaging assembly includes: a packaging substrate; a die assembled on the packaging substrate; a graphite thermal interface material (TIM) layer located on the die; a spacer frame located on the die and disposed along multiple sidewalls of the graphite thermal interface material (TIM) layer; an adhesive thermal interface material (TIM) layer located on the die and disposed along multiple outer sidewalls of the spacer frame; and a metal cover located on the graphite thermal interface material (TIM) layer. The spacer frame separates the adhesive thermal interface material (TIM) layer from the graphite thermal interface material (TIM) layer.

[0082] In one embodiment, the viscous thermal interface material (TIM) layer is a thermal gel or thermal adhesive having a matrix material and a filler. The matrix material includes silicone, polyolefin, resin, or epoxy resin. The filler includes alumina, magnesium oxide, aluminum nitride, boron nitride, or diamond powder.

[0083] In one embodiment, the integrated circuit (IC) package element further includes: a substrate adhesive located on a peripheral frame of the package substrate. A metal cap is secured to the peripheral frame by the substrate adhesive. The metal cap is secured to the die by an adhesive thermal interface material (TIM) layer.

[0084] In one embodiment, the metal cover rests directly on the graphite thermal interface material (TIM) layer and the spacer frame.

[0085] In one embodiment, the spacer frame encloses a region having an inner length and an inner width. The inner length is greater than the length of the graphite thermal interface material (TIM) layer, and the inner width is greater than the width of the graphite thermal interface material (TIM) layer.

[0086] In one embodiment, the elastic modulus of the spacer frame is greater than that of the graphite thermal interface material (TIM) layer.

[0087] In one embodiment, the spacer frame completely surrounds the graphite thermal interface material (TIM) layer, except for the corners of the TIM layer.

[0088] In one embodiment, the spacer frame includes: a first ring completely surrounding the graphite thermal interface material (TIM) layer; and a second ring completely surrounding the first ring, wherein the first ring and the second ring are spaced apart from each other.

[0089] In one embodiment, the graphite thermal interface material (TIM) layer includes graphite filler embedded in a matrix material, and the graphite filler has a vertically stacked structure.

[0090] Another aspect of this utility model relates to an integrated circuit (IC) packaging assembly. The IC packaging assembly includes: a packaging substrate; a first die assembled on the packaging substrate; a first thermal interface material (TIM) layer disposed on the center of the first die; a spacer frame disposed on multiple peripheral portions of the first die and along multiple sidewalls of the first TIM layer; a second die assembled on the packaging substrate; a second TIM layer disposed on the center of the second die; and a metal cover disposed on the first and second TIM layers. The first and second TIM layers comprise different materials.

[0091] In one embodiment, the first thermal interface material (TIM) layer comprises graphite, while the second thermal interface material (TIM) layer comprises aluminum, magnesium, boron, diamond, or silver.

[0092] In one embodiment, the integrated circuit (IC) package assembly further includes: an adhesive disposed on a first die and along a plurality of outer sidewalls of a spacer frame. The spacer frame separates the adhesive from a first thermal interface material (TIM) layer. The adhesive bonds a metal cap to the first die.

[0093] In one embodiment, the first thermal interface material (TIM) layer is substantially coplanar with the upper surface of the spacer frame.

[0094] In one embodiment, the spacer frame completely surrounds the first thermal interface material (TIM) layer. In another embodiment, the spacer frame includes a plurality of corner portions extending diagonally from the corners of the spacer frame.

[0095] In one embodiment, the spacer frame only partially surrounds the first thermal interface material (TIM) layer.

[0096] Another aspect of this utility model relates to a method for forming an integrated circuit (IC) package assembly. The method includes: forming a die on a package substrate; forming a graphite thermal interface material (TIM) layer on the die; forming a spacer frame on the die and along multiple sidewalls of the TIM layer; and fixing a metal cover to the package substrate, wherein the metal cover rests directly on the upper surface of the TIM layer and the spacer frame.

[0097] In one embodiment, forming the spacer frame further includes: placing the spacer frame to at least partially surround a plurality of sidewalls of a graphite thermal interface material (TIM) layer; and coating a spacer frame with an adhesive thermal interface material (TIM) adjacent to a plurality of peripheral portions of the bare die.

[0098] In one embodiment, the formed graphite thermal interface material (TIM) layer has a first height, the formed spacer frame has a second height, and the first height is greater than the second height. In another embodiment, fixing the metal cover includes compressing the graphite thermal interface material (TIM) layer until the metal cover is pressed against the upper surface of the spacer frame, wherein after fixing the metal cover, the first height becomes the second height.

[0099] Details of the device of this utility model will be described in the accompanying drawings. The foregoing has outlined the characteristic components of several embodiments of this utility model, enabling those skilled in the art to more readily understand its form. Those skilled in the art will understand that this utility model can be readily used as a basis for modifications or designs to other processes or structures to achieve the same purpose and / or obtain the same advantages as the embodiments described herein. Those skilled in the art will also understand that equivalent structures as described above do not depart from the spirit and scope of this utility model, and that modifications, substitutions, and refinements can be made without departing from its spirit and scope.

Claims

1. An integrated circuit package assembly, comprising: include: One packaging substrate; A bare die is assembled onto this packaging substrate; A graphite thermal interface material layer is located on the bare wafer; A spacer frame is located on the bare sheet and is disposed along multiple sidewalls of the graphite thermal interface material layer; A layer of viscous thermal interface material is located on the bare sheet and disposed along a plurality of outer sidewalls of the spacer frame; and A metal cover is located on the graphite thermal interface material layer, wherein the spacer frame separates the viscous thermal interface material layer from the graphite thermal interface material layer.

2. The integrated circuit package assembly of claim 1, wherein, Also includes: A base adhesive is located on a peripheral frame of the encapsulation substrate. The metal cover is fixed to the peripheral frame by the base adhesive, and The metal cover is fixed to the bare sheet by the viscous thermal interface material layer.

3. The integrated circuit package assembly of claim 1, wherein, The metal cover rests directly on the graphite thermal interface material layer and the spacer frame.

4. The integrated circuit package assembly of claim 1 or 2, wherein, Except for several corners of the graphite thermal interface material layer, the spacer frame completely surrounds the graphite thermal interface material layer.

5. The integrated circuit packaging assembly as described in claim 1 or 2, characterized in that, The interval frame includes: The first ring completely surrounds the graphite thermal interface material layer; and A second ring completely surrounds the first ring, wherein the first ring and the second ring maintain a distance from each other.

6. An integrated circuit package assembly, comprising: include: One packaging substrate; A first bare die is assembled onto the packaging substrate; A first thermal interface material layer is disposed on a central portion of the first bare wafer; A spacer frame is disposed on multiple peripheral portions of the first bare sheet and along multiple sidewalls of the first thermal interface material layer; A second die is assembled onto the packaging substrate; A second thermal interface material layer is disposed on a central portion of the second bare wafer; as well as A metal cover is disposed on the first thermal interface material layer and the second thermal interface material layer.

7. The integrated circuit package assembly of claim 6, wherein, Also includes: An adhesive is disposed on the first bare sheet and along a plurality of outer sidewalls of a spacer frame, wherein the spacer frame separates the adhesive from the first thermal interface material layer, and wherein the adhesive bonds the metal cover to the first bare sheet.

8. The integrated circuit package assembly of claim 6 or 7, wherein, The spacer frame completely surrounds the first thermal interface material layer.

9. The integrated circuit package assembly of claim 8, wherein, The partition frame includes multiple corner sections that extend diagonally from the multiple corner sections of the partition frame.

10. The integrated circuit package assembly of claim 6 or 7, wherein, The spacer frame only partially surrounds the first thermal interface material layer.

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