Semiconductor structure and forming method thereof
By using sacrificial layers of different materials in complementary field-effect transistors and controlling the etching depth, the problem of inadequate control of device region boundaries was solved, thereby improving the stability and performance of semiconductor structures.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-24
- Publication Date
- 2026-03-27
AI Technical Summary
When complementary field-effect transistors (CFETs) are stacked vertically with PMOS and NMOS, improper control of the device region boundaries can lead to problems such as unstable device threshold voltage and increased leakage current.
Using a first sacrificial layer and a second sacrificial layer made of different materials, with an etching selectivity greater than 1, the first sacrificial layer is selectively removed by etching while the second sacrificial layer is retained. The etching depth is controlled to avoid damaging the first device region, forming a first gate structure located on one side of the device region boundary. This ensures the stability of the second device region boundary during subsequent filling with work function material.
Effective control of device region boundaries avoids instability of device threshold voltage and increase of leakage current, thereby improving the stability and performance of semiconductor structures.
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Figure CN121751734A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present disclosure relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND
[0002] With the rapid development of semiconductor technology, semiconductor devices are developing towards higher component density and higher integration. The semiconductor device architecture has encountered challenges in the microscale. In order to better adapt to the requirement of device size scaling, semiconductor processes have gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as GAA (Gate-all-around) transistors, NSFET (Nanosheet Field-Effect Transistor), fork gate transistors, CFET (Complementary Field-Effect Transistors), etc. Among them, complementary field-effect transistors have become one of the candidate device architectures due to their greater scaling potential.
[0003] Complementary field-effect transistors optimize space utilization by stacking PMOS (P-channel metal-oxide-semiconductor field-effect transistor) and NMOS (N-channel metal-oxide-semiconductor field-effect transistor) in the vertical direction. However, the performance of complementary field-effect transistors still needs to be improved. SUMMARY
[0004] To solve the above problems, embodiments of the present disclosure provide a semiconductor structure and a forming method thereof to improve the performance of semiconductor devices.
[0005] Embodiments of the present disclosure provide a semiconductor structure forming method, comprising:
[0006] A base structure is provided, which includes a first device region and a second device region stacked vertically, the first device region has a plurality of first devices vertically separated and a plurality of first sacrificial layers surrounding the first devices, the second device region has a plurality of second devices vertically separated and a plurality of second sacrificial layers surrounding the second devices, the etching selectivity ratio of the materials of the first sacrificial layers and the second sacrificial layers is greater than 1, and the first sacrificial layers and the second sacrificial layers have a device region boundary therebetween;
[0007] The first sacrificial layers are removed, and a first work function material is filled in the first device region and the second device region;
[0008] removing the first work function material in the second device region to form a first gate structure surrounding the first device, the first gate structure being located at one side of the device region boundary;
[0009] removing the second sacrificial layer, filling the second work function material in the second device region to form a second gate structure surrounding the second device, the second gate structure being located at the other side of the device region boundary opposite to the first gate structure.
[0010] The embodiment of the present disclosure further provides a semiconductor structure, comprising:
[0011] a first device region, the first device region having a plurality of vertically discrete first devices and a first gate structure surrounding the first devices;
[0012] a second device region vertically stacked with the first device region, the second device region having a plurality of vertically discrete second devices and a second gate structure surrounding the second devices, the first device region and the second device region having a device region boundary.
[0013] The embodiment of the present disclosure provides a semiconductor structure and a forming method thereof. Different materials are applied to the first sacrificial layer and the second sacrificial layer in the base structure, and the etching selectivity ratio of the two is greater than 1. When the first sacrificial layer is removed, the second sacrificial layer is retained. When the first work function material is filled subsequently, the second sacrificial layer ensures that the second devices are not filled with the first work function material. Therefore, when the first work function material in the second device region is removed, the etching depth can be better controlled, and the first devices in the first device region are prevented from being damaged. The first gate structure is finally formed at one side of the device region boundary, that is, the device region boundary is controlled, and the stability of the semiconductor structure is improved. BRIEF DESCRIPTION OF DRAWINGS
[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are only embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of the provided drawings.
[0015] Figures 1 to 5 is a structure schematic diagram corresponding to each step in a semiconductor structure forming method of the prior art.
[0016] Figures 6 to 26 is a structure schematic diagram corresponding to each step in a semiconductor structure forming method provided by the embodiment of the present disclosure. DETAILED DESCRIPTION
[0017] As the background technology shows, the performance of complementary field-effect transistors (CFPTs) still needs improvement. This paper analyzes the reasons for this performance limitation in conjunction with a semiconductor structure formation method.
[0018] Complementary field-effect transistors (CFETs) optimize space utilization by vertically stacking PMOS and NMOS transistors. In the manufacturing process of CFETs, there is a boundary between the NMOS and PMOS regions. Improper control of this boundary can lead to problems such as unstable threshold voltage and increased leakage current, affecting the performance of the CFET device.
[0019] Specifically, Figures 1 to 5 This is a schematic diagram of the structure corresponding to each step in an existing semiconductor structure formation method.
[0020] First, in an existing method for forming a complementary field-effect transistor, it is necessary to... Figure 1 The substrate structure shown is processed, the substrate structure includes a plurality of vertically discrete first devices 101, a plurality of vertically discrete second devices 201 and a plurality of sacrificial layers 2, the sacrificial layers 2 surrounding the first devices 101 and the second devices 201; the device region boundary 3 is used as a virtual boundary to distinguish the regions where the first devices 101 and the second devices 201 are located.
[0021] In some specific embodiments, the first device 101 and the second device 201 are MOSFETs of different types. For example, the first device 101 is a PMOS and the second device 201 is an NMOS; or, the first device 101 is an NMOS and the second device 201 is a PMOS. Further, either the first device 101 or the second device 201 can be a nanosheet transistor. The material of the sacrificial layer 2 is a commonly used sacrificial layer material in semiconductor processes, such as Si3N4, SiO2, etc. In some embodiments, the material of the sacrificial layer 2 can be SiGe.
[0022] Next, the sacrificial layer 2 needs to be removed to form multiple channels between the multiple first devices 101, between the multiple second devices 201, and between the first devices 101 and the second devices 201, facilitating subsequent filling with work function material. The semiconductor structure after removing the sacrificial layer 2 is as follows: Figure 2 As shown, the removal of the sacrificial layer 2 can be achieved through an etching process.
[0023] After removing the sacrificial layer 2, the substrate structure is filled with a work function material 4, such as... Figure 3As shown, the work function material 4 surrounds the first device 101 and the second device 201. The work function material 4 is used to adjust the threshold voltage of the devices and improve device performance. Since different types of devices require different work function materials for adjustment, and the work function material 4 is used to adjust the threshold voltage of the first device 101, after filling the work function material 4, it is necessary to remove the unnecessary parts of the work function material so that the work function material 4 only surrounds the first device 101.
[0024] However, the process of removing unwanted portions of the work function material requires multiple etching operations on the semiconductor structure, for example, as... Figure 4 As shown, etching is first performed from the top of the substrate structure downwards to remove the work function material 4 on both sides of the second device 201. At this point, there is still unwanted work function material 4 in the channel between the second devices 201. Therefore, etching is also performed from the left and right sides of the second device 201 to remove the work function material 4 in the channel between the second devices 201, forming a structure as shown. Figure 5 The semiconductor structure shown.
[0025] During the above process, the work function material is inevitably over-etched. The work function material 4 cannot cover the first device 101 closest to the device region boundary 3. After subsequent filling of the area where the second device 201 is located with other work function materials, the device region boundary 3 cannot distinguish the areas where the first device 101 and the second device 201 are located. Furthermore, etching the work function material 4 may also damage the first device 101. Figure 5 As shown, the actual device region boundary is not located on the device region boundary 3. This situation will lead to problems such as unstable device threshold voltage and increased leakage current, affecting the performance of complementary field-effect transistor devices.
[0026] It is evident that in one existing method for forming a complementary field-effect transistor, the actual device region boundary between the NMOS and PMOS regions changes, leading to problems such as unstable device threshold voltage and increased leakage current, thus affecting the performance of the complementary field-effect transistor device.
[0027] To address the aforementioned issues, this disclosure provides a semiconductor structure formation method in which different materials are applied to a first sacrificial layer and a second sacrificial layer in the substrate structure, and the etching selectivity ratio between the two is greater than 1. When the first sacrificial layer is removed, the second sacrificial layer is retained. When the first work function material is subsequently filled, the second sacrificial layer ensures that the space between the second devices is not filled with the first work function material. Therefore, when removing the first work function material in the region of the second device, the etching depth can be better controlled, avoiding damage to the first device in the region of the first device. The first gate structure finally formed is located on one side of the device region boundary, that is, the device region boundary is controlled, improving the stability of the semiconductor structure.
[0028] To make the above-mentioned objects, features and advantages of this disclosure more apparent and understandable, specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.
[0029] Figures 6 to 26 This is a schematic diagram of the structure corresponding to each step in the semiconductor structure formation method provided in the embodiments of this disclosure.
[0030] like Figure 6 As shown, in the semiconductor structure formation method provided in the embodiments of this disclosure, firstly, a substrate structure is provided, the substrate structure including a first device region and a second device region stacked vertically, the first device region having a plurality of vertically discrete first devices 101 and a plurality of first sacrificial layers 102 surrounding the first devices 101, the second device region having a plurality of vertically discrete second devices 201 and a plurality of second sacrificial layers 202 surrounding the second devices 201, the etching selectivity ratio of the materials of the first sacrificial layer 102 and the second sacrificial layer 202 being greater than 1, and a device region boundary 3 being between the first sacrificial layer 102 and the second sacrificial layer 202.
[0031] In some embodiments, the materials of the first sacrificial layer 102 and the second sacrificial layer 202 are both SiGe materials, wherein the concentration of Ge in the material of the first sacrificial layer 102 is less than the concentration of Ge in the material of the second sacrificial layer 202, and the etching selectivity ratio of the first sacrificial layer 102 to the second sacrificial layer 202 is greater than 10.
[0032] Due to the characteristics of the SiGe material, the higher the Ge concentration, the slower the etching rate in the semiconductor structure forming method provided by the embodiments of the present disclosure. Specifically, wet etching can be used to etch the first sacrificial layer 102 and the second sacrificial layer 202. On this premise, the material of the first sacrificial layer 102 is expressed as Si1-xGex, and the material of the second sacrificial layer 202 is expressed as Si1-yGey, where 0 < x < y ≤ 1. By adjusting the values of x and y, that is, setting the Ge concentration in the materials of the first sacrificial layer 102 and the second sacrificial layer 202, the etching selectivity ratio of the first sacrificial layer 102 to the second sacrificial layer 202 can be greater than 10, improving the precision of the semiconductor structure process.
[0033] In some embodiments, the threshold voltages at which the first device 101 and the second device 201 operate are both the first threshold voltage.
[0034] Based on the substrate structure as Figure 6 shown, the first sacrificial layer 102 is removed. Specifically, as Figure 7 shown, the first sacrificial layer 102 is etched, and a plurality of first channels are formed between the plurality of first devices 101 and between the first device 101 and the second sacrificial layer 202. The first channels are spaces obtained by etching the first sacrificial layer 102 and are used to fill a work function material subsequently.
[0035] After forming the plurality of first channels, a first work function material 110 is filled in the first device region and the second device region.
[0036] Specifically, as Figure 8 shown, the first work function material 110 is filled in the first channels and the second device region, where the first work function material 110 surrounds the first device 101, the second device 201, and the second sacrificial layer 202. The first work function material 110 is used to adjust the threshold voltage of the first device 101 and improve the performance of the first device 101. The first work function material 110 can specifically be one or more of W, Cu, Ti, Ag, Pt, and Ni. When including multiple materials, the first work function material 110 is a composite of multiple materials of W, Cu, Ti, Ag, Pt, and Ni or an alloy thereof.
[0037] When filling the first work function material 110, since the second device 201 is surrounded by the second sacrificial layer 202, the first work function material 110 is only filled outside the second device 201 surrounded by the second sacrificial layer 202 in the second device region, which can avoid etching the work function material around the second device 201 in the vertical direction in subsequent processes and ensure the control of the device region boundary.
[0038] After filling the first work function material 110 in the first device region and the second device region, the first work function material 110 in the second device region is removed to form a first gate structure 111 surrounding the first device 101.
[0039] Specifically, such as Figure 9 As shown, a first work function material 110 is etched within the second device region to form a first gate structure 111 within the first device region, the first gate structure 111 surrounding the first device 101. The first gate structure 111, located within the first device region and formed according to the first work function material 110, is used to adjust the threshold voltage of the first device 101, improving its performance. Furthermore, during the etching of the first work function material 110, the second sacrificial layer 202 acts as a protective layer to prevent the work function material below the device region boundary 3 from being etched. The etched first gate structure 111 is located on one side of the device region boundary 3, and the device region boundary 3 is not offset.
[0040] After forming the first gate structure 111, the second sacrificial layer 202 also needs to be removed. Specifically, as shown in... Figure 10 As shown, the second sacrificial layer 202 is etched to form a plurality of second channels between the plurality of second devices 201 and between the second devices 201 and the first gate structure 111. The second channels are the spaces obtained by etching the second sacrificial layer 202 and are used for subsequent filling with work function material.
[0041] After forming multiple second channels, a second work function material is filled in the region of the second device to form a second gate structure 211 surrounding the second device 201. Specifically, as shown... Figure 11 As shown, a second work function material is filled in the second channel to form a second gate structure 211, and the second gate structure 211 surrounds the second device 201.
[0042] The second gate structure 211 is located within the second device region and is formed according to the second work function material. It is used to adjust the threshold voltage of the second device 201 and improve its performance. The material of the second gate structure 211, i.e., the second work function material, can be one or more of W, Cu, Ti, Ag, Pt, and Ni. When multiple materials are included, the second work function material is a composite or alloy of multiple materials selected from W, Cu, Ti, Ag, Pt, and Ni. Furthermore, the threshold voltage of the second work function material is the same as the threshold voltage of the first work function material 110, meaning that the second device 201 and the first device 101 operate at the same threshold voltage.
[0043] The second gate structure 211 is located on the other side of the device region boundary 3 opposite to the first gate structure 111. That is, one side of the device region boundary 3 is the first gate structure 111, and the other side is the second gate structure 211. It can be seen that the device region boundary 3 is controlled, avoiding the problems of unstable device threshold voltage and increased leakage current caused by the offset of the device region boundary, thus improving the stability of the semiconductor structure.
[0044] In such Figure 11 In the semiconductor structure shown, the second device 201 and the first device 101 operate at the same threshold voltage. However, in scenarios where devices in the same structure need to operate at different threshold voltages, to expand the application scenarios of the semiconductor structure, in some embodiments, device regions with different threshold voltages can be added.
[0045] In some implementations, such as Figure 12 As shown, the substrate structure further includes a third device region and a fourth device region stacked vertically. The third device region is adjacent to the first device region in the horizontal direction, and the fourth device region is adjacent to the second device region in the horizontal direction. The third device region has a plurality of vertically discrete third devices 301 and a third sacrificial layer 302 surrounding the third devices 301. The fourth device region has a plurality of vertically discrete fourth devices 401 and a fourth sacrificial layer 402 surrounding the fourth devices 401. The etching selectivity ratio of the materials of the third sacrificial layer 302 and the fourth sacrificial layer 402 is greater than 1.
[0046] In some specific embodiments, the third device 301 and the fourth device 401 are MOSFETs of different types, and the third device 301 is the same as the first device 101, and the fourth device 401 is the same as the second device 201. For example, the first device 101 and the third device 301 are both PMOS, and the second device 201 and the fourth device 401 are both NMOS; or, the first device 101 and the third device 301 are both NMOS, and the second device 201 and the fourth device 401 are both PMOS. Further, either the first device 101 or the second device 201 can be a nanosheet transistor.
[0047] The material of the third sacrificial layer 302 is the same as that of the first sacrificial layer 102, and the material of the fourth sacrificial layer 402 is the same as that of the second sacrificial layer 202. That is, the materials of the third sacrificial layer 302 and the fourth sacrificial layer 402 are SiGe materials with different concentrations. The concentration of Ge in the material of the third sacrificial layer 302 is the same as that of the first sacrificial layer 102 and is less than that of the material of the second sacrificial layer 202. The concentration of Ge in the material of the fourth sacrificial layer 402 is the same as that of the second sacrificial layer 202.
[0048] In some embodiments, the threshold voltage at which the third device 301 and the fourth device 401 operate is a second threshold voltage, which is different from the first threshold voltage.
[0049] Based on such Figure 12 The base structure shown is as follows: Figure 13 As shown, a first mask 501 is formed in the third device region and the fourth device region, the first mask 501 surrounding the third device 301, the third sacrificial layer 302, the fourth device 401, and the fourth sacrificial layer 402. In some specific embodiments, the material of the first mask 501 can be one or more combinations of PR (Photoresist), BARC (Bottom Anti-Reflection Coating), and SOC (Spin-On-Carbon). The first mask 501 is used to protect the devices and sacrificial layers in the third and fourth device regions from etching during the subsequent removal of the first sacrificial layer 102.
[0050] After forming the first mask 501, the first sacrificial layer 102 is removed. Specifically, as follows: Figure 14 As shown, the first sacrificial layer 102 is etched to form a plurality of first channels between the plurality of first devices 101, and between the first devices 101 and the second sacrificial layer 202. The first channels are spaces obtained by etching the first sacrificial layer 102 and are used for subsequent filling with work function material.
[0051] After removing the first sacrificial layer 102, the first mask 501 is removed, and the first work function material 110 is filled. Specifically, as shown... Figure 15As shown, when the first work function material 110 is filled in the first device region and the second device region, the first work function material 110 is also filled in the third device region and the fourth device region. At this time, the first work function material 110 surrounds the first device 101, the second device 201, the third device 301, the fourth device 401, the second sacrificial layer 202, the third sacrificial layer 302, and the fourth sacrificial layer 402. Specifically, the first work function material 110 can be one or more of W, Cu, Ti, Ag, Pt, and Ni. When multiple materials are included, the first work function material 110 is a composite or alloy of multiple materials selected from W, Cu, Ti, Ag, Pt, and Ni.
[0052] After filling with the first work function material 110, the first work function material 110 is removed from the second device region and the fourth device region. Specifically, as follows: Figure 16 As shown, the first work function material 110 in the second device region and the fourth device region is etched until the first work function material 110 above the boundary 3 of the device region is etched away, while the first work function material 110 in the first device region and the third device region is retained, providing a basis for the subsequent formation of the first gate structure 111.
[0053] Furthermore, during the etching of the first work function material 110 in the second and fourth device regions, the second sacrificial layer 202 and the fourth sacrificial layer 402 serve as protective layers to prevent the work function material below the device region boundary 3 from being etched.
[0054] After removing the first work function material 110 from the second device region and the fourth device region, a first gate structure 111 surrounding the first device 101 needs to be formed. Specifically, as shown... Figure 17 As shown, a second mask 502 needs to be formed in the second device region first. The second mask 502 surrounds the second device 201 and the second sacrificial layer 202. The second mask 502 is used to protect the work function material in the second device region from being etched during the subsequent formation of the first gate structure 111. In some specific embodiments, the material of the second mask 502 can be one or more combinations of PR, BARC, and SOC.
[0055] After forming the second mask 502, a first gate structure 111 surrounding the first device 101 can be formed, specifically, as shown in the figure. Figure 17As shown, a first work function material 110 is etched within the third device region to form the first gate structure 111 within the first device region, wherein the etching direction of the first work function material 110 is from top to bottom. The first gate structure 111 is located within the first device region and is formed based on the first work function material 110 to adjust the threshold voltage of the first device 101, thereby improving the performance of the first device 101. Furthermore, during the etching of the first work function material 110, the second mask 502 serves as a protective layer to prevent the work function material below the device region boundary 3 from being etched, and the etched first gate structure 111 is located on one side of the device region boundary 3.
[0056] After forming the first gate structure 111 surrounding the first device 101, the third sacrificial layer 302 needs to be removed, and the third work function material 310 is filled in the third device region to form the third gate structure 311 surrounding the third device 301.
[0057] Specifically, such as Figure 18 As shown, the third sacrificial layer 302 is etched to form a plurality of third channels between the plurality of third devices 301, and between the third devices 301 and the fourth sacrificial layer 402. The third channels are spaces obtained by etching the third sacrificial layer 302 and are used for subsequent filling with work function material. Before or after forming the plurality of third channels, the second mask 502 is removed to prevent it from interfering with subsequent processes.
[0058] Next, a third work function material 310 is filled into the third device region. Specifically, as shown... Figure 19 As shown, a third work function material 310 is filled in the third channel, the second device region, and the fourth device region. The third work function material 310 surrounds the second device 201, the third device 301, the fourth device 401, the second sacrificial layer 202, and the fourth sacrificial layer 402. The third work function material 310 is used to adjust the threshold voltage of the third device 301 and improve its performance. Specifically, the third work function material 310 can be one or more of W, Cu, Ti, Ag, Pt, and Ni. When multiple materials are included, the third work function material 310 is a composite or alloy of multiple materials selected from W, Cu, Ti, Ag, Pt, and Ni.
[0059] When filling the third work function material 310, since the second device 201 is surrounded by the second sacrificial layer 202, the third work function material 310 is only filled on the outside of the second device region where the second device 201 is surrounded by the second sacrificial layer 202. Similarly, the third work function material 310 is only filled on the outside of the fourth device 401 in the fourth device region where the fourth device 401 is surrounded by the fourth sacrificial layer 402. This avoids etching the work function material around the second device 201 and the fourth device 401 in the vertical direction in subsequent processes, thus ensuring control of the device region boundary.
[0060] In some specific embodiments, chemical mechanical polishing (CMP) is required after filling the third work function material 310 to ensure the flatness of the top of the third work function material 310 and improve the performance of the CFET.
[0061] After filling the third work function material 310, a third gate structure 311 surrounding the third device 301 needs to be formed. Specifically, as shown... Figure 20 As shown, the third work function material 310 in the second and fourth device regions is etched to form the third gate structure 311 in the third device region, which surrounds the third device 301. The third gate structure 311 is located within the third device region and is formed based on the third work function material 310. It is used to adjust the threshold voltage of the third device 301 and improve its performance. Furthermore, during the etching of the third work function material 310, the fourth sacrificial layer 402 serves as a protective layer to prevent the third work function material below the device region boundary 3 from being etched. The etched third gate structure 311 and the first gate structure 111 are located on the same side of the device region boundary 3.
[0062] After forming the first gate structure 111 and the third gate structure 311, it is necessary to remove the second sacrificial layer and fill the second work function material in the second device region to form a second gate structure surrounding the second device.
[0063] Specifically, such as Figure 21 As shown, a third mask 503 is first formed in the fourth device region, surrounding the fourth device 401 and the fourth sacrificial layer 402. The third mask 503 protects the device and sacrificial layer in the fourth device region from etching during the subsequent formation of the second gate structure 211. In some specific embodiments, the material of the third mask 503 can be one or more combinations of PR, BARC, and SOC.
[0064] After forming the third mask 503, the second sacrificial layer 202 is removed. Specifically, as follows:Figure 22 As shown, the second sacrificial layer 202 is etched to form a plurality of second channels between the plurality of second devices 201 and between the second devices 201 and the first gate structure 111. The second channels are spaces obtained by etching the second sacrificial layer 202 and are used for subsequent filling with a second work function material.
[0065] After forming multiple second channels, the third mask 503 also needs to be removed to avoid affecting subsequent processes.
[0066] After removing the third mask 503, as follows Figure 23 As shown, a second work function material 210 is simultaneously filled in both the second device region and the fourth device region. Specifically, the second work function material 210 can be one or more of W, Cu, Ti, Ag, Pt, and Ni. When multiple materials are included, the second work function material 210 is a composite or alloy of multiple materials selected from W, Cu, Ti, Ag, Pt, and Ni. Furthermore, the threshold voltage of the second work function material 210 is the same as the threshold voltage of the first work function material 110, meaning that the second device 201 and the first device 101 operate at the same threshold voltage.
[0067] After filling the second work function material 210, a second gate structure 211 needs to be formed in the second device region. Specifically, as shown... Figure 24 As shown, a second work function material 210 is etched within the fourth device region to form a second gate structure 211 surrounding the second device 201 within the second device region. The second gate structure 211 also serves to adjust the threshold voltage of the second device 201, thereby improving the performance of the second device 201.
[0068] After forming the second gate structure 211 surrounding the second device 201, the fourth sacrificial layer 402 needs to be removed to form the fourth gate structure 411 in the fourth device region.
[0069] Specifically, such as Figure 25 As shown, the fourth sacrificial layer is etched to form a plurality of fourth channels between the plurality of fourth devices 401 and between the fourth devices 401 and the third device region. The fourth channels are spaces obtained by etching the fourth sacrificial layer 402 and are used for subsequent filling with a fourth work function material.
[0070] After multiple fourth channels are formed, such as Figure 26As shown, a fourth work function material is filled in the fourth device region to form a fourth gate structure 411 surrounding the fourth device 401. The fourth gate structure 411 is located on the same side of the device region boundary 3 as the second gate structure 211. The fourth gate structure 411 is located in the fourth device region and is used to adjust the threshold voltage of the fourth device 401 to improve the performance of the fourth device 401. The material of the fourth gate structure 411, i.e., the fourth work function material, can specifically be one or more of W, Cu, Ti, Ag, Pt, and Ni. When multiple materials are included, the fourth work function material is a composite or alloy of multiple materials selected from W, Cu, Ti, Ag, Pt, and Ni.
[0071] Based on the above steps, the final semiconductor structure can be obtained. The semiconductor structure has four device regions, wherein the threshold voltage for the operation of the first device 101 and the second device 301 is the first threshold voltage, and the threshold voltage for the operation of the second device 201 and the fourth device 401 is the second threshold voltage.
[0072] As can be seen, different materials are applied to the sacrificial layers in the four device regions of the substrate structure, and the etching selectivity ratio between the first sacrificial layer 102 and the second sacrificial layer 202 is greater than 1, as is the etching selectivity ratio between the third sacrificial layer 302 and the fourth sacrificial layer 402. By using a mask and adjusting the etching sequence, the sacrificial layers inside the device regions are removed sequentially in the order of the first device region, the third device region, the second device region, and the fourth device region in the substrate structure, forming the corresponding gate structures. The above steps can better control the etching depth and avoid damage to the devices in each device region. The first gate structure 111 and the third gate structure 311 are finally located on the same side of the device region boundary, while the second gate structure 211 and the fourth gate structure 411 are located on the other side of the device region boundary. That is, the device region boundary is controlled, further improving the stability of the semiconductor structure.
[0073] This disclosure also provides a semiconductor structure, including:
[0074] A first device region having a plurality of vertically discrete first devices 101 and a first gate structure 111 surrounding the first devices 101;
[0075] A second device region is stacked perpendicularly to the first device region. The second device region has a plurality of vertically separated second devices 201 and a second gate structure 211 surrounding the second devices 201. A device region boundary 3 is provided between the first device region and the second device region.
[0076] In some embodiments, the semiconductor structure further includes:
[0077] The third device region is horizontally adjacent to the first device region. The third device region has a plurality of vertically discrete third devices 301 and a third gate structure 311 surrounding the third devices 301.
[0078] A fourth device region is stacked vertically to the third device region. The fourth device region is adjacent to the second device region in the horizontal direction. The fourth device region has a plurality of vertically separated fourth devices 401 and a fourth gate structure 411 surrounding the fourth devices 401. The contact surface between the third gate structure 311 and the fourth gate structure 411 is located on the boundary 3 of the device region.
[0079] In some embodiments, the threshold voltage at which the first device 101 and the second device 201 operate is a first threshold voltage, and the threshold voltage at which the third device 301 and the fourth device 401 operate is a second threshold voltage, wherein the second threshold voltage is different from the first threshold voltage.
[0080] In some embodiments, the first device 101 and the third device 301 are nanosheet N-channel metal-oxide-semiconductor field-effect transistors; the second device 201 and the fourth device 401 are nanosheet P-channel metal-oxide-semiconductor field-effect transistors.
[0081] While the above disclosure is provided, it is not limited thereto. Any person skilled in the art may make various alterations and modifications without departing from the spirit and scope of this disclosure; therefore, the scope of protection of this disclosure shall be determined by the scope defined in the claims.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A substrate structure is provided, the substrate structure including a first device region and a second device region stacked vertically, the first device region having a plurality of vertically discrete first devices and a plurality of first sacrificial layers surrounding the first devices, the second device region having a plurality of vertically discrete second devices and a plurality of second sacrificial layers surrounding the second devices, the etching selectivity ratio of the materials of the first sacrificial layers and the second sacrificial layers being greater than 1, and a device region boundary being formed between the first sacrificial layers and the second sacrificial layers. Remove the first sacrificial layer and fill the first device region and the second device region with a first work function material; Remove the first work function material in the second device region to form a first gate structure surrounding the first device, the first gate structure being located on one side of the device region boundary; The second sacrificial layer is removed, and a second work function material is filled in the second device region to form a second gate structure surrounding the second device. The second gate structure is located on the other side of the device region boundary opposite to the first gate structure.
2. The semiconductor structure formation method according to claim 1, characterized in that, The removal of the first sacrificial layer includes: etching the first sacrificial layer to form a plurality of first channels between the plurality of first devices and between the first devices and the second sacrificial layer; The step of filling the first work function material in the first device region and the second device region includes: filling the first work function material in the first channel and the second device region, wherein the first work function material surrounds the first device, the second device and the second sacrificial layer.
3. The semiconductor structure formation method as described in claim 2, characterized in that, The step of removing the first work function material in the second device region to form a first gate structure surrounding the first device includes: The first work function material in the second device region is etched to form the first gate structure in the first device region, and the first gate structure surrounds the first device.
4. The semiconductor structure formation method as described in claim 3, characterized in that, The removal of the second sacrificial layer includes: etching the second sacrificial layer to form a plurality of second channels between the plurality of second devices and between the second devices and the first gate structure; The step of filling the region of the second device with a second work function material to form a second gate structure surrounding the second device includes: filling the second channel with a second work function material to form a second gate structure, wherein the second gate structure surrounds the second device.
5. The semiconductor structure formation method according to claim 1, characterized in that, The substrate structure further includes a third device region and a fourth device region stacked vertically, wherein the third device region is adjacent to the first device region in the horizontal direction, and the fourth device region is adjacent to the second device region in the horizontal direction. The third device region has a plurality of vertically discrete third devices and a third sacrificial layer surrounding the third devices, and the fourth device region has a plurality of vertically discrete fourth devices and a fourth sacrificial layer surrounding the fourth devices. The etching selectivity ratio of the materials of the third sacrificial layer and the fourth sacrificial layer is greater than 1.
6. The semiconductor structure formation method as described in claim 5, characterized in that, The method further includes: Before removing the first sacrificial layer, a first mask is formed in the third device region and the fourth device region, the first mask surrounding the third device, the third sacrificial layer, the fourth device and the fourth sacrificial layer; After removing the first sacrificial layer, remove the first mask; When filling the first work function material in the first device region and the second device region, the first work function material is simultaneously filled in the third device region and the fourth device region; When removing the first work function material in the second device region, the first work function material in the fourth device region is also removed simultaneously.
7. The semiconductor structure formation method according to claim 6, characterized in that, The removal of the first sacrificial layer includes: The first sacrificial layer is etched to form a plurality of first channels between the plurality of first devices and between the first devices and the second sacrificial layer; When filling the first work function material in the first device region and the second device region, simultaneously filling the first work function material in the third device region and the fourth device region includes: A first work function material is filled in the first channel, the second device region, the third device region, and the fourth device region, wherein the first work function material surrounds the first device, the second device, the third device, the fourth device, the second sacrificial layer, the third sacrificial layer, and the fourth sacrificial layer.
8. The semiconductor structure formation method according to claim 7, characterized in that, When removing the first work function material in the second device region, removing the first work function material in the fourth device region includes: Etch the first work function material in the second device region and the fourth device region; The first gate structure surrounding the first device includes: A second mask is formed in the region of the second device, the second mask surrounding the second device and the second sacrificial layer; The first work function material in the third device region is etched to form the first gate structure in the first device region.
9. The semiconductor structure formation method as described in claim 8, characterized in that, The method further includes: After forming the first gate structure surrounding the first device, the third sacrificial layer is removed, and a third work function material is filled in the third device region to form a third gate structure surrounding the third device, wherein the third gate structure and the first gate structure are located on the same side of the boundary of the device region.
10. The semiconductor structure formation method as described in claim 9, characterized in that, The removal of the third sacrificial layer includes: The third sacrificial layer is etched to form a plurality of third channels between the plurality of third devices and between the third devices and the fourth sacrificial layer; Remove the second mask; The filling of the third work function material in the third device region includes: A third work function material is filled in the third channel, the second device region, and the fourth device region, and the third work function material surrounds the second device, the third device, the fourth device, the second sacrificial layer, and the fourth sacrificial layer; The formation of the third gate structure surrounding the third device includes: The third work function material in the second and fourth device regions is etched to form the third gate structure in the third device region, and the third gate structure surrounds the third device.
11. The semiconductor structure formation method according to claim 10, characterized in that, The method further includes: Before removing the second sacrificial layer, a third mask is formed in the region of the fourth device, the third mask surrounding the fourth device and the fourth sacrificial layer; After removing the second sacrificial layer, remove the third mask; While filling the second work function material in the second device region, the second work function material is simultaneously filled in the fourth device region.
12. The semiconductor structure formation method as described in claim 11, characterized in that, The removal of the second sacrificial layer includes: The second sacrificial layer is etched to form a plurality of second channels between the plurality of second devices and between the second devices and the first gate structure; The step of forming a second gate structure surrounding the second device within the second device region includes: The second work function material in the fourth device region is etched to form a second gate structure surrounding the second device in the second device region.
13. The semiconductor structure formation method according to claim 12, characterized in that, The method further includes: After forming a second gate structure surrounding the second device in the second device region, the fourth sacrificial layer is removed, and a fourth work function material is filled in the fourth device region to form a fourth gate structure surrounding the fourth device.
14. The semiconductor structure formation method as described in claim 13, characterized in that, The removal of the fourth sacrificial layer includes: etching the fourth pseudo-gate structure to form a plurality of fourth channels between the plurality of fourth devices and between the regions of the fourth devices and the third device.
15. The semiconductor structure formation method as described in claim 5, characterized in that, The first sacrificial layer and the second sacrificial layer are both made of SiGe material. The concentration of Ge in the material of the first sacrificial layer is lower than the concentration of Ge in the material of the second sacrificial layer, and the etching selectivity ratio of the first sacrificial layer to the second sacrificial layer is greater than 10. The material of the third sacrificial layer is the same as that of the first sacrificial layer, and the material of the fourth sacrificial layer is the same as that of the second sacrificial layer.
16. The semiconductor structure formation method according to claim 5, characterized in that: The threshold voltage for the operation of the first device and the second device is the first threshold voltage; The threshold voltage at which the third and fourth devices operate is the second threshold voltage, which is different from the first threshold voltage.
17. The semiconductor structure formation method according to claim 5, characterized in that, The first and third devices are nanosheet N-channel metal-oxide-semiconductor field-effect transistors; the second and fourth devices are nanosheet P-channel metal-oxide-semiconductor field-effect transistors.
18. A semiconductor structure, characterized in that, include: A first device region having a plurality of vertically discrete first devices and a first gate structure surrounding the first devices; A second device region is stacked perpendicularly to the first device region. The second device region has a plurality of vertically discrete second devices and a second gate structure surrounding the second devices. A device region boundary exists between the first device region and the second device region.
19. The semiconductor structure as claimed in claim 18, characterized in that, Also includes: A third device region is horizontally adjacent to the first device region, and the third device region has a plurality of vertically discrete third devices and a third gate structure surrounding the third devices. A fourth device region is stacked vertically to the third device region. The fourth device region is adjacent to the second device region in the horizontal direction. The fourth device region has a plurality of vertically discrete fourth devices and a fourth gate structure surrounding the fourth devices. The contact surface between the third gate structure and the fourth gate structure is located on the boundary of the device region.
20. The semiconductor structure as described in claim 18, characterized in that: The threshold voltage for the operation of the first and second devices is the first threshold voltage, and the threshold voltage for the operation of the third and fourth devices is the second threshold voltage, which is different from the first threshold voltage.
21. The semiconductor structure as described in claim 18, characterized in that: The first and third devices are nanosheet N-channel metal-oxide-semiconductor field-effect transistors; the second and fourth devices are nanosheet P-channel metal-oxide-semiconductor field-effect transistors.