Semiconductor device and forming method thereof

Abstract

The invention discloses a semiconductor device and a forming method thereof. The semiconductor device includes a substrate, a trench, a first gate dielectric layer, a first gate electrode, and a first plug. The substrate includes a medium voltage region and a low voltage region. The trench is disposed in the substrate and located in the medium voltage region. The first gate dielectric layer is disposed on a plane of the trench. A first gate electrode is disposed on the first gate dielectric layer. A first plug is disposed over the first gate electrode and the plane of the trench, the first plug electrically connecting the first gate electrode.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for forming the same, and more particularly to a semiconductor device having a medium-voltage (MV) element and a method for forming the same. Background Technology

[0002] With current semiconductor technology, the industry can integrate control circuits, memory, low-voltage operating circuits, and high-voltage operating circuits and components onto a single chip, thereby reducing costs and improving operational performance. High-voltage components such as vertically diffused metal-oxide-semiconductors (VDMOS), insulated-gate bipolar transistors (IGBTs), and laterally diffused metal-oxide-semiconductors (LDMOS), which are fabricated on a single chip, are widely used due to their superior power switching efficiency. As those skilled in the art know, these high-voltage components are often required to withstand high breakdown voltages and operate at low resistance values.

[0003] Furthermore, as semiconductor devices become increasingly smaller, transistor fabrication processes have undergone numerous improvements to produce small, high-quality transistors. For example, non-planar field-effect transistors, such as fin field-effect transistors (FinFETs), have largely replaced planar field-effect transistors as the current mainstream trend. However, as device sizes continue to shrink, it becomes increasingly difficult to simultaneously incorporate finFETs and other components within the same semiconductor device, and their fabrication processes face numerous limitations and challenges. Summary of the Invention

[0004] One object of the present invention is to provide a semiconductor device in which the plug for the electrical connection of the voltage component is disposed on a plane of a substrate trench and simultaneously overlapped with the gate electrode or diffusion region disposed below. As a result, the semiconductor device of the present invention can obtain better component flatness and a more compact placement space, which is beneficial to improving the overall operation performance and device efficiency.

[0005] One object of the present invention is to provide a method for forming a semiconductor device, wherein a medium-voltage element is formed on a plane of a substrate trench and simultaneously overlapped with a gate electrode or diffusion region below, so that the formed semiconductor device has better element flatness and a more compact placement space, thereby achieving better operational performance and device efficiency.

[0006] To achieve the above objectives, the present invention provides a semiconductor device including a substrate, a trench, a first gate dielectric layer, a first gate electrode, and a first plug. The substrate includes a medium-voltage region and a low-voltage region. The trench is disposed within the substrate and located within the medium-voltage region. The first gate dielectric layer is disposed on a plane of the trench. The first gate electrode is disposed on the first gate dielectric layer. The first plug is disposed above the plane of the first gate electrode and the trench, and the first plug is electrically connected to the first gate electrode.

[0007] To achieve the above objectives, the present invention provides a method for forming a semiconductor device, comprising the following steps: A substrate is provided, the substrate including a medium-voltage region and a low-voltage region. A trench is formed within the substrate, located within the medium-voltage region. A first gate dielectric layer is formed on a plane of the trench. A first gate electrode is formed on the first gate dielectric layer. A first plug is formed on the first gate electrode, located above the plane of the trench, the first plug being electrically connected to the first gate electrode. Attached Figure Description

[0008] Figures 1 to 2 This is a schematic diagram of a semiconductor device in the first embodiment of the present invention, wherein:

[0009] Figure 1 This is a top view schematic diagram of a semiconductor device in the first embodiment of the present invention; and

[0010] Figure 2 for Figure 1 A cross-sectional view along tangent A-A';

[0011] Figures 3 to 6 This is a schematic diagram of a method for forming a semiconductor device according to the first embodiment of the present invention, wherein:

[0012] Figure 3 This is a schematic cross-sectional view of a semiconductor device after the formation of a fin-like structure.

[0013] Figure 4 This is a schematic cross-sectional view of a semiconductor device after trenching has been formed.

[0014] Figure 5 This is a schematic cross-sectional view of a semiconductor device after the formation of the gate dielectric layer; and

[0015] Figure 6This is a schematic cross-sectional view of a semiconductor device after the gate electrode has been formed.

[0016] Figures 7 to 8 This is a schematic diagram of a semiconductor device in a second embodiment of the present invention, wherein:

[0017] Figure 7 This is a top view schematic diagram of a semiconductor device in the second embodiment of the present invention; and

[0018] Figure 8 for Figure 7 A cross-sectional view along tangent A-A';

[0019] Figure 9 This is a schematic diagram of a semiconductor device in the third embodiment of the present invention.

[0020] Symbol Explanation

[0021] 10, 20, 30: Semiconductor devices

[0022] 100: Base

[0023] 100H: High-voltage zone

[0024] 100L: Low-pressure area

[0025] 100M: Medium-voltage zone

[0026] 100p: Flat

[0027] 100t: Top surface

[0028] 102: Diffusion Zone

[0029] 102a: Diffusion region

[0030] 102t: Top surface

[0031] 104: Fin-like structure

[0032] 104t: Top surface

[0033] 106, 306: Shallow trench isolation

[0034] 110: Gate structure

[0035] 112: First gate dielectric layer

[0036] 112a: First gate dielectric material layer

[0037] 114: First gate electrode

[0038] 120, 220: First plug

[0039] 122: Second plug

[0040] 130: Gate structure

[0041] 132: Second gate dielectric layer

[0042] 134: Second gate electrode

[0043] 302: Doped region

[0044] 320: Third plug

[0045] 322: Fourth plug

[0046] 340: Gate structure

[0047] 342: Third gate dielectric layer

[0048] 344: Third gate electrode

[0049] D1, D2: Direction

[0050] R1, R2: Trench

[0051] S1, S2: Plane

[0052] Y: Vertical direction Detailed Implementation

[0053] To enable those skilled in the art to further understand this invention, several preferred embodiments are described below, along with accompanying drawings, to explain in detail the structure and desired effects of the invention. Furthermore, without departing from the spirit of the invention, the technical features in the different embodiments described below can be substituted, rearranged, or combined to form other embodiments.

[0054] Please refer to Figure 1 and Figure 2The diagram shows a top view and a cross-sectional view of a semiconductor device 10 according to a first embodiment of the present invention. The semiconductor device 10 includes a substrate 100, a trench R1, a first gate dielectric layer 112, a first gate electrode 114, and a first plug 120. The substrate 100 includes, for example, a silicon substrate, an epitaxial silicon substrate, a silicon containing substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto. The substrate 100 has at least a medium voltage (MV) region 100M and a low voltage (LV) region 100L defined thereon. The medium voltage region 100M is, for example, used to house a planar transistor, while the low voltage region 100L is, for example, a finned transistor. The medium voltage region 100M and the low voltage region 100L are, for example, as shown in the diagram. Figure 1 and Figure 2 The regions shown are arranged adjacent to each other, and are isolated from each other, for example, by shallow trench isolation 106 disposed in the substrate 100, but are not limited thereto. In another embodiment, other regions may be further defined on the substrate 100, such as a high voltage (HV) region (not shown) for arranging another planar transistor.

[0055] A trench R1 is disposed within a medium-voltage region 100M of the substrate 100, for example, as a recessed space recessed downward from the top surface 100t of the substrate 100 and having an overall flat plane S1. A first gate dielectric layer 112 and a first gate electrode 114 are sequentially disposed on the plane S1 of the trench R1, such that the first gate electrode 114 is located on the first gate dielectric layer 112. In one embodiment, the first gate electrode 114 includes a polysilicon gate electrode or a metal gate electrode. Thus, the first gate dielectric layer 112 and the first gate electrode 114 sequentially stacked on the plane S1 form a gate structure 110, which can be used together with other suitable components to form a medium-voltage transistor suitable for medium-voltage operation, but is not limited thereto. It should be noted that a first plug 120 is disposed on the first gate electrode 114 and electrically connected to the first gate electrode 114. The first plug 120 is positioned on the trench R1 in the vertical direction Y, exactly on the plane S1 of the trench R1, and completely overlaps the first gate electrode 114, as shown below. Figure 1 and Figure 2 As shown. That is to say, as... Figure 1As shown in the top view, the first plug 120 is entirely within the extension range of the trench R1, without extending onto the shallow trench isolation 106. Therefore, the first plug 120 achieves better component flatness and a more compact spatial configuration, which is beneficial for improving the overall operational performance and device efficiency of the semiconductor device 10.

[0056] For example Figure 1 and Figure 2 As shown, the semiconductor device 10 also includes a diffusion region 102 and two second plugs 122 disposed within a voltage region 100M in the substrate 100. The diffusion region 102 extends downward from the plane S1 of the trench R1 into the interior of the substrate 100, and contains suitable dopants, such as P-type or N-type dopants, so that the diffusion region 102 can serve as a P-type or N-type doped well. The two second plugs 122 are disposed on the plane S1 of the trench R1, i.e., on a top surface 102t of the diffusion region 102, and are located on opposite sides of the first plug 120, electrically connected to two source / drain regions (not shown) further disposed within the diffusion region 102. The top surface 102t of the diffusion region 102, i.e., the plane S1 of the trench R1, is, for example, lower than the top surface 100t of the substrate 100. Figure 2 As shown. On the other hand, the first gate electrode 114, the first plug 120, and each of the second plugs 122 are, for example, respectively extended in the same direction D1 and arranged sequentially in another direction D2 perpendicular to direction D1. That is, the first gate electrode 114, the first plug 120, and each of the second plugs 122 all present as shown. Figure 1 The diagram shows a rectangular structure, but is not limited to it. The first plug 120 is entirely located within the extension of the diffusion region 102 below and on the first gate electrode 114, thus allowing the first plug 120 to have a relatively compact spatial configuration.

[0057] The semiconductor device 10 also includes a plurality of fin structures 104 disposed within a low-voltage region 100L, a second gate dielectric layer 132, and a second gate electrode 134. The fin structures 104 are disposed, for example, on a plane 100p of the substrate 100, and are partially covered by a shallow trench isolation 106 and partially protrude beyond the surface of the shallow trench isolation 106. The top surface 104t of each fin structure 104 is flush with the top surface 100t of the substrate 100 and higher than the plane S1 of the trench R1, such as... Figure 2As shown. A second gate dielectric layer 132 and a second gate electrode 134 are sequentially disposed on the surfaces of the fin structure 104 and the shallow trench isolation 106. Specifically, the second gate dielectric layer 132 conformally covers the portions of the fin structure 104 that protrude from the shallow trench isolation 106, and the second gate electrode 134 is disposed on the second gate dielectric layer 132. In one embodiment, the second gate electrode 134 may include, for example, a polysilicon gate electrode or a metal gate electrode. Thus, the second gate dielectric layer 132 and the second gate electrode 134 sequentially stacked on the fin structure 104 constitute a gate structure 130, which can be combined with other suitable components to form a low-voltage transistor suitable for low-voltage operation, but is not limited thereto.

[0058] In this configuration, the semiconductor device 10 of this embodiment may simultaneously include a gate structure 110 disposed in the intermediate voltage region 100M and a gate structure 130 disposed in the low voltage region 100L, such that the gate structure 110 in the intermediate voltage region 100M subsequently functions as a medium voltage element operating at medium voltage, and the gate structure 130 in the low voltage region 100L subsequently functions as a low voltage element operating at low voltage. The intermediate voltage element refers, for example, to a semiconductor transistor with a starting voltage between 5 volts (V) and 10 volts, and the low voltage element refers, for example, to a semiconductor transistor with a starting voltage between 0.5 volts and 1 volt, but is not limited thereto. It should be noted that in this embodiment, the semiconductor device 10 has a trench R1 recessed downward from the top surface 100t of the substrate 100 within the medium-voltage region 100M of the substrate 100. The gate structure 110 and the second plug are then disposed on a flat plane S1 within the trench R1. This helps to mitigate the potential height difference between the gate structure 110 of the medium-voltage element and the gate structure 130 of the low-voltage element. Furthermore, the semiconductor device 10 further provides a first plug 120 electrically connected to the medium-voltage element on the plane S1 of the trench R1, allowing the first plug 120 to have better element flatness, thereby improving its structural stability and operation. Moreover, the first plug 120 is positioned to overlap the lower first gate electrode 114 and the diffusion region 102 in the vertical direction Y, making the configuration space of the first plug 120 more compact and further improving the overall performance and efficiency of the semiconductor device 10.

[0059] In order to enable those skilled in the art to easily understand the semiconductor device 10 of the present invention, the method of forming the semiconductor device 10 of the present invention will be further described below.

[0060] Please refer to Figures 3 to 6 The diagram shown is a schematic representation of a method for forming a semiconductor device 10 according to a preferred embodiment of the present invention. First, as... Figure 3As shown, a substrate 100 is provided, on which low-pressure regions 100L and medium-pressure regions 100M are defined adjacent to each other, and a fin structure 104 is formed in the low-pressure region 100L of the substrate 100. In one embodiment, the fin structure 104 is formed by, for example, including but not limited to, the following steps: First, a block-shaped substrate (not shown) is provided, and a self-aligned double patterning (SADP) or self-aligned reverse patterning (SARP) process is performed in a region of the block-shaped substrate (not shown, for example, a block where the low-pressure region 100L is to be formed), partially removing the block-shaped substrate in that region to form a plane 100P and fin structures 104 protruding from the plane 100P respectively. Among them, the top surface 104t of each fin structure 104 is flush with the top surface 100t of the base 100, while the plane 100P is lower than the top surface 100t of the base 100, such as Figure 3 As shown. Furthermore, prior to the formation of the fin-like structure 104, it is also possible to pre-form such a structure in another region of the blocky substrate (not shown, for example, the region where the intermediate pressure zone 100M is to be formed). Figure 3 A diffusion region 102a is shown. Alternatively, in another embodiment, the diffusion region 102a can be formed in the medium-pressure region 100M of the substrate 100 after the fin structure 104 has been formed. Figure 3 The diffusion region 102a is shown. The diffusion region 102a extends downwards from the top surface 100t of the substrate 100 into the interior of the substrate 100, and contains suitable dopants, such as P-type or N-type dopants, but is not limited thereto. In one embodiment, the depth of the diffusion region 102a is preferably greater than the depth of the shallow trench isolation 106, such as... Figure 3 As shown, but not limited to.

[0061] like Figure 4 As shown, a mask layer (not shown) covers the low-pressure region 100L of the substrate 100, while an etching process is performed on the medium-pressure region 100M of the substrate 100 to partially remove the substrate 100, forming a trench R1 and simultaneously forming a diffusion region 102. Specifically, the trench R1 is a recessed space formed by etching downwards from the top surface 100t of the substrate 100, exposing the top surface 102t of the diffusion region 102. In this operation, the trench R1 can have a relatively flat plane S1, which is the top surface 102t of the diffusion region 102, and plane S1 can be lower than the top surface 104t of the fin structure 104 and / or the top surface 100t of the substrate 100. Then, the mask layer is completely removed.

[0062] like Figure 5As shown, a patterning process for substrate 100 is performed through another mask layer (not shown) to form at least one shallow trench (not shown) on substrate 100. Then, a deposition process and an etch-back process are performed to form the shallow trench isolation 106. In one embodiment, the top surface of the shallow trench isolation 106 is flush with, for example, the plane S1 of the trench R1 (i.e., the top surface 102t of the diffusion region 102), but is not limited thereto. On the other hand, the shallow trench isolation 106 covers a portion of each fin structure 104, such that the remaining portion of each fin structure protrudes from the surface of the shallow trench isolation 106. Then, the other mask layer is completely removed, and then... Figure 5 As shown, a deposition process is performed on the plane S1 of trench R1 (i.e., the top surface 102t of diffusion region 102) to form a first gate dielectric material layer 112a on the plane S1 of trench R1. In one embodiment, the first gate dielectric material layer 112a includes dielectric materials such as silicon oxide and silicon oxynitride, but is not limited thereto. However, those skilled in the art will readily understand that the specific formation order of fin structure 104, shallow trench isolation 106, and trench R1 is not limited to the foregoing. In another embodiment, it is also possible to first form trench R1, etch fin structure 104, and then form shallow trench isolation 106.

[0063] like Figure 6 As shown, a gate material layer (not shown) is formed on the first gate dielectric material layer 112a, and the first gate dielectric layer 112 and the first gate electrode 114 are sequentially stacked on the plane S1 of the trench R1 by performing a patterning fabrication process. Thus, the first gate dielectric layer 112 and the first gate electrode 114 form the gate structure 110, and together with other suitable components formed subsequently, form a medium-voltage transistor suitable for medium-voltage operation. On the other hand, as... Figure 6As shown, after forming the gate structure 110, deposition and patterning processes are performed within the low-voltage region 100L of the substrate 100 to form a second gate dielectric layer 132 and a second gate electrode 134 sequentially stacked on the surfaces of the fin structure 104 and the shallow trench isolation 106. Thus, the second gate dielectric layer 132 and the second gate electrode 134 form the gate structure 130, which, together with other suitable components subsequently formed, forms a low-voltage transistor suitable for low-voltage operation, but is not limited thereto. In one embodiment, the first gate electrode 114 and / or the second gate electrode 134 may include, for example, a polysilicon gate electrode or a metal gate electrode, but is not limited thereto. Those skilled in the art will readily understand the specific formation sequence of the gate structures 110 and 130, which is not limited to the foregoing. In another embodiment, it is also possible to first form the first gate dielectric layer 112 and the second gate dielectric layer 132, and then simultaneously form the first gate electrode 114 and the second gate electrode 134. Subsequently, the first gate electrode 114 and the second gate electrode 134 can also be fabricated using a replacement metal gate (RMG) process to form a metal gate structure.

[0064] Subsequently, a first plug 120 electrically connected to the first gate electrode 114 and two second plugs 122 electrically connected to the two source / drain electrodes (not shown) formed in the medium-voltage region 100M of the substrate 100 can be formed, respectively, to complete the process as follows: Figure 1 and Figure 2The semiconductor device 10 shown is formed as follows. It should be noted that since the first plug 120 is formed on the plane S1 of the trench R1 in the vertical direction Y, better component flatness can be obtained, thereby improving its structural stability and operation. Furthermore, the first plug 120 is formed to completely overlap the lower first gate electrode 114 and diffusion region 102, without extending additionally to the adjacent shallow trench isolation 106. This avoids problems such as component height differences that may arise from differences in the material and flatness of the placement area, allowing for a more compact arrangement of the first plug 120, which is beneficial for improving the overall performance and device efficiency of the semiconductor device 10. Therefore, through the formation method of this embodiment, gate structures 110 and 130 can be formed in different regions of the substrate 100 (including the medium-voltage region 100M and the low-voltage region 100L), respectively. The gate structure 110 formed in the medium-voltage region 100M subsequently functions as a medium-voltage element operating at medium voltage, and the gate structure 130 formed in the low-voltage region 100L subsequently functions as a low-voltage element operating at low voltage. In other words, the formation method of this embodiment effectively integrates the fabrication processes of the medium-voltage and low-voltage elements, forming a plug structure with good element flatness and a more compact spatial arrangement while simplifying the steps. This results in the semiconductor device 10 achieving better operational performance and device efficiency.

[0065] Those skilled in the art will readily understand that, while meeting actual product requirements, the semiconductor device and its formation method of the present invention may have other forms, and are not limited to those described above. Further embodiments or variations of the semiconductor device and its formation method will be described below. For the sake of simplicity, the following description focuses on the differences between the embodiments, without repeating the similarities. Furthermore, identical elements in the embodiments of the present invention are designated with the same reference numerals to facilitate comparison between the embodiments.

[0066] Please refer to Figure 7 and Figure 8 The figures show a top view and a cross-sectional view of the semiconductor device 20 in the second embodiment of the present invention. The structure of the semiconductor device 20 in this embodiment is generally the same as that of the semiconductor device 10 in the first embodiment described above, also including a substrate 100, a trench R1, a first gate dielectric layer 112, and a first gate electrode 114. The similarities will not be repeated here. The main difference between this embodiment and the previous embodiment is that the first gate electrode 114 and the first plug 220 in this embodiment extend in two mutually perpendicular directions D1 and D2, respectively.

[0067] In detail, such as Figure 7 and Figure 8As shown, the first gate electrode 114 and each of the second plugs 122 extend in direction D1, arranged sequentially in direction D2 perpendicular to direction D1. The first plug 220 extends in direction D2, such that the extension direction D2 of the first plug 220 is perpendicular to the extension direction D1 of the first gate electrode 114. Furthermore, it should be noted that the first plug 220 is still disposed above the trench R1 in the vertical direction Y, and is located on the plane S1 of the trench R1. The first plug 220 completely overlaps the first gate electrode 114 and the diffusion region 102 below it, thus still achieving better device flatness and a more compact spatial arrangement, which is beneficial for improving the overall operational performance and device efficiency of the semiconductor device 20.

[0068] Please refer to Figure 9 The figures show cross-sectional schematic diagrams of the semiconductor device 30 in the third embodiment of the present invention. The structure of the semiconductor device 30 in this embodiment is generally the same as that of the semiconductor device 10 in the first embodiment, also including a substrate 100, a trench R1, a first gate dielectric layer 112, a first gate electrode 114, and a first plug 120. The similarities will not be repeated here. The main difference between this embodiment and the previous embodiments is that the substrate 100 in this embodiment further includes a high-voltage region 100H, and at least one shallow trench isolation 306, a third gate dielectric layer 342, a third gate electrode 344, and a third plug 320 disposed within the high-voltage region 100H of the substrate 100.

[0069] like Figure 9 As shown, the high-voltage region 100H is, for example, disposed on one side of the medium-voltage region 100M, for forming a high-voltage component in subsequent fabrication processes. This high-voltage component refers, for example, to a semiconductor transistor with an initial voltage between 10 volts and 20 volts, but is not limited thereto. Those skilled in the art will readily understand that the low-voltage region 100L, the medium-voltage region 100M, and the high-voltage region 100H on the substrate 100 can also be arranged in other orders, without regard to... Figure 9 The illustrated configuration is for illustrative purposes only. The high-voltage region 100H of the substrate 100 also includes a trench R2 recessed downwards from the top surface 100t of the substrate 100, located between two shallow trench isolations 306. A third gate dielectric layer 342 and a third gate electrode 344 are sequentially disposed on a plane S2 of the trench R2. Thus, the third gate dielectric layer 342 and the first gate electrode 344, sequentially stacked on plane S1, constitute a gate structure 340, which can be combined with other suitable components to form a high-voltage transistor suitable for high-voltage operation. In a preferred embodiment, the thickness of the third gate dielectric layer 342 is, for example, greater than the thickness of the first gate dielectric layer 112 and greater than the thickness of the second gate dielectric layer 132, but is not limited thereto.

[0070] In detail, the plane S2 of trench R2 is preferably lower than the plane S1 of trench R1 and the top surface 100t of substrate 100, so that the gate structure 340 subsequently formed on plane S2 can have a flush top surface with the gate structure 130 disposed in low voltage region 100L and the gate structure 110 disposed in medium voltage region 100M, that is, the top surface of the third gate electrode 344 is flush with the top surfaces of the first gate electrode 114 and the second gate electrode 134. Furthermore, the third plug 320 disposed on the third gate electrode 344 and electrically connected to the gate structure 340 can also be located above the plane S2 of trench R2 in the vertical direction Y, and overlap the lower third gate electrode 344. In other words, as seen in a top view (not shown), the third plug 320 can be completely located within the extension range of trench R2 without extending onto the adjacent shallow trench isolation 306, thus improving the device flatness of the third plug 320 and providing a more compact spatial configuration. On the other hand, the semiconductor device 30 also includes two doped regions 302 disposed within the high-voltage region 100H of the substrate 100, and two fourth plugs 322 electrically connected to the two doped regions 302 respectively. The two doped regions 302 are respectively disposed on opposite sides of the gate structure 340 in direction D2, such that two shallow trench isolations 306 are respectively located on one side of the gate structure 340 and between the doped regions 302. The two fourth plugs 322 are respectively disposed on the two doped regions 302 and electrically connected to them. In one embodiment, the doped regions 302 may contain suitable dopants, such as P-type or N-type dopants, to serve as the two source / drain regions of the high-voltage transistor, but are not limited thereto.

[0071] In this configuration, the semiconductor device 30 of this embodiment may simultaneously include a gate structure 340 disposed in the high-voltage region 100H, a gate structure 110 disposed in the medium-voltage region 100M, and a gate structure 130 disposed in the low-voltage region 100L. The gate structure 340 in the high-voltage region 100H subsequently functions as a high-voltage element for high-voltage operation, the gate structure 110 in the medium-voltage region 100M subsequently functions as a medium-voltage element for medium-voltage operation, and the gate structure 130 in the low-voltage region 100L subsequently functions as a low-voltage element for low-voltage operation. It should be noted that in this embodiment, the semiconductor device 30 has a first plug 120 electrically connected to the medium-voltage element disposed on the plane S1 of the trench R1, and a third plug 320 electrically connected to the high-voltage element disposed on the plane S2 of the trench R2. This allows both the first plug 120 and the third plug 320 to have better element flatness, thereby improving structural stability and operation, and further enhancing the overall performance and efficiency of the semiconductor device 30.

[0072] Overall, the semiconductor device and its formation method of the present invention form a plug for electrically connecting medium-voltage components on a plane of a substrate trench, simultaneously overlapping the underlying gate electrode or diffusion region. This results in better component flatness and a more compact spatial arrangement for the plug, thereby improving the overall operational performance and device efficiency of the semiconductor device. Furthermore, according to the semiconductor device formation method of the present invention, the fabrication process of the medium-voltage component can be effectively integrated with the fabrication processes of low-voltage components in other regions, thus forming a plug structure with better component flatness and a more compact spatial arrangement while simplifying the steps.

[0073] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A semiconductor device, comprising: The base includes the medium-pressure zone and the low-pressure zone; A trench is provided within the substrate and located within the medium-pressure zone; A first gate dielectric layer is disposed on the plane of the trench; A first gate electrode is disposed on the first gate dielectric layer; and A first plug is disposed on the plane of the first gate electrode and the trench, and the first plug is electrically connected to the first gate electrode.

2. The semiconductor device of claim 1, wherein, The first gate electrode and the first plug extend in the same direction.

3. The semiconductor device as claimed in claim 1, wherein, The first gate electrode and the first plug extend in two mutually perpendicular directions.

4. The semiconductor device of claim 1, wherein, The first gate electrode may be a polysilicon gate electrode or a metal gate electrode.

5. The semiconductor device of claim 1, further comprising: A diffusion zone is provided within the substrate and located within the medium-pressure zone; as well as Two second plugs are respectively disposed on opposite sides of the first plug and located on the top surface of the diffusion region, wherein the top surface of the diffusion region is lower than the top surface of the substrate.

6. The semiconductor device of claim 5, wherein, The two second plugs and the first gate electrode extend in the same direction.

7. The semiconductor device of claim 5, wherein, The plane of the trench is lower than the top surface of the substrate.

8. The semiconductor device of claim 5, further comprising: Multiple fin-like structures are disposed within the substrate and located within the low-pressure area; A second gate dielectric layer is conventionally disposed on the fin structures; and The second gate electrode is disposed on the second gate dielectric layer.

9. The semiconductor device of claim 8, wherein, The top surface of each fin structure is flush with the top surface of the substrate.

10. The semiconductor device of claim 8, wherein, The top surface of each fin structure is higher than the plane of the groove.

11. The semiconductor device of claim 8, wherein, The top surface of the second gate electrode is flush with the top surface of the first gate electrode.

12. A method for forming a semiconductor device, comprising: A substrate is provided, which includes a medium-pressure zone and a low-pressure zone; A trench is formed within the substrate, located within the medium-pressure zone; A first gate dielectric layer is formed on the plane of the trench; A first gate electrode is formed on the first gate dielectric layer; as well as A first plug is formed on the first gate electrode, located above the plane of the trench, and the first plug is electrically connected to the first gate electrode.

13. The method of forming a semiconductor device as claimed in claim 12, wherein, The first gate electrode and the first plug extend in the same direction.

14. The method of forming a semiconductor device as claimed in claim 12, wherein, The first gate electrode and the first plug extend in two mutually perpendicular directions.

15. The method of forming a semiconductor device as claimed in claim 12, further comprising: Multiple fin-like structures are formed within the substrate, located in the low-pressure area; A second gate dielectric layer is formed to cover the fin-like structures; as well as A second gate electrode is formed on the second gate dielectric layer.

16. The method of forming a semiconductor device as claimed in claim 15, wherein the trench is formed after the fin structures are formed, further comprising: Partial removal of a portion of the substrate located within the medium-pressure zone forms the trench, wherein the plane of the trench is lower than the top surface of the substrate and the top surface of each of the fin structures.

17. The method of forming a semiconductor device as claimed in claim 16, further comprising: A diffusion region is formed within the substrate, located within the medium-pressure region; as well as Second plugs are formed on opposite sides of the first plug, and the second plugs are located on the top surface of the diffusion region.

18. The method of forming a semiconductor device as claimed in claim 17, wherein, The top surface of the diffusion region is lower than the top surface of the substrate.

19. The method of forming a semiconductor device as claimed in claim 17, wherein, The second plug and the first gate electrode extend in the same direction.

Images