Forked-piece transistor with dielectric ridge with air gap

Abstract

Techniques are provided for forming a semiconductor device that includes a forked transistor having a self-aligned dielectric ridge, the dielectric ridge having an air gap. The air gap may constitute a majority of the total volume of the dielectric ridge, which reduces the dielectric constant of the dielectric ridge and reduces parasitic capacitance. In one example, first and second semiconductor devices have first and second semiconductor regions extending in a first direction between respective source and drain regions, respectively. The first and second semiconductor regions may include any number of nanosheets. A dielectric ridge extends in the first direction between the first and second semiconductor regions. The dielectric ridge includes a dielectric liner layer adjacent to each side of the first and second semiconductor regions. A remaining volume of the dielectric ridge is at least partially constrained by the dielectric liner, including an air gap. A dielectric cap structure may be included over the air gap.

Description

Background Technology

[0001] As integrated circuit dimensions continue to shrink, numerous challenges arise. For example, reducing the size of memory and logic cells becomes increasingly difficult, as does reducing the spacing between devices at different layers. With transistors being packaged more densely, the formation of certain device structures used to isolate adjacent transistors becomes challenging. Therefore, many significant challenges remain in the fabrication of semiconductor devices. Attached Figure Description

[0002] Figure 1A and 1B These are cross-sectional and plan views of some semiconductor devices according to embodiments of the present disclosure, showing a forked transistor with a dielectric ridge having an air gap.

[0003] Figure 2A-2N This is a cross-sectional view according to some embodiments of the present disclosure, illustrating various stages in an example process for forming a semiconductor device having a forked transistor with a dielectric ridge having an air gap.

[0004] Figure 3 This is a cross-sectional view of a semiconductor device having a forked transistor according to an embodiment of the present disclosure, the forked transistor having a dielectric ridge with an air gap and a conductive bridge on the dielectric ridge.

[0005] Figure 4 A cross-sectional view of a chip package comprising one or more semiconductor dies as described herein is shown according to some embodiments of the present disclosure.

[0006] Figure 5 This is a flowchart of a manufacturing process for a semiconductor device having a forked transistor according to an embodiment of the present disclosure, the forked transistor having a dielectric ridge with an air gap.

[0007] Figure 6 A computing system comprising one or more integrated circuits as described herein is illustrated according to embodiments of the present disclosure.

[0008] Although the following detailed description will be made with reference to exemplary embodiments, many alternatives, modifications, and variations will be apparent from this disclosure. As will be further understood, the figures are not necessarily drawn to scale or intended to limit this disclosure to the specific configurations shown. For example, while some figures typically represent perfect straight lines, right angles, and smooth surfaces, actual implementations of integrated circuit structures may have imperfect straight lines and right angles (e.g., some features may have tapered sidewalls and / or rounded corners) due to real-world limitations of the processing devices and technologies used, and some features may have surface topologies or otherwise be non-smooth. Detailed Implementation

[0009] This document provides techniques for forming semiconductor devices including forked transistors with self-aligned dielectric ridges having air gaps. The air gaps can constitute a large portion of the total volume of the dielectric ridges, which reduces the dielectric constant of the dielectric ridges and decreases parasitic capacitance. In an example, a first semiconductor device and a second semiconductor device each have a first semiconductor region and a second semiconductor region extending in a first direction between respective source and drain regions. A first gate structure extends over the first semiconductor region in a second direction, and a second gate structure extends over the second semiconductor region in a second direction. The first and second semiconductor regions may each comprise any number of nanosheets (or more generally, semiconductor bodies), wherein the first and second gate structures extend around three sides of each semiconductor body of the first and second semiconductor regions, respectively. The dielectric ridges extend directly between the first and second semiconductor regions in the first direction, although in some cases, an intervening gate dielectric layer may be present between the semiconductor regions and the dielectric ridges. The dielectric ridges include a dielectric liner along their outer surface. According to some embodiments, the remaining volume of the dielectric ridge, at least partially constrained by the dielectric liner, is free of material, thus forming an air gap. The air gap may be filled with one or more gases (e.g., oxygen, nitrogen), or may be empty. The top of the dielectric ridge includes a dielectric cap structure situated above the air gap. Numerous variations and embodiments will be apparent from this disclosure.

[0010] Overview

[0011] As mentioned above, many significant challenges remain in integrated circuit manufacturing. More specifically, as devices become smaller and more densely packaged, the fabrication of many structures becomes more challenging because the critical dimension (CD) of the structure pushes the limits of current manufacturing technologies. One such structure is the dielectric ridge of a forked transistor arrangement. More specifically, the dielectric ridge separates the gate structure from the semiconductor body (sometimes called nanosheets or nanoribbons) on either side of the dielectric ridge. The semiconductor body of the semiconductor device on either side of the dielectric ridge is adjacent to each side of the dielectric ridge, such that the gate does not extend completely around the semiconductor body. This structure allows forked transistors to be patterned very close together (e.g., with only the dielectric ridge between them). However, due to the densely packed nature of forked transistors, short circuits can become a problem if the integrity of the dielectric ridge is compromised during fabrication. More specifically, the dielectric ridge is formed early in the fabrication process (just after fin formation), which requires protection of the dielectric material through several subsequent processing operations (e.g., source and drain treatments, which include deposition and etching processes for forming internal gate spacers). However, protecting the dielectric ridge is challenging, and subsequent manufacturing processes often result in the etching away of portions of the ridge. To address this issue, the dielectric ridge is typically fabricated using high-k dielectric materials (e.g., silicon nitride), which are generally more robust in withstanding subsequent manufacturing processes (e.g., etch resistance). However, high-k materials lead to increased parasitic capacitance in the structure, which adversely affects transistor performance.

[0012] Therefore, and according to embodiments of this disclosure, this document provides a technique for forming self-aligned ridges between forked transistors, the self-aligned ridges including a large air gap through most of their volume, which significantly reduces the dielectric constant of the ridge structure. According to some embodiments, two semiconductor fins formed of alternating semiconductor materials extend parallel to each other along a first direction and are relatively close to each other (e.g., within 20 nm of each other) along an orthogonal second direction. Each fin of semiconductor material will eventually form a transistor on each side of the forked arrangement. Sacrificial ridges are formed between adjacent fins and remain thereafter after various additional fabrication processes are performed, such as forming source or drain regions at the ends of the fins, releasing nanosheets within each fin, and forming gate structures on the released nanosheets.

[0013] According to some embodiments, the sacrificial ridge material is removed after the gate structure is formed to leave a trench recess between adjacent devices. A dielectric liner is formed within the trench recess, and the remaining volume of the trench recess is filled with a volatile material. A porous liner is formed on top of the volatile material, such that the volatile material is surrounded by the dielectric liner and the porous liner. An annealing operation is then performed to sublimate the volatile material, after which the volatile material escapes through the porous liner to leave an air gap constrained by the dielectric liner and the porous liner. It should be understood that the term "air gap" as used herein can refer to any region without solid material. The air gap can include any concentration of inert gas (e.g., nitrogen or argon), and / or can be under vacuum pressure. A dielectric cap can be formed on the porous liner to improve the integrity of the ridge. Because the air gap has a dielectric constant close to 1.0, the ridge has an overall low dielectric constant compared to ridges formed from solid materials, especially compared to ridges formed primarily from high-k materials such as silicon nitride.

[0014] According to an embodiment, an integrated circuit includes a first semiconductor device, a second semiconductor device, and a ridge. The first semiconductor device has a first semiconductor material extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor material in a second direction. The second semiconductor device has a second semiconductor material extending from a second source or drain region in the first direction and a second gate structure extending over the second semiconductor material in the second direction. The ridge is located between the first semiconductor material and the second semiconductor material, and between the first gate structure and the second gate structure. The ridge includes a dielectric liner and an air gap. The dielectric liner has a first portion on the first semiconductor material and a second portion on the second semiconductor material. The air gap extends across the second direction from the first portion of the dielectric liner to the second portion of the dielectric liner.

[0015] According to an embodiment, an electronic device includes a chip package having one or more dies. At least one of the one or more dies includes a first semiconductor material, a first gate structure, a second semiconductor material, a second gate structure, and a ridge. The first semiconductor material extends in a first direction between a first source or drain region and a second source or drain region. The first gate structure extends in a second direction over the first semiconductor material. The second semiconductor material extends in the first direction between a third source or drain region and a fourth source or drain region. The second gate structure extends in the second direction over the second semiconductor material. The ridge is located between the first semiconductor material and the second semiconductor material, between the first source or drain region and the third source or drain region, and between the second source or drain region and the fourth source or drain region. The ridge includes a dielectric liner and an air gap. The dielectric liner has a first portion on the first semiconductor material and a second portion on the second semiconductor material. The air gap extends across the second direction from the first portion of the dielectric liner to the second portion of the dielectric liner.

[0016] According to an embodiment, an integrated circuit includes a first semiconductor device, a second semiconductor device, and a ridge. The first semiconductor device has a first semiconductor material, the second semiconductor device has a second semiconductor material, and the ridge is located between and contacts the first and second semiconductor materials. The ridge includes a first dielectric liner along the sidewalls of the ridge, a second dielectric liner at the top of the ridge, and a region within the central portion of the ridge that has no solid material and is constrained by the first and second dielectric liners.

[0017] According to another embodiment, a method of forming an integrated circuit includes: forming a first fin and a second fin, the first fin comprising a first semiconductor material and the second fin comprising a second semiconductor material, wherein the first fin and the second fin are adjacent and extend parallel to each other along a first direction; forming a first sacrificial material between the first fin and the second fin such that the first sacrificial material extends from the first semiconductor material to the second semiconductor material along a second direction substantially orthogonal to the first direction; forming a sacrificial gate over the first fin and the second fin along the second direction; forming a first source or drain region at opposite ends of the first fin and a second source or drain region at opposite ends of the second fin; replacing the sacrificial gate with one or more gate structures extending over the first semiconductor material and the second semiconductor material along the second direction; removing the first sacrificial material between the first semiconductor material and the second semiconductor material to form a trench recess; forming a first dielectric liner within the trench recess; forming a second sacrificial material within the remaining volume of the trench recess on the dielectric liner; forming a second dielectric liner on at least a portion of the top surface of the second sacrificial material; and annealing the integrated circuit to remove the second sacrificial material while retaining the second dielectric liner.

[0018] The source and drain regions can be, for example, doped portions of a given fin or substrate, or epitaxial regions deposited during etching and replacement source / drain formation processes. The type of dopant in the source and drain regions will depend on the polarity of the respective transistor. The gate structure can be implemented using a gate-first process or a gate-last process (sometimes referred to as a replacement metal gate or RMG process). Any number of semiconductor materials can be used to form the transistor, such as group IV materials (e.g., silicon, germanium, silicon-germanium) or group III-V materials (e.g., gallium arsenide, indium gallium arsenide).

[0019] The use of the techniques and structures provided herein can be detected using several suitable example analytical tools: electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); compositional mapping; X-ray crystallography or diffraction (XRD); energy-dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atomic probe imaging or tomographic imaging; local electrode atomic probe (LEAP) technology; 3D tomographic imaging; or high-resolution physical or chemical analysis. For example, in some example embodiments, such a tool can indicate the presence of a dielectric ridge in a forked structure having an air gap extending almost the entire width of the dielectric ridge (e.g., constrained by a dielectric liner on the edge of the dielectric ridge). In some embodiments, such a tool can indicate a conformal gate dielectric around the nanosheets such that at least a portion of the gate dielectric is also present directly between the semiconductor nanosheets and on the dielectric ridge. Many configurations and variations will be apparent from this disclosure.

[0020] It should be readily understood that the meanings of “above” and “on top of” in this disclosure should be interpreted in the broadest sense, such that “above” and “on top of” not only mean “directly on” something, but also include the meaning of being on something with an intermediate feature or layer therebetween. Furthermore, for ease of description, this document may use spatially relative terms such as “below”, “under”, “below”, “above”, “on top”, “top”, “bottom” to describe the relationship of one element or feature to another element or feature shown in the figures. In addition to the orientations shown in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein may be interpreted accordingly.

[0021] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A monolayer is a layer composed of a single layer of atoms of a given material. A layer may extend over the entire underlying or overlying structure, or may have a range smaller than that of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or non-homogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may lie between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes thereon. A layer may extend horizontally, vertically, and / or along a conical surface. A layer may conform to a given surface (whether planar or curved) and have a relatively uniform thickness throughout the layer.

[0022] As used herein, “materials with different compositions” or “materials with distinct compositions” refers to two materials with different chemical compositions. This compositional difference may be, for example, due to one material containing an element that the other does not (e.g., SiGe has a composition different from silicon), or due to one material having all the same elements as the second material, but at least one of these elements being intentionally present in a different concentration in one material relative to the other (e.g., SiGe with 70 atomic percent germanium is compositionally different from SiGe with 25 atomic percent germanium). In addition to this diversity of chemical compositions, materials may also have different dopants (e.g., gallium and magnesium) or the same dopants but at different concentrations. In other embodiments, materials with different compositions may also refer to two materials with different crystal orientations. For example, (110) silicon may be compositionally different from (100) silicon. Different orientations can be stacked, for example, by blanket wafer layer transfer. If the two materials are elementally different, then one material has elements that are not present in the other.

[0023] Architecture

[0024] Figure 1A This is a cross-sectional view of four example semiconductor devices 101a, 101b, 103a and 103b according to embodiments of the present disclosure. Figure 1B It is along Figure 1A A plan view of the semiconductor device, intercepted by the dashed line 1B-1B, and Figure 1A It shows along Figure 1B The cross-section is shown by the dashed line 1A-1A. It should be noted that, given the location of the cross-section shown, some material layers are... Figure 1B It is not visible in the plan view.

[0025] According to some embodiments, semiconductor devices 101a and 101b may be gate-all-around (GAA) transistors, and semiconductor devices 103a and 103b are part of a fork-plate structure or arrangement having a dielectric ridge 122. Other transistor topologies and types (e.g., finFETs, planar transistors) may also be used in conjunction with the fork-plate techniques and structures provided herein. According to some embodiments, a given semiconductor device may be formed as part of a GAA transistor or fork-plate arrangement based on its distance from adjacent semiconductor devices. Those devices formed relatively close together (e.g., semiconductor devices 103a and 103b) may form a fork-plate arrangement, while those formed far from adjacent devices (e.g., semiconductor devices 101a and 101b) may form GAA transistors or finFETs (e.g., tri-gate or dual-gate). Further details regarding the formation of semiconductor devices 101a, 101b, 103a, and 103b are provided herein. Semiconductor devices 101a, 101b, 103a, and 103b represent part of an integrated circuit that may include any number of similar semiconductor devices.

[0026] As can be seen, semiconductor devices are formed on substrate 102. Any number of semiconductor devices can be formed on substrate 102. Substrate 102 can be a bulk substrate, for example, comprising group IV semiconductor materials (e.g., silicon, germanium, or silicon-germanium), group III-V semiconductor materials (e.g., gallium arsenide, indium gallium arsenide, or indium phosphide), and / or any other suitable material on which transistors can be formed. Alternatively, substrate 102 can be a semiconductor-on-insulator substrate having the desired semiconductor layer on a buried insulating layer (e.g., silicon over silicon dioxide). Alternatively, substrate 102 can be a multilayer substrate or superlattice suitable for forming nanowires or nanoribbons (e.g., alternating layers of silicon and SiGe, or alternating layers of indium gallium arsenide and indium phosphide). Any number of substrates can be used. In some example embodiments, the lower portion (or all) of substrate 102 is removed and replaced with one or more back-side interconnect layers to form back-side signal and / or power wiring.

[0027] Each of semiconductor devices 101a and 101b includes one or more nanoribbons 104, which are spaced along one direction (e.g., between the source and drain regions) Figure 1AThe nanoribbons 104 (in the first direction of the page in the cross-sectional view) extend parallel to each other. The nanoribbon 104 is an example of a semiconductor region or semiconductor body extending between the source and drain regions. Similarly, each of the semiconductor devices 103a and 103b includes one or more nanosheets 105 that extend parallel to each other along the first direction between the respective source and drain regions. Generally, the term nanoribbon refers to a semiconductor region used in a GAA structure having a gate that surrounds all sides of the semiconductor region within the gate trench, and the term nanosheet refers to a semiconductor region used in a forked structure having a gate that surrounds only some sides of the semiconductor region within the gate trench. The semiconductor material of the nanoribbon 104 and nanosheet 105 can be formed from the substrate 102. In some embodiments, semiconductor devices 101a, 101b, 103a, and 103b may each include fins having alternating layers of material (e.g., alternating layers of silicon and SiGe), which facilitates the formation of the illustrated nanoribbon 104 and nanosheet 105 during the gate formation process, during which one type of alternating layer is selectively etched away to release another type of alternating layer in the channel region. According to some examples, the alternating layers may be blanket-deposited and then etched into fins or deposited into fin trenches. In the illustrated example, nanoribbon 104 and nanosheet 105 appear to have similar geometries. In other examples, nanoribbon 104 and nanosheet 105 may have different geometries, for example, in the case where nanoribbon 104 is thicker (in the vertical direction) than nanosheet 105. In some such cases, the nanosheet may be thinned during the gate formation process. In other such cases, the fins used to form nanoribbon 104 have a first geometric profile (configured to provide a relatively tall nanoribbon), while nanosheet 105 has a second geometric profile (configured to provide a relatively thin nanosheet).

[0028] Furthermore, it can be seen that adjacent semiconductor devices are separated at their bases by a dielectric filler 106, which may include silicon dioxide. The dielectric filler 106 provides shallow trench isolation (STI) between adjacent sub-fin regions 108 of any adjacent semiconductor device. The dielectric filler 106 can be any suitable dielectric material, such as silicon dioxide, alumina, or silicon oxynitride.

[0029] According to some embodiments, the sub-fin region 108 comprises the same semiconductor material as the substrate 102 and is adjacent to the dielectric filler 106. According to some embodiments, a nanoribbon 104 (or other semiconductor body) extends in a first direction between the source and drain regions to provide an active region (e.g., a semiconductor region below the gate) for a GAA transistor, and a nanosheet 105 extends in a first direction between the source and drain regions to provide an active region for a forked transistor. The source and drain regions are not in... Figure 1AIt is shown in the cross-section, but in Figure 1B In the top view, it can be seen that... Figure 1B In the top view, the nanoribbon 104 of semiconductor device 101a extends between source region 110a and drain region 112a, the nanoribbon 104 of semiconductor device 101b extends between source region 110b and drain region 112b, the nanosheet 105 of semiconductor device 103a extends between source region 110c and drain region 112c, and the nanosheet 105 of semiconductor device 103b extends between source region 110d and drain region 112d. Figure 1B A spacer structure 114 is also shown, which surrounds the ends of the nanoribbon 104 and nanosheet 105 and extends along the sidewalls of the gate structure to isolate the gate structure from adjacent source or drain regions. The spacer structure 114 may include a dielectric material, such as silicon nitride.

[0030] According to some embodiments, source regions 110a-d and drain regions 112a-d are epitaxial regions provided using an etching and replacement process. In other embodiments, one or both of the source and drain regions may be implanted doped native portions of, for example, semiconductor fins or substrates. Any semiconductor material suitable for the source and drain regions (e.g., group IV and group III-V semiconductor materials) can be used. Source regions 110a-d and drain regions 112a-d may include multiple layers, such as a substrate and a cap layer, to improve contact resistance. In any such case, the composition and doping of source regions 110a-d and drain regions 112a-d may be the same or different, depending on the type of transistor (e.g., n-type or p-type). For example, one transistor may be a p-type MOS (PMOS) transistor, while the other transistor may be an n-type MOS (NMOS) transistor. Any number of source and drain configurations and materials can be used.

[0031] According to some embodiments, gate structures extend over nanoribbons 104 and nanosheets 105 of different semiconductor devices. For example, a first gate structure extends across a page along a second direction over the nanoribbon 104 of semiconductor device 101a, a second gate structure extends along a second direction over the nanoribbon 104 of semiconductor device 101b, a third gate structure extends along a second direction over the nanosheet 105 of semiconductor device 103a, and a fourth gate structure extends along a second direction over the nanosheet 105 of semiconductor device 103b. The second direction (across) Figure 1A The page in the middle can be in the first direction (entering or leaving the page). Figure 1A(Orthogonal) Each gate structure includes a corresponding gate dielectric 116 and a gate electrode (or gate layer) 118. The gate dielectric 116 represents any number of dielectric layers present between the nanoribbon 104 / nanopie 105 and the gate electrode 118. The gate dielectric 116 may also be present on the surface of other structures within the gate trench, for example, on the top surface of the sub-fin region 108. A portion of the gate dielectric 116 around the nanopie 105 may be present along the sidewall surface of the dielectric ridge 122. The gate dielectric 116 may include any suitable gate dielectric material. In some embodiments, the gate dielectric 116 includes a layer of native oxide material (e.g., silicon dioxide) on the nanoribbon 104 and nanopie 105 constituting the channel region of the device, and a layer of high-k dielectric material (e.g., hafnium oxide) on the native oxide.

[0032] The gate electrode 118 can represent any number of conductive layers, such as any metal, metal alloy, or doped polycrystalline silicon layer. In some embodiments, the gate electrode 118 comprises one or more work function metals surrounding the nanoribbon 104 and nanosheet 105. In some embodiments, at least one of the semiconductor devices is a p-channel device comprising a work function metal of titanium surrounding its nanoribbon 104 or nanosheet 105, while another semiconductor device is an n-channel device comprising a work function metal of tungsten surrounding its nanoribbon 104 or nanosheet 105. The gate electrode 118 may also comprise a filler metal or other conductive material (e.g., tungsten, ruthenium, molybdenum, copper, aluminum) surrounding the work function metal to provide the overall gate electrode structure.

[0033] According to some embodiments, adjacent gate structures may be separated by a gate notch 120 along a second direction (e.g., across a page, from left to right), the gate notch 120 acting as a dielectric barrier or wall between the gate structures. The gate notch 120 extends vertically (e.g., third-upward) through at least the entire thickness of the adjacent gate structure. In some embodiments, the gate notch 120 also extends through the entire thickness of the dielectric filler 106. According to some embodiments, the gate notch 120 is formed of any amount of dielectric material. In some examples, the gate notch 120 comprises silicon nitride and may also comprise a core of silicon dioxide or silicon oxynitride. The gate notch 120 may have a top width along the second direction, for example, between about 15 nm and about 30 nm.

[0034] According to some embodiments, adjacent semiconductor devices 103a and 103b are part of a forked arrangement, with a dielectric ridge 122 between them. The dielectric ridge 122 similarly separates adjacent gate structures around nanosheets 105 in each of the semiconductor devices 103a and 103b. As shown, the dielectric ridge 122 extends vertically in a third direction through at least the entire thickness of the adjacent gate structures. Unlike the gate cutout 120, the dielectric ridge 122 is arranged close to the nanosheet 105 along a second direction such that no portion of the gate electrode 118 exists between the dielectric ridge 122 and the edge of the nanosheet 105 along the second direction. In some embodiments, at least a portion of the gate dielectric 116 encloses all sides of the nanosheet 105, such that at least a portion of the gate dielectric 116 is arranged directly between the dielectric ridge 122 and the nanosheet 105 along the second direction. In some embodiments, the dielectric ridge 122 directly contacts each side of the nanosheet 105.

[0035] from Figure 1B As can be seen, both the gate cutout 120 and the dielectric ridge 122 also extend in the first direction, such that they each cut at least across the entire width of the gate trench. According to some embodiments, the gate cutout 120 and / or the dielectric ridge 122 may further extend beyond the spacer body structure 114. In some examples, the gate cutout 120 and / or the dielectric ridge 122 extend in the first direction across more than one gate trench (e.g., cutting through more than one gate structure extending parallel along a second direction).

[0036] According to some embodiments, the dielectric ridge 122 includes a dielectric liner 124 along its outer edge. The dielectric liner 124 can be any suitable dielectric material, such as silicon nitride, silicon oxynitride, or silicon carbide. The dielectric liner 124 can be a high-k dielectric material to withstand various manufacturing processes occurring on the surrounding material. According to some embodiments, the dielectric liner 124 has a thickness of less than 5 nm, for example, between 1 nm and 3 nm. A dielectric layer 126 is disposed on top of the dielectric ridge 122 and can be part of a cap structure that also includes a dielectric filler 128. The dielectric layer 126 and the dielectric filler 128 together seal the top of the dielectric ridge 122. According to some embodiments, the dielectric layer 126 includes a porous dielectric material, such as any one of silicon dioxide, alumina, silicon nitride, silicon oxynitride, silicon carbide, or silicon carbide. The dielectric layer 126 can have a thickness of, for example, less than 5 nm, for example, between 1 nm and 3 nm. To give just a few examples, the dielectric filler 128 can be any suitable dielectric material, such as silicon nitride, silicon oxynitride, or silicon carbide nitride.

[0037] According to some embodiments, the dielectric ridge 122 includes an air gap 130 constrained by the dielectric liner 124 and the dielectric layer 126. Therefore, the air gap 130 can extend from a first portion of the dielectric liner 124 (e.g., on or directly adjacent to the nanosheet 105 of the semiconductor device 103a) across a second direction to a second portion of the dielectric liner 124 (e.g., on or directly adjacent to the nanosheet 105 of the semiconductor device 103b). In some embodiments, the air gap 130 can also extend along a third direction between a portion of the dielectric layer 126 and the dielectric liner 124 at the bottom of the dielectric ridge 122. As described above, the air gap 130 may not contain any solid material (e.g., only gas is present). In some examples, an inert gas such as argon or nitrogen may be present within the air gap 130.

[0038] Manufacturing method

[0039] Figure 2A-2N The figures, including cross-sectional views, collectively illustrate an example process for forming an integrated circuit having a semiconductor device with forked dielectric ridges having relatively large air gaps, according to embodiments of the present disclosure. Each figure shows an example structure produced from the process flow up to that point in time; therefore, the depicted structure evolves as the process flow continues, eventually forming... Figure 2N The structure shown is similar to... Figure 1A The structures shown are similar. The integrated circuit structure shown may be part of a larger integrated circuit including other integrated circuit systems not shown. Example materials and process parameters are given, but as will be understood, this disclosure is not intended to be limited to any particular such materials or parameters. Although the fabrication of a single dielectric ridge is shown in the above figures, it should be understood that any number of similar dielectric ridges can be fabricated on an integrated circuit as part of a fork structure using the same processes discussed herein.

[0040] Figure 2A A cross-sectional view of a substrate 201, according to an embodiment of the present disclosure, is shown. The substrate 201 has a series of material layers formed thereon. Alternating material layers may be deposited on the substrate 201, including sacrificial layers 202 alternating with semiconductor layers 204. The alternating layers are used to form GAA and forked transistor structures. Any number of alternating semiconductor layers 204 and sacrificial layers 202 may be deposited on the substrate 201. The above description of substrate 102 also applies to substrate 201.

[0041] According to some embodiments, the sacrificial layer 202 has a different material composition than the semiconductor layer 204. In some embodiments, the sacrificial layer 202 is silicon-germanium (SiGe), while the semiconductor layer 204 comprises a semiconductor material suitable for use as a nanoribbon, such as silicon (Si), SiGe, germanium, or a group III-V material such as indium phosphide (InP) or gallium arsenide (GaAs). In examples where SiGe is used in both the sacrificial layer 202 and the semiconductor layer 204, the germanium concentration differs between the sacrificial layer 202 and the semiconductor layer 204. For example, the sacrificial layer 202 may include a higher germanium content compared to the semiconductor layer 204. In some examples, the semiconductor layer 204 may be doped with an n-type dopant (to produce a p-channel transistor) or a p-type dopant (to produce an n-channel transistor).

[0042] While the dimensions may vary from one example embodiment to the next, the thickness of each sacrificial layer 202 may be between about 5 nm and about 20 nm. In some embodiments, the thickness of each sacrificial layer 202 is substantially the same (e.g., within 1-2 nm). The thickness of each semiconductor layer 204 may be approximately the same as the thickness of each sacrificial layer 202 (e.g., about 5-20 nm). Each of the sacrificial layer 202 and the semiconductor layer 204 may be deposited using any known or proprietary material deposition technique, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0043] Figure 2B The following is a description of the embodiments. Figure 2A The diagram shows a cross-sectional view of the structure after the formation of the fin patterning layer 205 and subsequently the formation of fins 209a-209d beneath the fin patterning layer 215. The fin patterning layer 205 can be any suitable hard mask material, such as a carbon hard mask (CHM), or any combination of material layers that can be easily removed after an etching process. The fin patterning layer 205 is patterned into multiple rows to form corresponding rows of fins from an alternating stack of sacrificial layer 202 and semiconductor layer 204. The multiple rows of fins extend longitudinally in a first direction (e.g., into and out of the page). Note that in the illustrated fin arrangement, the distance between fins 209c and 209d along a second direction (e.g., across the page) is less than the distance between fins 209b and 209d, and less than the distance between fins 209a and 209c. In this example, fins 209c and 209d are patterned more closely together as part of a fork structure, and fins 209a and 209b are patterned with a larger spacing between them and their adjacent fins to form a GAA structure.

[0044] According to some embodiments, an anisotropic etching process continues through the stacked layers into at least a portion of the substrate 201. The etched portion of the substrate 201 may be filled with a dielectric filler 206, which serves as shallow trench isolation (STI) between adjacent fins. The dielectric filler 206 may be any suitable dielectric material, such as silicon dioxide. According to some embodiments, sub-fin regions 208 represent the remaining portion of the substrate 201 between the dielectric fillers 206.

[0045] Figure 2C Depicting according to some embodiments Figure 2B The diagram shows a cross-sectional view of the structure after the formation of the sacrificial ridge material 210. The sacrificial ridge material 210 can be deposited using any suitable conformal deposition process (e.g., CVD, PECVD, or ALD). The sacrificial ridge material 210 can be any suitable material that can be safely removed later without damaging the surrounding structure. In some embodiments, the sacrificial ridge material 210 comprises silicon dioxide or aluminum oxide. Note that due to the distance between the different fins, the sacrificial ridge material 210 essentially fills the region between fins 209c and 209d, while leaving space between other assemblies of fins (e.g., between fins 209a and 209c and between fins 209d and 209b).

[0046] Figure 2D Depicting according to some embodiments Figure 2C The structure shown removes the sacrificial ridge material 210 from around fins 209a and 209b after an etch-back process, leaving a cross-sectional view of the sacrificial ridge material 210 between fins 209c and 209d. An isotropic etching process can be used to remove all exposed portions of the sacrificial ridge material 210. The portion of the sacrificial ridge material 210 between fins 209c and 209d is protected by these fins and thus remains after the other portions of the sacrificial ridge material have been removed. According to some embodiments, the top surface of the sacrificial ridge material 210 is substantially coplanar with or beneath the top surface of the fin patterning layer 205.

[0047] Figure 2E Depicting according to some embodiments Figure 2DThe diagram shows a cross-sectional view of the structure after the formation of a sacrificial gate 212 extending across the fin in a second direction (e.g., across the page). The sacrificial gate 212 may extend across the fin in a second direction orthogonal to the first direction. According to some embodiments, the fin patterning layer 205 may be removed using any suitable isotropic etching technique prior to the formation of the sacrificial gate 212. According to some embodiments, the sacrificial gate material is formed as a parallel strip across the integrated circuit and is removed in all areas not protected by the gate masking layer. The sacrificial gate 212 may be any suitable material that can be selectively removed without damaging the semiconductor material of the fin. In some examples, the sacrificial gate 212 comprises polysilicon. In some cases, the sacrificial gate 212 may also include a dielectric liner, such as an oxide of the fin material, covering the exposed surface of the fin. According to some embodiments, the top surface of the sacrificial gate 212 may be polished, for example, using chemical mechanical polishing (CMP), such that it is substantially coplanar with the top surface of the sacrificial ridge material 210.

[0048] After the sacrificial gate 212 is formed (and before it is replaced with a metal gate), additional semiconductor device structures, not shown in these cross-sections, are formed. These additional structures include spacer structures on the sidewalls of the sacrificial gate 212 and source and drain regions at either end of each fin. Such structures can be formed using any number of processing techniques.

[0049] Figure 2F Depicting according to some embodiments Figure 2E The diagram shows a cross-sectional view of the structure after the sacrificial gate 212 and sacrificial layer 202 have been removed. In examples where any gate shielding layer still exists, it can also be removed at this point. Once the sacrificial gate 212 is removed, the fins located beneath it are exposed.

[0050] According to some embodiments, the sacrificial layer 202 is selectively removed to release nanoribbons 214 and nanosheets 216 extending between respective source or drain regions. Each vertical assembly of nanoribbons 214 and nanosheets 216 represents a semiconductor or channel region of a different semiconductor device. The sacrificial gate 212 and sacrificial layer 202 can be removed using the same isotropic etching process or different isotropic etching processes.

[0051] Figure 2G Depicting according to some embodiments Figure 2FThe diagram shows a cross-sectional view of the structure after the gate structure has been formed and subsequently polished. The gate structure includes a gate dielectric 218 / 220 and a conductive gate electrode 222. The gate dielectric 218 may be formed around all sides of the nanoribbon 214 within the gate trench, and the gate dielectric 220 may be formed only around the exposed sides of the nanosheet 216 within the gate trench (e.g., not on the side directly adjacent to the sacrificial ridge material 210). The gate dielectrics 218 and 220 may be substantially identical and are formed together prior to the formation of the gate electrode 222. The gate dielectrics 218 / 220 may include any suitable dielectric material (e.g., silicon dioxide and / or high-k dielectric materials). Examples of high-k dielectric materials include, for example, hafnium oxide, hafnium silicate, lanthanum oxide, lanthanum alumina, zirconium oxide, zirconium silicate, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples. According to some embodiments, the gate dielectric 218 / 220 includes a layer of hafnium oxide with a thickness between about 1 nm and about 5 nm. In some embodiments, the gate dielectric 218 / 220 may include one or more silicates (e.g., titanium silicate, tungsten silicate, niobium silicate, and silicates of other transition metals). In some cases, the gate dielectric 218 / 220 may include a first layer on nanoribbon 214 and nanosheet 216 and a second layer on the first layer. The first layer may be an oxide (e.g., silicon dioxide) of a semiconductor material such as nanoribbon 214 and nanosheet 216, and the second layer may be a high-k dielectric material (e.g., hafnium oxide). More generally, the gate dielectric 218 / 220 may include any number of dielectric layers. According to some embodiments, the gate dielectric 218 / 220 is formed along all exposed surfaces within the gate trench, for example, along the inner sidewalls of the spacer structure, along the top surface of the dielectric filler 206 and the sub-fin region 208. In some examples, portions of the gate dielectric 220 may be formed on the sidewall surface of the sacrificial ridge material 210, for example, the surface between nanosheets 216.

[0052] As described above, the gate electrode 222 can represent any number of conductive layers. To name just a few examples, the conductive gate electrode 222 can be deposited using electroplating, electroless plating, CVD, PECVD, ALD, or PVD. In some embodiments, the gate electrode 222 comprises doped polysilicon, a metal, or a metal alloy. Suitable examples of metals or metal alloys include aluminum, tungsten, cobalt, molybdenum, ruthenium, titanium, tantalum, copper, and their carbides and nitrides. The gate electrode 222 may include, for example, a metal filler material and one or more work function layers, resistance reduction layers, and / or barrier layers. The work function layer may include, for example, a p-type work function material (e.g., titanium nitride) for a PMOS gate, or an n-type work function material (e.g., titanium aluminum carbide) for an NMOS gate. After forming the gate structure, the entire structure may be polished or planarized such that the top surface of the gate structure (e.g., the top surface of the gate electrode 222) is flush with the top surfaces of other semiconductor elements (e.g., spacer structures defining gate trenches). In some examples, masking can be used to facilitate the processing of one gate structure type while locations of other gate structure types are masked, and vice versa.

[0053] Figure 2H Depicting according to some embodiments Figure 2G The diagram shows a cross-sectional view of the structure after the gate notch 224 has been formed. A reactive ion etching (RIE) process can be used to etch trenches through the gate structure within the gate trench. The trenches extend longitudinally along a first direction (e.g., in and out of the page), and any number of additional gate trenches can be cut. According to some embodiments, the trenches are etched to a depth at least the entire height of the gate electrode 222. In some examples, the trenches extend into a portion of the dielectric filler 206 or a portion of the substrate 201.

[0054] According to some embodiments, one or more dielectric materials are used to fill etched trenches to form gate notch 224. In some examples, the one or more dielectric materials include one or more high-k dielectric materials, such as silicon nitride, silicon oxycarbide, or silicon oxynitride. In some examples, gate notch 224 includes a dielectric liner and a dielectric filler on the dielectric liner, wherein the dielectric liner is a high-k dielectric material and the dielectric filler is a low-k dielectric material (e.g., silicon dioxide).

[0055] Figure 2I Depicting according to some embodiments Figure 2H The diagram shows a cross-sectional view of the structure after the removal of the sacrificial ridge material 210. An isotropic etching process can be used to remove the sacrificial ridge material 210, leaving ridge recesses 226 between the nanosheets 216. Note that the gate electrode 222 can be protected from the etching process by the portion of the gate dielectric 220 present on the sidewalls of the sacrificial ridge material 210.

[0056] Figure 2J Depicting according to some embodiments Figure 2I The diagram shows a cross-sectional view of the structure after the dielectric liner 228 has been formed along all sides of the ridge recess 226. The dielectric liner 228 can be conformally deposited using any suitable technique (e.g., ALD, CVD, or PECVD). The dielectric liner 228 can have a thickness of, for example, less than 5 nm (e.g., between 1 nm and 3 nm) and can be any suitable high-k dielectric material. In some examples, the dielectric liner 228 comprises silicon nitride, silicon carbide, or silicon oxynitride. Note that portions of the dielectric liner 228 can be formed directly on the sidewall surface of the nanosheet 216.

[0057] Figure 2K Depicting according to some embodiments Figure 2J The diagram shows a cross-sectional view of the structure after another sacrificial material 230 has been formed within the remaining volume of the ridge recess 226. The sacrificial material 230 may be a volatile material formulated to sublimate at temperatures below approximately 400°C. In some examples, volatile polymer materials are used for the sacrificial material 230. The sacrificial material 230 may be deposited and polished or etched back such that the top surface of the sacrificial material 230 is coplanar with or recessed below the top surface of the gate electrode 222. During this process, the portion of the dielectric liner 228 at the top of the structure may also be removed.

[0058] Figure 2L Depicting according to some embodiments Figure 2K The diagram shows a cross-sectional view of the structure after the sacrificial material 230 has been further recessed and the dielectric layer 232 has been formed. Any suitable isotropic etching process can be used to recess the sacrificial material 230 below the top surface of the gate electrode 222. In some examples, the top surface of the sacrificial material 230 is recessed such that it is located below the top surface of the gate electrode 222, but above the topmost surface of the nanosheet 216.

[0059] According to some embodiments, a dielectric layer 232 is formed on the top surface of the sacrificial material 230, such that the sacrificial material 230 is constrained on all sides at least between the dielectric liner 228 and the dielectric layer 230. The dielectric layer 232 may be a porous dielectric material having a pore size at least larger than that of the sublimated molecules of the sacrificial material 230. In some examples, the dielectric layer 232 comprises silicon dioxide, alumina, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide nitride, or silicon carbide nitride. The dielectric layer 232 may have a similar or thinner thickness than the dielectric liner 228. In some examples, the thickness of the dielectric layer 232 is less than 5 nm, less than 3 nm, or between 1 nm and 3 nm.

[0060] Figure 2M Depicting according to some embodiments Figure 2L The structure shown is a cross-sectional view of the air gap 234 remaining after the removal of the sacrificial material 230. This structure can be heated to a temperature between approximately 200°C and 400°C for 30 minutes to 2 hours to sublimate the sacrificial material 230. The gaseous sacrificial material 230 can escape through the pores of the dielectric layer 232. As a result, the air gap 234 remains in the volume previously occupied by the sacrificial material 230. According to some embodiments, the air gap 234 extends along a second direction from a portion of the dielectric liner 228 to another portion of the dielectric liner 226. The air gap 234 can also extend along a third direction between the bottom of the dielectric liner 228 and the dielectric layer 232 at the top of the ridge structure. The air gap 234 can be completely encapsulated by the dielectric liner 228 and the dielectric layer 232. As mentioned above, the air gap 234 may include trace amounts of gas, such as nitrogen or argon.

[0061] Figure 2N Depicting according to some embodiments Figure 2M The structure shown is a cross-sectional view after a dielectric plug 236 is formed on dielectric layer 232 to form a cap structure at the top of the dielectric ridge. The dielectric plug 236 can be any suitable dielectric material, such as silicon nitride. In some examples, the dielectric plug 236 is polished after deposition such that the top surface of the dielectric plug 236 is substantially coplanar with the top surface of the adjacent spacer structure or gate notch 224.

[0062] Figure 3 Depicting according to some embodiments Figure 2M The diagram shows another cross-sectional view of the structure after which a conductive bridge 302 is optionally formed on the dielectric ridge. The conductive bridge 302 connects the gate electrode 222 between fork devices on either side of the dielectric ridge. According to some embodiments, a dielectric layer 304 is formed on this structure, and the conductive bridge 302 is formed through a portion of the dielectric layer 302. The dielectric layer 304 may be part of a first interconnect layer in the top-side interconnect region. The dielectric layer 304 may be any suitable dielectric material, such as silicon dioxide. The conductive bridge 302 may include any suitable semiconductor material, such as ruthenium, tungsten, cobalt, or molybdenum.

[0063] Figure 4 An example embodiment of a chip package 400 according to embodiments of the present disclosure is shown. As can be seen, the chip package 400 includes one or more dies 402. The one or more dies 402 may include at least one integrated circuit having a semiconductor device (e.g., any semiconductor device disclosed herein). In some example configurations, the one or more dies 402 may include any other circuitry for interfacing with other devices formed on the die or connected to the chip package 400.

[0064] As can be further seen, the chip package 400 includes a housing 404 bonded to a package substrate 406. The housing 404 can be any standard or proprietary housing and can provide, for example, electromagnetic shielding and environmental protection for components of the chip package 400. One or more dies 402 can be electrically coupled to the package substrate 406 using connections 408, which can be implemented using any number of standard or proprietary connection mechanisms, such as solder bumps, ball grid arrays (BGAs), pins, or wire bonding, to name just a few examples. The package substrate 406 can be any standard or proprietary package substrate, but in some cases includes a dielectric material having conductive paths (e.g., including conductive vias and lines) extending through the dielectric material between or at different locations on the various faces of the package substrate 406. In some embodiments, the thickness of the package substrate 406 can be less than 1 mm (e.g., between 0.1 mm and 0.5 mm), but any number of package geometries can be used. Additional conductive contacts 412 can be provided on opposite faces of the package substrate 406 for conductive contact, for example, a printed circuit board (PCB). One or more vias 410 extend through the thickness of the package substrate 406 to provide a conductive path between one or more connections 408 and one or more contacts 412. For ease of illustration, the vias 410 are shown as a single line through the package substrate 406, but other configurations may also be used (e.g., damascene, dual damascene, through-silicon vias, or meandering through the thickness of the substrate 406 to contact interconnect structures at one or more intermediate locations). In other embodiments, the vias 410 are fabricated from a plurality of smaller stacked vias, or staggered at different locations across the package substrate 406. In the illustrated embodiment, the contacts 412 are solder balls (e.g., for bump-based connections or ball grid array arrangements), but any suitable package bonding mechanism may be used (e.g., pins in a pin grid array arrangement or pads in a pad grid array arrangement). In some embodiments, solder resist is disposed between the contacts 412 to prevent short circuits.

[0065] In some embodiments, molding material 414 may be disposed around one or more dies 402 included within housing 404 (e.g., as an underfill material between die 402 and encapsulation substrate 406, and as an overfill material between die 402 and housing 404). While the size and weight of molding material 414 may vary from one embodiment to the next, in some embodiments, the thickness of molding material 414 is less than 1 mm. Example materials that may be used for molding material 414 include epoxy molding materials (as applicable). In some cases, molding material 414 is thermally conductive in addition to electrical insulation.

[0066] Methodology

[0067] Figure 5 This is a flowchart of a method 500 for forming at least a portion of an integrated circuit according to an embodiment. Various operations of method 500 can be performed... Figure 2A-2N The figures above illustrate the various operations of method 500. However, the relevance of the various operations of method 500 to the specific components shown in the figures above is not intended to imply any structural and / or usage limitations. Rather, the figures above provide an example embodiment of method 500. Other operations may be performed before, during, or after any operation of method 500. For example, method 500 is not explicitly described as all processes performed to form a common transistor structure. Some operations of method 500 may be performed in a different order than that shown.

[0068] According to some embodiments, method 500 begins with operation 502, in which at least two parallel semiconductor fins are formed. According to some embodiments, the fins comprise alternating layers of material (e.g., alternating silicon and SiGe layers), which facilitates the formation of nanoribbons and nanosheets during the gate formation process, during which one type of alternating layer is selectively etched away to release another type of alternating layer in the channel region, thereby enabling gate all-around (GAA) and fork-die processes. The alternating layers may be blanket-deposited and then etched into fins, or deposited into fin trenches. According to some embodiments, the fins also include a cap layer over each fin, which can serve as a hard mask to define the fin's location during, for example, a RIE process. The cap layer may be a dielectric material, such as silicon nitride, or any suitable hard mask material.

[0069] According to some embodiments, a dielectric layer is formed around the sub-fin portions of the fin. In some embodiments, the dielectric layer extends between each pair of adjacent parallel fins and extends longitudinally in the same direction as the fins. In some embodiments, the anisotropic etching process forming the fins also etches into a portion of the substrate, and the dielectric layer may be formed within a recessed portion of the substrate. Thus, the dielectric layer acts as shallow trench isolation (STI) between adjacent fins. The dielectric layer can be any suitable dielectric material, such as silicon dioxide.

[0070] Method 500 continues to operation 504, wherein a first sacrificial material is formed between the fins. According to some embodiments, the first sacrificial material is conformally deposited over all the fins on the substrate, and then etched back using, for example, an isotropic etching process. The etching process removes the first sacrificial material from around the fins that are sufficiently spaced apart, but the first sacrificial material remains between the fins that are closer together, because the fins protect the etchant from reaching the first sacrificial material between the fins. In some embodiments, the first sacrificial material comprises silicon dioxide or aluminum oxide.

[0071] Method 500 continues to operation 506, wherein a sacrificial gate and spacer structure are formed over the fin. The sacrificial gate can be patterned using a gate masking layer in strips extending orthogonally over the fin (a plurality of gate masking layers and corresponding sacrificial gates can be formed parallel to each other (e.g., forming a cross-shading pattern with the fin)). The gate masking layer can be any suitable hard mask material, such as CHM or silicon nitride. The sacrificial gate can be formed of any suitable material that can be selectively removed later without damaging the semiconductor material of the fin. In one example, the sacrificial gate comprises polysilicon. The spacer structure can be deposited and then etched back such that the spacer structure remains primarily only on the sidewalls of any exposed structure. According to some embodiments, the spacer structure can be any suitable dielectric material, such as silicon nitride or silicon oxynitride. The top surface of the sacrificial gate can be polished to be substantially coplanar with the top surface of the first sacrificial material.

[0072] Method 500 continues to operation 508, wherein a source region or drain region is formed at the end of the semiconductor region of each fin. Any portion of the fin not protected by the sacrificial gate and spacer structure can be removed using, for example, an anisotropic etching process, followed by epitaxial growth of the source or drain region from the exposed end of the semiconductor layer in the fin. In some examples, an internal gate spacer is formed via a source-drain recess prior to the epitaxial growth of the source and drain regions. In some example embodiments, the source or drain region is an NMOS source or drain region (e.g., epitaxial silicon) or a PMOS source or drain region (e.g., epitaxial SiGe). Another dielectric filler can be formed near each source or drain region to provide additional electrical isolation between adjacent regions. The dielectric filler can also extend over the top surface of the source or drain region. In some embodiments, a top-side conductive contact can be formed via the dielectric filler to contact one or more source or drain regions.

[0073] Method 500 continues to operation 510, in which the sacrificial gate is removed and replaced with a gate structure. The sacrificial gate can be removed using an isotropic etching process that selectively removes all material from the sacrificial gate, thereby exposing the individual fins between the set of spacer structures. According to some embodiments, any sacrificial layer within the exposed fins between the spacer structures can also be removed to release nanoribbons or nanosheets of semiconductor material (e.g., directly adjacent to the first sacrificial material).

[0074] The gate structure may include a gate dielectric and a gate electrode. According to some embodiments, the gate dielectric is first formed over an exposed semiconductor region between spacer structures, and then the gate electrode is formed within the remainder of the trench between the spacer structures. The gate dielectric may include any number of dielectric layers deposited using a CVD process such as ALD. The gate electrode may include any number of conductive material layers, such as any metal, metal alloy, or polysilicon. The gate electrode may be deposited using electroplating, electroless plating, CVD, ALD, PECVD, or PVD, to name just a few examples. A first sacrificial material may directly separate the first gate structure from the second gate structure, thereby acting as a dielectric ridge between nanosheets adjacent to either side of the first sacrificial material.

[0075] Method 500 continues to operation 512, wherein the first sacrificial material is removed to form a trench recess between nanosheets of adjacent devices. According to some embodiments, an isotropic etching process is used to remove the first sacrificial material. The first sacrificial material comprises a material that can be safely removed without damaging the surrounding material.

[0076] Method 500 continues to operation 514, wherein a dielectric liner is formed within the trench recess. The dielectric liner can be conformally deposited using any suitable technique (e.g., ALD, CVD, or PECVD). The dielectric liner can have a thickness of, for example, less than 5 nm (e.g., between 1 nm and 3 nm) and can be any suitable high-k dielectric material. In some examples, the dielectric liner comprises silicon nitride, silicon carbide, or silicon oxynitride. In some examples, portions of the dielectric liner are formed directly on the exposed sidewall surface of a nanosheet within the trench recess.

[0077] Method 500 continues to operation 516, wherein a second sacrificial material is formed within the remaining volume of the trench recess. According to some embodiments, the second sacrificial material is formed on a dielectric liner within the trench recess. The second sacrificial material may be a volatile material formulated to sublimate at a temperature below about 400°C. In some examples, a volatile polymer material is used as the second sacrificial material. The second sacrificial material may be deposited and then polished or etched back such that the top surface of the second sacrificial material is coplanar with or recessed below the top surface of the gate electrode or adjacent spacer structure.

[0078] Method 500 continues to operation 518, wherein a dielectric layer is formed on the top surface of the second sacrificial material. According to some embodiments, the dielectric layer is a porous dielectric material having a pore size at least larger than the sublimated molecules of the second sacrificial material. In some examples, the dielectric layer includes silicon dioxide, alumina, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide nitride, or silicon oxycarbide nitride. The dielectric layer may have a similar or thinner thickness than the dielectric liner. In some examples, the second sacrificial material is further recessed into a trench before the dielectric layer is formed to control the height of the final air gap. According to some embodiments, the second sacrificial material is at least completely encapsulated by the dielectric liner and the dielectric layer within the trench recess.

[0079] Method 500 continues to operation 520, in which the entire structure is annealed to sublimate and remove the second sacrificial material. The structure can be heated to a temperature between approximately 200°C and 400°C for 30 minutes to 2 hours to sublimate the second sacrificial material. The gaseous second sacrificial material can escape through the pores of the dielectric layer. As a result, the gas gap remains in the volume previously occupied by the second sacrificial material and constrained by the dielectric liner and dielectric layer. As described above, the gas gap may include trace amounts of gas, such as nitrogen or argon. After the removal of the second sacrificial material, the gas gap can be subjected to vacuum pressure.

[0080] Example System

[0081] Figure 6 This is an example computing system implemented using one or more integrated circuit structures disclosed herein, according to some embodiments of this disclosure. As can be seen, computing system 600 houses a motherboard 602. Motherboard 602 may include multiple components, including but not limited to a processor 604 and at least one communication chip 606, each of which may be physically and electrically coupled to motherboard 602 or otherwise integrated therein. As will be understood, motherboard 602 may be, for example, any printed circuit board (PCB), whether it is a motherboard, a daughterboard mounted on a motherboard, or the sole board of system 600, etc.

[0082] Depending on its application, computing system 600 may include one or more other components that may be physically and electrically coupled to motherboard 602, or may not be physically and electrically coupled to motherboard 602. These other components may include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), graphics processor, digital signal processor, cryptographic processor, chipset, antenna, display, touchscreen display, touchscreen controller, battery, audio codec, video codec, power amplifier, global positioning system (GPS) device, compass, accelerometer, gyroscope, speaker, camera, and mass storage devices (e.g., hard disk drive, compact optical disc (CD), digital versatile disc (DVD), etc.). Any components included in computing system 600 may include one or more integrated circuit structures or devices configured according to example embodiments, such as modules including integrated circuits on a substrate having various forked transistor structures as described herein. In some embodiments, multiple functions may be integrated into one or more chips (e.g., note that communication chip 606 may be part of or otherwise integrated into processor 604).

[0083] Communication chip 606 supports wireless communication for transmitting data to or from computing system 600. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., capable of transmitting data via modulated electromagnetic radiation through a non-solid-state medium. This term does not imply that the associated device does not contain any wiring, although they may not in some embodiments. Communication chip 606 can implement any of a variety of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 series), WiMAX (IEEE 802.16 series), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth and its derivatives, and any other wireless protocol designated as 3G, 4G, 5G, and above. Computing system 600 may include multiple communication chips 606. For example, the first communication chip 606 can be dedicated to short-range wireless communication such as Wi-Fi and Bluetooth, while the second communication chip 606 can be dedicated to long-range wireless communication such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, etc.

[0084] The processor 604 of the computing system 600 includes an integrated circuit die packaged within the processor 604. In some embodiments, the processor's integrated circuit die includes an onboard circuitry system implemented using one or more semiconductor devices as described herein. The term "processor" can refer to any device or part of a device, for example, that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that can be stored in registers and / or memory.

[0085] The communication chip 606 may also include an integrated circuit die packaged within the communication chip 606. According to some such example embodiments, the integrated circuit die of the communication chip includes one or more semiconductor devices as described herein. As will be understood from this disclosure, note that multi-standard wireless capabilities can be directly integrated into the processor 604 (e.g., where the functionality of any chip 606 is integrated into the processor 604, rather than having a separate communication chip). Furthermore, it should be noted that the processor 604 can be a chipset with such wireless capabilities. In short, any number of processors 604 and / or communication chips 606 can be used. Similarly, any chip or chipset can have multiple functions integrated therein.

[0086] In various embodiments, computing system 600 may be a laptop computer, netbook, notebook computer, smartphone, tablet computer, personal digital assistant (PDA), ultra-mobile PC, mobile phone, desktop computer, server, printer, scanner, monitor, set-top box, entertainment control unit, digital camera, portable music player, digital video recorder, or any other electronic device that processes data or employs one or more integrated circuit structures or devices formed using the various techniques disclosed herein, as described herein.

[0087] It will be understood that, in some embodiments, various components of the computing system 600 may be combined or integrated in a system-on-a-chip (SoC) architecture. In some embodiments, the components may be hardware components, firmware components, software components, or any suitable combination of hardware, firmware, or software.

[0088] Other example embodiments

[0089] The following examples relate to further embodiments, from which many permutations and configurations will become apparent.

[0090] Example 1 is an integrated circuit comprising: a first semiconductor device having a first semiconductor material extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor material in a second direction; a second semiconductor device having a second semiconductor material extending from a second source or drain region in the first direction and a second gate structure extending over the second semiconductor material in the second direction; and a ridge located between the first semiconductor material and the second semiconductor material and between the first gate structure and the second gate structure. The ridge includes a dielectric liner and an air gap, the dielectric liner having a first portion on the first semiconductor material and a second portion on the second semiconductor material, the air gap extending from the first portion of the dielectric liner across the second direction to the second portion of the dielectric liner.

[0091] Example 2 includes an integrated circuit according to Example 1, wherein the first semiconductor material comprises a first or more semiconductor nanosheets, and the second semiconductor material comprises a second or more semiconductor nanosheets.

[0092] Example 3 includes an integrated circuit according to Example 2, wherein the first or more semiconductor nanosheets and the second or more semiconductor nanosheets comprise germanium, silicon, or both.

[0093] Example 4 includes an integrated circuit according to any one of Examples 1-3, wherein the dielectric substrate comprises silicon and nitrogen.

[0094] Example 5 includes an integrated circuit according to any one of Examples 1-4, wherein the first semiconductor device further includes a first gate dielectric at least partially surrounding the first semiconductor material, and the second semiconductor device further includes a second gate dielectric at least partially surrounding the second semiconductor material.

[0095] Example 6 includes an integrated circuit according to Example 5, wherein the first gate dielectric is directly located on the first portion of the dielectric liner, and the first portion of the dielectric liner is directly located on the first semiconductor material; and the second gate dielectric is directly located on the second portion of the dielectric liner, and the second portion of the dielectric liner is directly located on the second semiconductor material.

[0096] Example 7 includes an integrated circuit according to Example 5 or 6, wherein both the first gate dielectric and the second gate dielectric comprise a high-k dielectric material.

[0097] Example 8 includes an integrated circuit according to any one of Examples 1-7, wherein the ridge further includes a dielectric cap located at the top of the ridge, and wherein the air gap is located below the dielectric cap.

[0098] Example 9 includes an integrated circuit according to Example 8, wherein the dielectric cap includes a dielectric layer and a dielectric plug on the dielectric layer.

[0099] Example 10 includes the integrated circuit according to Example 9, wherein the dielectric layer comprises a porous oxide material and the dielectric plug comprises silicon and nitrogen.

[0100] Example 11 includes an integrated circuit according to Example 9 or 10, wherein the air gap is directly adjacent to the dielectric layer.

[0101] Example 12 includes an integrated circuit according to any one of Examples 1-11, wherein the air gap is under vacuum pressure.

[0102] Example 13 includes an integrated circuit according to any one of Examples 1-12, wherein the ridge extends along the first direction between the first source or drain region and the second source or drain region.

[0103] Example 14 is a die comprising an integrated circuit according to any one of Examples 1-13.

[0104] Example 15 is an electronic device comprising a chip package having one or more dies. At least one of the one or more dies includes: a first semiconductor material extending in a first direction between a first source or drain region and a second source or drain region; a first gate structure extending in a second direction over the first semiconductor material; a second semiconductor material extending in the first direction between a third source or drain region and a fourth source or drain region; a second gate structure extending in the second direction over the second semiconductor material; and a ridge located between the first semiconductor material and the second semiconductor material, between the first source or drain region and the third source or drain region, and between the second source or drain region and the fourth source or drain region. The ridge includes a dielectric liner and an air gap, the dielectric liner having a first portion on the first semiconductor material and a second portion on the second semiconductor material, the air gap extending from the first portion of the dielectric liner across the second direction to the second portion of the dielectric liner.

[0105] Example 16 includes an electronic device according to Example 15, wherein the first semiconductor material comprises a first or more semiconductor nanosheets, and the second semiconductor material comprises a second or more semiconductor nanosheets.

[0106] Example 17 includes an electronic device according to Example 16, wherein the first or more semiconductor nanosheets and the second or more semiconductor nanosheets comprise germanium, silicon, or both.

[0107] Example 18 includes an electronic device according to any one of Examples 15-17, wherein the dielectric liner comprises silicon and nitrogen.

[0108] Example 19 includes an electronic device according to any one of Examples 15-18, wherein the first gate structure includes a first gate dielectric surrounding the first semiconductor material, and the second gate structure includes a second gate dielectric surrounding the second semiconductor material.

[0109] Example 20 includes the electronic device according to Example 19, wherein the first gate dielectric is located directly on the first portion of the dielectric liner, and the second gate dielectric is located directly on the second portion of the dielectric liner.

[0110] Example 21 includes an electronic device according to Example 19 or 20, wherein both the first gate dielectric and the second gate dielectric comprise a high-k dielectric material.

[0111] Example 22 includes an electronic device according to any one of Examples 15-21, wherein the ridge further includes a dielectric cap located at the top of the ridge, and wherein the air gap is located below the dielectric cap.

[0112] Example 23 includes the electronic device according to Example 22, wherein the dielectric cap includes a dielectric layer and a dielectric plug on the dielectric layer.

[0113] Example 24 includes the electronic device according to Example 23, wherein the dielectric layer comprises a porous oxide material and the dielectric plug comprises silicon and nitrogen.

[0114] Example 25 includes an electronic device according to Example 23 or 24, wherein the air gap is directly adjacent to the dielectric layer.

[0115] Example 26 includes an electronic device according to any one of Examples 15-25, wherein the air gap is under vacuum pressure.

[0116] Example 27 includes an electronic device according to any one of Examples 15-26, and further includes a printed circuit board, wherein the chip package is attached to the printed circuit board.

[0117] Example 28 is a method of forming an integrated circuit. The method includes: forming a first fin comprising a first semiconductor material and a second fin comprising a second semiconductor material, wherein the first fin and the second fin are adjacent and extend parallel to each other along a first direction; forming a first sacrificial material between the first fin and the second fin such that the first sacrificial material extends from the first semiconductor material to the second semiconductor material along a second direction substantially orthogonal to the first direction; forming a sacrificial gate over the first fin and the second fin along the second direction; forming a first source or drain region at opposite ends of the first fin and a second source or drain region at opposite ends of the second fin; replacing the sacrificial gate with one or more gate structures extending over the first semiconductor material and the second semiconductor material along the second direction; removing the first sacrificial material from between the first semiconductor material and the second semiconductor material to form a trench recess; forming a first dielectric liner within the trench recess; forming a second sacrificial material within the remaining volume of the trench recess on the dielectric liner; forming a second dielectric liner on at least a portion of the top surface of the second sacrificial material; and annealing the integrated circuit to remove the second sacrificial material while retaining the second dielectric liner.

[0118] Example 29 includes the method according to Example 28, wherein the first sacrificial material comprises silicon and oxygen.

[0119] Example 30 includes the method according to Example 28 or 29, wherein the first fin includes an alternating layer of the first semiconductor material and the first sacrificial layer, and the second fin includes an alternating layer of the second semiconductor material and the second sacrificial layer, and the method further includes removing the first sacrificial layer and the second sacrificial layer.

[0120] Example 31 includes the method according to any one of Examples 28-30, wherein the second sacrificial material has more pores than the first sacrificial material.

[0121] Example 32 includes the method according to any one of Examples 28-31, wherein the annealing includes annealing at a temperature between 200°C and 400°C.

[0122] Example 33 includes the method according to any one of Examples 28-32, further comprising forming a dielectric layer on the dielectric liner after the annealing.

[0123] Example 34 is an integrated circuit that includes a first semiconductor device having a first semiconductor material, a second semiconductor device having a second semiconductor material, and a ridge located between and in contact with the first and second semiconductor materials. The ridge includes a first dielectric liner along the sidewalls of the ridge, a second dielectric liner at the top of the ridge, and a region within the central portion of the ridge that has no solid material and is constrained by the first and second dielectric liners.

[0124] Example 35 includes an integrated circuit according to Example 34, wherein the first semiconductor material includes a first or more semiconductor nanosheets, and the second semiconductor material includes a second or more semiconductor nanosheets.

[0125] Example 36 includes an integrated circuit according to Example 35, wherein the first or more semiconductor nanosheets and the second or more semiconductor nanosheets comprise germanium, silicon, or both.

[0126] Example 37 includes an integrated circuit according to any one of Examples 34-36, wherein the first dielectric substrate comprises silicon and nitrogen.

[0127] Example 38 includes an integrated circuit according to any one of Examples 34-37, wherein the first semiconductor device further includes a first gate dielectric surrounding the first semiconductor material, and the second semiconductor device further includes a second gate dielectric surrounding the second semiconductor material.

[0128] Example 39 includes an integrated circuit according to Example 38, wherein the first gate dielectric is located directly on at least a portion of the first dielectric liner, and the second gate dielectric is located directly on at least a portion of the first dielectric liner.

[0129] Example 40 includes an integrated circuit according to Example 38 or 39, wherein both the first gate dielectric and the second gate dielectric comprise a high-k dielectric material.

[0130] Example 41 includes an integrated circuit according to any one of Examples 34-40, wherein the ridge further includes a dielectric plug located on the second dielectric substrate.

[0131] Example 42 includes the integrated circuit according to Example 41, wherein the second dielectric liner comprises a porous oxide material, and the dielectric plug comprises silicon and nitrogen.

[0132] Example 43 includes an integrated circuit according to any one of Examples 34-42, wherein the region without solid material is directly adjacent to both the first dielectric substrate and the second dielectric substrate.

[0133] Example 44 includes an integrated circuit according to any one of Examples 34-43, wherein the first semiconductor material extends from a first source or drain region in a first direction, and the second semiconductor material extends from a second source or drain region in the first direction, and the ridge extends in the first direction between the first source or drain region and the second source or drain region.

[0134] Example 45 includes an integrated circuit according to any one of Examples 34-44, wherein the region without solid material is under vacuum pressure.

[0135] Example 46 includes an integrated circuit according to any one of Examples 34-45, wherein the ridge directly contacts the first semiconductor material and the second semiconductor material.

[0136] Example 47 is a die comprising an integrated circuit according to any one of Examples 34-46.

[0137] For purposes of illustration and description, the above description of embodiments of the present disclosure has been provided. It is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Many modifications and variations are possible according to the present disclosure. It is intended that the scope of the disclosure be limited not by this detailed description, but by the appended claims.

Claims

1. An integrated circuit, comprising: A first semiconductor device, the first semiconductor device having a first semiconductor material extending from a first source or drain region in a first direction and a first gate structure extending over the first semiconductor material in a second direction; The second semiconductor device has a second semiconductor material extending from a second source or drain region in the first direction and a second gate structure extending over the second semiconductor material in the second direction. as well as A ridge, located between the first semiconductor material and the second semiconductor material and between the first gate structure and the second gate structure, wherein the ridge comprises: A dielectric liner having a first portion adjacent to the first semiconductor material and a second portion adjacent to the second semiconductor material; and An air gap extends from the first portion of the dielectric liner across the second direction to the second portion of the dielectric liner.

2. The integrated circuit according to claim 1, wherein, The first semiconductor material includes one or more first semiconductor nanosheets, and the second semiconductor material includes one or more second semiconductor nanosheets.

3. The integrated circuit according to claim 2, wherein, The first or more semiconductor nanosheets and the second or more semiconductor nanosheets include germanium, silicon, or both.

4. The integrated circuit according to claim 1, wherein, The dielectric liner comprises silicon and nitrogen.

5. The integrated circuit according to claim 1, wherein, The first semiconductor device further includes a first gate dielectric at least partially surrounding the first semiconductor material, and the second semiconductor device further includes a second gate dielectric at least partially surrounding the second semiconductor material.

6. The integrated circuit according to claim 5, wherein: The first gate dielectric is directly located on the first portion of the dielectric liner, and the first portion of the dielectric liner is directly located on the first semiconductor material; and The second gate dielectric is located directly on the second portion of the dielectric liner, and the second portion of the dielectric liner is located directly on the second semiconductor material.

7. The integrated circuit according to claim 5 or 6, wherein, Both the first gate dielectric and the second gate dielectric comprise a high-k dielectric material.

8. The integrated circuit according to any one of claims 1-7, wherein the ridge further comprises a dielectric cap located at the top of the ridge, wherein, The air gap is located below the dielectric cap.

9. The integrated circuit according to claim 8, wherein, The dielectric cap includes a dielectric layer and a dielectric plug on the dielectric layer.

10. The integrated circuit according to claim 9, wherein, The dielectric layer comprises a porous oxide material, and the dielectric plug comprises silicon and nitrogen.

11. The integrated circuit according to claim 9 or 10, wherein, The air gap is directly adjacent to the dielectric layer.

12. The integrated circuit according to any one of claims 1-7, wherein, The air gap is under vacuum pressure.

13. The integrated circuit according to any one of claims 1-7, wherein, The ridge extends along the first direction between the first source or drain region and the second source or drain region.

14. A die comprising an integrated circuit according to any one of claims 1-7.

15. An electronic device, comprising: A chip package, the chip package comprising one or more dies, at least one of the one or more dies comprising: A first semiconductor material, the first semiconductor material extending in a first direction between a first source or drain region and a second source or drain region; A first gate structure, the first gate structure extending in a second direction on the first semiconductor material; A second semiconductor material extends in the first direction between a third source or drain region and a fourth source or drain region. A second gate structure, the second gate structure extending in the second direction over the second semiconductor material; and A ridge, located between the first semiconductor material and the second semiconductor material, between the first source or drain region and the third source or drain region, and between the second source or drain region and the fourth source or drain region, wherein the ridge comprises: A dielectric liner having a first portion on the first semiconductor material and a second portion on the second semiconductor material; and An air gap extends from the first portion of the dielectric liner across the second direction to the second portion of the dielectric liner.

16. The electronic device according to claim 15, wherein, The first gate structure includes a first gate dielectric surrounding the first semiconductor material, and the second gate structure includes a second gate dielectric surrounding the second semiconductor material, wherein the first gate dielectric is directly located on the first portion of the dielectric liner, and the second gate dielectric is directly located on the second portion of the dielectric liner.

17. The electronic device according to claim 15 or 16, wherein, The ridge also includes a dielectric cap located at the top of the ridge, wherein the air gap is located below the dielectric cap.

18. The electronic device according to claim 17, wherein, The dielectric cap includes a dielectric layer and a dielectric plug on the dielectric layer.

19. The electronic device according to claim 18, wherein, The air gap is directly adjacent to the dielectric layer.

20. An integrated circuit, comprising: A first semiconductor device, the first semiconductor device having a first semiconductor material; A second semiconductor device, the second semiconductor device having a second semiconductor material; as well as A ridge, centrally aligned between the first semiconductor material and the second semiconductor material, wherein the ridge comprises: A first dielectric liner is provided along the sidewall of the ridge; A second dielectric liner, the second dielectric liner being located at the top of the ridge; and The region, which is located within the central portion of the ridge, contains no solid material and is constrained by the first dielectric liner and the second dielectric liner.

21. The integrated circuit according to claim 20, wherein, The first semiconductor device further includes a first gate dielectric surrounding the first conductor material, and the second semiconductor device further includes a second gate dielectric surrounding the second semiconductor material, wherein the first gate dielectric is directly located on at least a portion of the first dielectric liner, and the second gate dielectric is directly located on at least a portion of the first dielectric liner.

22. The integrated circuit according to claim 20, wherein, The ridge also includes a dielectric plug on the second dielectric liner.

23. The integrated circuit according to claim 22, wherein, The second dielectric liner comprises a porous oxide material, and the dielectric plug comprises silicon and nitrogen.

24. The integrated circuit according to claim 20, wherein, The first semiconductor material extends from the first source or drain region in the first direction, and the second semiconductor material extends from the second source or drain region in the first direction, and the ridge extends in the first direction between the first source or drain region and the second source or drain region.

25. The integrated circuit according to any one of claims 20-24, wherein, The ridge directly contacts the first semiconductor material and the second semiconductor material.

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