Silicon-controlled electrostatic protection device with low triggering and high maintaining voltage and preparation method of silicon-controlled electrostatic protection device

Abstract

The invention provides a silicon controlled electrostatic protection device with low triggering and high maintaining voltage and a preparation method thereof. A layer of P-type injection region is added below a third N + injection region bridged between a first N well and a first P well in an ion injection manner, and an avalanche breakdown surface is transferred to the third N + injection region and the P-type injection region, so that the trigger voltage of the device is reduced; by introducing the GGNMOS structure, after the SCR discharge path of the main path is opened, a shunting path on the surface still exists and is connected with the SCR discharge path in parallel for shunting, so that the maintaining voltage of the device is improved, and the overall robustness of the device is not obviously degraded due to the introduction of the GGNMOS structure. According to the invention, the trigger voltage can be reduced, the maintaining voltage can be increased, and the problem that the device structure is easy to latch due to over-high trigger voltage and over-low maintaining voltage can be avoided. Furthermore, the total finger length of the GGNMOS structure is adjusted by controlling the number of the GGNMOS transistors, and the maintaining voltage of the device can be adjusted.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a novel silicon-controlled static protection device with low trigger voltage and high holding voltage and a preparation method thereof. BACKGROUND

[0002] With the advancement of semiconductor process technology, the failure of integrated circuit chips and electronic products caused by electrostatic discharge (ESD) is becoming more and more serious. ESD protection of integrated circuit chips and electronic products has become one of the main problems faced by product engineers. The ESD design window is a problem that product engineers need to consider when designing ESD protection, including trigger voltage Vt1, trigger current It1, holding voltage Vh, holding current Ih, failure voltage Vt2, failure current It2, and on-resistance Ron. The trigger voltage Vt1 of the ESD protection device is less than the maximum voltage of the protected port of the core circuit (i.e. drain-source breakdown voltage), and the trigger voltage is usually lower than 10%~20% of the maximum voltage. The holding voltage Vh of the ESD protection device is higher than 1.1~1.2 times the normal working voltage VDD of the core circuit, so as to protect the core circuit from being unable to turn off due to the ESD protection device always being on and forming a latch-up. The failure current It2 of the ESD protection device is one of the important parameters for measuring the robustness of the ESD protection device, indicating the maximum current that the ESD protection device can withstand. If the core circuit is to be effectively protected, the clamping voltage of the ESD protection device should be less than the maximum voltage of the protected port when the failure current It2 is reached. The on-resistance Ron of the ESD protection device is the resistance characteristic after the device enters the holding point, and is related to the holding voltage Vh, the holding current Ih, the failure voltage Vt2, and the failure current It2. According to Ohm's law, the on-resistance Ron is represented as the ratio of the difference between the failure voltage Vt2 and the holding voltage Vh to the difference between the failure current It2 and the holding current Ih. The human body model HBM considers the equivalent resistance of the human body to be 1.5kΩ, and the HBM protection level is 1500 times the failure current It2.

[0003] The modes of ESD-induced failure are hard failure, soft failure, and potential failure. The causes of these failures can be divided into electrical failure and thermal failure. Thermal failure refers to the generation of several amperes to several tens of amperes of current in a local part of the chip when an ESD pulse occurs, which lasts for a short time but generates a large amount of heat, causing the local metal wiring to melt or causing the chip to produce a hot spot, thereby leading to secondary breakdown. Electrical failure refers to the electric field strength formed by the voltage applied to the gate oxide layer being greater than the dielectric strength, causing surface breakdown or dielectric breakdown. Due to the increasing threat of ESD to chips, the physical mechanism research has been increasingly valued.

[0004] The mainstream ESD devices are four kinds, respectively diode, triode (BJT), metal oxide semiconductor field effect transistor (MOSFET), silicon controlled rectifier (SCR), wherein diode and triode are used for low-voltage CMOS process, metal oxide semiconductor field effect transistor and silicon controlled rectifier structure are used for high-voltage BCD process. Compared with other ESD devices, the traditional unidirectional silicon controlled rectifier device has a double-conductance modulation mechanism, high unit area discharge rate, small unit parasitic capacitance and best robustness.

[0005] The existing unidirectional silicon controlled rectifier electrostatic protection device can generally reach about 3A in the single finger (total finger length 100um), but the trigger voltage Vt1 is close to the gate oxide breakdown voltage (Gate Oxide Breakdown Voltage, GOBV for short), and the holding voltage Vh is generally about 2V, which is far lower than the 1.1~1.2*VDD specified by the ESD window, so the device structure itself has the risk of latching.

[0006] Therefore, how to avoid the problem of easy latching of the device structure itself caused by the high trigger voltage and the low holding voltage existing in the existing silicon controlled rectifier electrostatic protection device has become a technical problem to be solved urgently. SUMMARY

[0007] The purpose of the present application is to provide a silicon controlled rectifier electrostatic protection device with low trigger and high holding voltage and a preparation method thereof, which can reduce the trigger voltage, improve the holding voltage, and avoid the problem of easy latching of the device structure itself caused by the high trigger voltage and the low holding voltage.

[0008] To achieve the above object, an embodiment of the present application provides a low-trigger high-maintenance voltage thyristor electrostatic protection device, comprising: a P-type substrate, a plurality of isolation structures are sequentially arranged in the P-type substrate along a first direction, wherein the first direction is parallel to the surface of the P-type substrate; a plurality of well regions, comprising a first N well, a first P well, a second N well and a second P well sequentially arranged in the P-type substrate along the first direction; a plurality of implanted regions, comprising a first N+ implanted region, a first P+ implanted region and a second N+ implanted region sequentially arranged in the first N well along the first direction and isolated by the isolation structures, a third N+ implanted region formed at the junction of the first N well and the first P well and bridging the first N well and the first P well and isolated by the isolation structures, a second P+ implanted region, a fourth N+ implanted region and a third P+ implanted region sequentially arranged in the first P well along the first direction and isolated by the isolation structures, and a fifth N+ implanted region formed in the second N well and isolated by the isolation structures; a P-type implanted region formed in the first P well below the third N+ implanted region for reducing the trigger voltage of the device; a GGNMOS structure formed in the second P well, the GGNMOS structure comprising at least one GGNMOS transistor, the GGNMOS transistor comprising a sixth N+ implanted region and a seventh N+ implanted region spaced apart in the second P well along the first direction, and a gate structure formed on the second P well, the GGNMOS structure for increasing the maintenance voltage of the device; wherein the first N+ implanted region, the first P+ implanted region and the fifth N+ implanted region are connected and serve as an anode of the device, the fourth N+ implanted region, the third P+ implanted region and the gate structure are connected and serve as a cathode of the device, the sixth N+ implanted region is short-circuited with the second P+ implanted region, and the seventh N+ implanted region is connected with the second N+ implanted region.

[0009] To achieve the above object, the application further provides a preparation method of a thyristor electrostatic protection device with low trigger voltage and high holding voltage, which comprises the following steps: providing a P-type substrate, wherein a plurality of isolation structures are sequentially arranged along a first direction in the P-type substrate, and the first direction is parallel to the surface of the P-type substrate; forming a first N well, a first P well, a second N well and a second P well sequentially arranged along the first direction in the P-type substrate; forming a first N+ implantation region, a first P+ implantation region and a second N+ implantation region sequentially arranged along the first direction and isolated by the isolation structures in the first N well, forming a third N+ implantation region across the first N well and the first P well and isolated by the isolation structures at the junction of the first N well and the first P well, forming a second P+ implantation region, a fourth N+ implantation region and a third P+ implantation region sequentially arranged along the first direction and isolated by the isolation structures in the first P well, and forming a fifth N+ implantation region isolated by the isolation structures in the second N well, wherein a P-type implantation region is further formed below the third N+ implantation region in the first P well; forming a GGNMOS structure in the second P well, wherein the GGNMOS structure comprises at least one GGNMOS transistor, the GGNMOS transistor comprises a sixth N+ implantation region and a seventh N+ implantation region spaced apart along the first direction and formed in the second P well, and a gate structure formed on the second P well; performing annealing treatment on all implantation regions; connecting the first N+ implantation region, the first P+ implantation region and the fifth N+ implantation region and taking them as an anode of the device, connecting the fourth N+ implantation region, the third P+ implantation region and the gate structure and taking them as a cathode of the device, short-circuiting the sixth N+ implantation region and the second P+ implantation region, and connecting the seventh N+ implantation region and the second N+ implantation region.

[0010] The above technical solution adds a P-type implantation region below the third N+ implantation region across the first N well and the first P well by ion implantation, so that the avalanche breakdown surface is transferred to the third N+ implantation region and the P-type implantation region, thereby reducing the trigger voltage of the device; the introduction of the GGNMOS structure still has a surface shunt path in parallel with the SCR discharge path after the opening of the main path SCR discharge path, so that the holding voltage of the device is improved, and the robustness of the device as a whole is not significantly degraded due to the introduction of the GGNMOS structure. The application can reduce the trigger voltage, improve the holding voltage, and avoid the problem that the device structure itself is prone to latching due to excessively high trigger voltage and excessively low holding voltage. Further, the number of GGNMOS transistors is controlled to adjust the total length of the GGNMOS structure, so that the holding voltage of the device can be adjusted. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort based on these drawings.

[0012] Figure 1 A sectional view of an existing unidirectional silicon-controlled static protection device; Figure 2 A sectional view of an existing unidirectional silicon-controlled static protection device; Figure 1 An equivalent circuit diagram of the existing unidirectional silicon-controlled static protection device shown in Figure 3 A TLP curve diagram of the existing unidirectional silicon-controlled static protection device shown in Figure 1 Figure 4 A sectional view of a low-trigger high-maintenance-voltage silicon-controlled static protection device provided by an embodiment of the present application; Figure 5 A sectional view of a low-trigger high-maintenance-voltage silicon-controlled static protection device provided by an embodiment of the present application; Figure 4 An equivalent circuit diagram of the low-trigger high-maintenance-voltage silicon-controlled static protection device shown in Figure 6 Figure 4 A TLP curve diagram of the low-trigger high-maintenance-voltage silicon-controlled static protection device shown in Figure 7 A step schematic diagram of a preparation method of the low-trigger high-maintenance-voltage silicon-controlled static protection device provided by an embodiment of the present application; Figure 8 A device sectional view of a P-type substrate provided by an embodiment of the present application; Figure 9 A device sectional view after forming a well region provided by an embodiment of the present application; Figure 10 A device sectional view after forming an injection region provided by an embodiment of the present application.

[0013] Explanation of reference signs: 10, P-type substrate; 101, field oxide isolation structure; 11, N well; 111, first N+ injection region; 112, first P+ injection region; 12, P well; 121, second N+ injection region; 122, second P+ injection region; 103, third N+ injection region; 40, P-type substrate; D1, first direction; 41, first N well; 411, first N+ injection region; 412, first P+ injection region; 413, second N+ injection region; ​​403, Third N+ Injection Region; 42. First P-well; 421. Second P+ injection region; 422. Fourth N+ injection region; 423. Third P+ injection region; 43. The second N-well; 431. Fifth N+ Injection Region; 44. Second P-trap; 441. Sixth N+ Injection Region; 442. Seventh N+ Injection Region 45. P-type injection region; 46. ​​GGNMOS structure; 461. Gate structure; 401. Isolation structure. Detailed Implementation

[0014] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0015] Research has found that existing unidirectional SCR electrostatic discharge (ESD) devices are prone to latch-up due to their high trigger voltage and low sustaining voltage. Please refer to the following: Figures 1-3 ,in, Figure 1 This is a cross-sectional view of an existing unidirectional silicon controlled rectifier (SCR) electrostatic discharge (ESD) device. Figure 2 for Figure 1 The equivalent circuit diagram of an existing unidirectional thyristor electrostatic discharge (ESD) device is shown below. Figure 3 for Figure 1 The diagram shows the TLP curve of an existing unidirectional silicon controlled rectifier (SCR) electrostatic discharge (ESD) device. Figures 1-3 As shown, an N-well 11 and a P-well 12 are formed above a P-type substrate 10. A first N+ implantation region 111 and a first P+ implantation region 112 are formed in the N-well 11, and a second N+ implantation region 121 and a second P+ implantation region 122 are formed in the P-well 12. A third N+ implantation region 103 is formed at the junction of the N-well 11 and the P-well 12, bridging the N-well 11 and the P-well 12. Adjacent implantation regions are isolated by a field oxide (FOX) isolation structure 101. The first N+ implantation region 111 and the first P+ implantation region 112 are connected and serve as the anode of the device; the second N+ implantation region 121 and the second P+ implantation region 122 are connected and serve as the cathode of the device.

[0016] When a positive ESD pulse reaches the anode (ANODE) ​​of the device and the cathode (CATHODE) is connected to a low potential, current will enter the N-well (N-11) through the first N+ injection region 111 connected to the anode. As the pulse voltage gradually increases, avalanche breakdown will occur at the reverse PN junction formed by the third N+ injection region 103 bridging the N-well (N-11) and the P-well (P-12), generating a large avalanche current inside the device. This current will be injected into the P-well (P-12) through the third N+ injection region 103 and flow through the parasitic P-well resistor Rpw to the second P+ injection region 122 connected to the cathode, forming the device trigger path. As the ESD current gradually increases, the potential in the P-well (P-12) is raised to 0.7V, at which point the parasitic transistor NPN will turn on. This parasitic transistor NPN will provide base current for the parasitic transistor PNP. When the parasitic transistor PNP also turns on, a positive feedback mechanism is formed, and the SCR (Silicon Controlled Rectifier) ​​path is fully turned on. Even without subsequent avalanche current, the SCR can still discharge large current due to the open bleed path, providing electrostatic protection for circuits with positive operating signal voltages. However, due to its high trigger voltage (close to the gate oxide breakdown voltage GOBV) and low sustaining voltage (typically around 2V, far below the 1.1~1.2*VDD specified by the ESD window), it is prone to latch-up.

[0017] To address the aforementioned technical problems, this invention designs a novel low-trigger, high-sustaining-voltage thyristor electrostatic discharge (ESD) device suitable for 5V I / O circuits based on a thyristor structure using CMOS technology.

[0018] Please refer to the following: Figures 4-6 ,in, Figure 4 This is a cross-sectional view of a silicon controlled rectifier (SCR) electrostatic discharge (ESD) device with low triggering voltage and high sustaining voltage provided in an embodiment of the present invention. Figure 5 for Figure 4 The equivalent circuit diagram of a thyristor electrostatic discharge (ESD) device with low trigger voltage and high sustaining voltage is shown. Figure 6 for Figure 4 The TLP curve of a thyristor electrostatic discharge (ESD) device with low trigger voltage and high sustaining voltage is shown.

[0019] like Figures 4-6 As shown, the low triggering and high sustaining voltage thyristor electrostatic discharge (ESD) device described in this embodiment includes: a P-type substrate 40, multiple well regions formed in the P-type substrate, multiple injection regions formed in each well region, a P-type injection region 45, and a GGNMOS structure 46.

[0020] Specifically, a plurality of isolation structures 401 are formed in the P-type substrate 40, arranged sequentially along a first direction D1; wherein, the first direction D1 is parallel to the surface of the P-type substrate 40. The plurality of isolation structures 401 are used to isolate adjacent implantation regions.

[0021] Specifically, the multiple well regions include a first N-well 41, a first P-well 42, a second N-well 43, and a second P-well 44 formed in the P-type substrate 40 and arranged sequentially along the first direction D1.

[0022] Specifically, the multiple injection regions include: a first N+ injection region 411, a first P+ injection region 412, and a second N+ injection region 413, which are sequentially formed in the first N-well 41 along the first direction D1 and isolated by the isolation structure 401; a third N+ injection region 403, which is formed at the junction of the first N-well 41 and the first P-well 42 and spans between the first N-well 41 and the first P-well 42 and is isolated by the isolation structure 401; a second P+ injection region 421, a fourth N+ injection region 422, and a third P+ injection region 423, which are sequentially formed in the first P-well 42 along the first direction D1 and isolated by the isolation structure 401; and a fifth N+ injection region 431, which is formed in the second N-well 43 and isolated by the isolation structure 401.

[0023] Specifically, the P-type injection region 45 is formed in the first P-well 42 and is located below the third N+ injection region 403. The P-type injection region 45 is used to reduce the trigger voltage of the device.

[0024] Specifically, the GGNMOS structure 46 is formed in the second P-well 44. The GGNMOS structure 46 includes at least one GGNMOS transistor. The GGNMOS transistor includes a sixth N+ injection region 441 and a seventh N+ injection region 442 formed in the second P-well 44 and spaced apart along the first direction D1, and a gate structure 461 formed on the second P-well 44. The GGNMOS structure 46 is used to improve the sustaining voltage of the device.

[0025] Specifically, the first N+ injection region 411, the first P+ injection region 412, and the fifth N+ injection region 431 are connected and serve as the anode of the device; the fourth N+ injection region 422, the third P+ injection region 423, and the gate structure 461 are connected and serve as the cathode of the device; the sixth N+ injection region 441 is shorted to the second P+ injection region 421, and the seventh N+ injection region 442 is connected to the second N+ injection region 413. The connections can be achieved through vias and metal layers; the short connections can be achieved through metal wires without any voltage applied. That is, the first P+ injection region 412, the first N-well 41, and the first P-well 42 form a parasitic PNP transistor; the first N-well 41, the first P-well 42, and the fourth N+ injection region 422 form a parasitic NPN transistor; the sixth N+ injection region 441 and the second P+ injection region 421 form a diode; and the second N+ injection region 413 and the seventh N+ injection region 442 can directly form a current path.

[0026] In this embodiment, when a positive ESD pulse reaches the anode (ANODE) ​​and the cathode (CATHODE) is connected to a low potential, current flows through the first N+ injection region 412 connected to the anode (ANODE) ​​into the first N-well 41, and through the fifth N+ injection region 431 connected to the anode (ANODE) ​​into the second N-well 43. When both the third N+ injection region 403 and the P-type injection region 45 experience avalanche breakdown, current flows through the third N+ injection region 403 and the P-type injection region 45 into the first P-well 42, and then flows to the third P+ injection region 423 connected to the cathode (CATHODE) to form the device trigger path. That is, when a positive ESD pulse reaches the anode of the device and the cathode is connected to a low potential, the current will enter the corresponding N-wells (the first N-well 41 and the second N-well 43) through the N+ injection regions connected to the anode. As the current gradually increases, the potential in the N-wells continuously rises, causing avalanche breakdown in the third N+ injection region 403 connected between the first N-well 41 and the first P-well 42, and the P-type injection region 45 located below it. After avalanche breakdown, the current enters the first P-well 42 through the third N+ injection region 403 and the P-type injection region 45, and flows through the parasitic P-well resistance Rpw in the first P-well 42 to the third P+ injection region 423 connected to the cathode CATHODE, forming a device trigger path. Due to the introduction of the P-type injection region 45, the trigger voltage of the device is reduced compared to the traditional unidirectional thyristor structure, thus enabling the thyristor electrostatic discharge protection device provided in this embodiment to have a lower trigger voltage and avoid latch-up.

[0027] In this embodiment, after the device trigger path is formed, the parasitic PNP transistor formed by the first P+ injection region 412, the first N-well 41, and the first P-well 42 is turned on, and the parasitic NPN transistor formed by the first N-well 41, the first P-well 42, and the fourth N+ injection region 422 is turned on, forming an SCR discharge path (SCR Path shown in the figure); the current flows into the seventh N+ injection region 442 through the second N+ injection region 413, the GGNMOS structure 46 is turned on, the diode formed by the sixth N+ injection region 441 and the second P+ injection region 421 is turned on, and the current flows into the fourth N+ injection region 422 through the second P+ injection region 421, forming a shunt path in parallel with the SCR discharge path. Specifically, the breakdown voltage of the third N+ injection region 403, which spans the first N-well 41 and the first P-well 42, and the P-type injection region 45 located below it, will be lower than the breakdown voltage of the GGNMOS structure 46. Therefore, the third N+ injection region 403 and the P-type injection region 45 will undergo avalanche breakdown preferentially over the GGNMOS structure 46. After the third N+ injection region 403 and the P-type injection region 45 have broken down, the parasitic PNP transistor and the parasitic NPN transistor will conduct, forming an SCR bleed path. At this time, the device has been successfully triggered, and its breakdown surface is located in the third N+ injection region 403 and the P-type injection region 45. Because the SCR bleed path is formed, the GGNMOS structure 46 does not need to undergo avalanche breakdown. Simultaneously, after the third N+ injection region 403 and the P-type injection region 45 undergo avalanche breakdown, a portion of the current will flow from the third N+ injection region 403 into the first N-well 41, through the second N+ injection region 413 into the seventh N+ injection region 442, thereby turning on the GGNMOS structure 46; the current flows through the diode formed by the GGNMOS structure 46, the sixth N+ injection region 441, and the second P+ injection region 421 into the second P+ injection region 421, and then flows back to the device cathode through the fourth N+ injection region 422, forming a shunt path in parallel with the SCR discharge path (GGNMOS Path shown by the dashed arrow in the figure).

[0028] The introduction of the GGNMOS structure 46 ensures that even after the main SCR discharge path is activated, a surface shunt path remains connected in parallel with the SCR discharge path, thereby increasing the device's sustaining voltage. In other words, by introducing a shunt path, the device's sustaining voltage is improved, and the overall robustness of the device is not significantly degraded by the introduction of the GGNMOS structure.

[0029] In this embodiment, one side of the P-type implantation region 45 is close to the junction of the first N-well 41 and the first P-well 42, and the other side shares the same isolation structure with the third N+ implantation region 403. By adding a layer of the P-type implantation region 45 under the third N+ implantation region 403 bridging the first N-well 41 and the first P-well 42 through ion implantation, the avalanche breakdown surface is shifted from the original third N+ implantation region 403 and the first P-well 42 to the third N+ implantation region 403 and the P-type implantation region 45, thereby reducing the device's trigger voltage.

[0030] In this embodiment, the GGNMOS structure 46 includes one GGNMOS transistor. In other embodiments, the GGNMOS structure 46 may include two or more GGNMOS transistors, and the total finger length of the GGNMOS structure can be adjusted by controlling the number of GGNMOS transistors. In a GGNMOS structure, "finger length" typically refers to the length of a single finger electrode in a multi-finger parallel structure. Each finger electrode can be considered as an independent MOS transistor structure, and the finger length is the relevant dimensional parameter of these individual MOS transistors. While keeping the single finger length constant, the total finger length gradually increases as the exponent increases; as the total finger length gradually increases, the shunt effect of the current path where the GGNMOS structure is located on the SCR discharge path becomes stronger, and the sustaining voltage of the device also increases accordingly. By controlling the number of GGNMOS transistors to adjust the total finger length of the GGNMOS structure, the sustaining voltage of the device can be adjusted.

[0031] In this embodiment, the plurality of isolation structures 401 includes ten isolation structures, from a first isolation structure to a tenth isolation structure. Specifically, the first isolation structure is disposed on the side of the first N+ injection region 411 away from the first P+ injection region 412; the second isolation structure is disposed between the first N+ injection region 411 and the first P+ injection region 412; the third isolation structure is disposed between the first P+ injection region 412 and the second N+ injection region 413; the fourth isolation structure is disposed between the second N+ injection region 413 and the third N+ injection region 403; and the fifth isolation structure is disposed between the third N+ injection region 403 and the second P+ injection region 421. The following isolation structures are provided: a sixth isolation structure is disposed between the second P+ injection region 421 and the fourth N+ injection region 422; a seventh isolation structure is disposed between the fourth N+ injection region 422 and the third P+ injection region 423; an eighth isolation structure is disposed between the third P+ injection region 423 and the fifth N+ injection region 431; a ninth isolation structure is disposed between the fifth N+ injection region 431 and the sixth N+ injection region 441; and a tenth isolation structure is disposed on the side of the seventh N+ injection region 442 away from the sixth N+ injection region 441. Specifically, the eighth isolation structure is disposed at the junction of the first P-well 42 and the second N-well 43 and spans between the first P-well 42 and the second N-well 43; and the ninth isolation structure is disposed at the junction of the second N-well 43 and the second P-well 44 and spans between the second N-well 43 and the second P-well 44.

[0032] In this embodiment, the isolation structure 401 is a shallow trench isolation (STI) structure. Compared with the traditional field oxide isolation (FOX) structure, the shallow trench isolation structure can achieve smaller device size and higher integration density, reduce parasitic effects and improve device stability, and can adapt to the complex structures of advanced processes. Specifically, the field oxide isolation structure is formed by a local oxidation process (LOCOS), in which the oxide layer extends into the silicon wafer (laterally), forming a "bird's beak" structure. This lateral expansion occupies additional chip area, preventing the spacing between adjacent devices from being reduced and limiting the improvement of integration density. The "bird's beak" structure also leads to uneven isolation layer thickness, which can easily cause leakage under high voltage or high frequency conditions. In contrast, the shallow trench isolation structure is formed by etching a shallow trench on the silicon wafer, then filling it with an insulating medium (such as silicon dioxide) and planarizing it. The entire process does not have lateral "bird's beak" expansion, and the isolation spacing between adjacent devices is determined only by the trench width, which can be greatly reduced, significantly increasing the number of transistors that can be integrated per unit area. Furthermore, shallow trench isolation structures are more compact, and the parasitic capacitance between adjacent devices (such as the capacitance between the source / drain region and the isolation region) is smaller than that of field oxide isolation structures. Reduced parasitic capacitance decreases signal latency, improves chip operating speed, and lowers dynamic power consumption. The trench filling process of shallow trench isolation structures can form a uniform and dense insulating layer, resulting in lower leakage risk and higher long-term device reliability. By adjusting the trench depth and width, shallow trench isolation structures can adapt to the isolation requirements of 3D devices, making them a standard isolation technology for advanced processes such as 7nm and 5nm, and more compatible with back-end processes. As chip manufacturing processes move into deep submicron (<0.25μm) and below, the process flexibility of shallow trench isolation structures becomes crucial.

[0033] In this embodiment, the low-trigger-voltage, high-sustaining-voltage SCR electrostatic discharge (ESD) device is applied to the ESD power rail clamping circuit in a 5V I / O circuit. Specifically, by modifying the circuit structure, the trigger voltage can be further reduced, resulting in a low-hysteresis, high-robustness (low-trigger-voltage, high-sustaining-voltage) power rail clamping circuit suitable for 5V I / O circuits.

[0034] Based on the same inventive concept, an embodiment of the present invention also provides a method for preparing the above-mentioned low-trigger-high-sustaining-voltage thyristor electrostatic discharge (ESD) device.

[0035] Please refer to the following: Figure 4 as well as Figures 7-10 ,in, Figure 7 This is a schematic diagram of the steps in a method for fabricating a silicon controlled rectifier (SCR) electrostatic discharge (ESD) device with low triggering voltage and high sustaining voltage according to an embodiment of the present invention. Figure 8 This is a cross-sectional view of a device with a P-type substrate provided in an embodiment of the present invention; Figure 9This is a cross-sectional view of the device after the formation of the well region according to an embodiment of the present invention; Figure 10 This is a cross-sectional view of the device after the implantation region is formed, according to an embodiment of the present invention.

[0036] like Figure 7 As shown, the fabrication method of the low-trigger-high-sustaining-voltage thyristor electrostatic discharge (ESD) device provided in this embodiment includes the following steps: S1, providing a P-type substrate, wherein a plurality of isolation structures are formed in the P-type substrate sequentially arranged along a first direction; S2, forming a first N-well, a first P-well, a second N-well, and a second P-well sequentially arranged along the first direction in the P-type substrate; S3, forming a first N+ injection region, a first P+ injection region, and a second N+ injection region sequentially arranged along the first direction and isolated by the isolation structures in the first N-well, and forming a third N+ injection region at the junction of the first N-well and the first P-well, bridging the first N-well and the first P-well and isolated by the isolation structures. S4. A second P+ injection region, a fourth N+ injection region, and a third P+ injection region are formed in the first P-well, arranged sequentially along the first direction and isolated by the isolation structure. A fifth N+ injection region is formed in the second N-well, isolated by the isolation structure. A P-type injection region located below the third N+ injection region is also formed in the first P-well. S5. A GGNMOS structure is formed in the second P-well. The GGNMOS structure includes at least one GGNMOS transistor. The GGNMOS transistor includes a sixth N+ injection region and a seventh N+ injection region formed in the second P-well and spaced apart along the first direction, and a gate structure formed on the second P-well. S6. All injection regions are annealed. S7. The first N+ injection region, the first P+ injection region, and the fifth N+ injection region are connected together and used as the anode of the device. The fourth N+ injection region, the third P+ injection region, and the gate structure are connected together and used as the cathode of the device. The sixth N+ injection region is short-circuited to the second P+ injection region. The seventh N+ injection region is connected to the second N+ injection region.

[0037] Please refer to step S1 and Figure 8 A P-type substrate 40 is provided, wherein a plurality of isolation structures 401 are formed therein along a first direction D1. The first direction D1 is parallel to the surface of the P-type substrate 40.

[0038] In this embodiment, the isolation structure 401 is a shallow trench isolation (STI) structure.

[0039] Please refer to step S2 and Figure 9A first N-well 41, a first P-well 42, a second N-well 43, and a second P-well 44 are formed sequentially along the first direction D1 in a P-type substrate 40. The method of forming each well layer can refer to the prior art, and will not be described in detail here.

[0040] Please refer to step S3 and Figure 10 In the first N-well 41, a first N+ implantation region 411, a first P+ implantation region 412, and a second N+ implantation region 413 are formed sequentially along the first direction D1 and isolated by the isolation structure 401. At the junction of the first N-well 41 and the first P-well 42, a third N+ implantation region 403 is formed, bridging the first N-well 41 and the first P-well 42 and isolated by the isolation structure 401. In the first P-well 42, a second P+ implantation region 421, a fourth N+ implantation region 422, and a third P+ implantation region 423 are formed sequentially along the first direction D1 and isolated by the isolation structure 401. In the second N-well 43, a fifth N+ implantation region 431 is formed and isolated by the isolation structure 401. A P-type implantation region 45 is also formed in the first P-well 42, located below the third N+ implantation region 403. Ion implantation of each implantation region can be referred to in the prior art, and will not be elaborated here.

[0041] In this embodiment, one side of the P-type implantation region 45 is close to the junction of the first N-well 41 and the first P-well 42, and the other side shares the same isolation structure with the third N+ implantation region 403. By adding a layer of the P-type implantation region 45 under the third N+ implantation region 403 bridging the first N-well 41 and the first P-well 42 through ion implantation, the avalanche breakdown surface is shifted from the original third N+ implantation region 403 and the first P-well 42 to the third N+ implantation region 403 and the P-type implantation region 45, thereby reducing the device's trigger voltage.

[0042] Please refer to step S4 and continue reading. Figure 10 A GGNMOS structure 46 is formed in the second P-well 44. The GGNMOS structure 46 includes at least one GGNMOS transistor. The GGNMOS transistor includes a sixth N+ injection region 441 and a seventh N+ injection region 442 formed in the second P-well 44 and spaced apart along the first direction D1, and a gate structure 461 formed on the second P-well 44. The sixth N+ injection region 441 and the seventh N+ injection region 442 can be formed synchronously with the injection regions in step S3. The formation method of the GGNMOS structure 46 can refer to existing technology and will not be described in detail here.

[0043] In this embodiment, the GGNMOS structure 46 includes one GGNMOS transistor. In other embodiments, the GGNMOS structure 46 may include two or more GGNMOS transistors, and the total finger length of the GGNMOS structure can be adjusted by controlling the number of GGNMOS transistors. While keeping the single finger length constant, the total finger length gradually increases as the finger length gradually increases; as the total finger length gradually increases, the shunt effect of the current path where the GGNMOS structure is located on the SCR discharge path becomes stronger, and the sustaining voltage of the device also increases accordingly. By controlling the number of GGNMOS transistors to adjust the total finger length of the GGNMOS structure, the sustaining voltage of the device can be adjusted. Please refer to step S5 to anneal all injection zones. Annealing is used to eliminate the migration of impurities in the injection zones.

[0044] Please refer to step S6 and Figure 4 The first N+ injection region 411, the first P+ injection region 412, and the fifth N+ injection region 431 are connected to form the anode of the device; the fourth N+ injection region 422, the third P+ injection region 423, and the gate structure 461 are connected to form the cathode of the device; the sixth N+ injection region 441 is shorted to the second P+ injection region 421; and the seventh N+ injection region 442 is connected to the second N+ injection region 413. The connections can be made through vias and metal layers; the shorting can be made through metal wires without any voltage connection. That is, the first P+ injection region 412, the first N-well 41, and the first P-well 42 form a parasitic PNP transistor; the first N-well 41, the first P-well 42, and the fourth N+ injection region 422 form a parasitic NPN transistor; the sixth N+ injection region 441 and the second P+ injection region 421 form a diode; and the second N+ injection region 413 and the seventh N+ injection region 442 can directly form a current path.

[0045] In the above embodiments, by adding a P-type implantation region 45 below the third N+ implantation region 403 bridging the first N-well 41 and the first P-well 42 via ion implantation, the avalanche breakdown surface is shifted from the original third N+ implantation region 403 and the first P-well 42 to the third N+ implantation region 403 and the P-type implantation region 45, thereby reducing the device's trigger voltage. By introducing the GGNMOS structure 46, even after the main path SCR bleed path is activated, a surface shunt path still exists in parallel with the SCR bleed path, thus improving the device's sustaining voltage, and the overall robustness of the device is not significantly degraded by the introduction of the GGNMOS structure. That is, the present invention can reduce the trigger voltage and increase the sustaining voltage, avoiding the latch-up problem inherent in the device structure caused by excessively high trigger voltage and excessively low sustaining voltage. Furthermore, by controlling the number of GGNMOS transistors and adjusting the total finger length of the GGNMOS structure, the sustaining voltage of the device can be adjusted.

[0046] It should be noted that the terms "comprising" and "having," and their variations, used in this invention document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; it should be understood that such use of data can be interchanged where appropriate. The term "one or more" depends at least in part on the context and can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, also at least in part on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features in embodiments of this invention can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention. In the various embodiments described above, each embodiment focuses on its differences from other embodiments; similar / identical parts between embodiments can be referred to mutually.

[0047] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A thyristor electrostatic discharge (ESD) device with low trigger voltage and high holding voltage, characterized in that, include: A P-type substrate, wherein a plurality of isolation structures are formed therein along a first direction, wherein the first direction is parallel to the surface of the P-type substrate; a plurality of well regions, including a first N-well, a first P-well, a second N-well, and a second P-well formed in the P-type substrate and arranged sequentially along the first direction; a plurality of injection regions, including a first N+ injection region, a first P+ injection region, and a second N+ injection region formed sequentially in the first N-well and isolated by the isolation structures along the first direction; a third N+ injection region formed at the junction of the first N-well and the first P-well and bridging the first N-well and the first P-well and isolated by the isolation structures; a second P+ injection region, a fourth N+ injection region, and a third P+ injection region formed sequentially in the first P-well and isolated by the isolation structures along the first direction; and a fifth N+ injection region formed in the second N-well and isolated by the isolation structures. The device includes: a P-type injection region formed in the first P-well and located below the third N+ injection region, used to reduce the device's trigger voltage; a GGNMOS structure formed in the second P-well, the GGNMOS structure including at least one GGNMOS transistor, the GGNMOS transistor including a sixth N+ injection region and a seventh N+ injection region formed in the second P-well and spaced apart along the first direction, and a gate structure formed on the second P-well, the GGNMOS structure being used to improve the device's sustaining voltage; wherein, the first N+ injection region, the first P+ injection region, and the fifth N+ injection region are connected and serve as the device's anode, the fourth N+ injection region, the third P+ injection region, and the gate structure are connected and serve as the device's cathode, the sixth N+ injection region is short-circuited to the second P+ injection region, and the seventh N+ injection region is connected to the second N+ injection region.

2. The thyristor electrostatic discharge (ESD) device with low trigger voltage and high sustaining voltage according to claim 1, characterized in that, When a positive ESD pulse reaches the anode and the cathode is connected to a low potential, the current enters the first N-well through the first N+ injection region connected to the anode, and enters the second N-well through the fifth N+ injection region connected to the anode. When both the third N+ injection region and the P-type injection region experience avalanche breakdown, the current enters the first P-well through the third N+ injection region and the P-type injection region, and flows to the third P+ injection region connected to the cathode to form the device trigger path.

3. The thyristor electrostatic discharge (ESD) device with low triggering voltage and high sustaining voltage according to claim 2, characterized in that, Once the device trigger path is formed, the parasitic PNP transistor formed by the first P+ injection region, the first N-well, and the first P-well is turned on, and the parasitic NPN transistor formed by the first N-well, the first P-well, and the fourth N+ injection region is turned on, forming an SCR discharge path; current flows through the second N+ injection region into the seventh N+ injection region, the GGNMOS structure is turned on, the diode formed by the sixth N+ injection region and the second P+ injection region is turned on, and current flows through the second P+ injection region into the fourth N+ injection region, forming a shunt path in parallel with the SCR discharge path.

4. The thyristor electrostatic discharge (ESD) device with low trigger voltage and high sustaining voltage according to claim 1, characterized in that, The P-type injection region is located near the junction of the first N-well and the first P-well on one side, and shares the same isolation structure with the third N+ injection region on the other side.

5. The thyristor electrostatic discharge (ESD) device with low trigger voltage and high sustaining voltage according to claim 1, characterized in that, The GGNMOS structure includes multiple GGNMOS transistors, and the total finger length of the GGNMOS structure is adjusted by controlling the number of GGNMOS transistors.

6. The thyristor electrostatic discharge (ESD) device with low trigger voltage and high sustaining voltage according to claim 1, characterized in that, The plurality of isolation structures include: a first isolation structure disposed on the side of the first N+ injection region away from the first P+ injection region; a second isolation structure disposed between the first N+ injection region and the first P+ injection region; a third isolation structure disposed between the first P+ injection region and the second N+ injection region; a fourth isolation structure disposed between the second N+ injection region and the third N+ injection region; a fifth isolation structure disposed between the third N+ injection region and the second P+ injection region; a sixth isolation structure disposed between the second P+ injection region and the fourth N+ injection region; a seventh isolation structure disposed between the fourth N+ injection region and the third P+ injection region; an eighth isolation structure disposed between the third P+ injection region and the fifth N+ injection region; a ninth isolation structure disposed between the fifth N+ injection region and the sixth N+ injection region; and a tenth isolation structure disposed on the side of the seventh N+ injection region away from the sixth N+ injection region.

7. The low trigger voltage, high sustaining voltage thyristor electrostatic discharge (ESD) protection device according to claim 1, characterized in that, The isolation structure is a shallow trench isolation structure.

8. The thyristor electrostatic discharge (ESD) device with low trigger voltage and high sustaining voltage according to claim 1, characterized in that, The low-trigger, high-sustaining-voltage thyristor electrostatic discharge (ESD) protection device is applied to the ESD power rail clamping circuit in the 5V I / O circuit.

9. A method for fabricating a silicon controlled rectifier (SCR) electrostatic discharge (ESD) device with low triggering voltage and high sustaining voltage, characterized in that, The method includes the following steps: providing a P-type substrate, wherein a plurality of isolation structures are formed therein along a first direction, wherein the first direction is parallel to the surface of the P-type substrate; forming a first N-well, a first P-well, a second N-well, and a second P-well in the P-type substrate along the first direction; forming a first N+ injection region, a first P+ injection region, and a second N+ injection region in the first N-well along the first direction and isolated by the isolation structures; forming a third N+ injection region at the junction of the first N-well and the first P-well, bridging the first N-well and the first P-well and isolated by the isolation structures; forming a second P+ injection region, a fourth N+ injection region, and a third P+ injection region in the first P-well along the first direction and isolated by the isolation structures; and forming a second N-well through the isolation structures. An isolated fifth N+ injection region is formed, wherein a P-type injection region is also formed in the first P-well below the third N+ injection region; a GGNMOS structure is formed in the second P-well, the GGNMOS structure including at least one GGNMOS transistor, the GGNMOS transistor including a sixth N+ injection region and a seventh N+ injection region formed in the second P-well and spaced apart along the first direction, and a gate structure formed on the second P-well; all injection regions are annealed; the first N+ injection region, the first P+ injection region, and the fifth N+ injection region are connected and used as the anode of the device; the fourth N+ injection region, the third P+ injection region, and the gate structure are connected and used as the cathode of the device; the sixth N+ injection region is short-circuited to the second P+ injection region; and the seventh N+ injection region is connected to the second N+ injection region.

10. The method according to claim 9, characterized in that, The GGNMOS structure includes multiple GGNMOS transistors, and the total finger length of the GGNMOS structure is adjusted by controlling the number of GGNMOS transistors.

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