Display device

Abstract

The invention provides a display device. The display device includes: a stretchable lower substrate; a plurality of plate patterns disposed on the lower substrate and spaced apart from each other; a plurality of line patterns disposed on the lower substrate between plate patterns adjacent in a first direction among the plurality of plate patterns and between plate patterns adjacent in a second direction different from the first direction among the plurality of plate patterns; a plurality of connecting lines disposed over each of the plurality of line patterns, the plurality of connecting lines being disposed over each of the plurality of line patterns; and a plurality of auxiliary patterns adjacent to the plurality of plate patterns on the lower substrate in an oblique line direction between the first direction and the second direction.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0129673, filed on September 25, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to a display device, and more specifically, to a stretchable display device. Background Technology

[0004] As display devices used in computer monitors, televisions, or mobile phones, there are organic light-emitting display devices (OLEDs) that are self-emissive and liquid crystal display devices (LCDs) that require a separate light source.

[0005] The applications of display devices have diversified to include personal digital assistants, computer monitors, and televisions, and research is underway on display devices with wide display areas and reduced size and weight.

[0006] Recently, as a next-generation display device, display devices manufactured by forming display units and wiring on a flexible substrate, such as plastic, a flexible material, so that they can be stretched in a specific direction and changed in various forms are attracting attention. Summary of the Invention

[0007] One objective of this invention is to provide a display device with improved impact resistance.

[0008] Another objective of this invention is to provide a display device in which damage to the connecting wires is suppressed.

[0009] Another objective of this invention is to provide a display device with improved tensile reliability.

[0010] The purpose of this invention is not limited to the above-described purpose, and other purposes not mentioned above will be clearly understood by those skilled in the art from the following description.

[0011] To achieve the above objectives, according to one aspect of the present invention, a display device may include: a stretchable lower substrate; a plurality of plate patterns disposed on the lower substrate and spaced apart from each other; a plurality of line patterns disposed on the lower substrate between plate patterns adjacent to each other along a first direction and between plate patterns adjacent to each other along a second direction different from the first direction; a plurality of connecting lines disposed above each of the plurality of line patterns; and a plurality of auxiliary patterns adjacent to the plurality of plate patterns on the lower substrate along an oblique direction between the first and second directions.

[0012] To achieve the above objectives, according to one aspect of the present invention, a display device may include: a stretchable lower substrate; a plurality of plate patterns disposed on the lower substrate and spaced apart from each other; a plurality of line patterns disposed on the lower substrate between adjacent plate patterns along a first direction and between adjacent plate patterns along a second direction different from the first direction; and a plurality of connecting lines disposed above each of the plurality of line patterns, wherein a first groove that does not overlap with the plurality of plate patterns and the plurality of line patterns is defined on the lower substrate.

[0013] To achieve the above objectives, according to one aspect of the present invention, a display device may include: a stretchable lower substrate having a first groove defined thereon; a stretchable upper substrate opposite to the lower substrate and defining a second groove overlapping the first groove; and a display panel disposed between the lower substrate and the upper substrate.

[0014] Further details of exemplary embodiments are included in the detailed description and accompanying drawings.

[0015] According to an exemplary embodiment of the present invention, the display device may include a damper (or internal blanking space) formed by a first groove defined on a lower substrate, a second groove defined on an upper substrate, and a through hole defined on a display panel. In this case, when a force (or impact) is applied to the display device from the outside, the force (or impact) applied from the outside is not directly transmitted to the display panel, but can be dispersed by gas (e.g., air) in the damper.

[0016] Therefore, the impact resistance of the display device can be improved, and damage to various components (e.g., connecting lines) included in the display device caused by external impacts can be suppressed. Thus, the tensile reliability of the display device can be improved.

[0017] The effects of the present invention are not limited to those described above. Other effects not mentioned above will be clearly understood by those skilled in the art based on the following description.

[0018] The objectives to be achieved by the present invention, the means for achieving these objectives, and the effects of the invention described above do not specify the essential features of the claims; therefore, the scope of the claims is not limited by the specific description of the invention. Attached Figure Description

[0019] The above and other aspects, features, and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. In the drawings:

[0020] Figure 1 This is a schematic side view of a display device according to an exemplary embodiment of the present invention;

[0021] Figure 2 This is a plan view illustrating a display device according to an exemplary embodiment of the present invention;

[0022] Figure 3 It is shown that it includes Figure 2 A plan view of an example of a lower substrate and an upper substrate in a display device;

[0023] Figure 4 It is shown Figure 2 Enlarged plan view of the example in Part A;

[0024] Figure 5 It shows along Figure 4 A cross-sectional view of an example taken from line III-III';

[0025] Figure 6 It shows along Figure 4 Example cross-sectional view of line IV-IV';

[0026] Figure 7 It is used to explain the inclusion of Figure 2 A view of an example of a damper formed in a display device, comprising a lower substrate, an upper substrate, and a display panel;

[0027] Figure 8A and Figure 8B This is a view used to illustrate an example of applying an impact to a display device according to a comparative example of the present invention;

[0028] Figures 9A to 9C This is a view used to illustrate an example of applying an impact to a display device according to an exemplary embodiment of the present invention;

[0029] Figures 10A to 10LThis is a process flow diagram illustrating a method for manufacturing a display device according to an exemplary embodiment of the present invention;

[0030] Figure 11 It is shown Figure 2 An enlarged plan view of another example of Part A;

[0031] Figure 12 This is a plan view illustrating a display device according to an exemplary embodiment of the present invention;

[0032] Figure 13 It is shown that it includes Figure 12 Plan view of an example of a lower substrate and an upper substrate in a display device. Detailed Implementation

[0033] When using terms such as “after,” “next,” “next,” and “before” to describe chronological relationships, the order is not necessarily sequential unless these terms are used with the terms “immediately” or “directly.”

[0034] When describing components of exemplary embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are used to distinguish one component from another, but the nature, order, or number of components is not limited by the terms. When a component is "linked," "joined," or "connected" to another component, the component may be directly linked or connected to the other component. However, unless specifically indicated otherwise, it should be understood that a third component may be inserted between components that can be indirectly linked or connected.

[0035] It should be understood that "at least one" includes all combinations of one or more related components. For example, "at least one of the first, second, and third components" means not only including the first, second, or third component, but also including all combinations of two or more of the first, second, and third components.

[0036] In this specification, "display device" may include a display device in the narrow sense, which includes a display panel and a driver for driving the display panel, such as a liquid crystal module (LCM), an organic light-emitting module (OLED module), and a quantum dot module. Furthermore, "display device" may further include set electronic apparatus or set equipment (or set unit) as finished or final products including LCMs, OLED modules, QD modules, etc., such as laptops, televisions or computer monitors, automotive display devices or equipment display devices including other vehicle types, and mobile electronic devices including smartphones or electronic boards.

[0037] Therefore, the display device of the present invention may include not only the display device itself in the narrow sense, such as LCM, OLED module, QD module, etc., but also application products or equipment as end consumer devices including LCD, OLED module, QD module, etc.

[0038] Furthermore, in some cases, an LCM, OLED module, or QD module consisting of a display panel and a driver can be narrowly defined as a "display device," and an electronic device comprising an LCM, OLED module, or QD module can be defined as a "unit equipment." For example, a display device in the narrow sense includes an LCD display panel, an OLED display panel, or a quantum dot display panel, and a source PCB that serves as a controller for driving the display panel. In contrast, a unit equipment can be a concept that further includes a unit PCB, where the unit PCB is a unit controller electrically connected to the source PCB to control the entire unit equipment.

[0039] As the display panel used in the exemplary embodiments of the present invention, any type of display panel can be used, such as a liquid crystal display panel, an OLED display panel, a quantum dot (QD) display panel, and an electroluminescent display panel. The display panel of the exemplary embodiments of the present invention is not limited to a specific display panel in which the bezel is bent using a flexible substrate for an OLED display panel and a backplate support structure below it. Furthermore, the display panel used in the display device according to the exemplary embodiments of the present invention is not limited in shape or size.

[0040] For example, when the display panel is an OLED display panel, the display panel may include multiple gate lines, multiple data lines, and multiple pixels formed at the intersections of gate lines and / or data lines. Furthermore, the display panel may be configured to include: an array of thin-film transistors (TFTs), which are elements for selectively applying voltage to each pixel; a light-emitting diode (LED) layer on the array; and an encapsulation substrate or encapsulation layer disposed on the array to cover the LED layer. The encapsulation layer protects the TFTs, LED layer, etc., from external impacts and inhibits moisture or oxygen from penetrating into the LED layer. Additionally, the layers formed on the array may include inorganic light-emitting layers, such as nanoscale material layers, quantum dots, etc.

[0041] The features of the various exemplary embodiments of the present invention may be combined or integrated with each other in part or in whole, and may be interlocked and operated in a variety of technical ways. The exemplary embodiments may be implemented independently or in association with each other.

[0042] In the following description, the invention will be described with reference to the accompanying drawings and exemplary embodiments. For purposes of description, the components shown in the drawings are at different scales than actual scales, and therefore the scales are not limited to those shown in the drawings.

[0043] In the following, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0044] The display device according to an exemplary embodiment of the present invention is a display device capable of displaying images even in a bent or extended state, and is also referred to as a stretchable display device, a flexible display device, and an expandable display device. Compared with general display devices of the related art, the display device of the present invention not only has high flexibility but also stretchability. Therefore, the user can bend or expand the display device and can freely change the shape of the display device according to the user's manipulation. For example, when the user pulls the display device by holding its end, the display device can expand in the direction of the user's pulling. Optionally, when the user places the display device on an uneven outer surface, the display device can be configured to bend according to the shape of the outer surface of the wall. Furthermore, when the force applied by the user is removed, the display device can return to its initial shape.

[0045] Figure 1 This is a schematic side view of a display device according to an exemplary embodiment of the present invention.

[0046] Reference Figure 1 According to an exemplary embodiment of the present invention, the display device 100 is stretchable in various directions on a planar surface. For example, the display device 100 may be stretchable along either a first direction X or a second direction Y different from the first direction X, or it may be two-dimensionally stretchable along both the first direction X and the second direction Y.

[0047] Therefore, a display device 100 according to an exemplary embodiment of the present invention may include a lower substrate 111, an upper substrate 112, and a display panel 10 disposed between the lower substrate 111 and the upper substrate 112.

[0048] The lower substrate 111 supports various components of the display device 100, and the upper substrate 112 can cover various components of the display device 100.

[0049] In one exemplary embodiment, the lower substrate 111 and upper substrate 112, which are flexible substrates, may include a bendable or expandable insulating material. The lower substrate 111 may be a stretchable lower substrate. The upper substrate 112 may be a stretchable upper substrate.

[0050] The elastic modulus of the lower substrate 111 and the upper substrate 112 can be from a few MPa to several hundred MPa. According to an exemplary embodiment, the ductile breaking rate of each of the lower substrate 111 and the upper substrate 112 can be 100% or higher. Here, ductile breaking rate refers to the elongation at which the object to be stretched breaks or fractures.

[0051] In one exemplary embodiment, a groove may be formed on each of the lower substrate 111 and the upper substrate 112. Furthermore, in this specification, a groove may be defined as a recess or a recessed portion.

[0052] For example, the lower substrate 111 includes a plurality of first grooves GRV1 formed on a planar surface (e.g., a top surface) opposite to the upper substrate 112. The plurality of first grooves GRV1 can be formed by removing at least a portion of the lower substrate 111 from the planar surface (e.g., the top surface opposite to the upper substrate 112). For example, the width (e.g., thickness) of the lower substrate 111 along a third direction Z in the region where the first grooves GRV1 are defined may be smaller than the width (e.g., thickness) of the lower substrate 111 along a third direction Z in the region where the first grooves GRV1 are not defined.

[0053] Furthermore, the upper substrate 112 may include a plurality of second grooves GRV2 formed on a planar surface (e.g., a bottom surface) opposite to the lower substrate 111. The plurality of second grooves GRV2 can be formed by removing at least a portion of the upper substrate 112 from the planar surface (e.g., the bottom surface opposite to the lower substrate 111). For example, the width (e.g., thickness) of the upper substrate 112 along the third direction Z in the region where the second grooves GRV2 are defined may be smaller than the width (e.g., thickness) of the upper substrate 112 along the third direction Z in the region where the second grooves GRV2 are not defined.

[0054] In one exemplary embodiment, each of the plurality of first grooves GRV1 defined on the lower substrate 111 may be configured to overlap with each of the plurality of second grooves GRV2 defined on the upper substrate 112. According to the exemplary embodiment, the overlapping first grooves GRV1 and second grooves GRV2 have the same shape and the same size, but are not limited thereto.

[0055] Therefore, a plurality of grooves GRV1 and GRV2 are defined in the lower substrate 111 and the upper substrate 112, which are configured to overlap each other on opposing planar surfaces (e.g., the top surface of the lower substrate 111 and / or the bottom surface of the upper substrate 112). Thus, an internal empty space can be defined between the lower substrate 111 and the upper substrate 112 by the first groove GRV1 and the second groove GRV2 configured to overlap each other. Here, the internal empty space may be defined as a damper DPR (or damping chamber), but the terminology is not limited thereto.

[0056] The display panel 10 can be disposed between the lower substrate 111 and the upper substrate 112. The display panel 10 includes a plurality of pixels and can display images through the plurality of pixels.

[0057] In one exemplary embodiment, the display panel 10 may include a plurality of through-holes HL. For example, openings are formed in at least one insulating layer included in the display panel 10 to form a plurality of through-holes HL.

[0058] Each of the plurality of through holes HL can be configured to overlap with a first groove GRV1 and a second groove GRV2 that are disposed overlapping each other. That is, the first groove GRV1, the second groove GRV2 and the through hole HL are configured to overlap each other, such that the damper DPR can be formed (or defined) between the lower substrate 111 and the upper substrate 112, i.e., formed (or defined) as an internal blank space in the display device 100.

[0059] According to an exemplary embodiment, the damper DPR (or internal blank space) formed by the first groove GRV1, the second groove GRV2, and the through hole HL can be filled with gas, such as air. In this case, when a force (or impact) is applied to the display device 100 from the outside, the force (or impact) is not directly transmitted to the display panel 10, but is dispersed by the air in the damper DPR. Therefore, the impact resistance of the display panel 10 (or display device 100) can be improved, and damage to the various components included in the display panel 10 (or display device 100) caused by external impacts can be suppressed.

[0060] Meanwhile, the exemplary embodiments of the present invention are not limited thereto, and the damper DPR (or internal blank space) formed by the first groove GRV1, the second groove GRV2 and the through hole HL can be filled with various types of gas.

[0061] Figure 2 This is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

[0062] At the same time, it has been referred to Figure 1The description of display panel 10 can refer to any component of the display device 100 described below, other than the lower substrate 111 and the upper substrate 112. That is, in this specification, all components included in the display device 100 and disposed between the lower substrate 111 and the upper substrate 112 can be defined as display panel 10.

[0063] Reference Figure 1 and Figure 2 The display device 100 according to an exemplary embodiment of the present invention may include a lower substrate 111, an upper substrate 112, a pattern layer 120, a plurality of pixels PX, a gate driver GD, a data driver DD, and a power supply PS.

[0064] The lower substrate 111 supports a pattern layer 120 on which a pixel PX, a gate driver GD, and a power supply PS are formed, and the upper substrate 112 can cover the pixel PX, the gate driver GD, and the power supply PS.

[0065] The lower substrate 111 may include an active area AA in which an image is displayed and a non-active area NA other than the active area AA. For example, a plurality of pixels PX are disposed on the active area AA, each pixel including a display element and a circuit element; and on the non-display area NA, a gate driver GD and a power supply PS for driving the plurality of pixels PX disposed in the active area AA may be disposed.

[0066] The pattern layer 120 can be disposed on the lower substrate 111.

[0067] In one exemplary embodiment, the pattern layer 120 may include: a plurality of first board patterns 121 and a plurality of first line patterns 122 disposed in an active region AA; and a plurality of second board patterns 123 and a plurality of second line patterns 124 disposed in an active region NA. For example, the plurality of first board patterns 121 and the plurality of second board patterns 123 are formed in the form of separate islands. The plurality of first line patterns 122 may be disposed between adjacent first board patterns 121 to connect adjacent first board patterns 121, and the plurality of second line patterns 124 connect adjacent first board patterns 121 and second board patterns 123 or adjacent second board patterns 123. The plurality of line patterns may be disposed on the lower substrate 111 between board patterns adjacent along a first direction and between board patterns adjacent along a second direction different from the first direction.

[0068] Multiple pixels PX are formed on multiple first plate patterns 121; and gate drivers GD and power supplies PS can be formed on multiple second plate patterns 123.

[0069] At the same time, despite Figure 2The image shows multiple first plate patterns 121 and multiple second plate patterns 123 having quadrilateral shapes, but is not limited thereto.

[0070] The plurality of first line patterns 122 and second line patterns 124 have curved shapes (e.g., sine wave shapes), but are not limited thereto. For example, the plurality of first line patterns 122 and second line patterns 124 may extend in a zigzag pattern, or may be formed in various shapes, such as shapes that extend by connecting multiple diamond patterns at the vertices.

[0071] In one exemplary embodiment, the pattern layer 120 may further include a plurality of first auxiliary patterns 125 disposed in the active region AA.

[0072] Multiple first auxiliary patterns 125 can be arranged in an island-like configuration, spaced apart from each other. Each of the multiple first auxiliary patterns 125 can be separate. Figure 2 The diagram shows multiple first auxiliary patterns 125 having quadrilateral shapes, but is not limited to this; the multiple first auxiliary patterns 125 can be modified in various forms.

[0073] In one exemplary embodiment, each of the plurality of first auxiliary patterns 125 is configured to be adjacent to the plurality of first plate patterns 121 in a direction different from the first direction X and the second direction Y. For example, each of the plurality of first auxiliary patterns 125 may be configured to be adjacent to the plurality of first plate patterns 121 in a diagonal direction (e.g., a third direction) between the first direction X and the second direction Y. Thus, as Figure 2 As shown, each of the plurality of first auxiliary patterns 125 may be disposed between adjacent first line patterns 122 along the first direction X and / or between adjacent first line patterns 122 along the second direction Y.

[0074] At the same time, such as Figure 2 As shown, unlike the first plate pattern 121 and the second plate pattern 123, the plurality of first auxiliary patterns 125 are not connected to the line patterns (e.g., the first line pattern 122 and the second line pattern 124), but can be spaced apart from each other.

[0075] At the same time, despite Figure 2 The illustration shows that multiple first auxiliary patterns 125 are only disposed in the active region AA. The exemplary embodiment is not limited to this, so that the multiple first auxiliary patterns 125 may be disposed only in the non-active region NA or all disposed in the active region AA and the non-active region NA.

[0076] In one exemplary embodiment, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, the plurality of second line patterns 124, and the plurality of first auxiliary patterns 125 may be rigid patterns. That is, the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, the plurality of second line patterns 124, and the plurality of first auxiliary patterns 125 may have greater rigidity than the lower substrate 111 and the upper substrate 112. Therefore, the elastic modulus and hardness of the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, the plurality of second line patterns 124, and the plurality of first auxiliary patterns 125 may be higher than the elastic modulus and hardness of the lower substrate 111. For example, the elastic modulus of the plurality of first plate patterns 121, the plurality of first line patterns 122, the plurality of second plate patterns 123, the plurality of second line patterns 124, and the plurality of first auxiliary patterns 125 may be 1000 times the elastic modulus of the lower substrate 111 and the upper substrate 112, but is not limited thereto.

[0077] Multiple first plate patterns 121, multiple first line patterns 122, multiple second plate patterns 123, multiple second line patterns 124, and multiple first auxiliary patterns 125 may be formed from a flexible plastic material having a flexibility lower than that of the lower substrate 111 and the upper substrate 112. For example, the multiple first plate patterns 121, multiple first line patterns 122, multiple second plate patterns 123, multiple second line patterns 124, and multiple first auxiliary patterns 125 may include at least one material of polyimide (PI), polyacrylate, and polyacetate. In this case, the multiple first plate patterns 121, multiple first line patterns 122, multiple second plate patterns 123, multiple second line patterns 124, and multiple first auxiliary patterns 125 may be formed from the same material, but are not limited thereto, and may be formed from different materials. According to an exemplary embodiment, when the multiple first plate patterns 121, multiple first line patterns 122, multiple second plate patterns 123, multiple second line patterns 124, and multiple first auxiliary patterns 125 are formed from the same material, the patterns may be integrally formed.

[0078] The gate driver GD provides gate signals to multiple pixels PX disposed in the active region AA. The gate driver GD includes multiple stages formed on multiple second plate patterns 123, and each stage of the gate driver GD is electrically connected to each other via multiple gate connection lines. Therefore, a gate signal output from any stage can be transmitted to another stage. Each stage can sequentially provide gate signals to multiple pixels PX connected to each stage.

[0079] The power supply PS is connected to the gate driver GD to provide the gate drive voltage and the gate clock voltage. Additionally, the power supply PS is connected to multiple pixels PX to provide a pixel drive voltage to each of the pixels PX.

[0080] A printed circuit board (PCB) includes a controller, such as an IC chip or circuit unit and / or memory or processor, to transmit signals and voltages used to drive display elements from the controller to the display elements. The PCB may include stretchable and non-stretchable areas to ensure stretchability. For example, in the non-stretchable area, the IC chip, circuit unit, memory, and processor are mounted; and in the stretchable area, wiring electrically connected to the IC chip, circuit unit, memory, and processor can be provided.

[0081] The data driver DD can provide data voltage to multiple pixels PX located in the active area AA. The data driver DD can be configured as an IC chip, and thus it can also be referred to as a data integrated circuit (D-IC).

[0082] Figure 3 It is shown that it includes Figure 2 Plan view of an example of a lower substrate and an upper substrate in a display device.

[0083] Reference Figure 3 A groove may be formed in each of the lower substrate 111 and the upper substrate 112. For example, as shown in reference... Figure 1 As described, the lower substrate 111 includes a plurality of first grooves GRV1 formed on a planar surface (e.g., top surface) opposite to the upper substrate 112, and the upper substrate 112 includes a plurality of second grooves GRV2 formed on a planar surface (e.g., bottom surface) opposite to the lower substrate 111.

[0084] In one exemplary embodiment, each of the plurality of first grooves GRV1 defined in the lower substrate 111 may overlap with each of the plurality of second grooves GRV2 defined in the upper substrate 112. For example, the plurality of first grooves GRV1 defined on the lower substrate 111 and the plurality of second grooves GRV2 defined on the upper substrate 112 may be formed in the same location on a planar surface.

[0085] Each of the plurality of first grooves GRV1 and each of the plurality of second grooves GRV2 may be disposed on the active region AA. For example, each of the plurality of first grooves GRV1 and each of the plurality of second grooves GRV2 may be configured to overlap with a plurality of first auxiliary patterns 125 included in the pattern layer 120. That is, each of the plurality of first grooves GRV1 and each of the plurality of second grooves GRV2 may be configured not to overlap with a plurality of first plate patterns 121 and a plurality of first line patterns 122 included in the pattern layer 120. Therefore, the damper DPR defined by the first grooves GRV1 and the second grooves GRV2 may be formed to overlap with the plurality of first auxiliary patterns 125. That is, the damper DPR may be formed in the region in which the plurality of first auxiliary patterns 125 are disposed.

[0086] Figure 4 It is shown Figure 2 An enlarged plan view of part A of the example.

[0087] Reference Figure 2 , Figure 3 and Figure 4 Multiple first board patterns 121 can be disposed on the active region AA of the lower substrate 111. The multiple first board patterns 121 are disposed on the lower substrate 111 at intervals from each other. For example, as... Figure 2 As shown, multiple first plate patterns 121 can be arranged in a matrix on the lower substrate 111, but are not limited thereto.

[0088] A pixel PX comprising multiple sub-pixels SPX may be disposed in the first plate pattern 121. Each of the sub-pixels SPX may include a display element (e.g., Figure 5 LED 170) and at least one transistor for driving the display element (e.g., Figure 5 (Drive transistor 160 and switching transistor 150).

[0089] Multiple sub-pixel SPXs may include, but are not limited to, red, green, and blue sub-pixels, and the colors of multiple sub-pixel SPXs may be modified to various colors as needed.

[0090] Multiple subpixels SPX can be connected to multiple connecting lines 181 and 182. That is, multiple subpixels SPX can be electrically connected to a first connecting line 181 extending in a first direction X and a second connecting line 182 extending in a second direction Y. The multiple connecting lines can be positioned above each of the multiple line patterns.

[0091] Furthermore, a plurality of first auxiliary patterns 125 may be disposed on the active region AA of the lower substrate 111. The plurality of first auxiliary patterns 125 are disposed on the lower substrate 111 at intervals from each other. For example, as shown... Figure 2 As shown, multiple first auxiliary patterns 125 can be arranged in a matrix on the lower substrate 111, but are not limited thereto.

[0092] In one exemplary embodiment, each of the plurality of first auxiliary patterns 125 is positioned adjacent to the plurality of first plate patterns 121 in a diagonal direction (or a third direction) between the first direction X and the second direction Y. Furthermore, the plurality of first auxiliary patterns may be positioned between first line patterns 122 adjacent along the first direction X and / or between first line patterns 122 adjacent along the second direction Y.

[0093] In addition, such as Figure 4As shown, unlike the first plate pattern 121 and the second plate pattern 123, the plurality of first auxiliary patterns 125 are not connected to the line patterns (e.g., the first line pattern 122 and the second line pattern 124), but are spaced apart from each other.

[0094] In one exemplary embodiment, each of the plurality of first auxiliary patterns 125 may include a first through-hole HL1. For example, at least a portion of each of the plurality of first auxiliary patterns 125 is removed to form the first through-hole HL1.

[0095] According to an exemplary embodiment, a first through hole HL1 formed in each of a plurality of first auxiliary patterns 125 may be formed in the central portion of the first auxiliary pattern 125, but is not limited thereto, and may be formed in various locations of the first auxiliary pattern 125.

[0096] The first through hole HL1, included in a plurality of first auxiliary patterns 125, can be configured to overlap with the first groove GRV1 and the second groove GRV2, which are disposed overlapping each other. That is, the first groove GRV1, the second groove GRV2 and the first through hole HL1 are configured to overlap each other, so that the damper DPR can be formed (or defined) between the lower substrate 111 and the upper substrate 112, i.e., formed (or defined) as an internal blank space in the display device 100.

[0097] Simultaneously, in this manner, the first through-hole HL1 included in each of the plurality of first auxiliary patterns 125, and the first groove GRV1 and the second groove GRV2 overlapping the first through-hole, are configured to be adjacent to the plurality of first plate patterns 121 on the planar surface along an oblique direction (or a third direction) between the first direction X and the second direction Y. Furthermore, the first through-hole HL1, the first groove GRV1, and the second groove GRV2 may be disposed between adjacent first line patterns 122 along the first direction X and / or between adjacent first line patterns 122 along the second direction Y.

[0098] At the same time, despite Figure 4 The diagram shows a first through-hole HL1 formed in a first auxiliary pattern 125, which is merely exemplary, and the number of first through-holes HL1 included in a first auxiliary pattern 125 is not limited thereto.

[0099] In the following text, reference will be made to Figure 5 and Figure 6 The cross-sectional structure of the display device 100 in the active region AA is described in more detail.

[0100] Figure 5 It shows along Figure 4 A cross-sectional view of an example taken from line III-III'.

[0101] Figure 6It shows along Figure 4 A cross-sectional view of an example taken from line IV-IV'.

[0102] First, refer to Figure 5 Multiple inorganic insulating layers may be disposed on multiple first plate patterns 121. For example, the multiple inorganic insulating layers may include a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, and a passivation layer 145. However, exemplary embodiments of the present invention are not limited thereto, and various inorganic insulating layers may be additionally disposed on multiple first plate patterns 121. One or more of the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, and passivation layer 145 as inorganic insulating layers may be omitted.

[0103] A buffer layer 141 may be disposed on a plurality of first plate patterns 121. The buffer layer 141 comprises an insulating material and may be formed on the plurality of first plate patterns 121 to protect various components of the display device 100 from the penetration of moisture (H2O) and oxygen (O2) from the exterior of the lower substrate 111 and the plurality of first plate patterns 121. However, the buffer layer 141 may be omitted depending on the structure or characteristics of the display device 100.

[0104] In one exemplary embodiment, the buffer layer 141 may be formed only in the region where the lower substrate 111 overlaps with the plurality of first plate patterns 121 and the plurality of second plate patterns 123. As described above, the buffer layer 141 may be formed of an inorganic material, so that the buffer layer 141 may easily break or be damaged during the stretching of the display device 100. Therefore, the buffer layer 141 is not formed in the region between the plurality of first plate patterns 121 and the plurality of second plate patterns 123. Instead, the buffer layer 141 is patterned to have a shape in which the plurality of first plate patterns 121 and the plurality of second plate patterns 123 are disposed only above the plurality of first plate patterns 121 and the plurality of second plate patterns 123. Therefore, in the display device 100 according to an exemplary embodiment of the present invention, the buffer layer 141 is formed only in the region overlapping with the plurality of first plate patterns 121 and the plurality of second plate patterns 123, which are rigid patterns. Therefore, even if the display device 100 is bent or stretched to deform, damage to the various components of the display device 100 can be suppressed.

[0105] A switching transistor 150, including a gate 151, an active layer 152, a source 153, and a drain 154, and a driving transistor 160, including a gate 161, an active layer 162, a source 153, and a drain 164, may be disposed on a buffer layer 141.

[0106] The active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may be disposed on the buffer layer 141. For example, the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160 may be formed of oxide semiconductor, or may be formed of amorphous silicon (a-Si), polycrystalline silicon (poly-Si), or organic semiconductor.

[0107] A gate insulating layer 142 may be disposed on the active layer 152 of the switching transistor 150 and the active layer 162 of the driving transistor 160. The gate insulating layer 142 includes an insulating material and electrically insulates the gate 151 of the switching transistor 150 from the active layer 152 of the switching transistor 150, and electrically insulates the gate 161 of the driving transistor 160 from the active layer 162 of the driving transistor 160.

[0108] The gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160 may be disposed on the gate insulating layer 142. The gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160 may be disposed on the gate insulating layer 142 and spaced apart from each other. Furthermore, the gate 151 of the switching transistor 150 overlaps with the active layer 152 of the switching transistor 150, and the gate 161 of the driving transistor 160 may overlap with the active layer 162 of the driving transistor 160.

[0109] The gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160 may be made of various metallic materials.

[0110] A first interlayer insulating layer 143 may be disposed on the gate 151 of the switching transistor 150 and the gate 161 of the driving transistor 160. The first interlayer insulating layer 143 includes an insulating material and can insulate the gate 161 of the driving transistor 160 from the intermediate metal layer IM.

[0111] An intermediate metal layer IM may be disposed on the first interlayer insulating layer 143. The intermediate metal layer IM may overlap with the gate 161 of the driving transistor 160. Therefore, a storage capacitor is formed in the overlapping region of the intermediate metal layer IM and the gate 161 of the driving transistor 160. For example, the gate 161 of the driving transistor 160, the first interlayer insulating layer 143, and the intermediate metal layer IM may form a storage capacitor. However, the placement region of the intermediate metal layer IM is not limited to this, and the intermediate metal layer IM may overlap with another electrode to form various forms of storage capacitors.

[0112] The second interlayer insulating layer 144 may be disposed on the intermediate metal layer IM. The second interlayer insulating layer 144 includes an insulating material and can insulate the gate 151 of the switching transistor 150 from the source 153 and drain 154 of the switching transistor 150. In addition, the second interlayer insulating layer 144 can insulate the intermediate metal layer IM from the source and drain 164 of the driving transistor 160.

[0113] The source 153 and drain 154 of the switching transistor 150 may be disposed on the second interlayer insulating layer 144. Furthermore, the source and drain 164 of the driving transistor 160 may be disposed on the second interlayer insulating layer 144. The source 153 and drain 154 of the switching transistor 150 may be disposed on the same layer and spaced apart from each other.

[0114] At the same time, despite Figure 5 The source of driving transistor 160 is omitted, but the source of driving transistor 160 may also be configured to be spaced apart from drain 164 on the same layer. In switching transistor 150, source 153 and drain 154 may contact active layer 152 for electrical connection. Furthermore, in driving transistor 160, source and drain 164 may contact active layer 162 for electrical connection. Additionally, the drain 154 of switching transistor 150 contacts the gate 161 of driving transistor 160 through a contact hole for electrical connection.

[0115] Gate pads and data pads DP can be disposed on the second interlayer insulating layer 144.

[0116] Specifically, the gate pad can transmit gate signals to multiple sub-pixels (SPX). The gate pad can be connected to the first connection line 181 via contact holes. Furthermore, the gate signal supplied from the first connection line 181 can be transmitted from the gate pad to the gate 151 of the switching transistor 150 via wiring formed on the first board pattern 121.

[0117] Furthermore, the data pad DP can transmit data voltage to multiple sub-pixels SPX. The data pad DP can be connected to the second connection line 182 via contact holes. In addition, the data voltage supplied from the second connection line 182 can be transmitted from the data pad DP to the source 153 of the switching transistor 150 via wiring formed on the first board pattern 121.

[0118] Furthermore, the voltage pad VP can transmit a low-potential voltage to multiple sub-pixels SPX. The voltage pad VP can be connected to the first connection line 181 via a contact hole. In addition, the low-potential voltage supplied from the first connection line 181 can be transmitted from the voltage pad VP to the N-terminal (negative terminal) 174 of the LED 170 via wiring formed on the first board pattern 121.

[0119] A passivation layer 145 may be formed on the switching transistor 150 and the driving transistor 160. That is, the passivation layer 145 may be configured to cover the switching transistor 150 and the driving transistor 160 to protect them from the penetration of moisture and oxygen. The passivation layer 145 may be formed of an inorganic material and may be configured as a single layer or a double layer, but is not limited thereto.

[0120] Furthermore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 are patterned to be formed only in the regions overlapping with the plurality of first plate patterns 121. Similar to the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may also be formed from inorganic materials. Therefore, during the stretching process of the display device 100, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 may easily break and be damaged. Therefore, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145 are not formed in the regions between the plurality of first plate patterns 121. Instead, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144 and the passivation layer 145 are patterned to have a shape having a plurality of first plate patterns 121 formed only above a plurality of first plate patterns 121.

[0121] A planarization layer 146 may be formed on the passivation layer 145. The planarization layer 146 planarizes the upper portion of the switching transistor 150 and the driving transistor 160. The planarization layer 146 may be configured as a single layer or multiple layers and may be formed of an organic material.

[0122] Reference Figure 5The planarization layer 146 may be configured to cover the top and side surfaces of the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, and passivation layer 145 on a plurality of first board patterns 121. Furthermore, the planarization layer 146 may be configured to surround the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, and passivation layer 145 together with the plurality of first board patterns 121. Specifically, the planarization layer 146 may be configured to cover the top and side surfaces of the passivation layer 145, the side surfaces of the first interlayer insulating layer 143, the second interlayer insulating layer 144, the side surfaces of the gate insulating layer 142, the side surfaces of the buffer layer 141, and a portion of the top surface of the plurality of first board patterns 121. Therefore, the planarization layer 146 can fill the steps on the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. In addition, the planarization layer 146 can enhance the adhesion strength of the connecting lines 181 and 182 disposed on the side surface of the planarization layer 146.

[0123] Reference Figure 5 The tilt angle of the side surface of the planarization layer 146 can be smaller than the tilt angle formed by the side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144, and the passivation layer 145. For example, the side surface of the planarization layer 146 can have a gentler slope than the slope formed by the side surfaces of the passivation layer 145, the first interlayer insulating layer 143, the second interlayer insulating layer 144, the gate insulating layer 142, and the buffer layer 141. Therefore, the connection lines 181 and 182, which are configured to contact the side surface of the planarization layer 146, are provided with a gentle slope, so that the stress generated in the connection lines 181 and 182 can be reduced when the display device 100 is stretched. Furthermore, the side surface of the planarization layer 146 has a relatively gentle slope, which can suppress cracks in the connecting lines 181 and 182 or their separation from the side surface of the planarization layer 146.

[0124] Reference Figure 4 and Figure 5 Connectors 181 and 182 can electrically connect to pads on a plurality of first board patterns 121. Connectors 181 and 182 can be disposed on a plurality of first line patterns 122. Furthermore, connectors 181 and 182 can extend onto the plurality of first board patterns 121 to electrically connect to gate pads and data pads DP on the plurality of first board patterns 121. Additionally, the first line patterns 122 are not disposed in areas between the plurality of first board patterns 121, in areas where connectors 181 and 182 are not disposed.

[0125] Connecting lines 181 and 182 may include a first connecting line 181 and a second connecting line 182. The first connecting line 181 and the second connecting line 182 may be disposed between a plurality of first plate patterns 121. The first connecting line 181 and the second connecting line 182 may include a metallic material.

[0126] More specifically, the first connecting line 181 refers to the wiring between the connecting lines 181 and 182 that extends along a first direction X between the plurality of first board patterns 121. The second connecting line 182 may refer to the wiring between the connecting lines 181 and 182 that extends along a second direction Y between the plurality of first board patterns 121.

[0127] Meanwhile, in the case of a typical display device, various wirings, such as multiple gate lines and multiple data lines, extend between multiple sub-pixels with linear shapes, and the multiple sub-pixels are connected to a single signal line. Therefore, in a typical display device, various wirings, such as gate lines, data lines, high-potential voltage lines, and reference voltage lines, extend from one side of the organic light-emitting display device to the other without being interrupted on the substrate.

[0128] In contrast, in the display device 100 according to an exemplary embodiment of the present invention, various wirings having a straight line shape considered to be used in general display devices, such as gate lines, data lines, high-potential voltage lines, reference voltage lines, or initialization voltage lines, may be provided only on the plurality of first board patterns 121 and the plurality of second board patterns 123. That is, in the display device 100 according to an exemplary embodiment of the present invention, linear wiring may be provided only on the plurality of first board patterns 121 and the plurality of second board patterns 123.

[0129] In a display device 100 according to an exemplary embodiment of the present invention, pads on two adjacent first board patterns 121 can be connected by connection lines 181 and 182. Therefore, connection lines 181 and 182 can electrically connect gate pads or data pads DP on two adjacent first board patterns 121. Thus, the display device 100 according to an exemplary embodiment of the present invention may include multiple connection lines 181 and 182 that electrically connect various wirings such as gate lines, data lines, high-potential voltage lines, and reference voltage lines between a plurality of first board patterns 121. For example, gate lines may be provided on a plurality of first board patterns 121 arranged adjacent to each other along a first direction X, and gate pads may be provided at both ends of the gate lines. In this case, multiple gate pads on a plurality of first board patterns 121 adjacent to each other in the first direction X can be connected to each other by a first connection line 181 serving as a gate line. Therefore, the gate lines provided on the plurality of first board patterns 121 and the first connection line 181 provided on the first line pattern 122 can be used as a single gate line. This gate line may be referred to as a scan signal line. Furthermore, as described above, wiring extending along the first direction X, among all the various wirings that may be included in the display device 100, such as light-emitting signal lines, low-potential voltage lines, and high-potential voltage lines, can also be electrically connected via the first connecting line 181.

[0130] Reference Figures 4 to 5 The first connection line 181 can connect to the gate pads on two adjacent first board patterns 121 arranged along the first direction X. The first connection line 181 can be used as a gate line, a light-emitting signal line, a high-potential voltage line, or a low-potential voltage line, but is not limited thereto. The gate pads on the plurality of first board patterns 121 arranged along the first direction X can be connected and transmit a gate voltage through the first connection line 181 used as a gate line.

[0131] In addition, refer to Figure 4 and Figure 5 The second connection line 182 can connect to data pads DP on two adjacent first board patterns 121 arranged along the second direction Y, specifically the data pads DP on two side-by-side first board patterns 121. The second connection line 182 can be used as a data line, a high-potential voltage line, a low-potential voltage line, or a reference voltage line, but is not limited thereto. Data pads DP on the multiple first board patterns 121 arranged along the second direction Y can be connected and transmit a data voltage via multiple second connection lines 182 used as data lines.

[0132] like Figure 5As shown, the first connecting line 181 may be configured to contact the top and side surfaces of the planarization layer 146 disposed on the first plate pattern 121. Furthermore, the first connecting line 181 may be formed to extend to the top surface of the first line pattern 122. Furthermore, the second connecting line 182 may be configured to contact the top and side surfaces of the planarization layer 146 disposed on the first plate pattern 121. Furthermore, the second connecting line 182 may be formed to extend to the top surface of the first line pattern 122.

[0133] However, it is not necessary to provide a rigid pattern in the area where the first connecting line 181 and the second connecting line 182 are not provided. Therefore, the first line pattern 122, which is a rigid pattern, is not provided below the first connecting line 181 and the second connecting line 182.

[0134] At the same time, refer to Figure 5 A dam 147 can be formed on the connection pads CNT, the connection lines 181 and 182, and the planarization layer 146. The dam 147 includes an insulating material and can divide adjacent sub-pixels SPX. The dam 147 can be configured to cover at least a portion of the connection lines 181 and 182 and the planarization layer 146. Furthermore, although in Figure 5 The diagram shows that the height of the embankment 147 is lower than the height of the LED 170, but the invention is not limited thereto, and the height of the embankment 147 may be equal to the height of the LED 170.

[0135] Reference Figure 5 LED 170 may be disposed on the connection pad CNT and the first connection line 181. LED 170 may include an n-type layer 171, an active layer 172, a p-type layer 173, an N-type electrode 174, and a P-type electrode (positive electrode) 175. The LED 170 of the display device 100 according to an exemplary embodiment of the present invention may have a flip-chip structure, wherein the N-type electrode 174 and the P-type electrode 175 are formed on one surface, but is not limited thereto.

[0136] The n-type layer 171 includes n-type impurities and can be disposed on a separate base substrate formed of a light-emitting material.

[0137] An active layer 172 may be disposed on an n-type layer 171. The active layer 172 may correspond to the light-emitting layer in the LED 170. A p-type layer 173, including p-type impurities, may be disposed on the active layer 172.

[0138] As described above, the LED 170 according to an exemplary embodiment of the present invention can be manufactured by sequentially laminating an n-type layer 171, an active layer 172, and a p-type layer 173, and then etching predetermined portions to form an N-electrode 174 and a P-electrode 175. In this case, predetermined portions serving as spaces for separating the N-electrode 174 and the P-electrode 175 from each other can be etched to expose a portion of the n-type layer 171. In other words, the surface of the LED 170 on which the N-electrode 174 and the P-electrode 175 are disposed is not a flat surface, but rather has different heights.

[0139] As described above, the N-type electrode 174 is disposed in the etched area and may be formed of a conductive material. Furthermore, the P-type electrode 175 is disposed in the unetched area and may also be formed of a conductive material. For example, the N-type electrode 174 is disposed on the n-type layer 171 exposed by the etching process, and the P-type electrode 175 may be disposed on the p-type layer 173. The P-type electrode 175 may be formed of the same material as the N-type electrode 174.

[0140] An adhesive layer AD is disposed on the top surface of the connecting pad CNT and the first connecting line 181, and between the connecting pad CNT and the first connecting line 181, so that the LED 170 can adhere to the connecting pad CNT and the first connecting line 181. At this time, the N-terminal 174 is disposed on the first connecting line 181, and the P-terminal 175 can be disposed on the connecting pad CNT.

[0141] The adhesive layer AD can be a conductive adhesive layer in which conductive spheres are dispersed within an insulating base component. Therefore, when heat or pressure is applied to the adhesive layer AD, the conductive spheres become electrically connected in the portion under heat or pressure to have conductive properties, while the unpressurized area can have insulating properties. For example, the N-pole 174 is electrically connected to the first connection line 181 via the adhesive layer AD, and the P-pole 175 is electrically connected to the connection pad CNT via the adhesive layer AD. After the adhesive layer AD is applied to the top surfaces of the first connection line 181 and the connection pad CNT using an inkjet printing method, the LED 170 is transferred onto the adhesive layer AD and pressurized and heated. In this way, the connection pad CNT is electrically connected to the P-pole 175, and the first connection line 181 can be electrically connected to the N-pole 174. However, except for the portions of the adhesive layer AD disposed between the N-pole 174 and the first connection pad 181, and the portions of the adhesive layer AD disposed between the P-pole 175 and the connection pad CNT, the remaining portions of the adhesive layer AD have insulating properties. Meanwhile, the adhesive layer AD can be divided to be respectively disposed on the connecting pad CNT and the first connecting line 181.

[0142] Furthermore, the connection pad CNT is electrically connected to the drain 164 of the driver transistor 160 to be applied with a drive voltage from the driver transistor 160, thereby driving the LED 170. Although in Figure 5The diagram shows that the connection pad CNT is not in direct contact with the drain 164 of the driving transistor 160, but is indirectly connected to it; however, the invention is not limited to this. Therefore, the connection pad CNT and the drain 164 of the driving transistor 160 can be in direct contact with each other. Furthermore, a low-potential driving voltage can be applied to the first connection line 181 to drive the LED 170. Therefore, when the display device 100 is turned on, different voltage levels applied to the connection pad CNT and the first connection line 181 are transmitted to the N-terminal 174 and the P-terminal 175, causing the LED 170 to emit light.

[0143] The upper substrate 112 is a substrate that supports various components disposed below the upper substrate 112. Specifically, the upper substrate 112 is formed by coating the upper substrate 112 onto the lower substrate 111 and the first plate pattern 121 with a material, and then hardening the material so that it is in contact with the lower substrate 111, the first plate pattern 121, the first line pattern 122 and the connecting lines 181 and 182.

[0144] At the same time, despite Figure 5 Although not shown, a polarizing layer may also be provided on the upper substrate 112. The polarizing layer can be used to polarize light incident from the outside of the display device 100 to reduce external light reflection. In addition, optical films other than the polarizing layer may be provided on the upper substrate 112.

[0145] Furthermore, the filler layer 190 may be disposed on the entire surface of the lower substrate 111 to fill the spaces between components disposed on the upper substrate 112 and the lower substrate 111. The filler layer 190 may be configured with a curable adhesive. Specifically, the material configuring the filler layer 190 is coated on the entire surface of the lower substrate 111 and then cured, such that the filler layer 190 is disposed between components located on the upper substrate 112 and the lower substrate 111. For example, the filler layer 190 may be an optically clear adhesive (OCA) and may be configured using acrylic-based adhesives, silicone-based adhesives, and urethane-based adhesives.

[0146] Reference Figure 6 The lower substrate 111 includes a plurality of first grooves GRV1, and the upper substrate 112 may include a plurality of second grooves GRV2. For example, the plurality of first grooves GRV1 are formed by removing at least a portion of the lower substrate 111 from a planar surface of the lower substrate 111 (e.g., the top surface opposite the upper substrate 112). The plurality of second grooves GRV2 are formed by removing at least a portion of the upper substrate 112 from a planar surface of the upper substrate 112 (e.g., the bottom surface opposite the lower substrate 111).

[0147] Multiple first auxiliary patterns 125 may be disposed on the lower substrate 111. For example, the multiple first auxiliary patterns 125 may be configured to overlap with the first groove GRV1 of the lower substrate 111.

[0148] In addition, such as Figure 6 As shown, the width of each of the plurality of first auxiliary patterns 125 (e.g., the width of each of the plurality of first auxiliary patterns 125 along the first direction X and the width of each of the plurality of first auxiliary patterns 125 along the second direction Y) may be greater than the width of the first groove GRV1. Therefore, each of the plurality of first auxiliary patterns 125 is not located within the first groove GRV1 of the lower substrate 111, and the bottom surface of the first auxiliary pattern 125 may be configured to be spaced apart from the planar surface of the lower substrate 111 in which the first groove GRV1 is defined. For example, the end of the bottom surface of each of the plurality of first auxiliary patterns 125 is configured to contact the planar surface of the portion of the lower substrate 111 in which the first groove GRV1 is not defined. The remaining portion of the bottom surface of each of the plurality of first auxiliary patterns 125 may be configured to be spaced apart from the planar surface of the portion of the lower substrate 111 in which the first groove GRV1 is defined.

[0149] In one exemplary embodiment, each of the plurality of first auxiliary patterns 125 may include a first through-hole HL1. For example, at least a portion of each of the plurality of first auxiliary patterns 125 is removed to form the first through-hole HL1. According to an exemplary embodiment, the first through-hole HL1 formed in each of the plurality of first auxiliary patterns 125 may be formed in the central portion of the first auxiliary pattern 125, but is not limited thereto.

[0150] A reinforcement layer RCL, comprising at least one insulating layer such as multiple inorganic insulating layers, may be disposed above each of the multiple first auxiliary patterns 125. For example, the reinforcement layer RCL may also be formed on the multiple first auxiliary patterns 125 by patterning the same inorganic insulating layer as the multiple inorganic insulating layers disposed on the multiple first plate patterns 121. For example, the reinforcement layer RCL may include a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, a passivation layer 145, and a planarization layer 146.

[0151] According to an exemplary embodiment, during the process of manufacturing the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, passivation layer 145, and planarization layer 146, in order to also form the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, passivation layer 145, and planarization layer 146 on the plurality of first auxiliary electrodes 125, the inorganic material used to form the buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, passivation layer 145, and planarization layer 146 is etched in the portions where the plurality of first plate patterns 121 and the plurality of first auxiliary patterns 125 are not provided, to form a reinforcement layer RCL.

[0152] In one exemplary embodiment, the reinforcement layer RCL may include a second via HL2. For example, at least a portion of each of the plurality of inorganic insulating layers included in the reinforcement layer RCL (e.g., buffer layer 141, gate insulating layer 142, first interlayer insulating layer 143, second interlayer insulating layer 144, passivation layer 145, and planarization layer 146) is removed to form the second via HL2.

[0153] According to an exemplary embodiment, the second through-hole HL2 formed in the reinforcing layer RCL may be formed in the central portion of the reinforcing layer RCL, but is not limited thereto, and may be formed in various locations.

[0154] Furthermore, the second through-hole HL2 formed in the reinforcing layer RCL may overlap with the first through-hole HL1 formed in the first auxiliary pattern 125. Therefore, the first through-hole HL1 and the second through-hole HL2 overlapping with the first through-hole can constitute a configuration already referenced. Figure 1 The described display panel 10 has a plurality of through holes HL. According to an exemplary embodiment, a first auxiliary pattern 125 including a first through hole HL1 and a reinforcing layer RCL disposed on the first auxiliary pattern 125 and having a second through hole HL2 can be defined as a flow control layer FCL. That is, through holes HL including the first through hole HL1 and the second through hole HL2 can be defined on the flow control layer FCL.

[0155] In one exemplary embodiment, the through-hole HL (e.g., the first through-hole HL1 and the second through-hole HL2) may be configured to overlap with the first groove GRV1 and the second groove GRV2 that overlap with each other. That is, the first groove GRV1, the second groove GRV2, the first through-hole HL1 and the second through-hole HL2 may be configured to overlap with each other, such that the damper DPR may be formed (or defined) between the lower substrate 111 and the upper substrate 112.

[0156] According to an exemplary embodiment, as described above, the damper DPR (or internal blank space) formed by the first groove GRV1, the second groove GRV2, the first through hole HL1, and the second through hole HL2 can be filled with gas, such as air. In this case, when a force (or impact) is applied to the display device 100 from the outside, the force (or impact) applied from the outside is not directly transmitted to the display device 100, but is dispersed by the air in the damper DPR. Therefore, the impact resistance of the display device 100 is improved, and damage to the various components included in the display device 100 (e.g., connecting lines 181 and 182 formed on the line pattern) caused by external impacts can be suppressed. Therefore, the tensile reliability of the display device 100 can be improved.

[0157] Meanwhile, the exemplary embodiments of the present invention are not limited thereto, and the damper DPR (or internal blank space) formed by the first groove GRV1, the second groove GRV2, the first through hole HL1 and the second through hole HL2 can be filled with various types of gas.

[0158] According to an exemplary embodiment, the width of each of the first groove GRV1 and the second groove GRV2 may be greater than the width of the through hole HL, for example, the width of each of the first through hole HL1 and the second through hole HL2.

[0159] Figure 7 It is used to explain the inclusion of Figure 2 A view of an example of a damper formed in a display device, comprising a lower substrate, an upper substrate, and a display panel.

[0160] Figure 8A and Figure 8B This is a view used to illustrate an example of applying an impact to a display device according to a comparative example of the present invention;

[0161] Figures 9A to 9C This is a view used to illustrate an example of applying an impact to a display device according to an exemplary embodiment of the present invention.

[0162] At the same time, Figure 8A and Figure 8B The image shows an example of applying an external impact to a display device 100_C according to a comparative example of the present invention, wherein no damper is formed in the display device 100_C. Figures 9A to 9C The image shows an example of applying an external impact to a display device 100 according to an exemplary embodiment of the present invention, wherein a damper is formed in the display device 100.

[0163] First, refer to Figure 7 As described above, the lower substrate 111 includes a first groove GRV1, and the upper substrate 112 includes a second groove GRV2. The through-hole HL of the display panel 10 can be formed to overlap with the first groove GRV1 and the second groove GRV2. Therefore, an internal blank space, i.e., a damper DPR, can be formed in the display device 100.

[0164] Here, when a force is applied to the display device 100 from the outside, a first force F1 based on air pressure is generated in the damper DPR (where the second groove GRV2 of the substrate (e.g., the upper substrate 112) located on the side surface where the force is applied) in the same direction as the direction of the force applied from the outside. At this time, as described above, the width of the through hole HL is smaller than the width of each of the first groove GRV1 and the second groove GRV2, so that the air flow rate in the through hole HL is instantaneously controlled (e.g., reduced). Therefore, the second force F2 generated by the air pressure in the damper DPR (where the first groove GRV1 of the lower substrate 111 is located) can be less than the first force F1. For example, the instantaneous control (e.g., reduction) of the air flow rate in the through hole HL generates resistance (e.g., a force based on air resistance) in the direction opposite to the direction in which the first force F1 is applied. Therefore, the second force F2 generated by the air pressure in the damper DPR (where the first groove GRV1 of the lower substrate 111 is located) can be less than the first force F1. The resistance based on airflow speed control acts in the opposite direction to the force applied from the outside, thereby suppressing damage to various components included in the display panel 10 caused by external impacts.

[0165] More specifically, refer to Figure 8A and Figure 8B When a force is applied from the outside of the display device 100_C according to the comparative example of the present invention along the object OBJ, no separate internal blank space is formed in the display device 100_C. Therefore, the force applied from the outside can be transmitted to the lower substrate 111_C, the upper substrate 112_C, and the display panel 10_C as is. Therefore, various components included in the display panel 10_C may be damaged by impacts applied from the outside. For example, the connecting wires included in the display device 100_C may be damaged by external impacts.

[0166] In contrast, refer to Figure 9A and Figure 9B When a force is applied along the object OBJ from the display device 100 according to an exemplary embodiment of the present invention, as referred to above... Figure 7In the damper DPR located in the second groove GRV2 of the substrate (e.g., upper substrate 112) on the side surface where the force is applied, a first force F1 based on air pressure is generated in the same direction as the force applied from the outside. The airflow velocity is instantaneously controlled (e.g., reduced) in the through-hole HL, such that the second force F2 generated according to the air pressure in the damper DPR (in which the first groove GRV1 of the lower substrate 111 is located) is less than the first force F1. For example, the airflow velocity is instantaneously controlled (e.g., reduced) in the through-hole HL, such that a third force F3 is generated in the direction opposite to the direction in which the first force F1 is applied, for example, based on a force based on air resistance. Therefore, the second force F2 generated according to the air pressure in the damper DPR where the first groove GRV1 of the lower substrate 111 is located is less than the first force F1. The third force F3, controlled based on airflow velocity, acts in the direction opposite to the force applied from the outside, thereby suppressing damage to various components included in the display panel 10 caused by external impacts.

[0167] At the same time, such as Figure 9C As shown, when the force applied from the outside along the object OBJ is kept constant, the fourth force F4 acting in the portion of the damper DPR in which the second groove GRV2 is formed and the fifth force F5 acting in the portion in which the first groove GRV1 is formed are in equilibrium. Therefore, the display device 100 can stably maintain the adjusted state.

[0168] At the same time, refer to Figure 7 According to an exemplary embodiment, the first distance d1 between the display panel 10 and the lower substrate 111 in which the first groove GRV1 is defined, and the second distance d2 between the display panel 10 and the upper substrate 112 in which the second groove GRV2 is defined, may be equal. For example, the first distance d1 and the second distance d2 are 100 μm, but are not limited thereto, and the first distance d1 and the second distance d2 may be determined according to the degree of control of the airflow rate.

[0169] Figures 10A to 10L This is a process flow diagram illustrating a method for manufacturing a display device according to an exemplary embodiment of the present invention.

[0170] At the same time, Figures 10A to 10L In the middle, it is shown that the reference has been made. Figure 5 and Figure 6 A cross-sectional view illustrating the manufacturing process of a display device 100 according to an exemplary embodiment of the present invention. For example, in Figures 10A to 10L In the middle, the references are shown in sequence. Figure 5 and Figure 6 The present invention describes a method for manufacturing a display device 100 according to an exemplary embodiment of the present invention. For ease of description, it will be based on a method already referenced. Figure 6The display device 100 is described using a cross-sectional view.

[0171] Furthermore, for ease of description, references will not be repeated. Figures 1 to 9C A description that has already been repeated.

[0172] At the same time, it will refer to Figures 10A to 10L The insulating, semiconductor, and metal layers described are formed using conventional manufacturing processes for circuit elements. These layers are formed by coating or deposition methods, and are selectively patterned using photolithography and etching processes to form various electrodes, patterns, and signal lines. Therefore, for ease of description, detailed descriptions will be omitted.

[0173] First, refer to Figure 10A A sacrificial layer SFL can be formed on the motherboard MSB.

[0174] The motherboard MSB is a substrate that supports components disposed on the lower substrate 111 during the manufacturing process of the display device 100. The motherboard MSB may be formed of a rigid material. For example, the motherboard MSB may be formed of glass, but is not limited thereto.

[0175] The motherboard MSB can be used to manufacture multiple display devices 100 simultaneously. For example, multiple units are defined on the motherboard MSB, and each unit may correspond to each of the multiple manufactured display devices.

[0176] The sacrificial layer SFL formed on the motherboard MSB is a layer used to separate the pattern layer 120 of the display device 100 from the motherboard MSB. The sacrificial layer SFL can be formed of a material in which the interfacial bonding force of the sacrificial layer SFL is broken down when irradiated with a laser, thereby weakening the adhesion strength with the pattern layer 120 of the display device 100. For example, the sacrificial layer SFL can be configured as a silicon nitride (SiNx) or silicon oxide (SiOx) or a laminate of silicon nitride and silicon oxide. The sacrificial layer SFL can be formed by depositing silicon nitride and silicon oxide on the entire surface of the motherboard MSB, but is not limited thereto.

[0177] Subsequently, a pattern layer 120 may be provided on the sacrificial layer SFL, and first to fifth insulating materials 141a to 145a may be provided on the pattern layer 120.

[0178] More specifically, firstly, further referencing Figure 10B A first insulating material 141a may be disposed on the pattern layer 120. The first insulating material 141a may be used to form a pattern that has been referenced. Figure 5 and Figure 6 The material of the buffer layer 141 described.

[0179] Meanwhile, even if not shown separately, a semiconductor layer for configuring active layers 152 and 162 is provided (e.g., deposited) on the first insulating material 141a, and at least a portion of the semiconductor layer is patterned to form active layers 152 and 162.

[0180] Next, further reference Figure 10C A second insulating material 142a may be disposed on the first insulating material 141a. The second insulating material 142a may be used to form a material that has been referenced. Figure 5 and Figure 6 The material of the gate insulating layer 142 is described.

[0181] Meanwhile, although not shown separately, a first metal layer for configuring gates 151 and 161 is disposed (e.g., deposited) on a second insulating material 142a, and at least a portion of the first metal layer is patterned to form gates 151 and 161.

[0182] Next, further reference Figure 10D A third insulating material 143a may be disposed on the second insulating material 142a. The third insulating material 143a may be used to form a material that has been referenced. Figure 5 and Figure 6 The material of the first interlayer insulation layer 143 is described.

[0183] Meanwhile, although not shown separately, a second metal layer for configuring the intermediate metal layer IM is disposed (e.g., deposited) on the third insulating material 143a, and at least a portion of the second metal layer is patterned to form the intermediate metal layer IM.

[0184] Next, further reference Figure 10E A fourth insulating material 144a may be disposed on the third insulating material 143a. The fourth insulating material 144a may be used to form a reference. Figure 5 and Figure 6 The material of the second interlayer insulation layer 144 is described.

[0185] Simultaneously, although not shown separately, a third metal layer is also formed (e.g., deposited) on the fourth insulating material 144a for configuring the plurality of pads DP and VP, source 153, and drains 154 and 164. At least a portion of the third metal layer is patterned to form the plurality of pads DP and VP, source 153, and drains 154 and 164.

[0186] Next, further reference Figure 10F A fifth insulating material 145a may be disposed on the fourth insulating material 144a. The fifth insulating material 145a may be used to form a material already referenced. Figure 5 and Figure 6 The described passivation layer 145 is an insulating material.

[0187] Next, further reference Figure 10G At least a portion of the fifth insulating material 145a, the fourth insulating material 144a, the third insulating material 143a, the second insulating material 142a, and the first insulating material 141a are removed (e.g., etched) using at least one mask. In this way, a passivation layer 145 (or the fifth insulating layer), a second interlayer insulating layer 144 (or the fourth insulating layer), a first interlayer insulating layer 143 (e.g., the third insulating layer), a gate insulating layer 142 (or the second insulating layer), and a buffer layer 141 (or the first insulating layer) can be formed. For example, among the fifth insulating material 145a, the fourth insulating material 144a, the third insulating material 143a, the second insulating material 142a, and the first insulating material 141a, those disposed in areas other than the regions where the pattern layer 120 is disposed of, including the plurality of first board patterns 121 and the plurality of first auxiliary patterns 125, are removed. In this way, a passivation layer 145 (or a fifth insulating layer), a second interlayer insulating layer 144 (or a fourth insulating layer), a first interlayer insulating layer 143 (or a third insulating layer), a gate insulating layer 142 (or a second insulating layer) and a buffer layer 141 (or a first insulating layer) can be formed.

[0188] For this purpose, photoresist is applied to a fifth insulating material 145a, a fourth insulating material 144a, a third insulating material 143a, a second insulating material 142a, and a first insulating material 141a disposed in the remaining areas, excluding the areas where the patterned layer 120 is formed, including the plurality of first plate patterns 121 and the plurality of first auxiliary patterns 125. Thereafter, at least one mask having mask openings overlapping the remaining areas can be used to form a passivation layer 145 (or the fifth insulating layer), a second interlayer insulating layer 144 (or the fourth insulating layer), a first interlayer insulating layer 143 (or the third insulating layer), a gate insulating layer 142 (or the second insulating layer), and a buffer layer 141 (or the first insulating layer), respectively.

[0189] Furthermore, in a portion of the regions where the fifth insulating material 145a, fourth insulating material 144a, third insulating material 143a, second insulating material 142a, and first insulating material 141a are located, the fifth insulating material 145a, fourth insulating material 144a, third insulating material 143a, second insulating material 142a, and first insulating material 141a are located to form a second through-hole HL2.

[0190] According to an exemplary embodiment, the passivation layer 145, the second interlayer insulating layer 144, the first interlayer insulating layer 143, the gate insulating layer 142, and the buffer layer 141 are etched according to soft etching conditions. Therefore, the side surface of each of the passivation layer 145, the second interlayer insulating layer 144, the first interlayer insulating layer 143, the gate insulating layer 142, and the buffer layer 141 has an overall inclined tapered structure.

[0191] Furthermore, a plurality of first plate patterns 121 and a plurality of auxiliary patterns 125 can be formed by removing (e.g., etching) at least a portion of the pattern layer 120 using at least one mask. For this purpose, after photoresist is applied to at least a portion of the pattern layer 120, a plurality of first plate patterns 121 and a plurality of first auxiliary patterns 125 can be formed using at least one mask having mask openings overlapping the corresponding areas.

[0192] Furthermore, a portion of the area in which the patterned layer 120 is formed of the plurality of first auxiliary patterns 125 is removed to form a first through-hole HL1. In an exemplary embodiment, the first through-hole HL1 may overlap with a second through-hole HL2.

[0193] Next, further reference Figure 10H A planarization layer 146 may be provided on the passivation layer 145. For example, the planarization layer 146 is formed by patterning after forming an insulating material for configuring the planarization layer on the passivation layer 145. For example, the planarization layer 146 may be patterned to be provided in a region in which a plurality of first plate patterns 121 and a plurality of first auxiliary patterns 125 are formed.

[0194] The planarization layer 146 is configured to cover the top and side surfaces of the buffer layer 141, the gate insulating layer 142, the first interlayer insulating layer 143, the second interlayer insulating layer 144 and the passivation layer 145, and may be configured to cover at least a portion of the top surface of the first board pattern 121 and the top surface of the first auxiliary pattern 125.

[0195] Furthermore, the planarization layer 146 is disposed in the region in which a plurality of first auxiliary patterns 125 are formed, such that the planarization layer 146 may not be formed in the region in which the first through hole HL1 and the second through hole HL2 are disposed.

[0196] Next, further reference Figure 10I A dam 147 may be provided on the planarization layer 146. The dam 147 may be configured to cover at least a portion of the connecting lines 181 and 182 and the planarization layer 146.

[0197] Next, further reference Figure 10JAn upper substrate 112 may be provided. The upper substrate 112 may be configured to cover various components disposed on the lower substrate 111, such as a pattern layer 120, a buffer layer 141, a gate insulating layer 142, a first interlayer insulating layer 143, a second interlayer insulating layer 144, a passivation layer 145, a planarization layer 146, and a dam 147. For example, the upper substrate 112 may be bonded by a fill layer 190.

[0198] Furthermore, as described above, the upper substrate 112 may include a plurality of second grooves GRV2 formed by removing at least a portion of the upper substrate 112. Each of the plurality of second grooves GRV2 may be configured to overlap with a first through-hole HL1 of the first auxiliary pattern 125 and / or a second through-hole HL2 of the reinforcing layer RCL disposed on the first auxiliary pattern 125.

[0199] Furthermore, the internal blank space (i.e., the damper DPR) is formed by the second groove GRV2, the first through hole HL1, and the second through hole HL2, and the damper DPR can be filled with gas (e.g., air). That is, no filling layer 190 is provided in the region in which the damper DPR is formed.

[0200] According to an exemplary embodiment, a filler layer 190 patterned to correspond to the shape of the second groove GRV2 may be attached to a surface of an upper substrate 112 that includes a plurality of second grooves GRV2. For example, the filler layer 190 may be patterned not to be formed in areas where the second grooves GRV2 (or dampers DPR) are disposed. For example, the filler layer 190 may be patterned by a printing technique (e.g., gravure offset printing, screen printing, or inkjet printing) and cured by thermosetting or UV curing to bond to the upper substrate 112.

[0201] Next, further reference Figure 10K It can perform a laser lift-off (LLO) process to separate the sacrificial layer SFL and the motherboard MSB from the pattern layer 120 of the display device 100.

[0202] Next, further reference Figure 10L A lower substrate 111 is provided to manufacture a display device 100. Furthermore, as described above, the lower substrate 111 may include a plurality of first grooves GRV1 formed by removing at least a portion of the lower substrate 111. Each of the plurality of first grooves GRV1 may be configured to overlap with a first through-hole HL1 of a first auxiliary pattern 125 and / or a second through-hole HL2 of a reinforcing layer RCL disposed on the first auxiliary pattern 125.

[0203] Furthermore, the internal blank space (i.e., the damper DPR) can be formed together with the second groove GRV2 through the first groove GRV1, the first through hole HL1, and the second through hole HL2.

[0204] Figure 11 It is shown Figure 2 An enlarged plan view of another example of part A.

[0205] at the same time, Figure 11 This shows the number of first through-holes HL1 formed in a first auxiliary pattern 125_1. Figure 4 The modified implementation is described below. Therefore, for ease of description, redundant descriptions will not be repeated.

[0206] Reference Figure 11 Multiple first auxiliary patterns 125_1 can be disposed on the active region AA of the lower substrate 111. The multiple first auxiliary patterns 125_1 are disposed on the lower substrate 111 at intervals from each other.

[0207] In one exemplary embodiment, each of the plurality of first auxiliary patterns 125_1 may include a plurality of first through holes HL1. For example, at least a portion of each of the plurality of first auxiliary patterns 125 is removed to form a plurality of first through holes HL1.

[0208] According to an exemplary embodiment, a plurality of first through holes HL1 formed in each of the plurality of first auxiliary patterns 125_1 may be formed in the central portion and each corner portion of the first auxiliary pattern 125_1. For example, one first auxiliary pattern 125_1 may include five first through holes HL1. As described above, the degree of control over the airflow velocity is changed by the first through holes HL1 of the damper DPR according to the number of first through holes HL1 formed in the first auxiliary pattern 125_1. Therefore, the number of first through holes HL1 formed in each of the plurality of first auxiliary patterns 125_1 may be determined according to the design of the display device 100.

[0209] Figure 12 This is a plan view illustrating a display device according to an exemplary embodiment of the present invention.

[0210] Figure 13 It is shown that it includes Figure 12 Plan view of an example of a lower substrate and an upper substrate in a display device.

[0211] Figure 12 and Figure 13 Show Figure 2 and Figure 3 The modified embodiment relates to the pattern layer 120_1 included in the display device 100_1 and the region therein having a first groove GRV1_1 and a second groove GRV2_1 formed in each of the lower substrate 111_1 and the upper substrate 112_1. Therefore, for ease of description, redundant descriptions will not be repeated.

[0212] Reference Figure 12 and13 The display device 100_1 according to an exemplary embodiment of the present invention may include a lower substrate 111_1, an upper substrate 112_1, a pattern layer 120_1, a plurality of pixels PX, a gate driver GD, a data driver DD, and a power supply PS.

[0213] Pattern layer 120_1 may include: a plurality of first plate patterns 121 and a plurality of first line patterns 122 disposed in the active region AA; and a plurality of second plate patterns 123 and a plurality of second line patterns 124 disposed in the non-active region NA.

[0214] In addition, in an exemplary embodiment, the pattern layer 120_1 may also include a plurality of first auxiliary patterns 125 disposed in the active region AA and a plurality of second auxiliary patterns 126 disposed in the non-active region NA.

[0215] Multiple second auxiliary patterns 126 can be arranged in the form of islands spaced apart from each other. Each of the multiple second auxiliary patterns 126 can be separate.

[0216] In addition, Figure 12 The diagram shows multiple second auxiliary patterns 126 having quadrilateral shapes, but is not limited to this; the multiple second auxiliary patterns 126 can be modified in various forms.

[0217] In one exemplary embodiment, each of the plurality of second auxiliary patterns 126 is configured to be adjacent to the plurality of second plate patterns 123 in a direction different from the first direction X and the second direction Y. For example, each of the plurality of second auxiliary patterns 126 may be configured to be adjacent to the plurality of second plate patterns 126 in a diagonal direction (e.g., a third direction) between the first direction X and the second direction Y. Thus, as Figure 12 As shown, each of the plurality of second auxiliary patterns 126 may be disposed between adjacent second line patterns 124 along the first direction X and / or between adjacent second line patterns 124 along the second direction Y.

[0218] In addition, such as Figure 12 As shown, unlike the first plate pattern 121 and the second plate pattern 123, the plurality of second auxiliary patterns 126 are not connected to the line patterns, such as the first line pattern 122 and the second line pattern 124, but can be set to be spaced apart from each other.

[0219] Further reference Figure 13 Grooves may be formed in each of the lower substrate 111_1 and the upper substrate 112_1. For example, the lower substrate 111_1 includes a plurality of first grooves GRV1_1 formed on a planar surface (e.g., a top surface) opposite to the upper substrate 112_1, and the upper substrate 112_1 may include a plurality of second grooves GRV2_1 formed on a planar surface (e.g., a bottom surface) opposite to the lower substrate 111_1.

[0220] In one exemplary embodiment, the plurality of first grooves GRV1_1 defined on the lower substrate 111_1 may include a plurality of first sub-grooves GRV11 formed in the active region AA and a plurality of second sub-grooves GRV12 formed in the non-active region NA. Furthermore, the plurality of second grooves GRV2_1 defined on the upper substrate 112_1 may include a plurality of third sub-grooves GRV21 formed in the active region AA and a plurality of fourth sub-grooves GRV22 formed in the non-active region NA.

[0221] In one exemplary embodiment, each of the plurality of first grooves GRV1_1 defined on the lower substrate 111_1 may overlap with each of the plurality of second grooves GRV2_1 defined on the upper substrate 112. For example, the plurality of first sub-grooves GRV11 defined on the lower substrate 111_1 and disposed in the active region AA and the plurality of third sub-grooves GRV21 defined on the upper substrate 112_1 and disposed in the active region AA may be formed in the same position on the planar surface. Similarly, the plurality of second sub-grooves GRV12 defined on the lower substrate 111_1 and disposed in the non-active region NA and the plurality of fourth sub-grooves GRV22 defined on the upper substrate 112_1 and disposed in the non-active region NA are formed in the same position on the planar surface.

[0222] Each of the plurality of first sub-grooves GRV11 and the plurality of third sub-grooves GRV21 can be configured to overlap with a plurality of first auxiliary patterns 125 included in pattern layer 120_1. That is, each of the plurality of first sub-grooves GRV11 and the plurality of third sub-grooves GRV21 can be configured not to overlap with a plurality of first plate patterns 121 and a plurality of first line patterns 122 included in pattern layer 120_1. Therefore, the damper DPR defined by the first sub-grooves GRV11 and the third sub-grooves GRV21 can be formed to overlap with the plurality of first auxiliary patterns 125.

[0223] Furthermore, each of the plurality of second sub-grooves GRV12 and the plurality of fourth sub-grooves GRV22 can be configured to overlap with the plurality of second auxiliary patterns 126 included in the pattern layer 120_1. That is, each of the plurality of second sub-grooves GRV12 and the plurality of fourth sub-grooves GRV22 can be configured not to overlap with the plurality of second plate patterns 123 and the plurality of second line patterns 124 included in the pattern layer 120_1. Therefore, the damper DPR defined by the second sub-grooves GRV12 and the fourth sub-grooves GRV22 can be formed to overlap with the plurality of second auxiliary patterns 126.

[0224] As described above, a damper DPR that controls airflow velocity during external impact is formed not only in the active region AA but also in the non-active region NA, within the internal blank space. Therefore, the impact resistance of the display device 100_1 is enhanced, thereby improving the tensile reliability of the display device 100_1.

[0225] As described above, a display device according to an exemplary embodiment of the present invention may include a damper (or internal blanking space) formed by a first groove defined on a lower substrate, a second groove defined on an upper substrate, and a through hole defined on a display panel. In this case, when a force (or impact) is applied to the display device from the outside, the force (or impact) applied from the outside is not directly transmitted to the display panel, but can be dispersed by gas (e.g., air) in the damper.

[0226] Therefore, the impact resistance of the display device can be improved, and damage to various components (e.g., connecting lines) included in the display device caused by external impacts can be suppressed. Thus, the tensile reliability of the display device can be improved.

[0227] Exemplary embodiments of the present invention can also be described as follows:

[0228] According to one aspect of the present invention, a display device may include: a stretchable lower substrate; a plurality of plate patterns disposed on the lower substrate and spaced apart from each other; a plurality of line patterns disposed on the lower substrate between plate patterns adjacent to each other along a first direction and between plate patterns adjacent to each other along a second direction different from the first direction; a plurality of connecting lines disposed above each of the plurality of line patterns; and a plurality of auxiliary patterns adjacent to the plurality of plate patterns on the lower substrate along an oblique direction between the first and second directions.

[0229] Each of the plurality of auxiliary patterns may be disposed among the plurality of line patterns.

[0230] Each of the plurality of line patterns may be disposed between adjacent plate patterns among the plurality of plate patterns to connect the adjacent plate patterns, and the plurality of auxiliary patterns and the plurality of line patterns may be disposed spaced apart from each other without being connected.

[0231] Each of the plurality of auxiliary patterns may include at least one first through hole.

[0232] The display device may further include a reinforcing layer comprising at least one insulating layer and disposed above each of the plurality of auxiliary patterns.

[0233] The reinforcing layer may include a second through-hole that overlaps with the at least one first through-hole.

[0234] A first groove that overlaps with the first through hole is defined on the lower substrate.

[0235] The width of the first groove can be greater than the width of the first through hole.

[0236] The display device may further include a stretchable upper substrate opposite to the lower substrate. A second groove overlapping the first through-hole may be defined on the upper substrate.

[0237] The width of the second groove can be greater than the width of the first through hole.

[0238] According to one aspect of the present invention, a display device includes: a stretchable lower substrate; a plurality of plate patterns disposed on the lower substrate and spaced apart from each other; a plurality of line patterns disposed on the lower substrate between adjacent plate patterns along a first direction and between adjacent plate patterns along a second direction different from the first direction; and a plurality of connecting lines disposed above each of the plurality of line patterns, wherein a first groove that does not overlap with the plurality of plate patterns and the plurality of line patterns is defined on the lower substrate.

[0239] The first groove may be configured to be adjacent to the plurality of plate patterns in a diagonal direction between the first direction and the second direction.

[0240] The display device may further include a plurality of auxiliary patterns on the lower substrate, the plurality of auxiliary patterns being configured to overlap with the first groove.

[0241] Each of the plurality of auxiliary patterns may include at least one first through hole.

[0242] The display device may further include a reinforcing layer comprising at least one insulating layer and disposed above each of the plurality of auxiliary patterns.

[0243] The reinforcing layer may include a second through-hole that overlaps with the at least one first through-hole.

[0244] The display device may further include a stretchable upper substrate opposite to the lower substrate. A second groove overlapping the first groove may be defined on the upper substrate.

[0245] According to one aspect of the present invention, a display device may include: a stretchable lower substrate having a first groove defined thereon; a stretchable upper substrate opposite to the lower substrate and defining a second groove overlapping the first groove; and a display panel disposed between the lower substrate and the upper substrate.

[0246] The display panel may include through holes that overlap with the first groove and the second groove.

[0247] The internal blank space formed by the first groove, the second groove, and the through hole can be filled with gas.

[0248] Although exemplary embodiments of the present invention have been described in detail with reference to the accompanying drawings, the present invention is not limited thereto and may be implemented in many different forms without departing from the inventive concept. Therefore, the exemplary embodiments of the present invention are provided for illustrative purposes only and are not intended to limit the inventive concept. The scope of the inventive concept is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are exemplary in all respects and do not limit the present invention. The scope of protection of the present invention should be interpreted based on the appended claims, and all inventive concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present invention.

Claims

1. A display device, comprising: Stretchable lower substrate; Multiple board patterns are disposed on the lower substrate and spaced apart from each other; Multiple line patterns are disposed on the lower substrate between adjacent plate patterns along a first direction and between adjacent plate patterns along a second direction different from the first direction. Multiple connecting lines are arranged above each of the multiple line patterns; as well as Multiple auxiliary patterns are adjacent to the multiple plate patterns on the lower substrate along a diagonal line direction between the first direction and the second direction.

2. The display device according to claim 1, wherein each of the plurality of auxiliary patterns is disposed between the plurality of line patterns.

3. The display device according to claim 1, wherein each of the plurality of line patterns is disposed between adjacent plate patterns among the plurality of plate patterns to connect the adjacent plate patterns, and the plurality of auxiliary patterns and the plurality of line patterns are configured to be spaced apart from each other and not connected.

4. The display device according to claim 1, wherein each of the plurality of auxiliary patterns includes at least one first through hole.

5. The display device according to claim 4, further comprising: A reinforcing layer comprising at least one insulating layer and disposed above each of the plurality of auxiliary patterns.

6. The display device according to claim 5, wherein the reinforcing layer includes a second through-hole overlapping the at least one first through-hole.

7. The display device according to claim 4, wherein the first groove overlapping the first through hole is defined on the lower substrate.

8. The display device according to claim 7, wherein the width of the first groove is greater than the width of the first through hole.

9. The display device according to claim 4, further comprising: A stretchable upper substrate opposite to the lower substrate. The second groove, which overlaps with the first through hole, is defined on the upper substrate.

10. The display device according to claim 9, wherein the width of the second groove is greater than the width of the first through hole.

11. A display device, comprising: Stretchable lower substrate; Multiple board patterns are disposed on the lower substrate and spaced apart from each other; Multiple line patterns are disposed on the lower substrate between adjacent plate patterns along a first direction and between adjacent plate patterns along a second direction different from the first direction. as well as Multiple connecting lines are arranged above each of the multiple line patterns. The first groove, which does not overlap with the plurality of plate patterns and the plurality of line patterns, is defined on the lower substrate.

12. The display device of claim 11, wherein the first groove is configured to be adjacent to the plurality of plate patterns in an oblique direction between the first direction and the second direction.

13. The display device according to claim 11, further comprising: Multiple auxiliary patterns on the lower substrate are configured to overlap with the first groove.

14. The display device of claim 13, wherein each of the plurality of auxiliary patterns includes at least one first through hole.

15. The display device according to claim 14, further comprising: A reinforcing layer comprising at least one insulating layer and disposed above each of a plurality of auxiliary patterns.

16. The display device of claim 15, wherein the reinforcing layer includes a second through-hole overlapping the at least one first through-hole.

17. The display device according to claim 11, further comprising: A stretched upper substrate opposite to the lower substrate. The second groove, which overlaps with the first groove, is defined on the upper substrate.

18. A display device, comprising: A stretchable lower substrate, on which a first groove is defined; A stretchable upper substrate, the upper substrate being opposite to the lower substrate and defining a second groove overlapping the first groove; and A display panel disposed between the lower substrate and the upper substrate.

19. The display device of claim 18, wherein the display panel includes a through hole overlapping the first recess and the second recess.

20. The display device of claim 19, wherein the internal blank space formed by the first groove, the second groove and the through hole is filled with gas.

21. The display device according to claim 18, further comprising: Multiple board patterns are disposed on the lower substrate and spaced apart from each other; as well as Multiple line patterns are disposed on the lower substrate between adjacent plate patterns along a first direction and between adjacent plate patterns along a second direction different from the first direction.

Images