Display device and electronic device including the same

Abstract

A display device and an electronic device including the same are provided, the electronic device including a display panel including: a substrate including a display area and a pad area; a thin film transistor in the display area and including a semiconductor layer, a gate layer on the semiconductor layer, and a first conductive layer electrically connected to the semiconductor layer; a second conductive layer on the thin film transistor and electrically connected to the first conductive layer; a pixel electrode on the second conductive layer and electrically connected to the second conductive layer; an input sensing layer on the pixel electrode and including a touch conductive layer and an organic insulating layer; a support pad layer in the pad region of the substrate and including the same material as the pixel electrode; a polymer pad on the support pad layer; and an upper pad layer on the polymer pad and including the same material as the touch conductive layer.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0131092, filed on September 26, 2024, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] Some aspects of the embodiments relate to a display device and an electronic device including the display device. Background Technology

[0003] Mobile electronic devices are widely used. These include not only compact electronic devices such as mobile phones, but also tablet PCs, which have recently gained widespread adoption.

[0004] To support various functions, such mobile electronic devices include display devices for providing users with visual information such as images or videos. Recently, as other components used to drive the display devices have been miniaturized, the proportion of display devices in electronic devices has been gradually increasing, and structures capable of bending display devices from a flat state to an angle are being developed.

[0005] The information disclosed in this background section is only used to enhance the understanding of the background art, and therefore the information discussed in this background art does not necessarily constitute prior art. Summary of the Invention

[0006] Some embodiments include a display device in which the pad and the signal pad are in precise contact with each other at a desired location.

[0007] In addition, one or more embodiments include a display panel having a pad (“pad”, or “soldering pad”) with a relatively reduced size.

[0008] However, this feature is an example, and the features of the embodiments according to this disclosure are not limited thereto.

[0009] Additional aspects will be set forth in part in the description which follows, and in part will be apparent from the description, or may be learned by practicing the disclosed embodiments.

[0010] According to some embodiments, a display device includes: a display panel including a substrate comprising a display area and a pad area, a display portion disposed in the display area of ​​the substrate, and a pad disposed in the pad area of ​​the substrate; and a connection circuit board including a signal pad electrically connected to the pad, wherein the display portion may include: a thin-film transistor on the substrate, and including a semiconductor layer, a gate layer on the semiconductor layer, and a first conductive layer electrically connected to the semiconductor layer; a second conductive layer on the thin-film transistor and electrically connected to the first conductive layer; a pixel electrode on the second conductive layer for electrically connecting to the second conductive layer; and an input sensing layer on the pixel electrode, and including a touch conductive layer and an organic insulating layer, wherein the pad may include: a support pad layer on the substrate and including the same material as the pixel electrode; a polymer pad on the support pad layer; and an upper pad layer on the polymer pad and including the same material as the touch conductive layer.

[0011] According to some embodiments, in a plan view, the polymer pad may be stacked with a support pad layer, and the support pad layer may support the polymer pad.

[0012] According to some embodiments, the upper pad may cover the polymer pad.

[0013] According to some embodiments, the pad may further include: a first conductive pad layer disposed between the substrate and the support pad layer, and may include the same material as the gate layer.

[0014] According to some embodiments, the pad may further include: a second conductive pad layer disposed between the first conductive pad layer and the support pad layer, in contact with the first conductive pad layer, and may include the same material as the first conductive layer.

[0015] According to some embodiments, the pad may further include: a third conductive pad layer disposed between the second conductive pad layer and the support pad layer, in contact with the second conductive pad layer, and may include the same material as the second conductive layer.

[0016] According to some embodiments, the pad may further include: a third conductive pad layer disposed between the first conductive pad layer and the support pad layer, in contact with the first conductive pad layer, and may include the same material as the second conductive layer.

[0017] According to some embodiments, the polymer pad and the support pad layer may each include a plurality of polymer pads and a plurality of support pad layers, and in a plan view, each of the plurality of support pad layers may be stacked with a corresponding polymer pad among the plurality of polymer pads.

[0018] According to some embodiments, multiple support pads may be spaced apart from each other.

[0019] According to some embodiments, the signal pad may contact the upper pad layer.

[0020] According to one or more embodiments, an electronic device includes a display panel and a connection circuit board electrically connected to the display panel, wherein the display panel may include: a substrate including a display area and a pad area; a thin-film transistor disposed in the display area of ​​the substrate and including a semiconductor layer, a gate layer on the semiconductor layer, and a first conductive layer electrically connected to the semiconductor layer; a second conductive layer on the thin-film transistor and electrically connected to the first conductive layer; a pixel electrode on the second conductive layer for electrical connection to the second conductive layer; an input sensing layer on the pixel electrode and including a touch conductive layer and an organic insulating layer; a support pad layer in the pad area of ​​the substrate and including the same material as the pixel electrode; a polymer pad on the support pad layer; and an upper pad layer on the polymer pad and including the same material as the touch conductive layer.

[0021] According to some embodiments, the connection circuit board may include a signal pad electrically connected to the upper pad layer.

[0022] According to some embodiments, in a plan view, the polymer pad may be stacked with a support pad layer, and the support pad layer may support the polymer pad.

[0023] According to some embodiments, the upper pad may cover the polymer pad.

[0024] According to some embodiments, the display panel may further include: a first conductive pad layer disposed between the substrate and the support pad layer, and may include the same material as the gate layer.

[0025] According to some embodiments, the display panel may further include: a second conductive pad layer disposed between the first conductive pad layer and the support pad layer, in contact with the first conductive pad layer, and may include the same material as the first conductive layer.

[0026] According to some embodiments, the display panel may further include: a third conductive pad layer disposed between the second conductive pad layer and the support pad layer, in contact with the second conductive pad layer, and may include the same material as the second conductive layer.

[0027] According to some embodiments, the display panel may further include: a third conductive pad layer disposed between the first conductive pad layer and the support pad layer, in contact with the first conductive pad layer, and may include the same material as the second conductive layer.

[0028] According to some embodiments, the polymer pad and the support pad layer may each include a plurality of polymer pads and a plurality of support pad layers, and in a plan view, each of the plurality of support pad layers may be stacked with a corresponding polymer pad among the plurality of polymer pads.

[0029] According to some embodiments, multiple support pads may be spaced apart from each other.

[0030] Other aspects, features, and characteristics besides those described above will become clear from the disclosed drawings, claims, and detailed description. Attached Figure Description

[0031] The above and other aspects, features, and characteristics of some disclosed embodiments will become clearer from the following description taken in conjunction with the accompanying drawings, in which: Figure 1 This is a schematic plan view of a display device according to some embodiments; Figure 2 This is a schematic cross-sectional view of a portion of a display panel according to some embodiments; Figure 3 This is a schematic plan view of a portion of the input sensing layer according to some embodiments; Figure 4 This is a plan view of the pad according to some embodiments; Figure 5 It is according to some embodiments along Figure 4 The line A-A' shown intercepts Figure 4 A schematic cross-sectional view of the pad; Figure 6 It is according to some embodiments along Figure 4 The line B-B' shown intercepts Figure 4 A schematic cross-sectional view of the pad; Figure 7 This is a schematic cross-sectional view of the pads and signal pads according to some embodiments; Figure 8 This is a schematic plan view of a pad according to some embodiments; Figure 9 It is according to some embodiments along Figure 4 The line A-A' shown intercepts Figure 4 A schematic cross-sectional view of the pad; Figure 10 It is according to some embodiments along Figure 4 The line A-A' shown intercepts Figure 4 A schematic cross-sectional view of the pad; Figure 11 It is according to some embodiments along Figure 4 The line A-A' shown intercepts Figure 4 A schematic cross-sectional view of the pad; Figure 12 It is according to some embodiments along Figure 4 The line A-A' shown intercepts Figure 4 A schematic cross-sectional view of the pad; and Figure 13 It is according to some embodiments along Figure 4 The line A-A' shown intercepts Figure 4 A schematic cross-sectional view of the pad. Detailed Implementation

[0032] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals always refer to the same elements. In this regard, the presented embodiments may take different forms and should not be construed as limited to the description set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain aspects of this specification. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. Throughout this disclosure, the expression “at least one of a, b, and c” means only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0033] Various modifications may be applied to the presented embodiments, and specific embodiments will be shown in the accompanying drawings and described in the detailed description section. The effects and features of the presented embodiments, as well as methods for achieving these effects and features, will become clearer with reference to the following detailed description taken in conjunction with the accompanying drawings. However, the presented embodiments can be implemented in various forms and are not limited to those presented below.

[0034] In the following description, embodiments will be described in detail with reference to the accompanying drawings, and in the description with reference to the drawings, the same or corresponding components are indicated by the same reference numerals, and some redundant descriptions may be omitted.

[0035] In the following embodiments, it will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another.

[0036] In the following embodiments, unless the context clearly specifies otherwise, the singular forms “a,” “an,” and “the” used herein are also intended to include the plural forms.

[0037] In the following embodiments, it will also be understood that the terms “comprising” and / or “including” and variations thereof as used herein indicate the presence of the stated features or elements, but do not exclude the presence or addition of one or more other features or elements.

[0038] In the following embodiments, it will be understood that when an element (such as a layer, film, region, or plate) is referred to as being "on" another element, the element may be directly on the other element, or there may be an intervening element therein.

[0039] For ease of explanation, the dimensions of the elements in the accompanying drawings may be exaggerated. For example, since the dimensions and thicknesses of the elements in the accompanying drawings are arbitrarily shown for ease of explanation, the following embodiments are not limited thereto.

[0040] In the following embodiments, the x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different axes that are not perpendicular to each other.

[0041] When an embodiment can be implemented differently, a particular process sequence can be performed in a different order than that described. For example, two consecutively described processes can be performed substantially simultaneously, or in the reverse order of their description.

[0042] In the instruction manual, the phrase "in the plan view" indicates a distance of 100° perpendicular to the base (see...). Figure 2 The plane viewed from a direction perpendicular to the base (see ) . In other words, expressing "in the plan view, A and B are spaced apart from each other" means: when viewed from a direction perpendicular to the base 100 (see ) Figure 2 When viewed from the direction of A, B are spaced apart from each other.

[0043] In the specification, the phrase "in a sectional view" indicates along a line perpendicular to the base 100 (see...). Figure 2 A section cut along the direction perpendicular to the base (see ). In other words, expressing "in the sectional view, A and B are spaced apart from each other" means: along the direction perpendicular to the base 100 (see ). Figure 2 In the cross-section cut along the direction of ), A and B are spaced apart from each other.

[0044] Figure 1 This is a schematic plan view of a display device 1 according to some embodiments.

[0045] Reference Figure 1 The display device 1 may include a display panel 10 and a connecting circuit board 300.

[0046] Display device 1 may be an electronic device including display panel 10. Electronic devices may include display devices for vehicles (including clusters, center information displays (CIDs) and / or passenger displays), wearable electronic devices that can be worn on any part of a user's body, electronic devices for medical purposes, robots, electronic devices for advertising or display and / or electronic devices for educational purposes.

[0047] Display panel 10 includes a display area DA and a peripheral area PA outside the display area DA. The display area DA is the portion used to display images, and multiple pixels PX can be arranged within the display area DA. In a plan view, the display area DA can have various shapes (e.g., circular, elliptical, polygonal, specific graphic shapes, etc.). Figure 1 In the diagram, the display area DA is shown as a roughly rectangular shape with rounded corners.

[0048] The peripheral region PA can be located outside the display area DA (e.g., outside the display area DA or outside the coverage area of ​​the display area DA). The peripheral region PA is the area where no image is displayed, and can represent the area surrounding the display area DA.

[0049] Each pixel PX may include a display element such as an organic light-emitting element. Each pixel PX may emit, for example, red, green, or blue light. Pixel PX may be connected to pixel circuitry including thin-film transistors (TFTs), storage capacitors, etc. Pixel circuitry may be connected to scan lines SL through which scan signals are transmitted, data lines DL intersecting SL and through which data signals are transmitted, drive voltage lines PL through which drive voltages are supplied, etc. Scan lines SL may extend in a first direction (e.g., the x-axis direction). Data lines DL and drive voltage lines PL may extend in a second direction (e.g., the y-axis direction). Pixel PX may emit light with a brightness corresponding to the electrical signals from the pixel circuitry, and pixel PX is electrically connected to the pixel circuitry. Display area DA may display a specific image by means of the light emitted from pixel PX. For reference, pixel PX may be defined as an emitting area that emits light of any color among red, green, and blue. Although Figure 1 A single pixel PX, a single data line DL, a single scan line SL, and a single drive voltage line PL are shown, but as those skilled in the art will understand, the display panel 10 may include any suitable number of pixels PX, data lines DL, scan lines SL, and drive voltage lines PL depending on the design and size of the display panel 10.

[0050] The peripheral area PA is the area where no pixels PX are arranged, and may be an area where no image is displayed. Power lines and the like for driving pixels PX can be arranged in the peripheral area PA. In addition, pads PD can be arranged in the peripheral area PA, and printed circuit boards including driving circuitry, integrated circuit (IC) components such as driver integrated circuits (ICs), and the aforementioned pads PD can be electrically connected to each other in the peripheral area PA.

[0051] Since the display panel 10 includes the substrate 100 which will be described below (see below) Figure 2 (or other figures), so it can be said that the substrate 100 described below has the aforementioned display area DA and peripheral area PA. In the following description, for convenience, the substrate 100 or display panel 10 is described as having a display area DA and peripheral area PA.

[0052] The pad area PDA with the pad PD can be defined on one side of the peripheral area PA. The pad area PDA can be an area electrically connected to the connection circuit board 300. The pad PD can be disposed in the pad area PDA of the substrate 100. For example, the pad PD can be electrically connected to or in direct contact with the signal pad SPD disposed on the lower surface of the connection circuit board 300. The pad PD of the pad area PDA can exchange electrical signals with the signal pad SPD. Therefore, the connection circuit board 300 can be electrically connected to the display panel 10.

[0053] The signal pad area SPDA, where signal pads SPDs are arranged, can be defined on the lower surface of the connection circuit board 300. In the signal pad area SPDA, the signal pad SPD can protrude in the downward direction. Conversely, in the pad area PDA, the pad PD can protrude in the upward direction.

[0054] The driver chip DIC can be disposed on the connection circuit board 300. The driver chip DIC may include an integrated circuit that drives the display panel 10. The integrated circuit may be a data driver integrated circuit that generates data signals, but is not limited thereto according to embodiments of this disclosure. The driver chip DIC can be mounted on the connection circuit board 300.

[0055] In the following description, the organic light-emitting display device is described as an example of display device 1 according to some embodiments, but display device 1 is not limited thereto. According to some embodiments, display device 1 may include an inorganic light-emitting display device (or an inorganic EL display device), a quantum dot light-emitting display device, etc. For example, the emitting layer of the display element included in display device 1 may include an organic material or an inorganic material. Furthermore, display device 1 may include an emitting layer and a quantum dot layer located in the path of light emitted from the emitting layer.

[0056] Figure 2 This is a schematic cross-sectional view of a portion of a display panel 10 according to some embodiments.

[0057] Reference Figure 2 The substrate 100 may include a display area DA and a peripheral area PA outside the display area DA. The substrate 100 may include various materials having flexible or bendable properties. For example, the substrate 100 may include glass, metal, or polymer resin. Furthermore, the substrate 100 may include polymer resins such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 may also be modified in various ways, such as having a multilayer structure having two layers, each comprising a polymer resin, and a layer comprising an inorganic material (silicon oxide, silicon nitride, silicon oxynitride, etc.) disposed between said two layers.

[0058] A buffer layer 101 may be located on the substrate 100. The buffer layer 101 may prevent or reduce the diffusion of impurity ions, prevent or reduce the penetration of moisture or external air, serve as a barrier layer for surface planarization, and / or serve as a barrier layer. The buffer layer 101 may comprise silicon oxide, silicon nitride, or silicon oxynitride. Furthermore, the buffer layer 101 may regulate the heating rate during the crystallization process for forming the semiconductor layer 110 to ensure uniform crystallization of the semiconductor layer 110.

[0059] A thin-film transistor (TFT) may be located on a substrate 100. The TFT may include a semiconductor layer 110, a gate layer 120, and a first conductive layer 130. The semiconductor layer 110 may be located on a buffer layer 101. The semiconductor layer 110 may include polysilicon and includes an undoped channel region and source and drain regions formed on both sides of the channel region and doped with impurities. The impurities vary depending on the type of TFT and may be N-type or P-type impurities.

[0060] A gate insulating film 102 may be located on the semiconductor layer 110. The gate insulating film 102 may be configured to ensure insulation between the semiconductor layer 110 and the gate layer 120. The gate insulating film 102 may include inorganic materials such as silicon oxide, silicon nitride, silicon oxynitride, etc., and may be disposed between the semiconductor layer 110 and the gate layer 120. Furthermore, the gate insulating film 102 may be formed to correspond to the entire surface of the substrate 100 and may have a structure in which contact holes are formed in predetermined portions. Therefore, an insulating film comprising inorganic materials can be formed by chemical vapor deposition (CVD) or atomic layer deposition (ALD). This also applies to the embodiments and their modifications described below.

[0061] The gate layer 120 may be located above the semiconductor layer 110. The gate layer 120 may be located on the gate insulating film 102. The gate layer 120 may be disposed in a position vertically stacked with the semiconductor layer 110, and may include at least one metal selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), cobalt (Co), calcium (Ca), titanium (Ti), tungsten (W), and copper (Cu).

[0062] Interlayer insulating film 103 may be located on gate layer 120. Interlayer insulating film 103 may cover gate layer 120. Interlayer insulating film 103 may include inorganic materials. For example, interlayer insulating film 103 may include metal oxide or metal nitride, and more specifically, the inorganic material may include silicon oxide (SiO2). y Silicon nitride (SiN) x), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) or zinc oxide (ZnO) x Zinc oxide (ZnO) x The interlayer insulating film 103 may be ZnO and / or ZnO2. In some embodiments, the interlayer insulating film 103 may have SiO y / SiN x or SiN x / SiO y Its dual structure.

[0063] The first conductive layer 130 may be located on the interlayer insulating film 103. The first conductive layer 130 may be electrically connected to the semiconductor layer 110. The first conductive layer 130 may be used as an electrode connected to the source / drain region of the semiconductor layer 110 through vias included in the interlayer insulating film 103 and the gate insulating film 102. The first conductive layer 130 may include one or more metals selected from Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Co, Ca, Mo, Ti, W, and Cu. For example, the first conductive layer 130 may include a Ti layer, an Al layer, and / or a Cu layer.

[0064] A first organic insulating layer 104 may be located on the first conductive layer 130. The first organic insulating layer 104 may be an organic insulating layer covering the upper portion of the first conductive layer 130 and having a generally flat upper surface for use as a planarization film. The first organic insulating layer 104 may include organic materials such as acryloyl, benzocyclobutene (BCB), or hexamethyldisiloxane (HMDSO). The first organic insulating layer 104 may be modified in various ways, such as having a single layer or multiple layers.

[0065] The second conductive layer 140 may be located above the first organic insulating layer 104. The second conductive layer 140 may be disposed above the thin-film transistor (TFT) and may be electrically connected to the first conductive layer 130. The second conductive layer 140 may contact the first conductive layer 130 through vias included in the first organic insulating layer 104. The second conductive layer 140 may include one or more metals selected from Mo, Al, Pt, Pd, Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, Co, Ca, Mo, Ti, W, and Cu. For example, the second conductive layer 140 may include a Ti layer, an Al layer, and / or a Cu layer.

[0066] The second organic insulating layer 105 may be located on the second conductive layer 140. The second organic insulating layer 105 may be an organic insulating layer that covers the upper part of the second conductive layer 140 and has a generally flat upper surface for use as a planarization film. The second organic insulating layer 105 may include organic materials such as acrylamide, BCB, or HMDSO. The second organic insulating layer 105 may be modified in various ways, such as having a single layer or multiple layers.

[0067] Furthermore, according to some embodiments, an additional conductive layer and an additional insulating layer may be disposed between the first conductive layer 130 and the pixel electrode 150, and can be applied in various embodiments. In this state, the additional conductive layer may include the same material as the aforementioned conductive layer and may have the same layer structure. The additional insulating layer may include the same material as the aforementioned organic insulating layer and may have the same layer structure.

[0068] Pixel electrode 150 may be located on the second organic insulating layer 105. Pixel electrode 150 may also be located on the second conductive layer 140 for electrical connection. Pixel electrode 150 may contact the second conductive layer 140 through contact holes formed in the second organic insulating layer 105. A display element may be located above pixel electrode 150. An organic light-emitting diode (OLED) may be used as the display element. In other words, an OLED may be disposed, for example, above pixel electrode 150. Pixel electrode 150 may include a light-transmitting conductive layer formed of a light-transmitting conductive oxide such as indium tin oxide (ITO), In₂O₃, or indium zinc oxide (IZO) and a reflective layer formed of a metal such as Al or Ag. For example, pixel electrode 150 may have a three-layer structure of ITO / Ag / ITO.

[0069] The pixel defining layer 106 may be located on the second organic insulating layer 105 and may cover the edge of the pixel electrode 150. In other words, the pixel defining layer 106 may cover the edge of the pixel electrode 150. The pixel defining layer 106 may have an opening corresponding to the pixel PX, and the opening may be formed to expose at least the central portion of the pixel electrode 150. The pixel defining layer 106 may include an organic material such as polyimide or HMDSO. Furthermore, a spacer 80 may be located on the pixel defining layer 106.

[0070] The first organic insulating layer 104, the second organic insulating layer 105, and the pixel defining layer 106 can be defined as an organic material layer OL.

[0071] Although spacer 80 is shown as being located in the peripheral region PA, spacer 80 may be located in the display region DA. Spacer 80 can prevent or reduce damage to the organic light-emitting diode due to mask sagging during manufacturing processes using masks. Spacer 80 may include an organic insulating material and may be formed as a single layer or multiple layers.

[0072] Intermediate layer 160 and counter electrode 170 may be located within an opening portion of pixel defining layer 106. Intermediate layer 160 may comprise a low molecular weight material or a polymer material, and when comprising a low molecular weight material, intermediate layer 160 may comprise a hole injection layer, a hole transport layer, an emitter layer, an electron transport layer, and / or an electron injection layer. When intermediate layer 160 comprises a polymer material, intermediate layer 160 may have a structure that typically includes a hole transport layer and an emitter layer.

[0073] The counter electrode 170 may include a light-transmitting conductive layer formed of a light-transmitting conductive oxide (such as ITO, In2O3, or IZO). The pixel electrode 150 serves as the anode, and the counter electrode 170 serves as the cathode. The polarity of the electrodes can be reversed.

[0074] The structure of the intermediate layer 160 is not limited to the description presented above, and the intermediate layer 160 can have various structures. For example, at least one of the layers forming the intermediate layer 160 can be integrally formed with the counter electrode 170. According to some embodiments, the intermediate layer 160 may include layers patterned to correspond to each of the pixel electrodes 150.

[0075] Counter electrode 170 can be disposed in display area DA and can be positioned across the entire surface of display area DA. In other words, counter electrode 170 can be integrally formed to cover multiple pixels PX. Counter electrode 170 can electrically contact common power lines disposed in peripheral area PA. According to some embodiments, counter electrode 170 can extend to barrier wall 200. Thin film encapsulation layer TFE can completely cover display area DA and extend toward peripheral area PA to cover at least a portion of peripheral area PA.

[0076] The thin-film encapsulation layer TFE can extend outside the common power line. The thin-film encapsulation layer TFE may include a first inorganic encapsulation layer 310, a second inorganic encapsulation layer 330, and an organic encapsulation layer 320 disposed therebetween. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each include one or more inorganic materials selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0077] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may each be a single layer or multiple layers comprising the aforementioned materials. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may comprise the same material or different materials. The thickness of the first inorganic encapsulation layer 310 and the thickness of the second inorganic encapsulation layer 330 may be different from each other. The thickness of the first inorganic encapsulation layer 310 may be greater than the thickness of the second inorganic encapsulation layer 330. Optionally, the thickness of the second inorganic encapsulation layer 330 may be greater than the thickness of the first inorganic encapsulation layer 310, or the thickness of the first inorganic encapsulation layer 310 and the thickness of the second inorganic encapsulation layer 330 may be the same as each other.

[0078] The organic encapsulation layer 320 may include monomeric or polymeric materials. Polymeric materials may include acrylic resins, epoxy resins, polyimides, polyethylene, etc. According to some embodiments, the organic encapsulation layer 320 may include acrylates.

[0079] The barrier 200 may be located in the peripheral region PA of the substrate 100. According to some embodiments, the barrier 200 may include a portion of a first organic insulating layer 104, a portion 230 of a second organic insulating layer 105, a portion 220 of a pixel defining layer 106, and a portion 210 of a spacer 80, but is not limited thereto according to embodiments of the present disclosure.

[0080] The barrier wall 200 can be arranged to surround the display area DA and can prevent or reduce the overflow of the organic encapsulation layer 320 of the thin-film encapsulation layer TFE to the outside of the substrate 100. The organic encapsulation layer 320 can contact the inner surface of the barrier wall 200 facing the display area DA. The contact between the organic encapsulation layer 320 and the inner surface of the barrier wall 200 can be understood as such that the first inorganic encapsulation layer 310 is located between the organic encapsulation layer 320 and the barrier wall 200 and the organic encapsulation layer 320 is in contact with the first inorganic encapsulation layer 310.

[0081] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may be disposed on the barrier wall 200 and may extend to the edge side of the substrate 100. However, in some cases, the barrier wall 200 may include multiple barrier walls.

[0082] The input sensing layer 400 may be located on the pixel electrode 150. Specifically, the input sensing layer 400 may be located on the thin-film encapsulation layer TFE. The input sensing layer 400 may have a multilayer structure. The input sensing layer 400 may include sensing electrodes, sensing signal lines (traces) connected to the sensing electrodes, and at least one insulating layer. The input sensing layer 400 may sense external input, for example, by a capacitive method. As described above, the operation of the input sensing layer 400 is not particularly limited, and in some embodiments, the input sensing layer 400 may sense external input by an electromagnetic induction method or a pressure sensing method.

[0083] The input sensing layer 400 may include a first insulating layer 410, an organic insulating layer 420, a second insulating layer 430, and a touch conductive layer MTL. The touch conductive layer MTL may include a first touch conductive layer MTL1 and a second touch conductive layer MTL2.

[0084] The first insulating layer 410 can be directly located on the thin-film encapsulation layer TFE. The first insulating layer 410 can include inorganic or organic materials and can be configured as a single layer or multiple layers. Organic materials can include at least one material selected from the group consisting of acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, and perylene resins. Inorganic materials can include materials selected from SiN... x Aluminum nitride (AlN), zirconium nitride (ZrN), titanium nitride (TiN), hafnium nitride (HfN), tantalum nitride (TaN), silicon oxide (SiO) y It is at least one material from the group consisting of Al2O3, TiO2, tin oxide (SnO2), cerium oxide (CeO2) and SiON.

[0085] The first insulating layer 410 can prevent or reduce damage to the thin-film encapsulation layer TFE and can be used to block interference signals that may be generated during the driving of the input sensing layer 400.

[0086] For example, both the first touch conductive layer MTL1 and the second touch conductive layer MTL2 can have a single-layer structure or a stacked multilayer structure. The single-layer conductive layer can include a metal layer or a transparent conductive layer. The metal layer can include Mo, Ag, Ti, Cu, Al, and their alloys. The transparent conductive layer can include transparent conductive oxides such as ITO, IZO, zinc oxide (ZnO), and indium tin zinc oxide (ITZO). Furthermore, the transparent conductive layer can include conductive polymers (such as PEDOT), metal nanowires, graphene, etc.

[0087] The conductive layer in a multilayer structure may include multiple metal layers. The multilayer metal layers may have a three-layer structure, such as Ti / Al / Ti. The conductive layer in a multilayer structure may include at least one metal layer and at least one transparent conductive layer.

[0088] The first touch conductive layer MTL1 and the second touch conductive layer MTL2 may each include multiple patterns. It is understood that the first touch conductive layer MTL1 includes a first conductive pattern, and the second touch conductive layer MTL2 includes a second conductive pattern. The first and second conductive patterns can form sensing electrodes.

[0089] The first touch conductive layer MTL1 and the second touch conductive layer MTL2 can be electrically connected to each other through contact holes. According to some embodiments, the first touch conductive layer MTL1 and the second touch conductive layer MTL2 can have a mesh structure, allowing light emitted from the display element to pass through it. In this configuration, the first touch conductive layer MTL1 and the second touch conductive layer MTL2 can be arranged not to overlap with the emitting region.

[0090] The organic insulating layer 420 may include organic materials. The organic materials may include at least one material selected from the group consisting of acrylic resins, methacrylic resins, polyisoprene, vinyl resins, epoxy resins, urethane resins, cellulose resins, and perylene resins. The organic insulating layer 420 may also include inorganic materials. The inorganic materials may include materials selected from SiN... x , AlN, ZrN, TiN, HfN, TaN, SiO y At least one material from the group consisting of Al2O3, TiO2, SnO2, CeO2 and SiON.

[0091] The second insulating layer 430 may be located on the second touch conductive layer MTL2. The second insulating layer 430 may have a single-layer structure or a multi-layer structure. The second insulating layer 430 may include organic materials, inorganic materials, or composite materials. Inorganic materials may include those selected from SiN. x , AlN, ZrN, TiN, HfN, TaN, SiO y The organic material may include at least one material selected from the group consisting of Al2O3, TiO2, SnO2, CeO2, and SiON. The organic material may include at least one material selected from the group consisting of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, and perylene resin. The first insulating layer 410 and the organic insulating layer 420 may completely cover the display area DA and may extend toward the peripheral area PA to cover at least a portion of the peripheral area PA.

[0092] In the following description, the thin-film transistor TFT, the second conductive layer 140, the pixel electrode 150, the intermediate layer 160, the counter electrode 170, the thin-film encapsulation layer TFE, and the input sensing layer 400 arranged in the display area DA of the substrate 100 are referred to as the display portion DPR.

[0093] Optical functional layers, etc., used to relatively improve the light extraction efficiency of display elements, can be located on the input sensing layer 400.

[0094] Figure 3 This is a schematic plan view of a portion of an input sensing layer 400 according to some embodiments.

[0095] exist Figure 3 The image shows only the driving electrode TE, sensing electrode RE, first sensing signal line TSL1, second sensing signal line TSL2, first input sensing pad TP1, second input sensing pad TP2, and metal patterns 510, 520, 530, and 540 included in the first touch conductive layer MTL1 and the second touch conductive layer MTL2 of the input sensing layer 400.

[0096] Reference Figure 2 and Figure 3 The input sensing layer 400 may include a touch sensing area TSA for sensing user touch and a touch peripheral area TPA disposed around the touch sensing area TSA. The touch sensing area TSA may be superimposed on the display area DA of the substrate 100, and the touch peripheral area TPA may be superimposed on the peripheral area PA of the substrate 100.

[0097] Both the driving electrode TE and the sensing electrode RE can have a rhomboid planar shape, but embodiments according to this disclosure are not limited to this. Figure 3 For ease of illustration, although shown as a planar shape with a rhomboid shape, the driving electrode TE, sensing electrode RE, first touch connection electrode BE1, and second touch connection electrode BE2 can be formed in a mesh or grid structure in the planar view. The sensing electrode RE can be arranged in a first direction (e.g., the x-axis direction) and can be electrically connected to each other. The driving electrode TE can be arranged in a second direction (e.g., the y-axis direction) intersecting the first direction (e.g., the x-axis direction) and can be electrically connected to each other. The driving electrode TE and sensing electrode RE can be spaced apart from each other. The driving electrode TE can be arranged parallel to each other in the second direction (e.g., the y-axis direction). In the intersection region of the sensing electrode RE and the driving electrode TE, driving electrodes TE adjacent to each other in the second direction (e.g., the y-axis direction) can be connected to each other via the first touch connection electrode BE1, and sensing electrodes RE adjacent to each other in the first direction (e.g., the x-axis direction) can be connected to each other via the second touch connection electrode BE2.

[0098] The first sensing signal line TSL1 and the second sensing signal line TSL2 can be arranged in the touch peripheral area TPA. The driving electrode TE of the touch sensing area TSA can be connected to the first sensing signal line TSL1. The first sensing signal line TSL1 can be connected to the first input sensing pad TP1.

[0099] The sensing electrode RE located at one end of the sensing electrode RE can be connected to the second sensing signal line TSL2 and the second input sensing pad TP2.

[0100] Some of the first sensing signal lines TSL1 and the second sensing signal lines TSL2 may be grounded wirings that are not connected to the drive electrode TE and the sensing electrode RE.

[0101] Metal patterns 510, 520, 530, and 540 may be arranged outside the first sensing signal line TSL1 and the second sensing signal line TSL2. Metal patterns 510, 520, 530, and 540 may include metal islands (or metal isolation areas) separate from the first sensing signal line TSL1 and the second sensing signal line TSL2, and may be electrically insulated from other components.

[0102] exist Figure 3 In this embodiment, the first metal pattern 510 and the fourth metal pattern 540 are arranged facing each other on the upper side of the touch peripheral area TPA, with the touch sensing area TSA between the first metal pattern 510 and the fourth metal pattern 540. The second metal pattern 520 and the third metal pattern 530 are arranged facing each other on the lower side of the touch peripheral area TPA, with the touch sensing area TSA between the second metal pattern 520 and the third metal pattern 530. However, the embodiments according to this disclosure are not limited to this. As described above, some of the metal patterns 510, 520, 530, and 540 may be provided or omitted.

[0103] According to some embodiments, the driving electrode TE, the sensing electrode RE, the second touch connection electrode BE2, and the metal patterns 510, 520, 530, and 540 can be configured as the second touch conductive layer MTL2, and the first touch connection electrode BE1 can be configured as the first touch conductive layer MTL1. In other words, the metal patterns 510, 520, 530, and 540 can include the same material as the driving electrode TE, the sensing electrode RE, and the second touch connection electrode BE2. In this configuration, the expression "A and B include the same material" in the specification means "A and B are formed together by the same process".

[0104] According to some embodiments, the driving electrode TE, the sensing electrode RE, and the second touch connection electrode BE2 can be configured as a first touch conductive layer MTL1, and the first touch connection electrode BE1 and the metal patterns 510, 520, 530, and 540 can be configured as the second touch conductive layer MTL2. In other words, the metal patterns 510, 520, 530, and 540 can include the same material as the first touch connection electrode BE1.

[0105] Figure 4 This is a plan view of a pad PD according to some embodiments. Figure 5 It is according to some embodiments along Figure 4 The schematic cross-sectional view of the pad PD cut off by line A-A' shown. Figure 6It is according to some embodiments along Figure 4 The schematic cross-sectional view of the pad PD cut off by line B-B' shown.

[0106] Figures 4 to 6 Can be applied to Figure 1 All or in the pad PD Figure 1 At least some of the pads in the PD.

[0107] For ease of explanation, Figure 4 The upper pad layer P5 and the second pad insulation layer PIL2 are not shown in the diagram.

[0108] Reference Figures 4 to 6 The pad PD may include a first conductive pad layer P1, a first pad insulating layer PIL1, a second conductive pad layer P2, a third conductive pad layer P3, a second pad insulating layer PIL2, a support pad layer P4, and an upper pad layer P5.

[0109] The first conductive pad layer P1 may be located on the substrate 100. The first conductive pad layer P1, serving as the bottommost layer of the pad PD, may include a conductive material. The first conductive pad layer P1 may be formed... Figure 4 The shape of the pad PD in the plan view.

[0110] The first conductive pad layer P1 can be connected to the gate layer 120 (see...). Figure 2 The first conductive pad layer P1 and the gate layer 120 are arranged in the same layer and may contain the same material. The first conductive pad layer P1 may have the same layer structure as the gate layer 120. The first conductive pad layer P1 may be configured as a body.

[0111] The first insulating layer PIL1 may be located on the first conductive pad layer P1. The first insulating layer PIL1 may cover the first conductive pad layer P1. The first insulating layer PIL1 may be connected to the interlayer insulating film 103 (see...). Figure 2 ) are arranged on the same layer and may include interlayer insulating film 103 (see Figure 2 The first pad insulating layer PIL1 may comprise the same material as the interlayer insulating film 103 (see...). Figure 2 The first pad insulating layer PIL1 can have the same layer structure as the interlayer insulating film 103 (see...). Figure 2 They are formed in the same process.

[0112] The first pad insulating layer PIL1 may include a first pad opening OPP1. The first pad opening OPP1 may include a plurality of first pad openings. The first pad openings OPP1 may be spaced apart from each other in a second direction (e.g., the y-axis direction). The first pad openings OPP1 may be stacked with the first conductive pad layer P1. The first pad openings OPP1 may expose at least a portion of the first conductive pad layer P1.

[0113] The second conductive pad layer P2 can be located on the first pad insulating layer PIL1. The second conductive pad layer P2 can be connected to the first conductive layer 130 (see...). Figure 2 ) are arranged on the same layer and may include the first conductive layer 130 (see Figure 2 The second conductive pad P2 may have the same material as the first conductive layer 130 (see...). Figure 2 The second conductive pad layer P2 can have the same layer structure as the first conductive layer 130 (see...). Figure 2 They are formed in the same process. The second conductive pad layer P2 can be integrally formed as a single body.

[0114] The second conductive pad P2 can be electrically connected to the first conductive pad P1. In a plan view, the second conductive pad P2 can be stacked with the first conductive pad P1. The second conductive pad P2 can contact the first conductive pad P1 through the first pad opening OPP1 of the first pad insulating layer PIL1.

[0115] The third conductive pad P3 can be located on the second conductive pad P2, and the third conductive pad P3 can be connected to the second conductive layer 140 (see...). Figure 2 Arranged on the same layer and may include a second conductive layer 140 (see...) Figure 2 The third conductive pad P3 may have the same material as the second conductive layer 140 (see...). Figure 2 The third conductive pad layer P3 can have the same layer structure as the second conductive layer 140 (see...). Figure 2 They are formed in the same process. The third conductive pad layer P3 can be integrally set as a single body.

[0116] The third conductive pad P3 can be electrically connected to the second conductive pad P2. The third conductive pad P3 can be stacked with the second conductive pad P2 in a plan view. The third conductive pad P3 can be in contact with the second conductive pad P2.

[0117] The second insulating layer PIL2 may be located on the first insulating layer PIL1. The second insulating layer PIL2 may be located on the third conductive pad layer P3 and may cover the third conductive pad layer P3. Specifically, the second insulating layer PIL2 may cover at least a portion of the third conductive pad layer P3. The second insulating layer PIL2 may cover at least a portion of the side surface and the top surface of the third conductive pad layer P3.

[0118] The second insulating layer PIL2 can be combined with the second organic insulating layer 105 (see...). Figure 2 ) are arranged in the same layer and may include a second organic insulating layer 105 (see Figure 2 The second pad insulating layer PIL2 may have the same material as the second organic insulating layer 105 (see...). Figure 2The second pad insulating layer PIL2 can have the same layer structure as the second organic insulating layer 105 (see...). Figure 2 They are formed in the same process.

[0119] The second pad insulating layer PIL2 may include a second pad opening OPP2. The second pad opening OPP2 may be stacked with the third conductive pad layer P3. The second pad opening OPP2 may expose at least a portion of the third conductive pad layer P3.

[0120] The support pad layer P4 can be located on the substrate 100. Specifically, the support pad layer P4 can be located on the third conductive pad layer P3. The first conductive pad layer P1 can be disposed between the substrate 100 and the support pad layer P4. The second conductive pad layer P2 can be disposed between the first conductive pad layer P1 and the support pad layer P4. The third conductive pad layer P3 can be disposed between the second conductive pad layer P2 and the support pad layer P4.

[0121] The support pad P4 can be used with the pixel electrode 150 (see...) Figure 2 ) are arranged on the same layer and may include pixel electrodes 150 (see Figure 2 The support pad layer P4 can have the same material as the pixel electrode 150 (see...). Figure 2 The same layer structure as the pixel electrode 150 (see [link]). The support pad layer P4 can be connected to the pixel electrode 150 (see [link]). Figure 2 They are formed in the same process. The support pad layer P4 can be integrally set as a single body.

[0122] The support pad layer P4 can be electrically connected to the third conductive pad layer P3. The support pad layer P4 can be stacked with the third conductive pad layer P3 in a plan view. The support pad layer P4 can be in contact with the third conductive pad layer P3. At least a portion of the support pad layer P4 can be accommodated in the second pad opening OPP2 of the second pad insulating layer PIL2. The support pad layer P4 can be spaced apart from the second pad insulating layer PIL2.

[0123] The polymer pad PO may be located on the support pad layer P4. The polymer pad PO may be stacked with the support pad layer P4 in a plan view. The support pad layer P4 may support the polymer pad PO. The polymer pad PO may form protrusions, and the polymer pad PO may protrude in a direction away from the substrate 100 (e.g., the z-axis direction).

[0124] Polymer pads (PO) can include polymeric materials. For example, polymeric materials can include acrylic resins, epoxy resins, polyimides, polyethylene, etc.

[0125] The material forming the polymer pad PO can be an insulating material and does not have to be a metallic material that is conductive. The polymer pad PO can have properties different from wiring or electrodes. Electrical signals may not be transmitted via the polymer pad PO, but rather via the signal pad SPD described below (see [link to SPD]). Figure 1 Direct contact with the upper padding layer P5 for transmission.

[0126] The polymer pads PO may include multiple polymer pads. The polymer pads PO may be spaced apart from each other in a second direction (e.g., the y-axis direction). In a plan view, the polymer pads PO may be evenly arranged between the first pad openings OPP1.

[0127] The upper pad P5 can be located on the polymer pad PO. The upper pad P5 can cover the upper surface and side surfaces of the polymer pad PO. The upper pad P5 can cover the upper surface of the support pad P4 that is not covered by the polymer pad PO. The upper pad P5 can cover the upper surface of the third conductive pad P3 that is not covered by the support pad P4 and the second pad insulating layer PIL2.

[0128] The upper pad layer P5 can be connected to the touch conductive layer MTL (see...) Figure 2 ) are arranged on the same layer and may include a touch conductive layer MTL (see Figure 2 The upper pad P5 can have the same material as the touch conductive layer MTL (see...). Figure 2 The same layer structure as the top pad P5. The top pad P5 can be connected to the touch conductive layer MTL (see...). Figure 2 They are formed in the same process. The upper padding layer P5 can be integrally set as a main body.

[0129] In detail, the upper pad layer P5 can be connected to the second touch conductive layer MTL2 (see... Figure 2 ) are arranged on the same layer and may include a second touch conductive layer MTL2 (see Figure 2 The upper pad layer P5 may have the same material as the second touch conductive layer MTL2 (see...). Figure 2 The same layer structure as the second touch conductive layer MTL2 (see [link]). The upper pad layer P5 can be connected to the second touch conductive layer MTL2 (see [link]). Figure 2 They are formed in the same process.

[0130] Figure 7 This is a schematic cross-sectional view of a pad PD and a signal pad SPD according to some embodiments.

[0131] exist Figure 7 middle, Figure 1 and Figure 5 The same reference numerals in the figures indicate the same elements, and some redundant descriptions may be omitted.

[0132] Reference Figure 7The pad PD can protrude upwards through the polymer pad PO, and the downward-protruding signal pad SPD and the upward-protruding pad PD can be in direct contact with each other. The lower surface of the signal pad SPD can be formed into a concave shape corresponding to the protruding shape of the pad PD. The concave shape of the lower surface of the signal pad SPD can correspond to the protruding shape of the upper surface of the pad PD, and therefore, the signal pad SPD and the pad PD can be in precise contact with each other at the desired location.

[0133] Reference Figure 4 and Figure 7 One conductive pad layer of the pad PD can be located on the polymer pad PO. In other words, only the upper pad layer P5 of the pad PD can be located on the polymer pad PO. Therefore, the contact area between the upper pad layer P5 and the signal pad SPD can be reduced. Therefore, the area of ​​the concave portion formed in the signal pad SPD can also be reduced. Therefore, the size of the pad PD can be reduced. Furthermore, the pad PD and the signal pad SPD can make precise contact with each other at the desired location.

[0134] The support layer P4 can have a higher hardness than each of the first conductive layer P1, the second conductive layer P2, and the third conductive layer P3. Furthermore, the support layer P4 can have a wider width than the polymer pad PO. Because the support layer P4 supports the polymer pad PO, deformation of the first conductive layer P1, the second conductive layer P2, and the third conductive layer P3 disposed beneath the polymer pad PO can be reduced during the process of pressing the pad PD and the signal pad SPD to bring them into close contact with each other. Therefore, the pad PD and the signal pad SPD can make precise contact with each other at the desired location.

[0135] Figure 8 This is a schematic plan view of an example of a pad PD according to some embodiments.

[0136] exist Figure 8 middle, Figure 4 The same reference numerals in the figures indicate the same elements, and some redundant descriptions may be omitted.

[0137] Reference Figure 8 The polymer pad PO and the support pad layer P4 can each include multiple polymer pads and multiple support pad layers.

[0138] The polymer pads PO may be spaced apart from each other in a second direction (e.g., the y-axis direction). The support pad layers P4 may also be spaced apart from each other in a second direction (e.g., the y-axis direction). In a plan view, each of the support pad layers P4 may be stacked with a corresponding polymer pad PO. In other words, one support pad layer P4 may be stacked with one polymer pad PO. In a plan view, the support pad layers P4 may be evenly arranged between the first pad openings OPP1.

[0139] Figure 9 It is according to some embodiments along Figure 4 A schematic cross-sectional view of the pad PD cut off by line A-A'.

[0140] exist Figure 9 middle, Figure 5 The same reference numerals in the figures indicate the same elements, and some redundant descriptions may be omitted.

[0141] Reference Figure 9 The pad PD may include a first conductive pad layer P1, a first pad insulating layer PIL1, a second conductive pad layer P2, a second pad insulating layer PIL2, a support pad layer P4, and an upper pad layer P5. In other words, the pad PD may not include a reference layer. Figure 5 The third conductive pad layer P3 is described.

[0142] The first conductive pad layer P1 may be located on the substrate 100. The first conductive pad layer P1 may include the gate layer 120 (see...). Figure 2 (The same material.)

[0143] The first pad insulating layer PIL1 may be located on the first conductive pad layer P1. The first pad insulating layer PIL1 may include an interlayer insulating film 103 (see...). Figure 2 (The same material.)

[0144] The second conductive pad layer P2 may be located on the first pad insulating layer PIL1. The second conductive pad layer P2 may include components adjacent to the first conductive layer 130 (see...). Figure 2 The same material. The second conductive pad layer P2 can be passed through the first pad opening OPP1 of the first pad insulating layer PIL1 (see...). Figure 4 It comes into contact with the first conductive pad layer P1.

[0145] The second pad insulating layer PIL2 may be located on the first pad insulating layer PIL1. The second pad insulating layer PIL2 may be located on the second conductive pad layer P2 and may cover the second conductive pad layer P2. The second pad insulating layer PIL2 may include components related to the second organic insulating layer 105 (see...). Figure 2 (The same material.)

[0146] The second pad insulating layer PIL2 may include a second pad opening OPP2. The second pad opening OPP2 may be stacked with the second conductive pad layer P2. The second pad opening OPP2 may expose at least a portion of the second conductive pad layer P2.

[0147] The support pad layer P4 may be located on the second conductive pad layer P2. The first conductive pad layer P1 may be disposed between the substrate 100 and the support pad layer P4. The second conductive pad layer P2 may be disposed between the first conductive pad layer P1 and the support pad layer P4. The support pad layer P4 may include the pixel electrode 150 (see...). Figure 2 (The same material.)

[0148] The support pad layer P4 can be electrically connected to the second conductive pad layer P2. The support pad layer P4 can be stacked with the second conductive pad layer P2 in a plan view. The support pad layer P4 can be in contact with the second conductive pad layer P2. At least a portion of the support pad layer P4 can be accommodated in the second pad opening OPP2 of the second pad insulating layer PIL2. The support pad layer P4 can be spaced apart from the second pad insulating layer PIL2.

[0149] The polymer pad PO may be located on the support pad layer P4. In a plan view, the polymer pad PO may be stacked with the support pad layer P4. The support pad layer P4 may support the polymer pad PO. The polymer pad PO may form a protrusion, and the polymer pad PO may protrude in a direction away from the substrate 100 (e.g., the z-axis direction).

[0150] The upper pad layer P5 may be located on the polymer pad PO. The upper pad layer P5 may cover the upper and side surfaces of the polymer pad PO. The upper pad layer P5 may cover the upper surface of the support pad layer P4 that is not covered by the polymer pad PO. The upper pad layer P5 may cover the upper surface of the second conductive pad layer P2 that is not covered by the support pad layer P4 and the second pad insulating layer PIL2. The upper pad layer P5 may include a touch conductive layer MTL (see...). Figure 2 The same material as the second touch conductive layer MTL2 (see...). Specifically, the upper pad layer P5 may include the same material as the second touch conductive layer MTL2 (see...). Figure 2 (The same material.)

[0151] Figure 10 It is according to some embodiments along Figure 4 A schematic cross-sectional view of the pad PD cut off by line A-A'.

[0152] exist Figure 10 middle, Figure 5 The same reference numerals in the figures indicate the same elements, and some redundant descriptions may be omitted.

[0153] Reference Figure 10 The pad PD may include a first conductive pad layer P1, a first pad insulating layer PIL1, a third conductive pad layer P3, a second pad insulating layer PIL2, a support pad layer P4, and an upper pad layer P5. In other words, the pad PD may not include a reference layer. Figure 5 The second conductive pad layer P2 is described.

[0154] The first conductive pad layer P1 may be located on the substrate 100. The first conductive pad layer P1 may include the gate layer 120 (see...). Figure 2 (The same material.)

[0155] The first pad insulating layer PIL1 may be located on the first conductive pad layer P1. The first pad insulating layer PIL1 may include an interlayer insulating film 103 (see...). Figure 2(The same material.)

[0156] The third conductive pad layer P3 may be located on the first pad insulating layer PIL1. The third conductive pad layer P3 may include the second conductive layer 140 (see...). Figure 2 The same material. The third conductive pad layer P3 can be passed through the first pad opening OPP1 of the first pad insulating layer PIL1 (see...). Figure 4 It comes into contact with the first conductive pad layer P1.

[0157] The second pad insulating layer PIL2 may be located on the first pad insulating layer PIL1. The second pad insulating layer PIL2 may be located on the third conductive pad layer P3 and may cover the third conductive pad layer P3. The second pad insulating layer PIL2 may include components related to the second organic insulating layer 105 (see...). Figure 2 (The same material.)

[0158] The second pad insulating layer PIL2 may include a second pad opening OPP2. The second pad opening OPP2 may be stacked with the third conductive pad layer P3. The second pad opening OPP2 may expose at least a portion of the third conductive pad layer P3.

[0159] The support pad layer P4 may be located on the third conductive pad layer P3. The first conductive pad layer P1 may be disposed between the substrate 100 and the support pad layer P4. The third conductive pad layer P3 may be disposed between the first conductive pad layer P1 and the support pad layer P4. The support pad layer P4 may include the pixel electrode 150 (see...). Figure 2 (The same material.)

[0160] The support pad layer P4 can be electrically connected to the third conductive pad layer P3. The support pad layer P4 can be stacked with the third conductive pad layer P3 in a plan view. The support pad layer P4 can be in contact with the third conductive pad layer P3. At least a portion of the support pad layer P4 can be accommodated in the second pad opening OPP2 of the second pad insulating layer PIL2. The support pad layer P4 can be spaced apart from the second pad insulating layer PIL2.

[0161] The polymer pad PO may be located on the support pad layer P4. In a plan view, the polymer pad PO may be stacked with the support pad layer P4. The support pad layer P4 may support the polymer pad PO. The polymer pad PO may form a protrusion, and the polymer pad PO may protrude in a direction away from the substrate 100 (e.g., the z-axis direction).

[0162] The upper pad layer P5 may be located on the polymer pad PO. The upper pad layer P5 may cover the upper and side surfaces of the polymer pad PO. The upper pad layer P5 may cover the upper surface of the support pad layer P4 that is not covered by the polymer pad PO. The upper pad layer P5 may cover the upper surface of the third conductive pad layer P3 that is not covered by the support pad layer P4 and the second pad insulating layer PIL2. The upper pad layer P5 may include a touch conductive layer MTL (see...). Figure 2 The same material as the second touch conductive layer MTL2 (see...). Specifically, the upper pad layer P5 may include the same material as the second touch conductive layer MTL2 (see...). Figure 2 (The same material.)

[0163] Figure 11 It is according to some embodiments along Figure 4 A schematic cross-sectional view of the pad PD cut off by line A-A'.

[0164] exist Figure 11 middle, Figure 5 The same reference numerals in the figures indicate the same elements, and some redundant descriptions may be omitted.

[0165] Reference Figure 11 The pad PD may include a first pad insulating layer PIL1, a second conductive pad layer P2, a third conductive pad layer P3, a second pad insulating layer PIL2, a support pad layer P4, and an upper pad layer P5. In other words, the pad PD may not include a reference layer. Figure 5 The first conductive pad layer P1 is described.

[0166] The first pad insulating layer PIL1 may be the bottom layer of the pad PD. The first pad insulating layer PIL1 may be located on the substrate 100. The first pad insulating layer PIL1 may cover the substrate 100. The first pad insulating layer PIL1 may include an interlayer insulating film 103 (see...) Figure 2 (The same material.)

[0167] The second conductive pad layer P2 may be located on the first pad insulating layer PIL1. The second conductive pad layer P2 may include components adjacent to the first conductive layer 130 (see...). Figure 2 The same material. The second conductive pad layer P2 can be electrically connected to the gate layer 120 (see...). Figure 2 According to some embodiments, the second conductive pad layer P2 can be formed by the first pad insulating layer PIL1 and / or the interlayer insulating film 103 (see...). Figure 2 The contact holes in the gate layer 120 (see) Figure 2 )touch.

[0168] The third conductive pad layer P3 may be located on the second conductive pad layer P2. The third conductive pad layer P3 may include components that are connected to the second conductive layer 140 (see...). Figure 2 The same material. The third conductive pad P3 can be electrically connected to the second conductive pad P2.

[0169] The second pad insulating layer PIL2 may be located on the first pad insulating layer PIL1. The second pad insulating layer PIL2 may be located on the third conductive pad layer P3 and may cover the third conductive pad layer P3. The second pad insulating layer PIL2 may include components related to the second organic insulating layer 105 (see...). Figure 2The same material. The second pad insulation layer PIL2 may include a second pad opening OPP2.

[0170] The support pad layer P4 may be located on the third conductive pad layer P3. The support pad layer P4 may include components associated with the pixel electrode 150 (see [link to relevant documentation]). Figure 2 The same material as the third conductive pad layer P3. The support pad layer P4 may be electrically connected to the third conductive pad layer P3. At least a portion of the support pad layer P4 may be accommodated in the second pad opening OPP2 of the second pad insulating layer PIL2. The polymer pad PO may be located on the support pad layer P4. The upper pad layer P5 may be located on the polymer pad PO. The upper pad layer P5 may include materials similar to the touch conductive layer MTL (see...). Figure 2 The same material as the second touch conductive layer MTL2 (see...). Specifically, the upper pad layer P5 may include the same material as the second touch conductive layer MTL2 (see...). Figure 2 (The same material.)

[0171] Figure 12 It is according to some embodiments along Figure 4 A schematic cross-sectional view of the pad PD cut off by line A-A'.

[0172] exist Figure 12 middle, Figure 5 The same reference numerals in the figures indicate the same elements, and some redundant descriptions may be omitted.

[0173] Reference Figure 12 The pad PD may include a first pad insulating layer PIL1, a second conductive pad layer P2, a second pad insulating layer PIL2, a support pad layer P4, and an upper pad layer P5. In other words, the pad PD may not include a reference layer. Figure 5 The first conductive pad layer P1 and the third conductive pad layer P3 are described.

[0174] The first pad insulating layer PIL1 may be the bottom layer of the pad PD. The first pad insulating layer PIL1 may be located on the substrate 100. The first pad insulating layer PIL1 may cover the substrate 100. The first pad insulating layer PIL1 may include an interlayer insulating film 103 (see...) Figure 2 (The same material.)

[0175] The second conductive pad layer P2 may be located on the first pad insulating layer PIL1. The second conductive pad layer P2 may include components adjacent to the first conductive layer 130 (see...). Figure 2 The same material. The second conductive pad layer P2 can be electrically connected to the gate layer 120 (see...). Figure 2 According to some embodiments, the second conductive pad layer P2 can be formed by the first pad insulating layer PIL1 and / or the interlayer insulating film 103 (see...). Figure 2 The contact holes in the gate layer 120 (see) Figure 2 )touch.

[0176] The second pad insulating layer PIL2 may be located on the first pad insulating layer PIL1. The second pad insulating layer PIL2 may be located on the second conductive pad layer P2 and may cover the second conductive pad layer P2. The second pad insulating layer PIL2 may include components related to the second organic insulating layer 105 (see...). Figure 2 The same material. The second pad insulation layer PIL2 may include a second pad opening OPP2.

[0177] The support pad layer P4 may be located on the second conductive pad layer P2. The support pad layer P4 may include components associated with the pixel electrode 150 (see...). Figure 2 The same material as the second conductive pad layer P2. The support pad layer P4 may be electrically connected to the second conductive pad layer P2. At least a portion of the support pad layer P4 may be accommodated in the second pad opening OPP2 of the second pad insulating layer PIL2. The polymer pad PO may be located on the support pad layer P4. The upper pad layer P5 may be located on the polymer pad PO. The upper pad layer P5 may include materials similar to the touch conductive layer MTL (see...). Figure 2 The same material as the second touch conductive layer MTL2 (see...). Specifically, the upper pad layer P5 may include the same material as the second touch conductive layer MTL2 (see...). Figure 2 (The same material.)

[0178] Figure 13 It is according to some embodiments along Figure 4 A schematic cross-sectional view of the pad PD cut off by line A-A'.

[0179] exist Figure 13 middle, Figure 5 The same reference numerals in the figures indicate the same elements, and some redundant descriptions may be omitted.

[0180] Reference Figure 13 The pad PD may include a first pad insulating layer PIL1, a third conductive pad layer P3, a second pad insulating layer PIL2, a support pad layer P4, and an upper pad layer P5. In other words, the pad PD may not include a reference layer. Figure 5 The first conductive pad layer P1 and the second conductive pad layer P2 are described.

[0181] The first pad insulating layer PIL1 may be the bottom layer of the pad PD. The first pad insulating layer PIL1 may be located on the substrate 100. The first pad insulating layer PIL1 may cover the substrate 100. The first pad insulating layer PIL1 may include an interlayer insulating film 103 (see...) Figure 2 (The same material.)

[0182] The third conductive pad layer P3 may be located on the first pad insulating layer PIL1. The third conductive pad layer P3 may include the second conductive layer 140 (see...). Figure 2 The same material. The third conductive pad layer P3 can be electrically connected to the gate layer 120 (see...). Figure 2According to some embodiments, the third conductive pad layer P3 can be formed by the first pad insulating layer PIL1 and / or the interlayer insulating film 103 (see...). Figure 2 The contact holes in the gate layer 120 (see) Figure 2 )touch.

[0183] The second pad insulating layer PIL2 may be located on the first pad insulating layer PIL1. The second pad insulating layer PIL2 may be located on the third conductive pad layer P3 and may cover the third conductive pad layer P3. The second pad insulating layer PIL2 may include components related to the second organic insulating layer 105 (see...). Figure 2 The same material. The second pad insulation layer PIL2 may include a second pad opening OPP2.

[0184] The support pad layer P4 may be located on the third conductive pad layer P3. The support pad layer P4 may include components associated with the pixel electrode 150 (see [link to relevant documentation]). Figure 2 The same material as the third conductive pad layer P3. The support pad layer P4 may be electrically connected to the third conductive pad layer P3. At least a portion of the support pad layer P4 may be accommodated in the second pad opening OPP2 of the second pad insulating layer PIL2. The polymer pad PO may be located on the support pad layer P4. The upper pad layer P5 may be located on the polymer pad PO. The upper pad layer P5 may include materials similar to the touch conductive layer MTL (see...). Figure 2 The same material as the second touch conductive layer MTL2 (see...). Specifically, the upper pad layer P5 may include the same material as the second touch conductive layer MTL2 (see...). Figure 2 (The same material.)

[0185] According to some embodiments of this disclosure, the visibility, durability, and quality of the display device can be relatively improved.

[0186] The features of the embodiments according to this disclosure are not limited to those described above, and those skilled in the art to which this disclosure pertains can clearly understand from the description various other features not described in the specification.

[0187] It should be understood that the embodiments described herein are to be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the claims and their equivalents.

Claims

1. A display device, the display device comprising: A display panel includes a base comprising a display area and a pad area, a display portion in the display area of ​​the base, and a pad in the pad area of ​​the base; as well as The connection circuit board includes a signal pad electrically connected to the pad. The display portion includes: a thin-film transistor on the substrate, comprising a semiconductor layer, a gate layer on the semiconductor layer, and a first conductive layer electrically connected to the semiconductor layer; a second conductive layer on the thin-film transistor and electrically connected to the first conductive layer; a pixel electrode on the second conductive layer and electrically connected to the second conductive layer; and an input sensing layer on the pixel electrode, comprising a touch conductive layer and an organic insulating layer. The pad includes: a support pad layer on the substrate and comprising the same material as the pixel electrode; a polymer pad on the support pad layer; and an upper pad layer on the polymer pad and comprising the same material as the touch conductive layer.

2. The display device according to claim 1, wherein, In the plan view, the polymer pad is stacked with the support pad layer, and The support pad layer supports the polymer pad.

3. The display device according to claim 1, wherein, The upper pad layer covers the polymer pad.

4. The display device according to claim 1, wherein, The pad further includes a first conductive pad layer between the substrate and the support pad layer, and comprises the same material as the gate layer.

5. The display device according to claim 4, wherein, The pad further includes a second conductive pad layer, which is located between the first conductive pad layer and the support pad layer, contacts the first conductive pad layer, and comprises the same material as the first conductive layer.

6. The display device according to claim 5, wherein, The pad further includes a third conductive pad layer, located between the second conductive pad layer and the support pad layer, in contact with the second conductive pad layer, and comprising the same material as the second conductive layer.

7. The display device according to claim 4, wherein, The pad further includes a third conductive pad layer, located between the first conductive pad layer and the support pad layer, in contact with the first conductive pad layer, and comprising the same material as the second conductive layer.

8. The display device according to claim 1, wherein, The polymer pad and the support pad layer each comprise a plurality of polymer pads and a plurality of support pad layers, and In the plan view, each of the plurality of support pad layers is stacked with a corresponding polymer pad among the plurality of polymer pads.

9. The display device according to claim 8, wherein, The plurality of support pads are spaced apart from each other.

10. The display device according to claim 1, wherein, The signal pad contacts the upper pad layer.

11. An electronic device, the electronic device comprising a display panel and a connection circuit board electrically connected to the display panel, in, The display panel includes: The substrate includes the display area and the pad area; A thin-film transistor, in the display region of the substrate, includes a semiconductor layer, a gate layer on the semiconductor layer, and a first conductive layer electrically connected to the semiconductor layer; A second conductive layer is disposed on the thin-film transistor and is electrically connected to the first conductive layer; A pixel electrode is located on the second conductive layer and is electrically connected to the second conductive layer. An input sensing layer is provided on the pixel electrode and includes a touch conductive layer and an organic insulating layer. A support pad layer, in the pad region of the substrate, and comprising the same material as the pixel electrode; Polymer pad, on the support pad layer; and An upper pad layer, on the polymer pad, comprises the same material as the touch conductive layer.

12. The electronic device according to claim 11, wherein, The connection circuit board includes a signal pad electrically connected to the upper pad layer.

13. The electronic device according to claim 11, wherein, In the plan view, the polymer pad is stacked with the support pad layer, and The support pad layer supports the polymer pad.

14. The electronic device according to claim 11, wherein, The upper pad layer covers the polymer pad.

15. The electronic device according to claim 11, wherein, The display panel further includes a first conductive pad layer between the substrate and the support pad layer, and comprises the same material as the gate layer.

16. The electronic device according to claim 15, wherein, The display panel further includes a second conductive pad layer, which is located between the first conductive pad layer and the support pad layer, contacts the first conductive pad layer, and comprises the same material as the first conductive layer.

17. The electronic device according to claim 16, wherein, The display panel further includes a third conductive pad layer, which is located between the second conductive pad layer and the support pad layer, contacts the second conductive pad layer, and comprises the same material as the second conductive layer.

18. The electronic device according to claim 15, wherein, The display panel further includes a third conductive pad layer, which is located between the first conductive pad layer and the support pad layer, contacts the first conductive pad layer, and comprises the same material as the second conductive layer.

19. The electronic device according to claim 11, wherein, The polymer pad and the support pad layer each comprise a plurality of polymer pads and a plurality of support pad layers, and In the plan view, each of the plurality of support pad layers is stacked with a corresponding polymer pad among the plurality of polymer pads.

20. The electronic device according to claim 19, wherein, The plurality of support pads are spaced apart from each other.

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