Substrate panel structure and manufacturing process

Abstract

The invention relates to a substrate panel structure and a manufacturing process. The invention discloses a substrate panel structure. The substrate panel structure comprises a plurality of sub-panels and a dielectric part, each of the sub-panels includes a plurality of substrate units. The dielectric portion is located between the sub-panels.

Description

[0001] This application is a divisional application of the invention patent application filed on August 14, 2019, with application number 201910747954.1 and invention title "Substrate Panel Structure and Manufacturing Process". Technical Field

[0002] This invention relates to a substrate panel structure and manufacturing process, and more specifically, to a substrate panel structure comprising a plurality of sub-panels, and a method for manufacturing the said substrate panel structure. Background Technology

[0003] In electronic devices, functional improvements and size reductions can be achieved by changing materials or altering structural design. Changing the materials of an electronic device requires corresponding modifications to the setup or parameters of production equipment and manufacturing methods, which is more complex and expensive than simply adjusting its structural design. Recently, one of the most effective ways to improve the functionality and reduce the size of electronic devices has been through structural designs with reduced line width / line space (L / S). Summary of the Invention

[0004] In some embodiments, according to one aspect, the substrate panel structure includes a plurality of sub-panels and dielectric portions. Each of the sub-panels includes a plurality of substrate units. The dielectric portions are located between the sub-panels.

[0005] In some embodiments, according to another aspect, the manufacturing process includes: (a) providing a plurality of intermediate panels, each intermediate panel including a circuit structure, wherein each of the intermediate panels includes a plurality of panel units, and the intermediate panels are separate and spaced apart from each other; (b) providing a dielectric material to form a plurality of first dielectric layers and dielectric portions, wherein each of the first dielectric layers is located on a corresponding one of the intermediate panels, and the dielectric portions are located between and connected to the dielectric layers; and (c) forming a plurality of redistribution layers on the first dielectric layers, wherein each of the redistribution layers is connected to a corresponding one of the circuit structures of the intermediate panels. Attached Figure Description

[0006] When with attachment Figure 1When reading this invention, one can best understand some aspects of the embodiments described in detail below. It should be noted that the various structures may not be drawn to scale, and the dimensions of the various structures may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figure 1 A top view illustrating an example of a substrate panel structure according to some embodiments of the present invention.

[0008] Figure 2 A top view illustrating an example of a substrate panel structure according to some embodiments of the present invention.

[0009] Figure 3 illustrate Figure 2 The cross-sectional view of the substrate panel structure 1 along line 3-3.

[0010] Figure 4 A cross-sectional view illustrating an example of a substrate panel structure according to some embodiments of the present invention.

[0011] Figure 5 A cross-sectional view illustrating an example of a substrate panel structure according to some embodiments of the present invention.

[0012] Figure 6 A cross-sectional view illustrating an example of a substrate panel structure according to some embodiments of the present invention.

[0013] Figure 7 A cross-sectional view illustrating an example of a substrate panel structure according to some embodiments of the present invention.

[0014] Figure 8 A cross-sectional view illustrating an example of a substrate panel structure according to some embodiments of the present invention.

[0015] Figure 9 A cross-sectional view illustrating an example of a substrate panel structure according to some embodiments of the present invention.

[0016] Figure 10 A cross-sectional view illustrating an example of a substrate panel structure according to some embodiments of the present invention.

[0017] Figure 11 A cross-sectional view illustrating an example of a substrate panel structure according to some embodiments of the present invention.

[0018] Figure 12 A cross-sectional view illustrating an example of a packaging unit according to some embodiments of the present invention.

[0019] Figure 13 A cross-sectional view illustrating an example of a packaging unit according to some embodiments of the present invention.

[0020] Figure 14A cross-sectional view illustrating an example of a packaging unit according to some embodiments of the present invention.

[0021] Figure 15 A cross-sectional view illustrating an example of a packaging unit according to some embodiments of the present invention.

[0022] Figure 16 A cross-sectional view illustrating an example of a packaging unit according to some embodiments of the present invention.

[0023] Figure 17 A cross-sectional view illustrating an example of a packaging unit according to some embodiments of the present invention.

[0024] Figure 18 A cross-sectional view illustrating an example of a packaging unit according to some embodiments of the present invention.

[0025] Figure 19 A cross-sectional view illustrating an example of a packaging unit according to some embodiments of the present invention.

[0026] Figure 20 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0027] Figure 21 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0028] Figure 22 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0029] Figure 23 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0030] Figure 24 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0031] Figure 25 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0032] Figure 26 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0033] Figure 27 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0034] Figure 28 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0035] Figure 29According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0036] Figure 30 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0037] Figure 31 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0038] Figure 32 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0039] Figure 33 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0040] Figure 34 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0041] Figure 35 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0042] Figure 36 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0043] Figure 37 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0044] Figure 38 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0045] Figure 39 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0046] Figure 40 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0047] Figure 41 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0048] Figure 42 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0049] Figure 43 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0050] Figure 44 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0051] Figure 45 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0052] Figure 46 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0053] Figure 47 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0054] Figure 48 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0055] Figure 49 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0056] Figure 50 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0057] Figure 51 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0058] Figure 52 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0059] Figure 53 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0060] Figure 54 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0061] Figure 55 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0062] Figure 56 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0063] Figure 57 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0064] Figure 58 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0065] Figure 59 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described.

[0066] Figure 60 According to some embodiments of the present invention, one or more stages of an example of a manufacturing process are described. Detailed Implementation

[0067] Throughout the drawings and detailed description, common reference numerals are used to indicate the same or similar components. Embodiments of the invention will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings.

[0068] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to reveal certain aspects of the invention. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which an additional feature may be formed or disposed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. This repetition is for the purposes of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0069] In the semiconductor-related industries, the precision of substrate panel products is challenged as the linewidth / pitch (L / S) of substrate panels gradually decreases. Manufacturing tolerances, including warpage caused by material variations and errors caused by manufacturing machines, typically occur in each individual layer of the substrate panel. For example, when a substrate panel contains three layers, the total tolerance will be the sum of the tolerances in the first, second, and third layers. In other words, as the number of layers (including the protective layer) of the substrate panel increases, the total tolerance of the substrate panel accumulates.

[0070] It is worth noting that within the same layer of the substrate panel, the tolerance, which can be expressed as the value of pattern shift, varies at different locations. The pattern shift value can be defined as the distance between the actual position of the pattern and its predetermined position. Typically, the pattern shift value is relatively small near the center of the substrate panel (e.g., the centroid) and relatively large further away from the center. The pattern shift value at a particular location is proportional to the distance between that location and the center. Therefore, the maximum value of the pattern shift occurs at the edges of the substrate panel and may increase with the size of the substrate panel. For example, in a 450 mm thick substrate panel... In a comparative substrate panel with an area of ​​450 mm and a single circuit layer having an L / S ratio of 2 μm / 2 μm, the pattern offset measured at the edge of the substrate panel is at least 3 μm to 5 μm. In addition to the pattern offset, the warpage of the substrate panel also increases as the size of the substrate panel increases. Due to the pattern offset and warpage of the substrate panel, semiconductor dies cannot be accurately mounted onto the substrate.

[0071] To address at least the aforementioned problems, embodiments of the present invention provide a substrate panel structure comprising a plurality of sub-panels. At least a portion of each of the sub-panels can be formed separately and then combined into the substrate panel structure. For example, one or more circuits of the sub-panels can be formed separately at a relatively small scale, thereby reducing the maximum pattern offset of the substrate panel structure.

[0072] Figure 1 A top view illustrating an example of a substrate structure 1' according to some embodiments of the present invention is provided. The substrate panel structure 1' includes a plurality of sub-panels 2' and dielectric portions 14' located between the sub-panels 2'. Each of the sub-panels 2' includes a plurality of substrate units 20'. The sub-panels 2' are labeled with "m". Arranged in the "n" pattern, where "m" and "n" are integers equal to or greater than 2. For example, ... Figure 1 As shown, the substrate panel structure 1' contains 2 Two sub-panels 2'. However, the number of sub-panels 2' in the substrate panel 1' can be greater than 2. 2, and “m” and “n” can be unequal to each other. Similarly, the substrate unit 20’ of sub-panel 2’ can be “o”. Arranged in the pattern "p", where "o" and "p" are integers, and at least one of "o" and "p" is greater than 1. For example, as Figure 1 As shown, each of the sub-panels 2' contains 5 Five substrate units 20'. In some embodiments, the size of each of the sub-panels 2' is less than 500 mm. 500 mm. That is, the length of each side edge of sub-panel 2' may be shorter than 500 mm, for example, shorter than 400 mm, shorter than 300 mm, or shorter than 200 mm. In some embodiments, all sub-panels 2' are known-good sub-panels.

[0073] Figure 2 A top view illustrating an example of a substrate panel structure 1 according to some embodiments of the present invention. Figure 3 Explanation along Figure 2 The image shows a cross-sectional view of substrate panel structure 1 taken along line 3-3. Similar to... Figure 1The substrate panel structure 1' shown in the diagram also includes multiple sub-panels 2 and dielectric portions 14. The dielectric portions 14 are located between and surrounding the sub-panels 2. Each sub-panel 2 includes multiple substrate units 20. Each substrate unit 20 corresponds to a packaging unit, for example... Figure 12 The package unit 7 shown in the image. However, for simplicity and clarity, Figure 2 and 3 Each of the sub-panels 2 shown contains 2 2 substrate units 20, instead of Figure 1 The 5 shown in Five substrate units 20'.

[0074] Sub-panel 2 may include a first sub-panel 2a and a second sub-panel 2b, and a gap "g" is formed between adjacent sub-panels 2 (e.g., the first sub-panel 2a and the second sub-panel 2b). Figure 2 As can be seen, two adjacent sub-panels 2 (e.g., first sub-panel 2a and second sub-panel 2b) may not be aligned with each other or may not be parallel to each other. Therefore, the gap "g" between them may have an inconsistent width. However, in other embodiments, two adjacent sub-panels 2 may be substantially parallel to each other, and the gap "g" between them may have a consistent width.

[0075] The substrate cells 20 of each of the sub-panels 2 are close to each other. For example, adjacent substrate cells 20 in the first sub-panel 2a may be physically connected to each other or separated by a cutting line or saw street. That is, the substrate cells 20 in the first sub-panel 2a may be defined by a cutting line or saw street. After mounting multiple semiconductor dies onto each of the sub-panels 2 and / or forming a package on each of the sub-panels 2, these substrate cells 20 can be separated by a singulating process along the cutting line or saw street to form multiple package units (e.g., Figure 12 The packaging unit 7 shown in the image. Figure 2 and 3 As shown, due to the gap "g" between adjacent units in sub-panel 2 (e.g., first sub-panel 2a and second sub-panel 2b), the pitch P1 between adjacent units in substrate cells 20 of the first sub-panel 2a is smaller than the pitch P2 between the closest substrate cell 20 of the first sub-panel 2a and the substrate cell 20 of the second sub-panel 2b. The "pitch" between two substrate cells 20 can refer to the distance between the center of one substrate cell 20 and the center of the other substrate cell 20.

[0076] refer toFigure 3 Each of the sub-panels 2 has a first surface 21, a second surface 22 opposite to the first surface 21, and a side surface 23 extending between the first surface 21 and the second surface 22. In some embodiments, at least a portion of the side surface 23 is an imaginary surface or an imaginary plane. The side surface 23 may be a cutting line or saw cut for separating the sub-panel 2 from the substrate panel structure 1. Figure 3 As shown, the first surface 21 is the upper surface, and the second surface 22 is the lower surface. Each of the sub-panels 2 includes a first dielectric layer 3, a redistribution layer 4, a protective layer 25, at least one solder connector 26, a circuit structure 5, and a second dielectric layer 6. Similarly, each of the substrate units 20 may include at least a portion of the first dielectric layer 3, at least a portion of the redistribution layer 4, at least a portion of the protective layer 25, at least one solder connector 26, at least a portion of the circuit structure 5, and at least a portion of the second dielectric layer 6. For illustrative purposes, Figure 2 The components of substrate unit 20 are not shown in the image.

[0077] Figure 3 A first sub-panel 2a and a second sub-panel 2b are shown that are substantially identical to each other. However, the first sub-panel 2a and the second sub-panel 2b may be different from each other. For example, the components, arrangement, material, size, and position relative to the dielectric portion 14 of the first sub-panel 2a may be different from those of the second sub-panel 2b.

[0078] The first dielectric layer 3 includes a first surface 31 and a second surface 32 opposite to the first surface 31. For example... Figure 3 As shown, the first surface 31 is the upper surface, and the second surface 32 is the lower surface. The first dielectric layer 3 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the first dielectric layer 3 may comprise, or be formed from, a cured photoimageable dielectric (PID) material, such as an epoxy resin containing a photoinitiator or polyimide (PI). The first dielectric layer 3 defines at least one via 30 that extends through the first dielectric layer 3 and is between the first surface 31 and the second surface 32. In some embodiments, the thickness of the first dielectric layer 3 may be from about 3 μm to about 20 μm, preferably from about 3 μm to about 15 μm. The material of the first dielectric layer 3 in the first sub-panel 2a may be substantially the same as the material of the dielectric layer 3 in the second sub-panel 2b. However, the thickness of the first dielectric layer 3 in the first sub-panel 2a may be substantially the same as or slightly different from the thickness of the dielectric layer 3 in the second sub-panel 2b.

[0079] The redistribution layer 4 is located on the first dielectric layer 3. The redistribution layer 4 may be located on the second surface 32 of the first dielectric layer 3 and within the via 30. The redistribution layer 4 may include a seed layer 41 located on the first dielectric layer 3 and a conductive layer 42 located on the seed layer 41. The seed layer 41 may be made of, for example, titanium or copper. In some embodiments, the seed layer 41 may include a titanium layer and a copper layer. For example, the conductive layer 42 may be made of a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 41 may be omitted, and the conductive layer 42 may directly contact the first dielectric layer 3. The redistribution layer 4 may include at least one conductive via 43 located in the via 30 of the first dielectric layer 3 and at least one conductive pad 44 located on the second surface 32 of the first dielectric layer 3. In some embodiments, the redistribution layer 4 may further include at least one trace (not shown). In some embodiments, the line width / line spacing (L / S) of the repeating layer 4 may be equal to or greater than 10 μm / 10 μm. The material and L / S of the repeating layer 4 in the first sub-panel 2a may be substantially the same as those of the repeating layer 4 in the second sub-panel 2b.

[0080] A protective layer 25 is located on the second surface 32 of the first dielectric layer 3 and on the repeating layer 4. The protective layer 25 has a first surface 251 and a second surface 252 opposite to the first surface 251. The first surface 251 contacts the lower surface of the first dielectric layer 3 (i.e., the second surface 32). The second surface 252 may be a portion of the lower surface (i.e., the second surface 22) of each of the sub-panels 2. In some embodiments, the protective layer 25 further includes a portion 254 extending into the gap “g” between the sub-panels 2 and located on the dielectric portion 14. The protective layer 25 may comprise, for example, a curable photoimageable dielectric (PID) material comprising an epoxy resin or polyimide (PI) containing a photoinitiator, or a solder resist layer, or formed thereof. The protective layer 25 covers the repeating layer 4, and at least a portion of the repeating layer 4 (e.g., conductive pad 44) ​​is exposed from the protective layer 25 for external connection. In some embodiments, the thickness of the protective layer 25 is from about 10 μm to about 30 μm. The material of the protective layer 25 in the first sub-panel 2a may be substantially the same as the material of the protective layer 25 in the second sub-panel 2b. However, the thickness of the protective layer 25 in the first sub-panel 2a may be substantially the same as or slightly different from the thickness of the protective layer 25 in the second sub-panel 2b.

[0081] The solder connector 26 is located on an exposed portion of the reabsorbent layer 4, such as the conductive pad 44 of the reabsorbent layer 4. The material of the solder connector 26 may be a conductive metal, such as tin, or another metal or a combination of metals.

[0082] The circuit structure 5 is adjacent to the first surface 31 of the first dielectric layer 3. For example, as...Figure 3 As shown, circuit structure 5 is embedded in first dielectric layer 3 and exposed from first surface 31 of first dielectric layer 3. Circuit structure 5 may include a seed layer 51 and a conductive layer 52. Seed layer 51 is exposed from first surface 31 of first dielectric layer 3. The material of seed layer 51 may be, for example, titanium or copper. In some embodiments, seed layer 51 may include titanium layer and copper layer. Conductive layer 52 covers seed layer 51. For example, the material of conductive layer 52 may be a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, seed layer 51 may be omitted, and conductive layer 52 may be exposed from first surface 31 of first dielectric layer 3. Circuit structure 5 includes at least one conductive pad 53, at least one conductive via 54, and at least one trace 55. Conductive pad 53, conductive via 54, and trace 55 may be formed integrally and concurrently. In some embodiments, conductive via 54 is located on and integrally formed with conductive pad 53. Conductive via 54 protrudes from first dielectric layer 3. The conductive via 54 can be adapted to connect to a semiconductor die (e.g., as shown in the image). Figure 12 (As shown in the diagram). The conductive via 54 has an upper surface 541 that is at a level higher than the upper surface (i.e., the first surface 31) of the first dielectric layer 3. The trace 55 has an upper surface 551 that is substantially coplanar with the upper surface 31 of the first dielectric layer 3. In some embodiments, the L / S ratio of the circuit structure 5 may be equal to or less than 2 μm / 2 μm. The redistribution layer 4 is electrically connected to the circuit structure 5. For example, a portion of the redistribution layer 4 (e.g., the conductive via 43) is embedded in the first dielectric layer 3 and contacts and is electrically connected to the circuit structure 5. For example, the conductive via 43 penetrates the first dielectric layer 3 to contact the circuit structure 5. The material and L / S ratio of the circuit structure 5 in the first sub-panel 2a may be the same as or different from the material and L / S ratio of the circuit structure 5 in the second sub-panel 2b.

[0083] The second dielectric layer 6 is located on the first dielectric layer 3. The second dielectric layer 6 has a first surface 61, a second surface 62 opposite to the first surface 61, and a side surface 63 extending between the first surface 61 and the second surface 62. Figure 3 As shown, the first surface 61 is the upper surface, and the second surface 62 is the lower surface. The first surface 61 of the dielectric layer 6 is a portion of the upper surface (i.e., the first surface 21) of the sub-panel 2. The side surface 63 is a portion of the side surface 23 of the sub-panel 2. The second dielectric layer 6 may be located on the first surface 31 of the first dielectric layer 3 and on the circuit structure 5. The lower surface (i.e., the second surface 62) of the second dielectric layer 6 may contact the upper surface (i.e., the first surface 31) of the first dielectric layer 3. Figure 3As shown, the seed layer 51 of circuit structure 5 is located between the conductive layer 52 and the second dielectric layer 6 of circuit structure 5. The upper surface 551 of the trace 55 of circuit structure 5 contacts the lower surface (i.e., the second surface 62) of the second dielectric layer 6. The second dielectric layer 6 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the second dielectric layer 6 may contain, or be formed from, a curable photoimaging dielectric (PID) material, such as epoxy resin or polyimide (PI) containing a photoinitiator. The material of the second dielectric layer 6 may be the same as or different from that of the first dielectric layer 3. The thickness of the second dielectric layer 6 may be from 5 μm to 20 μm. The material and thickness of the second dielectric layer 6 in the first sub-panel 2a may be the same as or different from those in the second sub-panel 2b.

[0084] The conductive via 54 of the circuit structure 5 may be embedded in and exposed from the second dielectric layer 6. For example, the second dielectric layer 6 may define at least one via 60 that penetrates the second dielectric layer 6 and is located between the first surface 61 and the second surface 62. The conductive via 54 of the circuit structure 5 may be located in the via 60 of the second dielectric layer 6 and exposed from the first surface 61 of the second dielectric layer 6. The seed layer 51 of the conductive via 54 of the circuit structure 5 is located in the via 60 of the second dielectric layer 6 and is located between the conductive layer 52 and the second dielectric layer 6. In some embodiments, the portion of the seed layer 51 of the conductive via 54 of the circuit structure 5 adjacent to the first surface 61 of the second dielectric layer 6 is omitted, and the conductive layer 52 of the conductive via 54 of the circuit structure 5 is exposed from the first surface 61 of the second dielectric layer 6. Therefore, the upper surface 541 of the conductive via 54 is recessed from the upper surface (i.e., the first surface 61) of the second dielectric layer 6. Figure 3 As shown, the second dielectric layers 6 of the sub-panels 2 are not connected to each other, and the material and structure of the second dielectric layers 6 can be different between the sub-panels 2.

[0085] Dielectric portions 14 are located between sub-panels 2. For example, dielectric portions 14 fill the gap "g" formed between two adjacent sub-panels 2 (e.g., first sub-panel 2a and second sub-panel 2b). Dielectric portions 14 have an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. At least a portion of the side surface 143 is an imaginary surface or an imaginary plane. Figure 3 As shown, the dielectric portion 14 has at least one side surface 143 corresponding to each of the sub-panels 2.

[0086] In some embodiments, the dielectric portion 14 covers and contacts at least a portion of the side surface 23 of each of the sub-panels 2. For example, side surface 143 of the dielectric portion 14 contacts and is substantially coplanar with side surface 63 of the second dielectric layer 6 of each of the sub-panels 2. In some embodiments, the first dielectric layer 3 of each of the sub-panels 2 is formed integrally and simultaneously with the dielectric portion 14. For example, the sub-panels 2 and the dielectric layer 3 of the dielectric portion 14 may be integrally and simultaneously formed as a single structure. That is, there is no boundary or interface between the dielectric portion 14 and the first dielectric layer 3 of the sub-panel 2.

[0087] In some embodiments, such as Figure 3 As shown, the upper surface 141 of the dielectric portion 14 is at a level higher than the upper surface (i.e., the first surface 21) of each of the sub-panels 2 and / or the first surface 61 of the second dielectric layer 6. Therefore, the dielectric portion 14 has an inner surface 145 defining a cavity 140 above the upper surface (i.e., the first surface 21) of each of the sub-panels 2. The cavity 140 fully exposes the second dielectric layer 6 of each of the sub-panels 2, such as the first surface 61 of the second dielectric layer 6. The upper surface 541 of the conductive via 54 is exposed in the cavity 140. The inner surface 145 may be a portion of the side surface 143 of the dielectric portion 14. The side surface 63 of the second dielectric layer 6 is substantially coplanar with the inner surface 145 of the cavity 140.

[0088] The dielectric portion 14 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the dielectric portion 14 may comprise, or be formed from, a cured photoimaging dielectric (PID) material, such as an epoxy resin containing a photoinitiator or polyimide (PI). The material of the dielectric portion 14 may be the same as the material of the first dielectric layer 3 of each of the sub-panels 2. In some embodiments, the thickness of the dielectric portion 14 may be from about 100 μm to about 300 μm. Figure 3 As shown, the thickness of the first dielectric layer 3 is less than the thickness of the dielectric portion 14. However, in other embodiments, the thickness of the first dielectric layer 3 may be substantially equal to or greater than the thickness of the dielectric portion 14.

[0089] In the substrate panel structure 1, layers with a smaller L / S ratio (i.e., circuit structure 5 and the second dielectric layer 6) are formed in each of the sub-panels 2, while layers with a larger L / S ratio (i.e., redistribution layer 4 and the first dielectric layer 3) are formed simultaneously across the entire substrate panel structure 1. Layers with a smaller L / S ratio are more sensitive to pattern shift than layers with a larger L / S ratio. Since layers with a smaller L / S ratio are formed individually at a smaller scale (i.e., each of the sub-panels 2 has a smaller size or area), the maximum value of the pattern shift, for example, in each of the circuit structures 5, is quite small. Therefore, the effect of pattern shift on layers with a smaller L / S ratio can be reduced. Furthermore, the warpage of the second dielectric layer 6 can also be reduced. On the other hand, layers with a larger L / S ratio that are more tolerant of pattern shift can be formed simultaneously on a larger scale, reducing production time and cost. The larger pattern shift of layers with a larger L / S ratio does not affect layers with a smaller L / S ratio. Therefore, the substrate panel structure 1 formed from the sub-panels 2 has the same maximum pattern shift value as the sub-panels 2.

[0090] For example, in a 300 mm In a sub-panel 2 with an area of ​​300 mm, the pattern offset value measured at its edge can be approximately 1 μm to 2 μm. The substrate panel structure 1 comprises at least 2... Two such sub-panels 2 thus provide a maximum pattern offset value of approximately 1 μm to 2 μm. That is, the pattern offset values ​​of the sub-panels 2 will not accumulate. Therefore, although the substrate panel structure 1 according to the invention has a diameter greater than 600 mm... It has an area of ​​600 mm, but its maximum pattern offset (e.g., about 1 μm to 2 μm) is significantly less than that of a 450 mm area. The maximum pattern offset value of the 450 mm area comparison substrate (e.g., at least 3 μm to 5 μm). Since the maximum values ​​of pattern offset and warpage are reduced, the semiconductor die can be precisely mounted to the predetermined position on the sub-panel 2 (i.e., on the circuit structure 5).

[0091] Figure 4 A cross-sectional view illustrating an example of a substrate panel structure 1a according to some embodiments of the present invention is provided. The substrate panel structure 1a also includes a plurality of sub-panels 2 (including a first sub-panel 2a and a second sub-panel 2b), and a dielectric portion 14 located between the sub-panels 2. Each of the sub-panels 2 includes a plurality of substrate units 20. The components and arrangement of the substrate panel structure 1a, including the sub-panels 2 and the substrate units 20, are similar to... Figure 2 and 3 The substrate panel structure 1 shown herein, except for the dielectric portion 14, is as described below.

[0092] like Figure 4As shown, the upper surface 141 of the dielectric portion 14 is at a level lower than the upper surface (i.e., the first surface 21) of each of the sub-panels 2. (omitted) Figure 2 and 3 The cavity 140 of the substrate panel structure 1 shown in the figure. The upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface (i.e., the first surface 31) of the first dielectric layer 3 and / or the lower surface (i.e., the second surface 62) of the second dielectric layer 6 of each of the sub-panels 2. The side surface 63 of the second dielectric layer 6 is not covered by the dielectric portion 14 and is therefore exposed and is a free surface.

[0093] Figure 5 A cross-sectional view illustrating an example of a substrate panel structure 1b according to some embodiments of the present invention is provided. The substrate panel structure 1b includes a plurality of sub-panels 2c and dielectric portions 14 located between the sub-panels 2c. Each of the sub-panels 2c includes a plurality of substrate units 20c. Except as described below, the substrate panel structure 1b is similar to... Figure 2 and 3 The substrate panel structure shown in the figure is 1.

[0094] like Figure 5 The image shown is omitted. Figure 2 and 3 The second dielectric layer 6 is shown in the diagram. Furthermore, the conductive vias 54 of the circuit structure 5 are also omitted. Therefore, the first surface 57 of the circuit structure 5 (which is located on...) Figure 5 The upper surface of the circuit structure 5 (shown as the top surface) is fully exposed, for example, within the cavity 140 defined by the dielectric portion 14. The entire upper surface of the circuit structure 5 (i.e., the first surface 57) may be substantially coplanar with the upper surface of the first dielectric portion 3 (i.e., the first surface 31). Therefore, the conductive pad 53 and the trace 55 are exposed within the cavity 140. The conductive pad 53 may be adapted to connect to a semiconductor die. Figure 5 The circuit structure 5 shown is a single-layer circuit without a seed layer (i.e., a conductive layer). However, the circuit structure 5 may also include one or more seed layers.

[0095] Figure 6 A cross-sectional view illustrating an example of a substrate panel structure 1c according to some embodiments of the present invention is provided. The substrate panel structure 1c also includes a plurality of sub-panels 2c and dielectric portions 14 located between the sub-panels 2c. Each of the sub-panels 2c includes a plurality of substrate units 20c. The components and arrangement of the substrate panel structure 1c, including the sub-panels 2c and the substrate units 20c, are similar to... Figure 5 The substrate panel structure 1b shown in the figure, except for the dielectric portion 14 described below.

[0096] like Figure 6As shown, the upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface (i.e., the first surface 21) of each of the sub-panels 2c. (omitted) Figure 5 The cavity 140 of the substrate panel structure 1b shown in the figure. The upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface (i.e., the first surface 31) of the first dielectric layer 3 of each of the sub-panels 2c and / or the upper surface (i.e., the first surface 57) of the circuit structure 5.

[0097] Figure 7 A cross-sectional view illustrating an example of a substrate panel structure 1d according to some embodiments of the present invention is provided. The substrate panel structure 1d also includes a plurality of sub-panels 2d and dielectric portions 14 located between the sub-panels 2d. Each of the sub-panels 2d includes a plurality of substrate units 20d. The substrate panel structure 1d is similar to... Figure 6 The substrate panel structure 1c shown in the figure, except for the following.

[0098] like Figure 7 As shown, circuit structure 5 is not embedded in the first dielectric layer 3. Circuit structure 5 protrudes from the first dielectric layer 3. For example, circuit structure 5 is located on the upper surface (i.e., the first surface 31) of the first dielectric layer 3. The first surface 57 (which is as follows) Figure 7 The lower surface shown in the figure contacts the upper surface of the first dielectric layer 3 (i.e., the first surface 31) and is substantially coplanar with it.

[0099] Figure 8 A cross-sectional view illustrating an example of a substrate panel structure 1e according to some embodiments of the present invention is shown. The substrate panel structure 1e also includes a plurality of sub-panels 2e and dielectric portions 14 located between the sub-panels 2e. Each of the sub-panels 2e includes a plurality of substrate units 20e. The substrate panel structure 1e is similar to... Figure 2 and 3 The substrate panel structure 1 shown in the figure further includes an additional dielectric layer 3e and an additional redistribution layer 4e.

[0100] Figure 8 The structure, configuration, materials, and relative positions of the first dielectric layer 3, the redistribution layer 4, the circuit structure 5, the second dielectric layer 6, and the dielectric portion 14 in the substrate panel structure 1e shown are similar to those in [the original text]. Figure 2 and 3 The structure, configuration, materials, and relative positions of the first dielectric layer 3, the redistribution layer 4, the circuit structure 5, the second dielectric layer 6, and the dielectric portion 14 in the substrate panel structure 1 shown in the figure are not described redundantly.

[0101] An additional dielectric layer 3e is located on the first dielectric layer 3 and covers the repeating layer 4. The additional layer 3e may further include a portion 34e that extends into the gap “g” between the sub-panels 2e and is located on the dielectric portion 14. The additional dielectric layer 3e may be made of an insulating material or a dielectric material (e.g., polypropylene (PP)). It should be noted that the additional dielectric layer 3e may comprise, or be formed from, a curable photoimageable dielectric (PID) material, such as an epoxy resin containing a photoinitiator or polyimide (PI). The material of the additional dielectric layer 3e may be the same as or different from the material of the first dielectric layer 3. The material of the additional dielectric layer 3e in each of the sub-panels 2e may be the same and may be formed integrally and simultaneously. The additional dielectric portions 3e of the sub-panels 2e may be connected to each other through the extension portion 34e. The additional dielectric layer 3e defines at least one via 30e to expose at least a portion of the repeating layer 4, such as the conductive pad 44 of the repeating layer 4.

[0102] The additional redistribution layer 4e is located on the additional dielectric layer 3e and within the via 30e. The additional redistribution layer 4e may also include a seed layer 41e located on the additional dielectric layer 3e and a conductive layer 42e located on the seed layer 41e. The materials of the seed layer 41e and conductive layer 42e of the additional redistribution layer 4e may be the same as the materials of the seed layer 41 and conductive layer 42 of the redistribution layer 4. The additional redistribution layer 4e may include at least one conductive via 43e located within the via 30e of the additional dielectric layer 3e and at least one conductive pad 44e located on the additional dielectric layer 3e. The additional redistribution layer 4e is electrically connected to the redistribution layer 4, for example, through the conductive via 43e. In some embodiments, the additional redistribution layer 4e may further include at least one trace (not shown). The L / S ratio of the additional redistribution layer 4e may be substantially equal to or greater than 10 μm / 10 μm. The L / S of the additional re-fabricated layer 4e can be substantially the same as that of the re-fabricated layer 4. The material and L / S of the additional re-fabricated layer 4e in each of the sub-panels 2e can be the same, and they can be formed integrally and simultaneously.

[0103] A protective layer 25 is located on the additional dielectric layer 3e and the additional redistribution layer 4e. The protective layer 25 has a first surface 251 and a second surface 252 opposite to the first surface 251. The first surface 251 contacts the additional dielectric layer 3e. The second surface 252 may be a portion of the lower surface (i.e., the second surface 22) of each of the sub-panels 2e. In some embodiments, the protective layer 25 further includes a portion 254 extending into the gap “g” between adjacent sub-panels 2e and located on an extension portion 34e of the additional dielectric layer 3e. The protective layer 25 may comprise, for example, a curable photoimageable dielectric (PID) material comprising an epoxy resin or polyimide (PI) containing a photoinitiator, or a solder resist layer, or formed thereof. The protective layer 25 covers the additional redistribution layer 4e. At least a portion of the additional redistribution layer 4e (e.g., conductive pad 44e) is exposed from the protective layer 25 for external connectivity. The solder connector 26 is located on an exposed portion of the additional redistribution layer 4e, such as the conductive pad 44e of the additional redistribution layer 4e. In some embodiments, the panel structure 1e may include more than one additional dielectric layer 3e and more than one additional redistribution layer 4e.

[0104] Figure 9 A cross-sectional view illustrating an example of a substrate panel structure 1f according to some embodiments of the present invention is shown. The substrate panel structure 1f also includes a plurality of sub-panels 2f and dielectric portions 14 located between the sub-panels 2f. Each of the sub-panels 2f includes a plurality of substrate units 20f.

[0105] refer to Figure 9 Each of the sub-panels 2f has a first surface 21, a second surface 22 opposite to the first surface 21, and a side surface 23 extending between the first surface 21 and the second surface 22. In some embodiments, at least a portion of the side surface 23 is an imaginary surface or an imaginary plane. Figure 9 As shown, the first surface 21 is the upper surface, and the second surface 22 is the lower surface. Each of the sub-panels 2f includes a first dielectric layer 3, a circuit layer 27, a redistribution layer 4, a second dielectric layer 6, a circuit structure 5, a protective layer 25, and at least one solder connector 26. Similarly, each of the substrate units 20f may include at least a portion of the first dielectric layer 3, at least a portion of the circuit layer 27, at least a portion of the redistribution layer 4, at least a portion of the second dielectric layer 6, at least a portion of the circuit structure 5, at least a portion of the protective layer 25, and at least one solder connector 26.

[0106] The first dielectric layer 3 includes a first surface 31 and a second surface 32 opposite to the first surface 31. For example... Figure 9As shown, the first surface 31 is the upper surface, and the second surface 32 is the lower surface. The first surface 31 of the first dielectric layer 3 may be a portion of the upper surface (i.e., the first surface 21) of each of the sub-panels 2f. The first dielectric layer 3 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the first dielectric layer 3 may comprise, or be formed from, a curable photoimaging dielectric (PID) material, such as an epoxy resin containing a photoinitiator or polyimide (PI).

[0107] The circuit layer 27 is adjacent to the second surface 32 of the first dielectric layer 3. The circuit layer 27 may be embedded in the first dielectric layer 3 and exposed from the second surface 32 of the first dielectric layer 3. The circuit layer 27 may include a seed layer 271 and a conductive layer 272. The seed layer 271 is located between the conductive layer 272 and the first dielectric layer 3. The material of the seed layer 271 may be, for example, titanium or copper. In some embodiments, the seed layer 271 may include a titanium layer and a copper layer. For example, the material of the conductive layer 272 may be a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 271 may be omitted, and the conductive layer 272 may directly contact the first dielectric layer 3. The circuit layer 27 may include at least one conductive pad 274, and may further include at least one trace (not shown). The circuit layer 27 including the conductive pad 274 and the trace may be formed by patterning a metal layer.

[0108] The first dielectric layer 3 may further define vias 30 that expose portions of the circuit layer 27, such as conductive pads 274 of the circuit layer 27. A redistribution layer 4 is located on the first dielectric layer 3 and within the vias 30. The redistribution layer 4 may include a seed layer 41 and a conductive layer 42. The seed layer 41 is located between the conductive layer 42 and the first dielectric layer 3. The seed layer 41 may be made of, for example, titanium or copper. In some embodiments, the seed layer 41 may include a titanium layer and a copper layer. For example, the conductive layer 42 may be made of a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 41 may be omitted, and the conductive layer 42 may directly contact the first dielectric layer 3. The redistribution layer 4 may include at least one conductive via 43 and may further include at least one trace (not shown). The conductive via 43 is located within the via 30 and contacts and electrically connects to the circuit layer 27. Solder material 77 is located on the conductive via 43 of the redistribution layer 4 for external connection. Solder material 77 may be made of tin, or another metal or a combination of metals.

[0109] The second dielectric layer 6 is located on the second surface 32 of the first dielectric layer 3 and covers the circuit layer 27. The second dielectric layer 6 has a first surface 61, a second surface 62 opposite to the first surface 61, and a side surface 63 extending between the first surface 61 and the second surface 62. Figure 9As shown, the first surface 61 is the upper surface, and the second surface 62 is the lower surface. The first surface 61 of the second dielectric layer 6 contacts the first dielectric layer 3 and the circuit layer 27. The side surface 63 of the second dielectric layer 6 is a portion of the side surface 23 of each of the sub-panels 2f. The second dielectric layer 6 may have at least one via 60 to expose a portion of the circuit layer 27, such as the conductive pad 274 of the circuit layer 27. The second dielectric layer 6 may be made of an insulating material or dielectric, such as polypropylene (PP). It should be noted that the second dielectric layer 6 may contain, or be formed from, a curable photoimaging dielectric (PID) material, such as an epoxy resin containing a photoinitiator or polyimide (PI).

[0110] The circuit structure 5 is located on the second surface 62 of the second dielectric layer 6 and in the via 60 of the second dielectric layer 6. The circuit structure 5 may include a seed layer 51 and a conductive layer 52. The seed layer 51 is located on the second dielectric layer 6, in the via 60 of the second dielectric layer 6, and on the redistribution layer 4. The conductive layer 52 is located on the seed layer 51. For example, the seed layer 51 may be made of titanium or copper. In some embodiments, the seed layer 51 may include a titanium layer and a copper layer. For example, the conductive layer 52 may be made of a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 51 may be omitted, and the conductive layer 52 may directly contact the second dielectric layer 6 and / or the redistribution layer 4. The circuit structure 5 includes at least one conductive pad 53, at least one conductive via 54, and at least one trace 55. The conductive pad 53, the conductive via 54, and the trace 55 may be formed integrally and simultaneously. In some embodiments, a conductive via 54 is located on and integrally formed with the conductive pad 53. The conductive via 54 is located in a via 60 of the second dielectric layer 6 to contact and electrically connect to a circuit layer 27 embedded in the first dielectric layer 3. Therefore, the redistribution layer 4 is electrically connected to the circuit structure 5 via the circuit layer 27. That is, each of the redistribution layers 4 is electrically connected to a corresponding one of the circuit structures 5 via a corresponding one of the circuit layers 27. In some embodiments, the L / S ratio of the circuit structure 5 may be equal to or less than 2 μm / 2 μm.

[0111] A protective layer 25 is located on the second dielectric layer 6 and covers the circuit structure 5. That is, the second dielectric layer 6 is sandwiched between the first dielectric layer 3 and the protective layer 25. The protective layer 25 has a first surface 251 and a second surface 252 opposite to the first surface 251. The first surface 251 contacts the lower surface of the second dielectric layer 6 (i.e., the second surface 62). The second surface 252 may be a portion of the lower surface of each of the sub-panels 2f (i.e., the second surface 22). In some embodiments, the protective layer 25 further includes a portion 254 extending into the gap “g” between the sub-panels 2f and located on the dielectric portion 14. The extended portion 254 of the protective layer 25 may contact portions of the side surface 63 of the second dielectric layer 6. The protective layer 25 exposes portions of the circuit structure 5, such as the conductive pad 53 of the circuit structure 5, for external connection. The protective layer 25 may contain, for example, a curable photoimaging dielectric (PID) material containing an epoxy resin or polyimide (PI) with a photoinitiator, or a solder resist layer, or formed therefrom.

[0112] The solder connector 26 is located on an exposed portion of the circuit structure 5, such as on the conductive pad 53 of the circuit structure 5. The material of the solder connector 26 may be a conductive metal, such as tin, or another metal or a combination of metals.

[0113] The dielectric portion 14 is located between the sub-panels 2f. For example, the dielectric portion 14 is located in the gap "g" between the sub-panels 2f. The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. At least a portion of the side surface 143 is an imaginary surface or an imaginary plane. Figure 9 As shown, the upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface (i.e., the first surface 21) of each of the sub-panels 2f and / or the upper surface (i.e., the first surface 31) of the first dielectric layer 3. The lower surface 142 of the dielectric portion 14 is at a level below the lower surface (i.e., the second surface 32) of the first dielectric layer 37 and the upper surface (i.e., the first surface 61) of the second dielectric layer 6, but above the lower surface (i.e., the second surface 62) of the second dielectric layer 6. However, in other embodiments, the lower surface 142 of the dielectric portion 14 may be substantially coplanar with the lower surface (i.e., the second surface 32) of the first dielectric layer 3 and the upper surface (i.e., the first surface 61) of the second dielectric layer 6, or may be substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6.

[0114] In some embodiments, the dielectric portion 14 covers and contacts at least a portion of the side surface 23 of each of the sub-panels 2f. For example, the side surface 143 of the dielectric portion 14 contacts and is substantially coplanar with the side surface 63 of the second dielectric layer 6 of each of the sub-panels 2f. In some embodiments, the first dielectric layer 3 of each of the sub-panels 2f is formed integrally and simultaneously with the dielectric portion 14. For example, the sub-panels 2f and the dielectric layer 3 of the dielectric portion 14 may be integrally and simultaneously formed as a monolithic structure. That is, there is no boundary or interface between the dielectric portion 14 and the first dielectric layer 3 of the sub-panel 2f.

[0115] The dielectric portion 14 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the dielectric portion 14 may comprise, or be formed from, a cured photoimaging dielectric (PID) material, such as an epoxy resin containing a photoinitiator or polyimide (PI). The material of the dielectric portion 14 may be the same as the material of the first dielectric layer 3 of each of the sub-panels 2f. Figure 9 As shown, the thickness of the first dielectric layer 3 is less than the thickness of the dielectric portion 14. However, in other embodiments, the thickness of the first dielectric layer 3 may be substantially equal to or greater than the thickness of the dielectric portion 14.

[0116] Figure 10 A cross-sectional view illustrating an example of a substrate panel structure 1g according to some embodiments of the present invention is shown. The substrate panel structure 1g also includes a plurality of sub-panels 2g and dielectric portions 14 located between the sub-panels 2g. Each of the sub-panels 2g includes a plurality of substrate units 20g.

[0117] refer to Figure 10 Each of the sub-panels 2g has a first surface 21, a second surface 22 opposite to the first surface 21, and a side surface 23 extending between the first surface 21 and the second surface 22. In some embodiments, at least a portion of the side surface 23 is an imaginary surface or an imaginary plane. Figure 10 As shown, the first surface 21 is the upper surface, and the second surface 22 is the lower surface. Each of the sub-panels 2g includes a first dielectric layer 3, a circuit structure 5, a redistribution layer 4, and at least one solder connector 26. Similarly, each of the substrate units 20g may include at least a portion of the first dielectric layer 3, at least a portion of the circuit structure 5, at least a portion of the redistribution layer 4, and at least one solder connector 26.

[0118] The first dielectric layer 3 includes a first surface 31, a second surface 32 opposite to the first surface 31, and a side surface 33 extending between the first surface 31 and the second surface 32. Figure 10As shown, the first surface 31 is the upper surface, and the second surface 32 is the lower surface. The first surface 31 of the first dielectric layer 3 may be a portion of the upper surface (i.e., the first surface 21) of each of the sub-panels 2g, the second surface 32 of the dielectric layer 3 may be a portion of the lower surface (i.e., the second surface 22) of each of the sub-panels 2g, and the side surface 33 of the first dielectric layer 3 may be a portion of the side surface 23 of the sub-panel 2g. The first dielectric layer 3 may be made of an insulating material or a dielectric material, such as polypropylene (PP). It should be noted that the first dielectric layer 3 may contain, or be formed from, a curable photoimaging dielectric (PID) material, such as an epoxy resin containing a photoinitiator or polyimide (PI).

[0119] The circuit structure 5 is adjacent to the first surface 31 of the first dielectric layer 3. For example, as... Figure 10 As shown, the circuit structure 5 is embedded in the first dielectric layer 3 and exposed from the first surface 31 of the first dielectric layer 3. The material of the circuit structure 5 may be, for example, a conductive metal, such as copper, or another metal or a combination of metals. Figure 10 A circuit structure 5 consisting of a single layer is shown. However, in some embodiments, the circuit structure 5 may also include other layers, such as one or more seed layers. The circuit structure 5 includes at least one conductive pad 53 and at least one trace 55. The conductive pad 53 and the trace 55 may be formed integrally and simultaneously. The trace 55 has an upper surface 551, which is at a level below the upper surface 31 of the first dielectric layer 3. In some embodiments, the L / S ratio of the circuit structure 5 may be equal to or less than 2 μm / 2 μm.

[0120] The first dielectric layer 3 may further define at least one via 30, such that a portion of the circuit structure 5, such as the conductive pad 53 of the circuit structure 5, may be exposed in the via 30 and from the second surface 32 of the dielectric layer 3.

[0121] The redistribution layer 4 is electrically connected to the circuit structure 5. For example, the redistribution layer 4 includes at least one conductive via 43 located in and embedded in the first dielectric layer 3 via 30. The conductive via 43 penetrates the first dielectric layer 3 to contact and electrically connect to the circuit structure 5, such as a conductive pad 53 of the circuit structure 5. In some embodiments, the redistribution layer 4 may further include at least one trace (not shown). For example, the material of the redistribution layer 4 may be a conductive metal, such as copper, or another metal or combination of metals. In some embodiments, one or more seed layers may be located between the redistribution layer 4 and the first dielectric layer 3. In some embodiments, the linewidth / spacing (L / S) of the redistribution layer 4 may be equal to or greater than 10 μm / 10 μm.

[0122] The solder connector 26 is located on and electrically connected to the conductive via 43 of the overlay layer 4. The material of the solder connector 26 may be a conductive metal, such as tin, or other metals or combinations of metals. Under bump metallization (UBM) 46 may be located between the conductive via 43 and the solder connector 26.

[0123] Dielectric portions 14 are located between sub-panels 2g. For example, a gap "g" is defined between two adjacent sub-panels 2g, and the dielectric portions 14 are located within the gap "g". The dielectric portions 14 have an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. At least a portion of the side surface 143 is an imaginary surface or an imaginary plane. Figure 10 As shown, the dielectric portion 14 has at least one side surface 143 corresponding to each of the sub-panels 2g. The upper surface 141 of the dielectric portion 14 is at a level lower than the upper surface (i.e., the first surface 21) of each of the sub-panels 2g and / or the upper surface (i.e., the first surface 31) of the first dielectric layer 3. The lower surface 142 of the dielectric portion 14 is substantially coplanar with the lower surface (i.e., the second surface 22) of each of the sub-panels 2g and / or the lower surface (i.e., the second surface 32) of the first dielectric layer 3.

[0124] In some embodiments, the dielectric portion 14 covers and contacts at least a portion of the side surface 23 of each of the sub-panels 2g. For example, the side surface 143 of the dielectric portion 14 contacts and is substantially coplanar with the side surface 23 and / or the side surface 33 of the first dielectric layer 3 of each of the sub-panels 2g. In some embodiments, the first dielectric layer 3 of each of the sub-panels 2g is integrally and simultaneously formed with the dielectric portion 14. For example, the dielectric layer 3 and the dielectric portion 14 of the sub-panel 2g may be integrally and simultaneously formed as a single structure. That is, there is no boundary or interface between the dielectric portion 14 and the first dielectric layer 3 of the sub-panel 2g.

[0125] The dielectric portion 14 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the dielectric portion 14 may comprise, or be formed from, a curable photoimaging dielectric (PID) material, such as an epoxy resin containing a photoinitiator or polyimide (PI). The material of the dielectric portion 14 may be the same as the material of the first dielectric layer 3 of each of the sub-panels 2g. The thickness of the first dielectric layer 3 may be greater than the thickness of the dielectric portion 14.

[0126] like Figure 10As shown, at least one semiconductor die 74 is connected to each of the substrate units 20g. That is, multiple semiconductor dies 74 are connected to each of the sub-panels 2g. The semiconductor die 74 may include bumps 75 and UBM 76. Bumps 75 are located on the lower surface 741 of the semiconductor die 74, and UBM 76 is located on bumps 75. The material of bumps 75 may be copper. UBM 76 may include a first layer 761, a second layer 762, and a third layer 763 sequentially located on bumps 75. For example, the material of the first layer 761 may be nickel, the material of the second layer 762 may be palladium, and the material of the third layer 763 may be gold, but is not limited thereto. The UBM 76 of the semiconductor die 74 may be electrically connected to the conductive pads 53 of the circuit structure 5 via solder material 77 located therebetween. Solder material 77 may be made of tin, or another metal or combination of metals.

[0127] An encapsulant 78 is located on and covers the substrate panel structure 1g. For example, the encapsulant 78 is located on the first dielectric layer 3 of each of the sub-panels 2g, and covers and encapsulates the semiconductor die 74. The encapsulant 78 may further include a portion 784 located in the gap "g" between the sub-panels 2g and on the dielectric portion 14. The portion 784 of the encapsulant 78 contacts the side surface 33 of the first dielectric layer 3. The encapsulant 78 may be a molding compound. The substrate panel structure 1g and the encapsulant 78 can be separated into multiple packaging units through a monomerization process, for example... Figure 16 The packaged unit shown in the image is 7g.

[0128] Figure 11 A cross-sectional view illustrating an example of a substrate panel structure 1h according to some embodiments of the present invention is shown. The substrate panel structure 1h also includes a plurality of sub-panels 2h and dielectric portions 14 located between the sub-panels 2h. Each of the sub-panels 2h includes a plurality of substrate units 20h.

[0129] refer to Figure 11 Each of the sub-panels 2h has a first surface 21, a second surface 22 opposite to the first surface 21, and a side surface 23 extending between the first surface 21 and the second surface 22. In some embodiments, at least a portion of the side surface 23 is an imaginary surface or an imaginary plane. Figure 11 As shown, the first surface 21 is the upper surface, and the second surface 22 is the lower surface. Each of the sub-panels 2h includes a second dielectric layer 6, a plurality of conductive pillars 28, a circuit structure 5, a first dielectric layer 3, a redistribution layer 4, and at least one solder connector 26. Similarly, each of the substrate units 20h may include at least a portion of the second dielectric layer 6, a plurality of conductive pillars 28, at least a portion of the circuit structure 5, at least a portion of the first dielectric layer 3, at least a portion of the redistribution layer 4, and at least one solder connector 26.

[0130] The second dielectric layer 6 has a first surface 61, a second surface 62 opposite to the first surface 61, and a side surface 63 extending between the first surface 61 and the second surface 62. Figure 11 As shown, the first surface 61 is the upper surface, and the second surface 62 is the lower surface. The first surface 61 of the dielectric layer 6 is a portion of the upper surface (i.e., the first surface 21) of the sub-panel 2h. The side surface 63 is a portion of the side surface 23 of the sub-panel 2h. The second dielectric layer 6 defines a plurality of vias 60 that penetrate the second dielectric layer 6 and are located between the first surface 61 and the second surface 62. The second dielectric layer 6 may be made of an insulating material or a dielectric material (e.g., polypropylene (PP)). It should be noted that the second dielectric layer 6 may contain, or be formed from, a curable photoimaging dielectric (PID) material, such as an epoxy resin containing a photoinitiator or polyimide (PI).

[0131] The conductive pillars 28 are located in the vias 60 of the second dielectric layer 6, and both ends of each of the conductive pillars 28 are exposed from the second dielectric layer 6. The material of the conductive pillars 28 may be, for example, a conductive metal, such as copper, or another metal or combination of metals.

[0132] The circuit structure 5 is adjacent to the first surface 61 of the second dielectric layer 6 and electrically connected to the conductive pillar 28. For example, as Figure 11 As shown, circuit structure 5 is located on the first surface 61 of the second dielectric layer 6, and a portion of circuit structure 5 extends into the via 60 to contact the conductive pillar 28. Circuit structure 5 may include a seed layer 51 and a conductive layer 52. The seed layer 51 is located between the conductive layer 52 and the second dielectric layer 6, and between the conductive layer 52 and the conductive pillar 28. The material of the seed layer 51 may be, for example, titanium or copper. In some embodiments, the seed layer 51 may include a titanium layer and a copper layer. For example, the material of the conductive layer 52 may be a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 51 may be omitted, and the conductive layer 52 may directly contact the second dielectric layer 6 and / or the conductive pillar 28. Circuit structure 5 includes at least one conductive pad 53 and at least one trace 55. The conductive pad 53 and the trace 55 may be formed integrally and simultaneously. In some embodiments, the L / S ratio of circuit structure 5 may be equal to or less than 2 μm / 2 μm.

[0133] The redistribution layer 4 is adjacent to the second surface 62 of the second dielectric layer 6. For example, as in... Figure 11As shown, the redistribution layer 4 is located on the second surface 62 of the second dielectric layer 6, and a portion of the redistribution layer 4 extends into the via 60 to contact the conductive post 28. The redistribution layer 4 is electrically connected to the circuit structure 5 via the conductive post 28. The redistribution layer 4 may include a seed layer 41 and a conductive layer 42. The seed layer 41 is located between the conductive layer 42 and the second dielectric layer 6, and between the conductive layer 42 and the conductive post 28. The material of the seed layer 41 may be, for example, titanium or copper. In some embodiments, the seed layer 41 may include a titanium layer and a copper layer. For example, the material of the conductive layer 42 may be a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 41 may be omitted, and the conductive layer 42 may directly contact the second dielectric layer 6 and the conductive post 28. The redistribution layer 4 may include at least one conductive pad 44 and at least one trace 45. In some embodiments, the linewidth / spacing (L / S) of the redistribution layer 4 may be equal to or greater than 10 μm / 10 μm.

[0134] The first dielectric layer 3 is located on the second surface 62 of the second dielectric layer 6 and covers the redistribution layer 4. The first dielectric layer 3 includes a first surface 31 and a second surface 32 opposite to the first surface 31. Figure 11 As shown, the first surface 31 is the upper surface, and the second surface 32 is the lower surface. The upper surface of the first dielectric layer 3 (i.e., the first surface 31) can contact the lower surface of the second dielectric layer 6 (i.e., the second surface 62).

[0135] The first dielectric layer 3 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the first dielectric layer 3 may comprise, or be formed from, a curable photoimaging dielectric (PID) material, such as an epoxy resin containing a photoinitiator or polyimide (PI). The first dielectric layer 3 defines at least one via 30 to expose at least a portion of the reel layer 4, such as the conductive pad 44 of the reel layer 4.

[0136] The solder connector 26 is located in the via 30 of the first dielectric layer 3 and is on and electrically connected to the exposed portion of the re-layer 4 (e.g., conductive pad 44). The solder connector 26 may be made of a conductive metal, such as tin, or other metals or combinations thereof. A barrier layer 47 and a wetting layer 48 may be located between the conductive pad 44 and the solder connector 26. The barrier layer 47 may be made of nickel, and the wetting layer may be made of gold.

[0137] Dielectric portions 14 are located between sub-panels 2h. For example, a gap "g" is defined between two adjacent sub-panels 2h, and dielectric portions 14 are located within the gap "g". Dielectric portions 14 have an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. At least a portion of the side surface 143 is an imaginary surface or an imaginary plane. Figure 11 As shown, the upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface of the first dielectric layer 3 (i.e., the first surface 31) and the lower surface of the second dielectric layer 6 of each of the sub-panels 2h (i.e., the second surface 62), and is lower than the upper surface of each of the sub-panels 2h (i.e., the first surface 21). The lower surface 142 of the dielectric portion 14 is substantially coplanar with the lower surface of each of the sub-panels 2h (i.e., the second surface 22) and / or the lower surface of the first dielectric layer 3 (i.e., the second surface 32). The side surface 143 of the dielectric portion 14 is substantially coplanar with the side surface 63 of the second dielectric layer 6 of each of the sub-panels 2h.

[0138] In some embodiments, the dielectric portion 14 covers and contacts at least a portion of the side surface 23 of each of the sub-panels 2h. In some embodiments, the first dielectric layer 3 of each of the sub-panels 2h is formed integrally and simultaneously with the dielectric portion 14. For example, the dielectric layer 3 and the dielectric portion 14 of the sub-panel 2h may be integrally and simultaneously formed as a single structure. That is, there is no boundary or interface between the dielectric portion 14 and the first dielectric layer 3 of the sub-panel 2h.

[0139] like Figure 17 As shown, at least one semiconductor die 74 is connected to each of the substrate cells 20h. That is, multiple semiconductor dies 74 are connected to each of the sub-panels 2h. The semiconductor die 74 may include bumps 75 and UBM 76. Bumps 75 are located on the lower surface 741 of the semiconductor die 74, and UBM 76 is located on bumps 75. The material of bumps 75 may be copper. UBM 76 may include a first layer 761 and a second layer 762 sequentially located on bumps 75. For example, the material of the first layer 761 may be nickel, and the material of the second layer 762 may be palladium, but is not limited thereto. In some embodiments, UBM 76 may include three layers made of nickel, palladium, and gold. The UBM 76 of the semiconductor die 74 may be electrically connected to the conductive pads 53 of the circuit structure 5 via solder material 77 located therebetween. Solder material 77 may be made of tin, or another metal or combination of metals.

[0140] Encapsulant 78 is located on and covers the substrate panel structure 1h. For example, encapsulant 78 is located on the second dielectric layer 6 of each of the sub-panels 2h, and covers and encapsulates the semiconductor die 74. Encapsulant 78 includes a portion 784 located in the gap "g" formed between two adjacent sub-panels 2h and on the dielectric portion 14. Encapsulant 78 may contact and cover the side surface 63 of the second dielectric layer 6. Encapsulant 78 may be a molding compound. The substrate panel structure 1h and encapsulant 78 can be separated into multiple packaging units by a monomerization process, for example... Figure 12 The packaging unit 7h shown in the image.

[0141] Figure 3 A cross-sectional view illustrating an example of a packaging unit 7 according to some embodiments of the present invention. The packaging unit 7 corresponds to... Figure 4 or Figure 13 Each of the substrate units 20 shown herein. That is, the packaging unit 7 includes the substrate unit 20 and further includes a semiconductor die 74 and an encapsulant 78.

[0142] Semiconductor die 74 is connected to substrate cell 20. Semiconductor die 74 may include bumps 75 located on the lower surface 741 of semiconductor die 74. The bumps 75 of semiconductor die 74 are electrically connected to conductive vias 54 of circuit structure 5 of substrate cell 20 via solder material 77, the solder material being located between the bumps and the conductive vias. Solder material 77 may be made of tin, or another metal or combination of metals.

[0143] Encapsulant 78 is located on substrate cell 20 and covers at least a portion of substrate cell 20 and / or semiconductor die 74. For example, encapsulant 78 is located between the second dielectric layer 6 of substrate cell 20 and semiconductor die 74, and encapsulates bump 75 and solder material 77. Encapsulant 78 may be underfill or molding compound.

[0144] Figure 5 A cross-sectional view illustrating an example of a packaging unit 7c according to some embodiments of the present invention. The packaging unit 7c corresponds to... Figure 6 or Figure 14 Each of the substrate units 20c shown herein. That is, the packaging unit 7c includes the substrate unit 20c and further includes a semiconductor die 74 and an encapsulant 78.

[0145] Semiconductor die 74 is connected to substrate cell 20c. Semiconductor die 74 may include bumps 75 located on the lower surface 741 of semiconductor die 74. The bumps 75 of semiconductor die 74 are electrically connected to conductive pads 53 of circuit structure 5 of substrate cell 20c via solder material 77, the solder material being located between the bumps and the conductive vias. Solder material 77 may be made of tin, or another metal or combination of metals.

[0146] Encapsulant 78 is located on substrate cell 20c and covers at least a portion of substrate cell 20c and / or semiconductor die 74. For example, encapsulant 78 is located between the first dielectric layer 3 of substrate cell 20c and semiconductor die 74, and encapsulates portions of bump 75, solder material 77, and circuit structure 5. Encapsulant 78 may be underfill or molding compound.

[0147] Figure 7 A cross-sectional view illustrating an example of a semiconductor package 7d according to some embodiments of the present invention. Package unit 7d corresponds to... Figure 15 Each of the substrate units 20d shown herein. That is, the packaging unit 7d includes the substrate unit 20d and further includes a semiconductor die 74 and an encapsulant 78.

[0148] Semiconductor die 74 is connected to substrate cell 20d. Semiconductor die 74 may include bumps 75 located on the lower surface 741 of semiconductor die 74. The bumps 75 of semiconductor die 74 are electrically connected to conductive pads 53 of circuit structure 5 of substrate cell 20d via solder material 77, said solder material 77 being located between the bumps 75 and the conductive pads 53. Solder material 77 may be made of tin, or another metal or combination of metals.

[0149] Encapsulant 78 is located on substrate cell 20d and covers at least a portion of substrate cell 20d and / or semiconductor die 74. For example, encapsulant 78 is located between the first dielectric layer 3 of substrate cell 20d and semiconductor die 74, and encapsulates portions of bump 75, solder material 77, and circuit structure 5. Encapsulant 78 may be underfill or molding compound.

[0150] Figure 9 A cross-sectional view illustrating an example of a semiconductor package 7f according to some embodiments of the present invention. Package unit 7f corresponds to... Figure 16 Each of the substrate units 20f shown herein. That is, the packaging unit 7f includes the substrate unit 20f and further includes a semiconductor die 74 and an encapsulant 78.

[0151] Semiconductor die 74 is connected to substrate cell 20f. Semiconductor die 74 may include bumps 75 on the lower surface 741 of semiconductor die 74, and UBM 76 on the bumps 75. UBM 76 may include a first layer 761 and a second layer 762 sequentially located on the bumps 75. For example, the first layer 761 may be made of nickel, and the second layer 762 may be made of palladium, but is not limited thereto. In some embodiments, UBM 76 may include three layers made of nickel, palladium, and gold. The UBM 76 of semiconductor die 74 is connected to the redistribution layer 4 of substrate cell 20f, such as the conductive via 43 of redistribution layer 4, via soldering material 77.

[0152] Encapsulant 78 is located on substrate cell 20f and covers at least a portion of substrate cell 20f and / or semiconductor die 74. For example, encapsulant 78 is located on the first dielectric layer 3 of substrate cell 20f and covers and encapsulates semiconductor die 74, bumps 75 and UBM 76 of semiconductor die 74, solder material 77, and redistribution layer 4 of substrate cell 20f. Encapsulant 78 may be underfill or molding compound.

[0153] Figure 10 A cross-sectional view illustrating an example of a packaging unit 7g according to some embodiments of the present invention. The packaging unit 7g corresponds to... Figure 10 Each of the substrate units 20g shown herein. That is, the packaging unit 7g includes the substrate unit 20g, and further includes a semiconductor die 74 and an encapsulant 78. The semiconductor 74 and the encapsulant 78 are... Figure 17 The same applies to those described in [the text]. Therefore, they will not be repeated here.

[0154] Figure 11 A cross-sectional view illustrating an example of a semiconductor package 7h according to some embodiments of the present invention. The package unit 7h corresponds to... Figure 11 Each of the substrate units 20h shown herein. That is, the packaging unit 7h includes the substrate unit 20h, and further includes a semiconductor die 74 and an encapsulant 78. The semiconductor 74 and the encapsulant 78 are... Figure 18 The same applies to those described in [the text]. Therefore, they will not be repeated here.

[0155] Figure 3 A cross-sectional view illustrating an example of a semiconductor package 7k according to some embodiments of the present invention. Package unit 7k corresponds to... Figure 4 or Figure 12 Each of the substrate units 20 shown herein. That is, the packaging unit 7 includes the substrate unit 20 and further includes a semiconductor die 74 and an encapsulant 78. The packaging unit 7k is similar to Figures 19 to 26 The encapsulation unit 7 shown in the figure completely covers the semiconductor die 74 except that the encapsulant 78 of the encapsulation unit 7k completely covers the semiconductor die 74.

[0156] Figure 2 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is used to manufacture a substrate panel structure, for example... Figure 12 and 3 The substrate panel structure 1 shown in the figure, and / or Figure 19 The packaging unit 7 shown in the figure is the packaging unit.

[0157] refer to Figure 19An intermediate support 81 is provided. The intermediate support 81 may include a releasing film 82 disposed thereon. A seed layer is formed or disposed on the intermediate support 81 by, for example, sputtering. Figure 20 As shown, the seed layer includes a titanium layer 83 and a copper layer 84 sequentially located on the release membrane 82 of the intermediate carrier 81.

[0158] refer to Figure 20 A second dielectric layer 6 is formed on the seed layer (e.g., copper layer 84). The second dielectric layer 6 has a first surface 61, a second surface 62 opposite to the first surface 61, and a side surface 63 extending between the first surface 61 and the second surface 62. Figure 12 As shown, a first surface 61 is the upper surface, and a second surface 62 is the lower surface. The first surface 61 contacts a seed layer (e.g., copper layer 84). A second dielectric layer 6 defines at least one via 60 that penetrates the second dielectric layer 6 and is located between the first surface 61 and the second surface 62 to expose a portion of the seed layer (e.g., copper layer 84). A circuit structure 5 is then formed on the second surface 62 of the second dielectric layer 6 and in the via 60 of the second dielectric layer 6. The circuit structure 5 includes a seed layer 51 and a conductive layer 52. The seed layer 51 is located between the conductive layer 52 and the second dielectric layer 6, and between the conductive layer 52 and the seed layer (e.g., copper layer 84) in the via 60. For example, the seed layer 51 can be formed by sputtering, and the conductive layer 52 can be formed by electroplating. The material of the seed layer 51 can be, for example, titanium or copper. In some embodiments, the seed layer 51 may comprise a titanium layer and a copper layer. For example, the material of the conductive layer 52 may be a conductive metal, such as copper, or another metal or combination of metals. The circuit structure 5 includes at least one conductive pad 53, at least one conductive via 54, and at least one trace 55. The conductive pad 53, conductive via 54, and trace 55 may be formed integrally and simultaneously. In some embodiments, the conductive via 54 is located on and integrally formed with the conductive pad 53. The conductive via 54 of the circuit structure 5 may be located in a via 60 of the second dielectric layer 6. That is, each of the circuit structures 5 includes a via 60 located in a corresponding one of the second dielectric layers 6. The trace 55 has an upper surface 551 that contacts and is substantially coplanar with the lower surface 62 of the second dielectric layer 6. In some embodiments, the L / S ratio of the circuit structure 5 may be equal to or less than 2 μm / 2 μm. Thus, an intermediate panel 8 is formed. The intermediate panel 8 includes a plurality of panel units 80 connected to each other. Each of the panel units 80 corresponds to a packaging unit, such as... Figure 19 The packaging unit 7 shown in the image.

[0159] For illustrative purposes, Figure 21 and 20Only one intermediate panel 8 is shown. However, multiple intermediate panels 8 can be provided or formed via the processes mentioned above. Each of the intermediate panels 8 includes a circuit structure 5, and these intermediate panels 8 are separate from each other. That is, multiple intermediate carriers 81 can be provided, and a second dielectric layer 6 can be formed on each of the intermediate carriers 81. Similarly, the circuit structure 5 can be formed on each of the intermediate carriers 81, for example, on the second dielectric layer 6, thus forming each intermediate panel 8. Since the intermediate panels 8 can be formed individually, the materials and structures of each of the intermediate panels 8 can be different from each other.

[0160] refer to Figure 21 A main carrier 91 is provided. The main carrier 91 includes a soft-releasing film 92 disposed thereon. An intermediate panel 8 is disposed on the main carrier 91 and partially embedded in the soft-releasing film 92. The intermediate carrier 81 is located between the main carrier 91 and the circuit structure 5. The lower surface 921 of the soft-releasing film 92 is at a level higher than the upper surface (i.e., the first surface 61) of the second dielectric layer 6. The intermediate panels 8 are spaced apart from each other, and a gap "g" is defined between adjacent intermediate panels 8. For illustrative purposes, Figure 22 Only two middle panels 8 are displayed. However, there can be more than two middle panels 8.

[0161] refer to Figure 22 A dielectric material is provided on the main carrier 91 to form a plurality of first dielectric layers 3 and a dielectric portion 14. The dielectric material covers the intermediate panel 8 and the soft release film 92. Each of the first dielectric layers 3 is located on a corresponding one of the intermediate panels 8. The dielectric portion 14 is located in the gap “g” between two adjacent intermediate panels 8 and on the soft release film 92. The dielectric portion 14 is located between and connects the first dielectric layers 3. The first dielectric layers 3 and the dielectric portion 14 are simultaneously and integrally formed into a single structure. That is, there is no boundary or interface between the dielectric portion 14 and the first dielectric layers 3. The dielectric material may be an insulating material or a dielectric material, such as polypropylene (PP). It should be noted that the dielectric material may comprise, for example, a curable photoimaging dielectric (PID) material containing an epoxy resin or polyimide (PI) with a photoinitiator, or be formed therefrom. Therefore, the first dielectric layer 3 and the dielectric portion 14 may be made of an insulating or dielectric material such as polypropylene (PP), or may contain or be formed of a curable photoimaging dielectric (PID) material such as epoxy resin containing a photoinitiator or polyimide (PI).

[0162] The first dielectric layer 3 includes a first surface 31 and a second surface 32 opposite to the first surface 31. For example... Figure 23As shown, the first surface 31 is the upper surface, and the second surface 32 is the lower surface. The upper surface of the first dielectric layer 3 (i.e., the first surface 31) contacts the lower surface of the second dielectric layer 6 (i.e., the second surface 62), and is therefore substantially coplanar with the upper surface 551 of the trace 55 of the circuit structure 5. In some embodiments, the thickness of the first dielectric layer 3 may be from about 3 μm to about 20 μm, preferably from about 3 μm to about 15 μm.

[0163] The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. The upper surface 141 contacts the lower surface 921 of the soft release membrane 92 and is therefore at a level higher than the upper surface (i.e., the first surface 61) of the second dielectric layer 6. At least a portion of the side surface 143 is an imaginary surface or imaginary plane. The side surface 143 can contact and is substantially coplanar with the side surface 63 of the second dielectric layer 6, and can further contact the release membrane 82 and the intermediate carrier 81.

[0164] refer to Figure 24 At least one via 30 is formed through each of the first dielectric layers 3 by means of, for example, photolithography or drilling. The via 30 exposes portions of the circuit structure 5, such as the conductive pad 53 of the circuit structure 5. Then, a plurality of redistribution layers 4 are formed on the first dielectric layer 3, and each of the redistribution layers 4 is electrically connected to a corresponding one in the current structure 5 of the intermediate panel 8. The redistribution layers 4 are located on the second surface 32 of the first dielectric layer 3 and in the via 30. The redistribution layer 4 may include a seed layer 41 located on the first dielectric layer 3 and a conductive layer 42 located on the seed layer 41. The material of the seed layer 41 may be, for example, titanium or copper. In some embodiments, the seed layer 41 may include a titanium layer and a copper layer. For example, the seed layer 41 may be formed by sputtering, and the conductive layer 42 may be formed by electroplating. For example, the material of the conductive layer 42 may be a conductive metal, such as copper, or another metal or combination of metals. The redistribution layer 4 may include at least one conductive via 43 located in the via 30 of the first dielectric layer 3, and at least one conductive pad 44 located on the second surface 32 of the first dielectric layer 3. The redistribution layer 4 is electrically connected to the circuit structure 5 via the conductive via 43. In some embodiments, the redistribution layer 4 may further include at least one trace (not shown). In some embodiments, the linewidth / spacing (L / S) of the redistribution layer 4 may be equal to or greater than 10 μm / 10 μm.

[0165] refer to Figure 25A protective layer 25 is formed on the first dielectric layer 3 and covers the reel layer 4. The protective layer 25 has a first surface 251 and a second surface 252 opposite to the first surface 251. The first surface 251 contacts the second surface 32 of the first dielectric layer 3. In some embodiments, the protective layer 25 further includes a portion 254 extending into the gap “g” between the intermediate panels 8 and located on the dielectric portion 14. The protective layer 25 may comprise, for example, a curable photoimageable dielectric (PID) material comprising an epoxy resin or polyimide (PI) including a photoinitiator, or a solder resist layer, or formed therefrom. The protective layer 25 covers the reel layer 4, and at least a portion of the reel layer 4 (e.g., a conductive pad 44) ​​is exposed from the protective layer 25 for external connection. In some embodiments, the thickness of the protective layer 25 is from about 10 μm to about 30 μm. At least one solder connector 26 is then formed on the exposed portion of the reel layer 4, such as the conductive pad 44 of the reel layer 4. The material of the solder connector 26 may be a conductive metal, such as tin, or another metal or combination of metals.

[0166] refer to Figure 2 The main carrier 91, including the soft release layer 92, is removed. Then, the intermediate carrier 81, including the release film 82, is removed, exposing the seed layer (e.g., titanium layer 83). The seed layer (e.g., titanium layer 83 and copper layer 84) is then removed, for example, by etching, thus forming... Figure 26 and 3 The substrate panel structure 1 shown is illustrated. Each of the intermediate panels 8 corresponds to a corresponding one of the sub-panels 2. During the etching process, a portion of the seed layer 51 of the circuit structure 5 adjacent to the first surface 61 of the second dielectric layer 6 may also be removed, thus exposing the conductive layer 52 of the conductive via 54 from the first surface 61 of the second dielectric layer 6. Consequently, the upper surface 541 of the conductive via 54 is recessed from the upper surface (i.e., the first surface 61) of the second dielectric layer 6.

[0167] refer to Figure 12Then, multiple semiconductor dies 74 are connected or mounted to the circuit structure 5 of each of the intermediate panels 8 (i.e., sub-panels 2 in the substrate panel structure 1). For example, at least one semiconductor die 74 is connected to each of the substrate units 20. The semiconductor die 74 may include bumps 75 located on the lower surface 741 of the semiconductor die 74. The bumps 75 of the semiconductor die 74 are electrically connected to conductive vias 54 of the circuit structure 5 of the substrate unit 20 via solder material 77, which is located between the bumps 75 and the conductive vias 54. The solder material 77 may be made of tin, or another metal or combination of metals. Then, multiple encapsulants 78 are formed on each of the substrate units 20 to cover the corresponding one of the semiconductor dies 74. For example, the encapsulant 78 is located between the second dielectric layer 6 and the semiconductor die 74 and encapsulates the bumps 75 and the solder material 77. Then, each of the sub-panels 2 is monomerized. That is, each of the individual intermediate panels 8 (e.g., including the second dielectric layer 6 and circuit structure 5), each of the first dielectric layer 3, and each of the redistribution layer 4 form a plurality of package units, for example... Figure 27 The encapsulation unit 7 shown in the figure. For example, the edge of each sub-panel 2 can be cut along the side surface 23 to remove the dielectric portion 14 and portion 254 of the protective layer 25 during the monomerization process.

[0168] In contrast manufacturing processes (e.g., reconstitution processes), the intermediate panel is first diced into multiple separate panel units. These panel units are then picked up and placed on a host carrier. Next, other layers, such as dielectric layers and redistribution layers, are formed on the host carrier, and multiple semiconductor dies are then attached to the panel units. The reason for dicing the intermediate panel into panel units is that the intermediate panel is typically a circular wafer, so the dicing process effectively reduces wasted wafer area. However, the placement of these panel units on the host carrier by machine can cause positional offsets of approximately 1 μm to 3 μm. That is, the spacing between these panel units is inconsistent, so the semiconductor dies cannot be precisely bonded to the panel units.

[0169] In contrast, since the intermediate panel 8 in the above-described manufacturing process of the present invention comprises a plurality of panel units 80 connected to each other, the spacing between the plurality of panel units 80 is not affected by the pick-and-place process. That is, the spacing between the panel units in the same intermediate panel is substantially consistent, so semiconductor dies can be precisely mounted onto the panel units.

[0170] Figure 2 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is also used to manufacture, for example... Figure 12 and 3The substrate panel structure 1 shown herein, and / or for example, the substrate panel structure of the substrate panel structure 1, and / or for example, Figures 19 to 20 The packaging unit 7 shown is the packaging unit. The initial stage of the process described is related to... Figure 27 The stages described herein are the same or similar. Figure 20 illustrate Figure 27 The stage following the stage described in the text.

[0171] Figure 21 The stages shown in the text are similar to Figure 27 The stages shown herein, except as described below. Figure 21 As shown, the main carrier 91 includes a hard-releasing film 92a, rather than... Figure 22 The soft release film 92 is shown in the diagram. Therefore, the intermediate panel 8 is positioned on, rather than embedded in, the hard release film 92a. A gap "g" is defined between adjacent panels in the intermediate panel 8. A resin material 93, for example photoresist, is applied to the gap "g" defined between adjacent panels in the intermediate panel 8. The resin material 93 can be applied to the hard release film 92a before the intermediate panel 8 is placed, so that the intermediate panel 8 can be embedded in the resin material 93. Alternatively, the resin material 93 can be applied to the gap "g" after the intermediate panel 8 is placed. The lower surface 931 of the resin material 93 is at a level higher than the upper surface (i.e., the first surface 61) of the second dielectric layer 6. Similar to... Figure 27 In a subsequent stage shown, the lower surface 931 of the resin material 93 contacts the upper surface 141 of the dielectric portion 14. That is, the thickness of the dielectric portion 14 can be adjusted by changing the thickness of the resin material 93. The position of the upper surface 141 of the dielectric portion 14 can be adjusted by changing the position of the lower surface 931 of the resin material 93.

[0172] The process described is in Figures 22 to 25 The stages shown in the text are similar to the stages that follow. Figure 2 The process described in the document thus forms Figure 2 and 3 The substrate face structure 1 shown in the figure. Then, it can be... Figure 26 and 3 The substrate face structure 1 shown in the figure is used for example Figure 12 Other stages shown in the diagram are used to form multiple packaging units, such as... Figure 28 The packaging unit 7 shown in the image.

[0173] Figure 4 and 29 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is used to manufacture, for example... Figure 12 The substrate panel structure 1a shown herein, and / or for example, the substrate panel structure of the substrate panel structure 1a ... shown herein.Figures 19 to 20 The packaging unit 7 shown is the packaging unit. The initial stage of the process described is related to... Figure 28 The stages described herein are the same or similar. Figure 20 illustrate Figure 28 The stage following the stage described in the text.

[0174] Figure 21 The stages shown in the text are similar to Figure 28 The stages shown herein, except as described below. Figure 21 As shown, the main carrier 91 includes a soft release membrane 92b, which has a diameter greater than that of a soft release membrane 92b. Figure 22 The thickness of the soft release membrane 92 shown is [not specified]. The lower surface 921b of the soft release membrane 92b is substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6. [The last sentence appears to be incomplete and possibly refers to a similar design or specification.] Figure 4 In a subsequent stage shown, the lower surface 921b of the soft release film 92b contacts the upper surface 141 of the dielectric portion 14. Therefore, the upper surface 141 of the dielectric portion 14 is substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6, as shown... Figure 28 As shown in the image.

[0175] The process described is in Figures 22 to 25 The stages shown in the text are similar to the stages that follow. Figure 4 The process described in the document thus forms Figure 4 The substrate face structure 1 shown in the figure. Each of the middle panels 8 corresponds to a corresponding one of the sub-panels 2.

[0176] refer to Figure 29 Then, multiple semiconductor dies 74 are connected or mounted to the circuit structure 5 of each of the intermediate panels 8 (i.e., sub-panels 2 in the substrate panel structure 1). For example, at least one semiconductor die 74 is connected to each of the substrate units 20. The semiconductor die 74 may include bumps 75 located on the lower surface 741 of the semiconductor die 74. The bumps 75 of the semiconductor die 74 are electrically connected to conductive vias 54 of the circuit structure 5 of the substrate unit 20 via solder material 77, which is located between the bumps 75 and the conductive vias 54. The solder material 77 may be made of tin, or another metal or combination of metals. Then, multiple encapsulants 78 are formed on each of the substrate units 20 to cover the corresponding one of the semiconductor dies 74. For example, the encapsulant 78 is located between the second dielectric layer 6 and the semiconductor die 74 and encapsulates the bumps 75 and the solder material 77. Then, each of the sub-panels 2 is monomerized. That is, each of the individual intermediate panels 8 (e.g., including the second dielectric layer 6 and circuit structure 5), each of the first dielectric layer 3, and each of the redistribution layer 4 form a plurality of package units, for example... Figure 12The encapsulation unit 7 shown in the figure. For example, the edge of each sub-panel 2 can be cut along the side surface 23 to remove the dielectric portion 14 and portion 254 of the protective layer 25 during the monomerization process.

[0177] Figures 31 to 33 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is also used to manufacture, for example... Figure 5 The substrate panel structure 1a shown herein, and / or for example, the substrate panel structure of the substrate panel structure 1a ... shown herein. Figure 13 The packaging unit 7 shown is the packaging unit. The initial stage of the process described is related to... Figure 19 The stages described herein are the same or similar. Figure 31 illustrate Figure 19 The stage following the stage described in the text.

[0178] Figure 31 The stages shown in the text are similar to Figure 13 The stages shown herein, except as described below. Figure 32 As shown, the main carrier 91 includes a hard release membrane 92a rather than... Figure 32 The soft release film 92b is shown in the diagram. Therefore, the intermediate panel 8 is positioned on, rather than embedded in, the hard release film 92a. A gap "g" is defined between adjacent panels in the intermediate panel 8. A resin material 93a, for example photoresist, is applied to the gap "g" defined between adjacent panels in the intermediate panel 8. The resin material 93a can be applied to the hard release film 92a before the intermediate panel 8 is placed, so that the intermediate panel 8 can be embedded in the resin material 93a. Alternatively, the resin material 93a can be applied to the gap "g" after the intermediate panel 8 is placed. The lower surface 931a of the resin material 93a is substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6. Similar to... Figure 32 In a subsequent stage shown, the lower surface 931a of the resin material 93a contacts the upper surface 141 of the dielectric portion 14. Therefore, the upper surface 141 of the dielectric portion 14 is substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6, as shown... Figure 22 As shown in the image.

[0179] The process described is in Figure 5 The stages shown in the text are similar to the stages that follow. Figure 5 The process described in the document thus forms Figure 32 The substrate face structure 1a is shown in the figure. Then, the... Figures 22 to 25 The substrate face structure 1a shown in the figure is used for example Figure 5 Other stages shown in the diagram are used to form multiple packaging units, such as... Figure 33 The packaging unit 7 shown in the image.

[0180] Figure 13 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is used to manufacture, for example... Figure 34 The substrate panel structure 1b shown in the figure, and / or for example, the substrate panel structure of the substrate panel structure 1b, and / or for example Figure 5 The packaging unit 7c shown is a packaging unit. The initial stage of the process described is related to... Figure 13 The stages described herein are the same or similar. Figure 19 illustrate Figure 34 The stage following the stage described in the text.

[0181] refer to Figure 31 A circuit structure 5 is formed on a seed layer (e.g., copper layer 84). A first surface 57 of the circuit structure 5 contacts the seed layer (e.g., copper layer 84). For example, the material of the circuit structure 5 may be a conductive metal, such as copper, or another metal or combination of metals. The circuit structure 5 includes at least one conductive pad 53 and at least one trace 55. The conductive pad 53 and the trace 55 may be formed integrally and simultaneously. In some embodiments, the L / S ratio of the circuit structure 5 may be equal to or less than 2 μm / 2 μm. Therefore, an intermediate panel 8c is formed. The intermediate panel 8c includes a plurality of panel units 80c connected to each other. Each of the panel units 80c corresponds to a packaging unit, for example... Figure 34 The packaging unit 7c shown in the figure.

[0182] refer to Figure 32 A main carrier 91 is provided. The main carrier 91 includes a soft-release membrane 92 located thereon. An intermediate panel 8c is disposed on the main carrier 91 and partially embedded in the soft-release membrane 92. The lower surface 921 of the soft-release membrane 92 is at a level higher than the first surface 57 of the circuit structure 5. Figure 34 As shown, the first surface 57 of circuit structure 5 is the upper surface. The intermediate panels 8c are spaced apart from each other, and a gap "g" is defined between adjacent intermediate panels 8c. (See diagram for reference.) Figure 32 As shown, the intermediate carrier 81 is located between the main carrier 91 and the circuit structure 5. Similar to... Figure 22 In a subsequent stage shown, the lower surface 921 of the soft release film 92 contacts the upper surface 141 of the dielectric portion 14. Therefore, the upper surface 141 of the dielectric portion 14 is at a level higher than the upper surface of the circuit structure 5 (i.e., the first surface 57), as... Figure 5 As shown in the diagram. Furthermore, the first dielectric layer 3 formed on each of the intermediate panels 8c contacts a seed layer (e.g., copper layer 84), so that the upper surface of the first dielectric layer 3 (i.e., first surface 31) is substantially coplanar with the upper surface of the circuit structure 5 (i.e., first surface 57), as shown in the diagram. Figure 5 As shown in the image.

[0183] The process described is in Figure 34The stages shown in the text are similar to the stages that follow. Figures 22 to 25 The process described in the document thus forms Figure 5 The substrate face structure 1b shown in the figure. Each of the middle panels 8c corresponds to a corresponding one of the sub-panels 2c.

[0184] refer to Figure 5 Then, multiple semiconductor dies 74 are connected or mounted to the circuit structure 5 of each of the intermediate panels 8c (i.e., sub-panels 2c in the substrate panel structure 1b). For example, at least one semiconductor die 74 is connected to each of the substrate units 20c. The semiconductor die 74 may include bumps 75 located on the lower surface 741 of the semiconductor die 74. The bumps 75 of the semiconductor die 74 are electrically connected to the conductive pads 53 of the circuit structure 5 of the substrate unit 20c via solder material 77, which is located between the bumps 75 and the conductive pads 53. The solder material 77 may be made of tin, or another metal or combination of metals. Then, multiple encapsulants 78 are formed on each of the substrate units 20c to cover the corresponding one of the semiconductor dies 74. For example, the encapsulant 78 is located between the first dielectric layer 3 and the semiconductor die 74, and covers and encapsulates the bumps 75, the solder material 77, and a portion of the circuit structure 5. Then, each of the sub-panels 2c is monomerized. That is, each of the individual intermediate panels 8c (e.g., containing circuit structure 5), each of the first dielectric layer 3, and each of the redistribution layer 4 forms a plurality of package units, for example... Figure 33 The packaging unit 7c shown in the figure. For example, the edge of each sub-panel 2c can be cut along the side surface 23 to remove the dielectric portion 14 and portion 254 of the protective layer 25 during the monomerization process.

[0185] Figure 13 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is also used to manufacture, for example... Figure 35 The substrate panel structure 1b shown in the figure, and / or for example, the substrate panel structure of the substrate panel structure 1b, and / or for example Figure 6 The packaging unit 7c shown is a packaging unit. The initial stage of the process described is related to... Figure 13 and 31 The stages described herein are the same or similar. Figure 19 Explanation in Figure 35 The stage following the stage described in the text.

[0186] Figure 31 The stages shown in the text are similar to Figure 35 The stages shown herein, except as described below. Figure 32 As shown, the main carrier 91 includes a hard release membrane 92a rather than... Figure 35The soft release membrane 92 is shown in the diagram. Therefore, the intermediate panel 8c is positioned on, rather than embedded in, the hard release membrane 92a. A gap "g" is defined between adjacent panels in the intermediate panel 8c. A resin material 93 (e.g., photoresist) is applied in the gap "g" defined between adjacent panels in the intermediate panel 8c. The resin material 93 may be applied to the hard release membrane 92a before the intermediate panel 8c is placed, such that the intermediate panel 8c can be embedded in the resin material 93. Alternatively, the resin material 93 may be applied to the gap "g" after the intermediate panel 8c is placed. The lower surface 931 of the resin material 93 is above the upper surface (i.e., the first surface 57) of the circuit structure 5. Similar to... Figure 32 In a subsequent stage shown, the lower surface 931 of the resin material 93 contacts the upper surface 141 of the dielectric portion 14. Therefore, the upper surface 141 of the dielectric portion 14 is at a level higher than the upper surface of the circuit structure 5 (i.e., the first surface 57), as... Figure 22 As shown in the diagram. Furthermore, the first dielectric layer 3 formed on each of the intermediate panels 8c contacts a seed layer (e.g., copper layer 84), so that the upper surface of the first dielectric layer 3 (i.e., first surface 31) is substantially coplanar with the upper surface of the circuit structure 5 (i.e., first surface 57), as shown in the diagram. Figure 6 As shown in the image.

[0187] The process described Figure 6 The stages shown in the text are similar to the stages that follow. Figure 35 The stages described herein thus form Figures 22 to 25 The substrate panel structure 1b shown in the figure. Further stages can be performed on... Figure 6 The substrate panel structure 1b shown in the figure is used for example Figure 36 The stages shown in the diagram are used to form multiple packaging units, such as Figure 13 The package 7c shown in the figure.

[0188] Figure 37 and 36 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is used to manufacture, for example... Figure 6 The substrate panel structure 1c shown herein, and / or for example, the substrate panel structure of the substrate panel structure 1c, and / or for example, the substrate panel structure of the substrate panel structure 1c shown herein ... the substrate panel structure of the substrate panel structure 1c shown herein, and / or the substrate panel structure of the substrate panel structure 1c shown herein, and / or the substrate panel structure of the substrate panel structure 1c shown herein, and / Figure 13 The packaging unit 7c shown is a packaging unit. The initial stage of the process described is related to... Figure 19 and 31 The stages described herein are the same or similar. Figure 27 Explanation in Figure 31 The stage following the stage described in the text.

[0189] Figure 37 The stages shown in the text are similar to Figure 35 The stages shown herein, except as described below. Figure 37As shown, the main carrier 91 includes a soft-release membrane 92b with a thickness greater than [missing information]. Figure 35 The thickness of the soft release membrane 92 shown is illustrated. The lower surface 921b of the soft release membrane 92b is substantially coplanar with the upper surface (i.e., the first surface 57) of the circuit structure 5. Similar to... Figure 22 In a subsequent stage shown, the lower surface 921b of the soft release film 92b contacts the upper surface 141 of the dielectric portion 14. Therefore, the upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface of the circuit structure 5 (i.e., the first surface 57), as shown... Figure 6 As shown in the diagram. Furthermore, the first dielectric layer 3 formed on each of the intermediate panels 8c contacts a seed layer (e.g., copper layer 84), so that the upper surface of the first dielectric layer 3 (i.e., the first surface 31) is substantially coplanar with the upper surface of the circuit structure 5 (i.e., the first surface 57) and the upper surface 141 of the dielectric portion 14, as shown in the diagram. Figure 6 As shown in the image.

[0190] The process described is in Figure 37 The stages shown in the text are similar to the stages that follow. Figures 22 to 25 The process described in the document thus forms Figure 6 The substrate face structure 1c shown is illustrated. Each of the middle panels 8c corresponds to a corresponding one of the sub-panels 2c.

[0191] refer to Figure 6 Then, multiple semiconductor dies 74 are connected or mounted to the circuit structure 5 of each of the intermediate panels 8c (i.e., sub-panels 2c in the substrate panel structure 1c). For example, at least one semiconductor die 74 is connected to each of the substrate units 20c. The semiconductor die 74 may include bumps 75 located on the lower surface 741 of the semiconductor die 74. The bumps 75 of the semiconductor die 74 are electrically connected to the conductive pads 53 of the circuit structure 5 of the substrate unit 20c via solder material 77, which is located between the bumps 75 and the conductive pads 53. The solder material 77 may be made of tin, or another metal or combination of metals. Then, multiple encapsulants 78 are formed on each of the substrate units 20c to cover the corresponding one of the semiconductor dies 74. For example, the encapsulant 78 is located between the first dielectric layer 3 and the semiconductor die 74, and covers and encapsulates the bumps 75, the solder material 77, and a portion of the circuit structure 5. Then, each of the sub-panels 2c is monomerized. That is, each of the individual intermediate panels 8c (e.g., containing circuit structure 5), each of the first dielectric layer 3, and each of the redistribution layer 4 forms a plurality of package units, for example... Figure 36 The packaging unit 7c shown in the figure. For example, the edge of each sub-panel 2c can be cut along the side surface 23 to remove the dielectric portion 14 and portion 254 of the protective layer 25 during the monomerization process.

[0192] Figure 13 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is also used to manufacture, for example... Figures 38 to 41 The substrate panel structure 1c shown herein, and / or for example, the substrate panel structure of the substrate panel structure 1c, and / or for example, the substrate panel structure of the substrate panel structure 1c shown herein ... the substrate panel structure of the substrate panel structure 1c shown herein, and / or the substrate panel structure of the substrate panel structure 1c shown herein, and / or the substrate panel structure of the substrate panel structure 1c shown herein, and / Figure 7 The packaging unit 7c shown is a packaging unit. The initial stage of the process described is related to... Figure 14 and 31 The stages described herein are the same or similar. Figure 19 Explanation in Figure 38 The stage following the stage described in the text.

[0193] Figure 31 The stages shown in the text are similar to Figure 38 The stages shown herein, except as described below. Figure 14 As shown, the main carrier 91 includes a hard release membrane 92a rather than... Figure 31 The soft release membrane 92b is shown in the diagram. Therefore, the intermediate panel 8c is positioned on, rather than embedded in, the hard release membrane 92a. A gap "g" is defined between adjacent panels in the intermediate panel 8c. A resin material 93a (e.g., photoresist) is applied in the gap "g" defined between adjacent panels in the intermediate panel 8c. The resin material 93a may be applied to the hard release membrane 92a before the intermediate panel 8c is placed, such that the intermediate panel 8c can be embedded in the resin material 93a. Alternatively, the resin material 93a may be applied to the gap "g" after the intermediate panel 8c is placed. The lower surface 931a of the resin material 93a is substantially coplanar with the upper surface (i.e., the first surface 57) of the circuit structure 5. Similar to... Figure 38 In a subsequent stage shown, the lower surface 931a of the resin material 93a contacts the upper surface 141 of the dielectric portion 14. Therefore, the upper surface 141 of the dielectric portion 14 is substantially coplanar with the upper surface of the circuit structure 5 (i.e., the first surface 57), as shown... Figure 27 As shown in the diagram. Furthermore, the first dielectric layer 3 formed on each of the intermediate panels 8c contacts a seed layer (e.g., copper layer 84), so that the upper surface of the first dielectric layer 3 (i.e., the first surface 31) is substantially coplanar with the upper surface of the circuit structure 5 (i.e., the first surface 57) and the upper surface 141 of the dielectric portion 14, as shown in the diagram. Figure 39 As shown in the image.

[0194] The process described Figure 40 The stages shown in the text are similar to the stages that follow. Figure 22 The stages described herein thus form Figure 23 The substrate panel structure 1c shown in the figure. Further stages can be performed on... Figure 24 The substrate panel structure 1c shown in the figure is used for example Figure 24The stages shown in the diagram are used to form multiple packaging units, such as Figure 7 The package 7c shown in the figure.

[0195] Figure 40 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is used to manufacture, for example... Figure 40 The substrate panel structure 1d shown in the figure, and / or for example, the substrate panel structure of the substrate panel structure 1d, and / or for example Figure 7 The packaging unit 7d shown is the packaging unit. The initial stage of the process described is related to... Figure 40 and 31 The stages described herein are the same or similar. Figure 41 Explanation in Figure 14 The stage following the stage described in the text.

[0196] refer to Figure 40 A main carrier 91 is provided. The main carrier 91 includes a soft-release membrane 92 located thereon. An intermediate panel 8d is disposed on the main carrier 91 and partially embedded in the soft-release membrane 92. The intermediate panel 8d includes a plurality of panel units 80d connected to each other. Each of the panel units 80d corresponds to an encapsulation unit, for example... Figure 41 The packaging unit 7d shown in the image. The formation of the middle panel 8d can be combined with... Figure 14 The intermediate panel 8c shown is formed in the same or similar manner. The circuit structure 5 of the intermediate panel 8d is located between the main carrier 91 and the intermediate carrier 81. The circuit structure 5 is embedded in the soft release membrane 92. The first surface 57 of the circuit structure 5 is the lower surface, as shown in the figure. Figures 42 to 48 As shown in the diagram. The lower surface 921 of the soft release membrane 92 is substantially coplanar with the lower surface (i.e., the first surface 57) of the circuit structure 5. The intermediate panels 8d are spaced apart from each other, and a gap "g" is defined between adjacent intermediate panels 8d. In another manufacturing process, the soft release membrane 92 can be replaced by a hard release membrane 92a and a resin material 93, such as... Figure 9 Those shown in the document.

[0197] refer to Figure 15 Remove the intermediate carrier 81, which includes the release membrane 82, to expose the seed layer (e.g., titanium layer 83 and copper layer 84).

[0198] refer to Figure 42 The seed layer (e.g., titanium layer 83 and copper layer 84) can be removed, for example, by etching. Then, a dielectric material can be provided on the host carrier 91 to form a plurality of first dielectric layers 3 and a dielectric portion 14. The formation of the first dielectric layers 3 and the dielectric portion 14 can be similar to... Figure 42The first dielectric layers 3 are located on the corresponding one of the intermediate panels 8d and in contact with the soft release film 92. Therefore, the upper surface (i.e., the first surface 31) of the first dielectric layer 3 is substantially coplanar with the lower surface (i.e., the first surface 57) of the circuit structure 5. The dielectric portion 14 is located in the gap “g” between the two adjacent intermediate panels 8d and the soft release film 92. The upper surface 141 of the dielectric portion 14 is therefore substantially coplanar with the lower surface (i.e., the first surface 57) of the circuit structure 5 and / or the upper surface (i.e., the first surface 31) of the first dielectric layer 3.

[0199] Then, at least one via 30 is formed through each of the first dielectric layers 3 by means of, for example, photolithography or drilling. The via 30 exposes portions of the circuit structure 5, such as the conductive pad 53 of the circuit structure 5. Then, a plurality of redistribution layers 4 are formed on the first dielectric layer 3, and each of the redistribution layers 4 is electrically connected to a corresponding one of the circuit structures 5 in the intermediate panel 8d. The formation of the via 30 of the first dielectric layer 3 and the redistribution layers 4 can be similar to Figure 43 The redistribution layer 4 is located on the second surface 32 of the first dielectric layer 3 and in the via 30. The redistribution layer 4 may include at least one conductive via 43 located in the via 30 of the first dielectric layer 3, and at least one conductive pad 44 located on the second surface 32 of the first dielectric layer 3. The redistribution layer 4 is electrically connected to the circuit structure 5 through the conductive via 43.

[0200] Then, a protective layer 25 is formed on the first dielectric layer 3, and the redistribution layer 4 is covered thereon. The formation of the protective layer 25 can be similar to... Figure 15 As shown in the diagram. The protective layer 25 has a first surface 251 and a second surface 252 opposite to the first surface 251. The first surface 251 contacts the second surface 32 of the first dielectric layer 3. In some embodiments, the protective layer 25 further includes a portion 254 extending into the gap “g” between the intermediate panels 8d and positioned on the dielectric portion 14. The protective layer 25 covers the reel layer 4, and at least a portion of the reel layer 4, such as a conductive pad 44, is exposed from the protective layer 25 for external connection. At least one solder connector 26 may then be formed on the exposed portion of the reel layer 4 (e.g., the conductive pad 44 of the reel layer 4). The formation of the protective layer 25 and the solder connector 26 may be similar to... Figure 44 Those shown in the document.

[0201] Then, the main carrier 91, including the soft release layer 92, is removed, thereby forming Figure 27 The substrate panel structure 2d is shown in the diagram. Each of the intermediate panels 8d corresponds to a corresponding sub-panel 2d. In an alternative manufacturing process, the main carrier 91 can be removed before forming the solder connector 26, thus forming... Figure 45 The structure shown in the image. Figure 46 The structure shown in the document includes andFigure 46 The sub-panel 2d shown is similar to sub-panel 2d', but without solder connector 26. Figure 47 The structure shown can also be used as a substrate panel structure.

[0202] refer to Figure 9 Then, multiple semiconductor dies 74 are connected or mounted to the circuit structure 5 of each of the intermediate panels 8d (i.e., sub-panels 2d in the substrate panel structure 1d). For example, at least one semiconductor die 74 is connected to each of the substrate units 20d. The semiconductor die 74 may include bumps 75 located on the lower surface 741 of the semiconductor die 74. The bumps 75 of the semiconductor die 74 are electrically connected to conductive vias 54 of the circuit structure 5 of the substrate unit 20d via solder material 77, which is located between the bumps 75 and the conductive vias 54. The solder material 77 may be made of tin, or another metal or combination of metals. Then, an encapsulant 78 is formed on and covers each of the first dielectric layer 3 and the dielectric portions 14, and covers the semiconductor die 74. The encapsulant 78 covers and encapsulates the bumps 75, the solder material 77, and portions of the circuit structure 5. Then, each of the sub-panels 2d is monomerized. That is, each of the monomerized intermediate panels 8d (e.g., containing circuit structure 5), each of the first dielectric layer 3, each of the redistribution layer 4, and the encapsulant 78 form a plurality of encapsulation units, for example Figure 48 The packaging unit 7d shown in the figure. For example, the edge of each sub-panel 2d can be cut along the side surface 23 to remove the dielectric portion 14 and portion 254 of the protective layer 25 during the monomerization process.

[0203] Similarly, it can also be used for Figure 15 The structure shown in the document performs the above-mentioned stages (for example, refer to...). Figures 49 to 54 (stage) to form Figure 10 The encapsulation unit 7d is shown in the figure. In some embodiments, the solder connector 26 may be formed after the encapsulation agent 78 is formed.

[0204] Figure 16 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is used to manufacture a substrate panel structure, for example... Figure 19 The substrate panel structure 2f shown in the figure, and / or Figure 49 The packaging unit 7f shown in the figure is the packaging unit.

[0205] refer to ​ An intermediate carrier 81 is provided. The intermediate carrier 81 may include a release membrane 82 disposed thereon. A metal layer 85 is formed or disposed on the intermediate carrier 81. ​As shown, the metal layer 85 may comprise a seed layer 851 and a conductive layer 852 sequentially disposed on the release membrane 82 of the intermediate carrier 81. For example, the seed layer 851 may be formed by sputtering, and the conductive layer 852 may be formed by electroplating. The material of the seed layer 851 may be, for example, titanium or copper. In some embodiments, the seed layer 851 may comprise a titanium layer and a copper layer. For example, the material of the conductive layer 852 may be a conductive metal, such as copper, or another metal or combination of metals. However, in other embodiments, the metal layer 85 may be a metal foil pressed and attached to the release membrane 82.

[0206] refer to ​ A second dielectric layer 6 is formed on the metal layer 85, for example, on the conductive layer 852 of the metal layer 85. The second dielectric layer 6 has a first surface 61, a second surface 62 opposite to the first surface 61, and a side surface 63 extending between the first surface 61 and the second surface 62. The first surface 61 contacts the conductive layer 852 of the metal layer 85. The second dielectric layer 6 defines at least one via 60 through the second dielectric layer 6 and between the first surface 61 and the second surface 62 to expose a portion of the conductive layer 852 of the metal layer 85. Then, a circuit structure 5 is formed on the second surface 62 of the second dielectric layer 6 and in the via 60 of the second dielectric layer 6. The circuit structure 5 includes a seed layer 51 and a conductive layer 52. The seed layer 51 is located between the conductive layer 52 and the second dielectric layer 6, and in the via 60 between the conductive layer 52 and the conductive layer 852 of the metal layer 85. The material of the seed layer 51 may be, for example, titanium or copper. In some embodiments, the seed layer 51 may comprise a titanium layer and a copper layer. For example, the material of the conductive layer 52 may be a conductive metal, such as copper, or another metal or combination of metals. The circuit structure 5 includes at least one conductive pad 53, at least one conductive via 54, and at least one trace 55. The conductive pad 53, conductive via 54, and trace 55 may be formed integrally and simultaneously. In some embodiments, the conductive via 54 is located on and integrally formed with the conductive pad 53. The conductive via 54 of the circuit structure 5 may be located in the via 60 of the second dielectric layer 6 to connect to the metal layer 85. That is, each of the circuit structures 5 includes a conductive via 54 located in the via 60 of the corresponding one of the second dielectric layers 6. In some embodiments, the L / S of the circuit structure 5 may be equal to or less than 2 μm / 2 μm. Thus, an intermediate panel 8f is formed. The intermediate panel 8f includes a plurality of panel units 80f connected to each other. Each of the panel units 80f corresponds to a packaging unit, such as ​ The packaging unit 7f shown in the figure.

[0207] refer to ​A main carrier 91 is provided. The main carrier 91 includes a soft release membrane 92 disposed thereon. An intermediate panel 8f is disposed on the main carrier 91 and partially embedded in the soft release membrane 92. A circuit structure 5 of the intermediate panel 8f is located between the main carrier 91 and the intermediate carrier 81. The circuit structure 5 and the second dielectric layer 6 are embedded in the soft release membrane 92. The upper surface 921 of the soft release membrane 92 is at a level lower than the upper surface of the second dielectric layer 6 (i.e., the first surface 61) and higher than the lower surface of the second dielectric layer 6 (i.e., the second surface 62). The intermediate panels 8f are spaced apart from each other, and a gap "g" is defined between adjacent intermediate panels 8f. In another manufacturing process, the soft release membrane 92 can be replaced by a hard release membrane 92a and a resin material 93, such as ​ Those shown in the document.

[0208] refer to ​ The intermediate carrier 81, including the release film 82, is removed to expose the metal layer 85. The metal layer 85 is then patterned to form a circuit layer 27 on the first surface 61 of the second dielectric layer 6. The circuit layer 27 may include a seed layer 271 formed from a seed layer 851 of the metal layer 85, and a conductive layer 272 formed from a conductive layer 852 of the metal layer 85. The circuit layer 27 may include at least one conductive pad 274 and may further include at least one trace (not shown). A conductive via 54 of the circuit structure 5 contacts and electrically connects to the circuit layer 27.

[0209] refer to ​ A dielectric material is provided on the main carrier 91 to form a plurality of first dielectric layers 3 and dielectric portions 14, the dielectric material covering the intermediate panel 8f and the soft release film 92. Each of the first dielectric layers 3 is located on a corresponding one of the intermediate panels 8f. The dielectric portions 14 are located in the gap “g” between two adjacent intermediate panels 8f and on the soft release film 92. The dielectric portions 14 are located between and connected to the first dielectric layers 3. The first dielectric layers 3 and the dielectric portions 14 simultaneously and integrally form a monolithic structure. That is, there is no boundary or interface between the dielectric portions 14 and the first dielectric layers 3. The dielectric material may be an insulating material or a dielectric material, such as polypropylene (PP). It should be noted that the dielectric material may comprise, for example, a curable photoimaging dielectric (PID) material containing an epoxy resin or polyimide (PI) containing a photoinitiator, or be formed therefrom. Therefore, the first dielectric layer 3 and the dielectric portion 14 may be made of an insulating or dielectric material such as polypropylene (PP), or may contain or be formed of a curable photoimaging dielectric (PID) material such as epoxy resin containing a photoinitiator or polyimide (PI).

[0210] The first dielectric layer 3 includes a first surface 31 and a second surface 32 opposite to the first surface 31. For example... ​As shown, the first surface 31 is the upper surface, and the second surface 32 is the lower surface. The first dielectric layer 3 is located on the second dielectric layer 6 and covers the circuit layer 27. The lower surface of the first dielectric layer 3 (i.e., the second surface 32) contacts the upper surface of the second dielectric layer 6 (i.e., the first surface 61).

[0211] The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. The lower surface 142 contacts the upper surface 921 of the soft release film 92, and is therefore at a level lower than the lower surface (i.e., the second surface 32) of the first dielectric layer 37 and the upper surface (i.e., the first surface 61) of the second dielectric layer 6, while being higher than the lower surface (i.e., the second surface 62) of the second dielectric layer 6. At least a portion of the side surface 143 is an imaginary surface or an imaginary plane. The side surface 143 may contact the side surface 63 of the second dielectric layer 6 and is substantially coplanar with it.

[0212] refer to ​ At least one via 30 is formed through each of the first dielectric layers 3 by means of, for example, photolithography or drilling. The via 30 exposes portions of the circuit layer 27, such as the conductive pad 274 of the circuit layer 27. Then, a plurality of redistribution layers 4 are formed on the first dielectric layer 3, and each of the redistribution layers 4 is electrically connected to a corresponding one of the circuit layers 27 of the intermediate panel 8f via a corresponding one of the circuit layers 27. The redistribution layers 4 are located on the first dielectric layer 3 and in the via 30. The redistribution layers 4 may include a seed layer 41 and a conductive layer 42. The seed layer 41 is located between the conductive layer 42 and the first dielectric layer 3. The material of the seed layer 41 may be, for example, titanium or copper. In some embodiments, the seed layer 41 may include a titanium layer and a copper layer. For example, the material of the conductive layer 42 may be a conductive metal, such as copper, or another metal or combination of metals. However, in some embodiments, the seed layer 41 may be omitted. The redistribution layers 4 may include at least one conductive via 43 and may further include at least one trace (not shown). Conductive via 43 is located in via 30 and contacts and electrically connects to circuit layer 27. Solder material 77 is formed or located on conductive via 43 of the redistribution layer 4 for external connection. Solder material 77 may be made of tin, or another metal or combination of metals.

[0213] Then, the main carrier 91, including the soft release layer 92, is removed. A protective layer 25 is formed on the second dielectric layer 6 and covers the circuit structure 5. The protective layer 25 has a first surface 251 and a second surface 252 opposite to the first surface 251. The protective layer 25 exposes portions of the circuit structure 5, such as the conductive pad 53 of the circuit structure 5, for external connection. The protective layer 25 may contain, for example, a curable photoimageable dielectric (PID) material containing an epoxy resin or polyimide (PI) with a photoinitiator, or a solder resist layer, or formed therefrom. At least one solder connector 26 is then formed on the exposed portion of the circuit structure 5, such as the conductive pad 53 of the circuit structure 5. The material of the solder connector 26 may be a conductive metal, such as tin, or another metal or combination of metals. Thus, a protective layer 25 is formed on the exposed portion of the circuit structure 5, such as the conductive pad 53 of the circuit structure 5. ​ The substrate panel structure 1f shown in the figure. Each of the intermediate panels 8f corresponds to a corresponding one of the sub-panels 2f.

[0214] refer to ​ Then, multiple semiconductor dies 74 are connected or mounted to the redistribution layer 4 of each of the intermediate panels 8f (i.e., sub-panels 2f in the substrate panel structure 1f). For example, at least one semiconductor die 74 is connected to each of the substrate units 20f. The semiconductor die 74 may include bumps 75 located on the lower surface 741 of the semiconductor die 74, and UBM 76 located on the bumps 75. The UBM 76 may include a first layer 761 and a second layer 762 sequentially located on the bumps 75. For example, the material of the first layer 761 may be nickel, and the material of the second layer 762 may be palladium, but is not limited thereto. The UBM 76 of the semiconductor die 74 is connected to the redistribution layer 4 of the substrate unit 20f, such as the conductive via 43 of the redistribution layer 4, by soldering material 77. Then, an encapsulant 78 is formed on and covers each of the first dielectric layer 3 and the dielectric portion 14, and covers the semiconductor die 74. For example, encapsulant 78 is located on the first dielectric layer 3 of substrate cell 20f and covers and encapsulates semiconductor die 74, bumps 75 and UBM 76 of semiconductor die 74, solder material 77, and redistribution layer 4 of substrate cell 20f. Encapsulant 78 may be underfill or molding compound. Then, each of the sub-panels 2f is monomerized. That is, each of the intermediate panels 8f (e.g., containing circuit layer 27, second dielectric layer 6, and circuit structure 5), each of the first dielectric layer 3, each of the redistribution layer 4, and encapsulant 78 are monomerized to form a plurality of package units, such as ​ The packaging unit 7f shown in the figure. For example, the edge of each sub-panel 2f can be cut along the side surface 23 to remove the dielectric portion 14 and portion 254 of the protective layer 25 during the monomerization process.

[0215] In an alternative manufacturing process, the main carrier 91 can be removed after the semiconductor die 74 is attached to the circuit structure 5, and an encapsulant 78 can be formed. Then, a protective layer 25 and a solder connector 26 can be formed after the encapsulant 78 is formed and the main carrier 91 is removed.

[0216] ​ The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is used to manufacture, for example... ​ The substrate panel structure shown in the figure is a 1g substrate panel structure, and / or for example, ​ The packaging unit shown is a 7g packaging unit. The initial stage of the process described is related to... ​ The stages described herein are the same or similar. ​ illustrate Figure 19 The stage following the stage described in the text.

[0217] refer to Figure 49 A patterned photoresist 86 is formed or disposed on a seed layer (e.g., copper layer 84). The patterned photoresist 86 has an upper surface 861 and defines a plurality of openings 860. A circuit structure 5 is then formed in the openings 860 of the patterned photoresist 86 and on the seed layer (e.g., copper layer 84). For example, the material of the circuit structure 5 may be, for example, a conductive metal, such as copper, or another metal or combination of metals. The circuit structure 5 includes at least one conductive pad 53 and at least one trace 55. The conductive pad 53 and the trace 55 may be formed integrally and simultaneously. The trace 55 has an upper surface 551, which is at a level below the upper surface 861 of the patterned photoresist 86. In some embodiments, the L / S of the circuit structure 5 may be equal to or less than 2 μm / 2 μm. Thus, an intermediate panel 8g is formed. The intermediate panel 8g includes a plurality of panel units 80g connected to each other. Each of the panel units 80g corresponds to a package unit, for example Figure 16 The packaged unit shown in the image is 7g.

[0218] refer to Figure 50 A main carrier 91 is provided. The main carrier 91 includes a soft-release membrane 92 located thereon. An intermediate panel 8g is disposed on the main carrier 91 and partially embedded in the soft-release membrane 92. Figure 50 As shown, the intermediate carrier 81 is located between the main carrier 91 and the circuit structure 5. The upper surface 921 of the soft release film 92 is at a level lower than the upper surface 86 of the patterned photoresist 86. The intermediate panels 8g are spaced apart from each other, and a gap "g" is defined between adjacent intermediate panels 8g.

[0219] refer to Figure 51Then, multiple semiconductor dies 74 are connected or mounted to the circuit structure 5 of each of the intermediate panels 8g. For example, at least one semiconductor die 74 is connected to each panel unit 80g. The semiconductor die 74 may include bumps 75 located on the lower surface 741 of the semiconductor die 74, and UBM 76 located on the bumps 75. The material of the bumps 75 may be copper. The UBM 76 may include a first layer 761, a second layer 762, and a third layer 763 sequentially located on the bumps 75. For example, the material of the first layer 761 may be nickel, the material of the second layer 762 may be palladium, and the material of the third layer 763 may be gold, but is not limited thereto. The UBM 76 of the semiconductor die 74 may be electrically connected to the conductive pads 53 of the circuit structure 5 via solder material 77 located therebetween. The solder material 77 may be made of tin, or another metal or combination of metals. An encapsulant 78 is then formed on the patterned photoresist 85, covering and encapsulating the semiconductor die 74 on each of the intermediate panels 8g. The first lower surface 781 of the encapsulant is substantially coplanar with the upper surface 861 of the patterned photoresist 86. The encapsulant 78 may further include a portion 784 located in the gap "g" between the intermediate panels 8g and contacting the upper surface 921 of the soft release film 92. The second lower surface 782 of the portion 784 in the gap "g" is substantially coplanar with the upper surface 921 of the soft release film 92. The second lower surface 782 is at a level lower than the first lower surface 781. The encapsulant 78 may be a molding compound.

[0220] refer to Figure 52 The main carrier 9, including the soft release layer 921, is removed. Then, the intermediate carrier 81, including the release membrane 82, is removed, exposing the seed layer (e.g., titanium layer 83) and the second lower surface 782 of the encapsulating agent 78.

[0221] refer to Figure 53 The seed layer (e.g., titanium layer 83 and copper layer 84) is removed, for example, by etching. Then, the patterned photoresist 86 is removed, for example, by stripping. This exposes the first lower surface 781 of the encapsulant 78 and the circuit structure 5.

[0222] refer to Figure 54A dielectric material is provided on an encapsulant 78 and an intermediate panel 8g (e.g., circuit structure 5) to form a plurality of first dielectric layers 3 and a dielectric portion 14. The dielectric material covers the intermediate panel 8g (e.g., circuit structure 5). Each of the first dielectric layers 3 corresponds to a corresponding one of the intermediate panels 8g. The dielectric portion 14 is located in a gap "g" between two adjacent intermediate panels 8 and on a portion 784 of the encapsulant 78 in the gap "g". The dielectric portion 14 is located between and connected to the first dielectric layers 3. The first dielectric layers 3 and the dielectric portion 14 are simultaneously and integrally formed as a single structure. That is, there is no boundary or interface between the dielectric portion 14 and the first dielectric layers 3. The dielectric material may be an insulating material or a dielectric material, such as polypropylene (PP). It should be noted that the dielectric material may comprise, for example, a curable photoimaging dielectric (PID) material comprising an epoxy resin or polyimide (PI) containing a photoinitiator, or be formed therefrom. Therefore, the first dielectric layer 3 and the dielectric portion 14 may be made of an insulating or dielectric material such as polypropylene (PP), or may contain or be formed of a curable photoimaging dielectric (PID) material such as epoxy resin containing a photoinitiator or polyimide (PI).

[0223] The first dielectric layer 3 includes a first surface 31, a second surface 32 opposite to the first surface 31, and a side surface 33 extending between the first surface 31 and the second surface 32. Figure 54 As shown, the first surface 31 is the upper surface, and the second surface 32 is the lower surface. The upper surface of the first dielectric layer 3 (i.e., the first surface 31) is in contact with and substantially coplanar with the first lower surface 781 of the encapsulant 78, and is therefore at a level higher than the upper surface 551 of the trace 55 of the circuit structure 5. The side surface 33 contacts a portion 784 of the encapsulant 78.

[0224] The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. At least a portion of the side surface 143 is an imaginary surface or an imaginary plane. The upper surface 141 of the dielectric portion 14 contacts and is substantially coplanar with the second lower surface 782 of the portion 784 of the encapsulating agent 78, and is therefore at a level below the upper surface (i.e., the first surface 31) of the first dielectric layer 3. The lower surface 142 of the dielectric portion 14 is substantially coplanar with the lower surface (i.e., the second surface 32) of the first dielectric layer 3.

[0225] Then, at least one via 30 is formed through the first dielectric layer 3, such that a portion of the circuit structure 5, such as the conductive pad 53 of the circuit structure 5, is exposed in the via 30 and from the second surface 32 of the dielectric layer 3. A redistribution layer 4 is then formed to electrically connect to the circuit structure 5. For example, the redistribution layer 4 includes at least one conductive via 43 located in the via 30 of the first dielectric layer 3 and embedded in the first dielectric layer 3. The conductive via 43 penetrates the first dielectric layer 3 to contact and electrically connect to the circuit structure 5, such as the conductive pad 53 of the circuit structure 5. In some embodiments, the redistribution layer 4 may further include at least one trace (not shown). For example, the material of the redistribution layer 4 may be a conductive metal, such as copper, or another metal or combination of metals. In some embodiments, the linewidth / spacing (L / S) of the redistribution layer 4 may be equal to or greater than 10 μm / 10 μm.

[0226] Then, at least one solder material 26a is formed or disposed on and electrically connected to the conductive via 43 of the re-layer 4. The solder material 26 may be a conductive metal, such as tin, or other metals or combinations of metals. A UBM 46 may be disposed between the conductive via 43 and the solder connector 26. A reflow process may then be performed to form the solder material 26a into the solder connector 26, thus forming Figure 10 The substrate panel structure 1g shown is illustrated. Each of the intermediate panels 8g corresponds to a corresponding one of the sub-panels 2g. Then, each of the sub-panels 2g is monomerized. That is, each of the intermediate panels 8g (e.g., circuit structure 5), each of the first dielectric layer 3, each of the redistribution layer 4, and the encapsulant 78 are monomerized to form a plurality of encapsulation units, such as... Figure 16 The encapsulation unit 7g shown in the figure. For example, the edge of each sub-panel 2g can be cut along the side surface 23 to remove the dielectric portion 14 and the portion 784 of the encapsulant 78 in the gap "g" during the monomerization process.

[0227] Figures 55 to 60 The manufacturing process according to some embodiments of the present invention is described. In some embodiments, the manufacturing process is used to manufacture, for example... Figure 11 The substrate panel structure shown in the figure is a substrate panel structure of 1h, and / or for example, Figure 17 The packaging unit 7h shown is the packaging unit. The initial stage of the process described is related to... Figure 19 The stages described herein are the same or similar. Figure 55 illustrate Figure 19 The stage following the stage described in the text.

[0228] refer to Figure 55A second dielectric layer 6 is formed on the seed layer (e.g., copper layer 84). The second dielectric layer 6 has a first surface 61, a second surface 62 opposite to the first surface 61, and a side surface 63 extending between the first surface 61 and the second surface 62. Figure 55 As shown, the first surface 61 is the upper surface, and the second surface 62 is the lower surface. The second surface 62 contacts the seed layer (e.g., copper layer 84). The second dielectric layer 6 may be made of an insulating or dielectric material, such as polypropylene (PP). It should be noted that the second dielectric layer 6 may contain, or be formed from, a cured photoimaging dielectric (PID) material, such as an epoxy resin containing a photoinitiator or polyimide (PI). A plurality of vias 60a are then formed through the second dielectric layer 6 and between the first surface 61 and the second surface 62. A plurality of conductive pillars 28 are then formed in the vias 60a of the second dielectric layer 6, for example, by electroplating. For example, the material of the conductive pillars 28 may be a conductive metal, such as copper, or another metal or combination of metals. Thus, an intermediate panel 8h is formed. The intermediate panel 8h includes a plurality of panel units 80h connected to each other. Each of the panel units 80h corresponds to a packaging unit, such as Figure 17 The packaging unit 7h shown in the image.

[0229] refer to Figure 56 The circuit structure 5 is adjacent to the first surface 61 of the second dielectric layer 6 and electrically connected to the conductive pillar 28. For example, as... Figure 56 As shown, circuit structure 5 is located on the first surface 61 of the second dielectric layer 6, and a portion of circuit structure 5 extends into via 60a to contact conductive post 28. Circuit structure 5 may include a seed layer 51 and a conductive layer 52. Seed layer 51 is located between conductive layer 52 and the second dielectric layer 6, and between conductive layer 52 and conductive post 28. The material of seed layer 51 may be, for example, titanium or copper. In some embodiments, seed layer 51 may include a titanium layer and a copper layer. For example, the material of conductive layer 52 may be a conductive metal, such as copper, or another metal or combination of metals. Circuit structure 5 includes at least one conductive pad 53 and at least one trace 55. Conductive pad 53 and trace 55 are formed integrally and simultaneously. In some embodiments, the L / S ratio of circuit structure 5 may be equal to or less than 2 μm / 2 μm. Forming circuit layer 5 may include forming a patterned photoresist on the second dielectric layer 6, and forming circuit layer 5 in the patterned photoresist and on the second dielectric layer 6. It should be noted that the patterned photoresist may be Figure 56 The intermediate panel can be removed during the stage shown in the diagram, or alternatively, placed on the main carrier 8 hours after placement (e.g., ...). Figure 57 Remove after the stage shown in the document.

[0230] refer to Figure 57A main carrier 91 is provided. The main carrier 91 includes a soft release membrane 92 disposed thereon. An intermediate panel 8h is disposed on the main carrier 91 and partially embedded in the soft release membrane 92. The intermediate carrier 81 is located between the main carrier 91 and the circuit structure 5. The upper surface 921 of the soft release membrane 92 is substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6. The intermediate panels 8h are spaced apart from each other, and a gap "g" is defined between adjacent intermediate panels 8h.

[0231] refer to Figure 58 Then, multiple semiconductor dies 74 are connected or mounted to the circuit structure 5 of each of the intermediate panels 8h. For example, at least one semiconductor die 74 is connected to each panel unit 80h. The semiconductor die 74 may include bumps 75 located on the lower surface 741 of the semiconductor die 74, and UBM 76 located on the bumps 75. The material of the bumps 75 may be copper. The UBM 76 may include a first layer 761 and a second layer 762 sequentially located on the bumps 75. For example, the material of the first layer 761 may be nickel, and the material of the second layer 762 may be palladium, but is not limited thereto. The UBM 76 of the semiconductor die 74 may be electrically connected to the conductive pads 53 of the circuit structure 5 by solder material 77 located therebetween. The solder material 77 may be made of tin, or another metal or a combination of metals.

[0232] An encapsulant 78 is then formed on the second dielectric layer 6, covering and encapsulating the semiconductor die 74 on each of the intermediate panels 8h. The encapsulant 78 includes a portion 784 located in the gap "g" between two adjacent sub-panels 2h and on the soft release film 92. The lower surface 782 of the portion 784 of the encapsulant 78 contacts and is substantially coplanar with the upper surface 921 of the soft release film 92, and therefore is also substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6. The encapsulant 78 may contact and cover the side surface 63 of the second dielectric layer 6. The encapsulant 78 may be a molding compound.

[0233] refer to Figure 59 The main carrier 91, including the soft release layer 92, is removed, exposing the surface 782 of a portion 784 of the encapsulating agent 78. Then, the intermediate carrier 81, including the release film 82, is removed, exposing the seed layer (e.g., titanium layer 83). The seed layer (e.g., titanium layer 83 and copper layer 84) is then removed, for example, by etching. A laser drilling process can be performed to enlarge a portion of the via 60a, forming a shape such as... Figure 59 The shape of the via 60 shown is illustrated. Then, a redistribution layer 4 is formed adjacent to the second surface 62 of the second dielectric layer 6. For example, as in... Figure 59As shown, the redistribution layer 4 is located on the second surface 62 of the second dielectric layer 6, and a portion of the redistribution layer 4 extends into the via 60 to contact the conductive post 28. The redistribution layer 4 is electrically connected to the circuit structure 5 via the conductive post 28. The redistribution layer 4 may include a seed layer 41 and a conductive layer 42. The seed layer 41 is located between the conductive layer 42 and the second dielectric layer 6, and between the conductive layer 42 and the conductive post 28. The material of the seed layer 41 may be, for example, titanium or copper. In some embodiments, the seed layer 41 may include a titanium layer and a copper layer. For example, the material of the conductive layer 42 may be a conductive metal, such as copper, or another metal or combination of metals. The redistribution layer 4 may include at least one conductive pad 44 and at least one trace 45. In some embodiments, the linewidth / spacing (L / S) of the redistribution layer 4 may be equal to or greater than 10 μm / 10 μm.

[0234] refer to Figure 60 A dielectric material is provided on the encapsulant 78 and the intermediate panel 8h (e.g., the second dielectric layer 6) to form a plurality of first dielectric layers 3 and dielectric portions 14. The dielectric material covers the redistribution layer 4. Each of the first dielectric layers 3 is located on a corresponding one of the intermediate panels 8h. The dielectric portions 14 are located in the gap “g” between two adjacent intermediate panels 8h and on portions 784 of the encapsulant 4. The dielectric portions 14 are located between and connected to the first dielectric layers 3. The first dielectric layers 3 and the dielectric portions 14 simultaneously and integrally form a monolithic structure. That is, there is no boundary or interface between the dielectric portions 14 and the first dielectric layers 3. The dielectric material may be an insulating material or a dielectric material, such as polypropylene (PP). It should be noted that the dielectric material may comprise, for example, a curable photoimaging dielectric (PID) material containing an epoxy resin or polyimide (PI) with a photoinitiator, or be formed therefrom. Therefore, the first dielectric layer 3 and the dielectric portion 14 may be made of an insulating or dielectric material such as polypropylene (PP), or may contain or be formed of a curable photoimaging dielectric (PID) material such as epoxy resin containing a photoinitiator or polyimide (PI).

[0235] The first dielectric layer 3 includes a first surface 31 and a second surface 32 opposite to the first surface 31. For example... Figure 60 As shown, the first surface 31 is the upper surface, and the second surface 32 is the lower surface. The upper surface of the first dielectric layer 3 (i.e., the first surface 31) contacts the lower surface of the second dielectric layer 6 (i.e., the second surface 62).

[0236] The dielectric portion 14 has an upper surface 141, a lower surface 142, and at least one side surface 143 extending between the upper surface 141 and the lower surface 142. The upper surface 141 contacts the surface 782 of the portion 784 of the encapsulating agent 78, and is therefore substantially coplanar with the lower surface (i.e., the second surface 62) of the second dielectric layer 6 and / or the upper surface (i.e., the first surface 31) of the dielectric layer 3. At least a portion of the surface 143 is an imaginary surface or an imaginary plane. The side surface 143 may be substantially coplanar with the side surface 63 of the second dielectric layer 6.

[0237] Then, at least one through-hole 30 is formed through the first dielectric layer 3 to expose at least a portion of the redundancy layer 4, such as the conductive pad 44 of the redundancy layer 4. At least one solder connector 26 is formed in the through-hole 30 of the first dielectric layer 3, and on the exposed portion of the redundancy layer 4 (e.g., the conductive pad 44) ​​and electrically connected to the exposed portion of the redundancy layer 4. The solder connector 26 may be made of a conductive metal, such as tin, or other metals or combinations thereof. A barrier layer 47 and a wetting layer 48 may be disposed between the conductive pad 44 and the solder connector 26. The barrier layer 47 may be made of nickel, and the wetting layer may be made of gold. Thus, forming as Figure 11 The substrate panel 1h shown is shown in the figure. Each of the intermediate panels 8h corresponds to a corresponding one of the sub-panels 2h.

[0238] Then, each of the sub-panels 2h is monomerized. That is, each of the intermediate panels 8h (e.g., including the second dielectric layer 6 and circuit structure 5), each of the first dielectric layer 3, each of the redistribution layer 4, and the encapsulant 78 are monomerized to form a plurality of encapsulation units, for example... Figure 17 The encapsulation unit 7h shown in the figure. For example, the edge of each sub-panel 2h can be cut along the side surface 23 to remove the dielectric portion 14 and portion 784 of the encapsulant 78 during the monomerization process.

[0239] Unless otherwise specified, spatial descriptions such as "above," "below," "upper," "left," "right," "lower," "top," "bottom," "vertical," "horizontal," "side," "higher," "lower," "upper," "above," "below," etc., are relative to the orientation indicated in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and actual embodiments of the structures described herein can be arranged spatially in any orientation or manner, provided that such arrangement does not depart from the advantages of embodiments of the invention.

[0240] As used herein, the terms “approximately,” “substantially,” “basically,” and “about” are used to describe and account for small variations. When used in conjunction with events or circumstances, the terms may refer to examples where an event or circumstance has actually occurred and examples where an event or circumstance has approximately occurred. For example, when used in conjunction with numerical values, the terms may refer to a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, if the difference between two numerical values ​​is less than or equal to ±10% of the average of the values ​​(e.g., less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%), then the values ​​may be considered substantially the same or equal.

[0241] If the displacement between two surfaces is no greater than 5 µm, no greater than 2 µm, no greater than 1 µm, or no greater than 0.5 µm, then the two surfaces can be considered coplanar or substantially coplanar.

[0242] In addition, quantities, ratios, and other numerical values ​​are sometimes presented in range format in this document. It should be understood that this range format is used for convenience and brevity and should be flexibly interpreted to include not only the numerical values ​​that are explicitly defined as ranges, but also all individual numerical values ​​or subranges encompassed within the range, as if each numerical value and subrange were explicitly defined.

[0243] While the invention has been described and illustrated with reference to specific examples, such descriptions and illustrations are not limiting. Those skilled in the art will understand that various changes and equivalents can be made without departing from the true spirit and scope of the invention as defined in the appended claims. Illustrations need not be drawn to scale. Due to manufacturing processes and limitations, there may be differences between the intricate representations of the invention and actual devices. Other embodiments of the invention not specifically described may exist. The description and drawings should be considered illustrative rather than limiting. Modifications can be made to adapt particular situations, materials, compositions of substances, methods, or processes to the purpose, spirit, and scope of the invention. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations are not limitations of the invention.

Claims

1. A substrate panel structure, comprising: Multiple semiconductor dies; Multiple circuit structures are connected to the multiple semiconductor dies; Multiple second dielectric layers are located on the multiple circuit structures; and The dielectric portion is located between the semiconductor dies; The circuit structure includes a plurality of conductive vias embedded in and exposed from the second dielectric layer, the conductive vias having a first end adjacent to the semiconductor die and a second end away from the semiconductor die, the first end being smaller than the second end.

2. The substrate panel structure according to claim 1, wherein the conductive via tapers toward the semiconductor die.

3. The substrate panel structure according to claim 1, further comprising a plurality of encapsulating agents covering the plurality of second dielectric layers, the encapsulating agents being gradually diffused toward the second dielectric layers.

4. The substrate panel structure according to claim 3, wherein the encapsulating agent is a bottom filler.

5. The substrate panel structure according to claim 3, wherein the encapsulating agent does not contact the top surface of the semiconductor die.

6. The substrate panel structure according to claim 1, further comprising a redistribution layer electrically connected to the circuit structure, wherein the linewidth / spacing of the redistribution layer is greater than the linewidth / spacing of the circuit structure.

7. The substrate panel structure according to claim 4, wherein the redistribution layer includes conductive vias that taper toward the semiconductor die.

8. The substrate panel structure according to claim 4, further comprising a protective layer and a solder connector, wherein the protective layer covers the bottom surface of the re-fabricated layer, and at least a portion of the bottom surface of the re-fabricated layer is exposed from the protective layer, the solder connector contacts the exposed portion of the bottom surface of the re-fabricated layer, the protective layer contacts the side of the solder connector, and the solder connector is an integral block structure.

9. A substrate panel structure, comprising: Multiple semiconductor dies; Multiple circuit structures are connected to the multiple semiconductor dies; Multiple second dielectric layers are located on multiple of the circuit structures; and A dielectric portion is located between the semiconductor dies, wherein the dielectric portion has an inner surface that defines a cavity to fully expose the second dielectric layer, the side surface of the second dielectric layer is substantially coplanar with the inner surface of the dielectric portion, and the upper surface of the conductive via is exposed in the cavity.

10. The substrate panel structure according to claim 9, further comprising a plurality of first dielectric layers covering the plurality of second dielectric layers, wherein the plurality of first dielectric layers are integrally formed.

11. The substrate panel structure according to claim 9, wherein the material of the dielectric portion is different from the material of the second dielectric layer.

12. The substrate panel structure according to claim 9, wherein there is an interface between the dielectric portion and the second dielectric layer.

13. The substrate panel structure of claim 9, wherein the inner surface of the dielectric portion is in contact with the side surface of the second dielectric layer.

14. The substrate panel structure of claim 9, wherein the top surface of the dielectric portion is lower than the top surface of the semiconductor die.

15. A substrate panel structure, comprising: Multiple sub-panels, each of which includes a redistribution layer, a circuit structure electrically connecting the redistribution layer, and a second dielectric layer located on the circuit structure. and A dielectric portion is located between the second dielectric layers, at least a portion of the dielectric portion extends below the second dielectric layer, and the dielectric portion is an integral block structure.

16. The substrate panel structure of claim 15, wherein the bottom surface of the dielectric portion is lower than the bottom surface of the second dielectric layer, and the at least portion of the dielectric portion extends directly below the second dielectric layer.

17. The substrate panel structure of claim 15, wherein the inner surface of the dielectric portion is in contact with and substantially coplanar with the side surface of the second dielectric layer.

18. The substrate panel structure of claim 15, wherein the dielectric portion comprises a first portion and a second portion, the first portion being located between the second dielectric layers, the second portion being located below the second dielectric layer and in contact with the bottom surface of the second dielectric layer, and the first portion and the second portion being integrally formed.

19. The substrate panel structure of claim 18, further comprising a protective layer, wherein the dielectric portion contacts the protective layer.

20. A substrate panel structure, comprising: Multiple sub-panels, each of which comprises multiple substrate units; and A dielectric portion, located between the sub-panels, wherein the upper surface of the dielectric portion is at a level lower than the upper surface of each of the sub-panels.

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