Array substrate, display panel and display device

Abstract

The invention discloses an array substrate, a display panel and a display device. The array substrate comprises: a substrate (1); a first conductive layer (20) located on one side of the substrate (1); the first conductive layer (20) comprises: a plurality of first electrodes (2); the second conducting layer (30) is located on the side, away from the substrate (1), of the first conducting layer (20), and the second conducting layer (30) and the first conducting layer (20) are mutually insulated; the second conductive layer (30) comprises: a plurality of second electrodes (3); the orthographic projection of the second electrode (3) on the substrate (1) is overlapped with the orthographic projection of the first electrode (2) on the substrate (1); the second electrode (3) is provided with a plurality of slits (F); wherein an end portion of the slit (F) has at least one first corner portion (A); a plurality of first notches (Q1) are formed in the edge of the first electrode (2), and at least one second corner part (B) is arranged on the side, facing the slit (F), of each first notch (Q1); the orthographic projection of the first notch (Q1) on the substrate (1) and the orthographic projection of the slit (F) on the substrate (1) are not overlapped, and the second corner part (B) and the first corner part (A) are oppositely arranged.

Description

Array substrate, display panel and display device Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate, a display panel, and a display device. Background Technology

[0002] With the continuous upgrading of the ultra-high-definition video industry, display panels have become basically ubiquitous. At present, display panels (such as LCD TVs) are developing towards larger sizes, higher resolution, and higher transmittance. However, display panels using Advanced Super Dimension Switching (ADS) technology have dark lines at the edges and center of pixels, resulting in lower transmittance and contrast.

[0003] Summary of the Invention

[0004] This disclosure provides an array substrate, a display panel, and a display device. The array substrate includes:

[0005] Substrate;

[0006] A first conductive layer is located on one side of the substrate; the first conductive layer includes: a plurality of first electrodes;

[0007] A second conductive layer is located on the side of the first conductive layer away from the substrate and is insulated from the first conductive layer; the second conductive layer includes: a plurality of second electrodes; the orthographic projection of the second electrodes on the substrate overlaps with the orthographic projection of the first electrodes on the substrate; the second electrodes have a plurality of slits;

[0008] The slit has at least one first corner at its end; the first electrode has multiple first notches at its edge, and the side of the first notch facing the slit has at least one second corner; the orthographic projection of the first notch on the substrate does not overlap with the orthographic projection of the slit on the substrate, and the second corner is disposed opposite to the first corner.

[0009] In one possible implementation, the at least one first corner portion includes: a first sharp corner; the at least one second corner portion includes: a second sharp corner disposed opposite to the first sharp corner; the first sharp corner and the second sharp corner have a first gap between their orthographic projections on the substrate and the orthographic projections on the substrate.

[0010] In one possible implementation, the at least one first corner portion includes: a first chamfer; the at least one second corner portion includes: a second chamfer disposed opposite to the first chamfer; the first chamfer has a second gap between its orthographic projection on the substrate and the second chamfer's orthographic projection on the substrate.

[0011] In one possible implementation, for the same first notch, the second chamfer is opposite to the first chamfer at one of the slit ends, and the second sharp corner is opposite to the first sharp corner at the adjacent other slit end.

[0012] In one possible implementation, the second electrode includes: two first outer edges extending along a first direction, the extension direction of the first outer edges being the same as the arrangement direction of the plurality of slits; the orthographic projection of the first notch on the substrate overlaps with the orthographic projection of the first outer edges on the substrate.

[0013] In one possible implementation, the first notch includes two first edges disposed opposite to each other; the extension direction of the first edges is parallel to the extension direction of the slit, and the portion of the region between the extension lines of the two first edges of the same first notch in the orthographic projection on the substrate overlaps with the region between two adjacent slits in the orthographic projection on the substrate.

[0014] In one possible implementation, the first notch further includes: a second edge, one end of which is connected to a first edge and the other end of which is connected to another first edge;

[0015] The orthographic projection of the second edge onto the substrate and the orthographic projection of the slit onto the substrate are both located on the same side of the first outer edge; and the maximum distance between the orthographic projection of the second edge onto the substrate and the orthographic projection of the first outer edge onto the substrate is less than or equal to the maximum distance between the orthographic projection of the slit onto the substrate and the orthographic projection of the first outer edge onto the substrate.

[0016] In one possible implementation, the edge of the first electrode also has a plurality of second notches; the second notches are located between two adjacent first notches, and the orthographic projection of the second notches on the substrate is opposite to the orthographic projection of the first sharp corner on the substrate.

[0017] In one possible implementation, the second notch has two third sharp angles on the side facing the slit.

[0018] In one possible implementation, the width of the second notch in the first direction is smaller than the width of the first notch parallel to the first direction, the first direction being the same as the arrangement direction of the slits;

[0019] The length of the second notch perpendicular to the first direction is equal to the length of the first notch perpendicular to the first direction.

[0020] In one possible implementation, the first outer edge has a break at a certain location; the edge of the first electrode also has a plurality of third notches; the portion of the third notches projected onto the substrate at least partially overlaps with the projection of the break onto the substrate at the same location.

[0021] In one possible implementation, the second electrode includes: a plurality of branches, the slit being located between adjacent branches; each branch having a fourth apex at the break location; the orthographic projection of the fourth apex onto the substrate overlaps with a portion of the orthographic projection of the third notch onto the substrate.

[0022] The third notch has a fifth sharp angle that is positioned opposite the fourth sharp angle.

[0023] In one possible implementation, the shape of the third notch is the same as the shape of the first notch.

[0024] In one possible implementation, a plurality of the branches are spaced apart between adjacent fractures; the fractures of the two first outer edges are misaligned.

[0025] In one possible implementation, the second electrode includes: a first branch group and a second branch group arranged along a first direction; both the first branch group and the second branch group include multiple branches; the branches of the first branch group and the second branch group extend in different directions; in the boundary region between the first branch group and the second branch group, some of the branches are broken and have a sixth sharp angle at the broken end;

[0026] The first electrode further includes: a plurality of first hollows; the orthographic projection of the plurality of first hollows on the substrate is the orthographic projection of the boundary area between the first branch group and the second branch group on the substrate, and the orthographic projection of the first hollows on the substrate does not overlap with the orthographic projection of the sixth sharp corner on the substrate; the first hollow includes a first hollow end and a second hollow end, and the width of the first hollow gradually decreases in the first direction from the first hollow end to the second hollow end;

[0027] The second hollowed-out end is positioned opposite to the sixth pointed corner in the substrate, as its orthogonal projection onto the substrate.

[0028] In one possible implementation, the orthographic projection of the end of the sixth apex along an extension line perpendicular to the first direction onto the substrate overlaps with the orthographic projection of the first cutout onto the substrate.

[0029] In one possible implementation, the first cutout is located within the orthographic projection of the substrate, as the slit is projected onto the substrate.

[0030] In one possible implementation, the second electrode includes: a first branch group and a second branch group arranged along a first direction; both the first branch group and the second branch group include multiple branches; the ends of each branch of the first branch group are disconnected from each other on a first side and connected to each other on a second side; the ends of each branch of the second branch group are disconnected from each other on the second side and connected to each other on the first side.

[0031] In the region where the first branch group is located, the orthographic projection of each of the first notches on the substrate is located on the second side; in the region where the second branch group is located, the orthographic projection of each of the first notches on the substrate is located on the first side.

[0032] This disclosure also provides a display panel, which includes the array substrate as described in this disclosure.

[0033] In one possible implementation, the display panel further includes: a first polarizer attached to the light-emitting side of the display panel; the first polarizer includes: a liquid crystal layer, the long axis of which is perpendicular to the substrate.

[0034] In one possible implementation, the liquid crystal layer comprises: liquid crystal, and a dichroic dye mixed in the liquid crystal.

[0035] In one possible implementation, the dichroic dye comprises one or a combination of the following:

[0036] In one possible implementation, the first polarizer further includes an alignment film layer in contact with the liquid crystal layer.

[0037] This disclosure also provides a display device, which includes the display panel as described in this disclosure. Attached Figure Description

[0038] Figure 1 is a schematic diagram of the light effect simulation of a conventional pixel;

[0039] Figure 2A is a partial schematic diagram of an array substrate provided in an embodiment of this disclosure;

[0040] Figure 2B can be one of the enlarged schematic diagrams of the dashed box S1 in Figure 2A;

[0041] Figure 2C can be a schematic diagram of a single film layer of the first conductive layer in Figure 2B;

[0042] Figure 2D is a schematic diagram of a single film layer of the second conductive layer in Figure 2B;

[0043] Figure 2E can be a schematic diagram of a single film layer of the first conductive layer in Figure 2A;

[0044] Figure 2F can be a schematic diagram of a single film layer of the gate line layer in Figure 2A;

[0045] Figure 2G can be a schematic diagram of a single film layer with the active layer in Figure 2A;

[0046] Figure 2H can be a schematic diagram of a single film layer of the data line layer in Figure 2A;

[0047] Figure 2I can be a schematic diagram of a single film layer of the second conductive layer in Figure 2A;

[0048] Figure 2J is a schematic diagram of the black matrix corresponding to Figure 2A;

[0049] Figure 3A is a second partial schematic diagram of the array substrate provided in an embodiment of this disclosure;

[0050] Figure 3B is an enlarged view of Figure 3A at the dashed box S2;

[0051] Figure 4A is a third partial schematic diagram of the array substrate provided in the embodiment of this disclosure;

[0052] Figure 4B is an enlarged view of Figure 4A at point S3 (dashed box);

[0053] Figure 4C can be a schematic diagram of a single film layer of the first conductive layer in Figure 4B;

[0054] Figure 4D is a schematic diagram of a single film layer of the second conductive layer in Figure 4B;

[0055] Figure 4E can be a schematic diagram of a single film layer of the first conductive layer in Figure 4A;

[0056] Figure 4F can be a schematic diagram of a single film layer of the second conductive layer in Figure 2A;

[0057] Figure 4G can be seen as an enlarged schematic diagram of Figure 4E at the dashed box S4.

[0058] Figure 5 is a fourth partial schematic diagram of the array substrate provided in the embodiments of this disclosure;

[0059] Figure 6 shows a typical pixel light effect simulation diagram;

[0060] Figure 7 is a pixel light effect simulation diagram provided in an embodiment of this disclosure;

[0061] Figure 8A is a schematic diagram of the electric field distribution at the dark field section of the pixel edge in a conventional pixel.

[0062] Figure 8B is a schematic diagram of the brightness distribution of a regular pixel at the dark field section along the pixel edge;

[0063] Figure 9A is a schematic diagram of the electric field distribution at the dark field section position of the pixel edge provided in an embodiment of the present invention;

[0064] Figure 9B is a schematic diagram of the brightness distribution of a pixel at the dark field section position along the pixel edge provided in an embodiment of the present invention;

[0065] Figure 10 is a schematic diagram of the first polarizer provided in an embodiment of this disclosure;

[0066] Figure 11 is a comparative schematic diagram of light passing through a conventional polarizer and a first polarizer provided in the embodiments of this disclosure. Detailed Implementation

[0067] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. Implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0068] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that an element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0069] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviation from the specific value, as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%. In this specification, “substantially the same” may mean a difference of less than 10%.

[0070] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0071] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which the constituent elements are described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0072] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0073] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on the "elements that have a certain electrical function," as long as they enable the transmission of electrical signals between the connected components. Examples of "elements that have a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with one or more functions.

[0074] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain terminal, drain region, or drain) and the source electrode (source terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0075] Furthermore, the gate of a transistor can be referred to as the control electrode. In cases where transistors with opposite polarities are used, or where the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0076] In this specification, "parallel" refers to a state in which two straight lines form an angle of -10° or more and less than 10°, and therefore can include a state in which the angle is -5° or more and less than 5°. Similarly, "perpendicular" refers to a state in which two straight lines form an angle of 80° or more and less than 100°, and therefore can include a state in which the angle is 85° or more and less than 95°.

[0077] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0078] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0079] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0080] In ADS mode display products with horizontal slits, under L255 screen conditions, the liquid crystal electric field is disordered at the edge of the pixel along the data line direction, and the proportion of ineffective electric field is too large, resulting in obvious dark fields in that area (as shown in Figure 1, where the left side is an enlarged schematic diagram of the area within the dotted frame on the right). The dark edges cause the overall light efficiency of the ADS mode display panel to be 3% to 5% lower, and the contrast ratio to drop by 60 to 100.

[0081] In view of this, referring to Figures 2A-2I, where Figure 2B can be a partially enlarged schematic diagram of Figure 2A at the dashed box S1, Figure 2C can be a schematic diagram of a single film of the first conductive layer in Figure 2B, Figure 2D can be a schematic diagram of a single film of the second conductive layer in Figure 2B, Figure 2E can be a schematic diagram of a single film of the first conductive layer in Figure 2A, Figure 2F can be a schematic diagram of a single film of the gate line layer in Figure 2A, Figure 2G can be a schematic diagram of a single film of the active layer in Figure 2A, Figure 2H can be a schematic diagram of a single film of the data line layer in Figure 2A, and Figure 2I can be a schematic diagram of a single film of the second conductive layer in Figure 2A, this disclosure provides an array substrate, comprising: an array substrate, wherein:

[0082] Substrate 1;

[0083] A first conductive layer 20 is located on one side of the substrate 1; the first conductive layer 20 includes a plurality of first electrodes 2;

[0084] The second conductive layer 30 is located on the side of the first conductive layer 20 away from the substrate 1 and is insulated from the first conductive layer 20. The second conductive layer 30 includes: a plurality of second electrodes 3; the orthographic projection of the second electrodes 3 onto the substrate 1 overlaps with the orthographic projection of the first electrodes 2 onto the substrate 1; the second electrodes 3 have a plurality of slits F.

[0085] The slit F has at least one first corner A at its end; the edge of the first electrode 2 has a plurality of first notches Q1, and the side of the first notch Q1 facing the slit F has at least one second corner B; the orthographic projection of the first notch Q1 onto the substrate 1 does not overlap with the orthographic projection of the slit F onto the substrate 1, and the second corner B is disposed opposite to the first corner A.

[0086] In ADS display mode, the liquid crystal deflection requires a greater horizontal electric field component. By changing the structure of the first conductive layer 20 and the second conductive layer 30, the electric field distribution between the two electrodes is altered, increasing the horizontal component of the electric field acting on the liquid crystal and effectively improving light efficiency. In ADS display mode, charge easily accumulates at the sharp points of the second electrode 3 (e.g., in the middle or at the edge of the pixel electrode), resulting in a dense distribution of electric field lines between the second conductive layer 30 and the first conductive layer 20, a larger vertical electric field component, and a disordered electric field region with a larger proportion of dark fields. In this embodiment, the first electrode 2 has a first notch Q1 at a position corresponding to the end of the slit F of the second electrode 3. The orthographic projection of the first notch Q1 onto the substrate 1 does not overlap with the orthographic projection of the slit F onto the substrate 1. That is, the orthographic projection of the first notch Q1 onto the substrate 1 and the orthographic projection of the slit F onto the substrate 1 are not identical. There is a horizontal spacing between them, which can increase the horizontal component electric field between the second conductive layer 30 and the first conductive layer 20 at the first corner A of the slit F; moreover, the first notch Q1 is provided with a second corner B corresponding to the first corner A of the slit F. For the dense electric field generated by charge accumulation at the first corner A of the end of the slit F, the second corner B of the first notch Q1 can have a pulling and balancing effect, which can reduce the vertical electric field between the second conductive layer 30 and the first conductive layer 20 at the first corner A of the slit F, reduce the dark field ratio, and thus improve the light efficiency and contrast of the display panel.

[0087] Specifically, see Figures 6 and 7. Figure 6 is a conventional pixel light effect simulation diagram, and Figure 7 is a pixel light effect simulation diagram provided by the embodiment of this disclosure. It has been verified that compared with the light effect and contrast of conventional display panels, the light effect and contrast of the display panel provided by the embodiment of this disclosure are improved by 1.6% in transmittance and by about 50 in contrast. To clearly compare the effect of the first notch Q1 on the improvement of pixel light efficiency, the electric field equipotential line distribution curve and the brightness distribution curve were extracted from the dark field longitudinal section of the pixel edge along the data line direction, as shown in Figures 8A, 8B, 9A, and 9B. Figure 8A is a schematic diagram of the electric field distribution at the dark field section of a conventional pixel edge; Figure 8B is a schematic diagram of the brightness distribution at the dark field section of a conventional pixel edge; Figure 9A is a schematic diagram of the electric field distribution at the dark field section of a pixel edge (e.g., along the first outer edge w1 in Figure 2A) provided by the embodiment of the present invention; and Figure 9B is a schematic diagram of the brightness distribution at the dark field section of a pixel edge provided by the embodiment of the present invention. In Figures 8A and 9A, the area within the lower dashed box is the insulating layer J between the first conductive layer 20 and the second conductive layer 30. Above the insulating layer J is the second conductive layer 30, above the second conductive layer 30 is the alignment layer PI, and above the alignment layer PI is the liquid crystal layer (where small columnar bodies represent liquid crystals). (Crystal C), the arrow indicates the direction of force on the liquid crystal, and the black curved line represents the electric field line (equipotential line); the horizontal axis of Figures 8B and 9B represents different positions along the dark field section of the pixel edge (such as along the first outer edge w1 in Figure 2A), and the horizontal axis of Figures 8B and 9B represents the transmittance; combined with Figures 8A and 9B, it can be seen that at the position of the dark field section of the pixel edge (such as along the first outer edge w1 in Figure 2A), after setting the first notch Q1, the electric field distribution changes significantly (the horizontal component of the electric field increases), the liquid crystal arrangement changes accordingly, and the light efficiency is significantly improved; see also the transmittance distribution curve along the longitudinal section in Figure 9B, the integral area of ​​the curve is the brightness of the pixel edge, which is significantly improved compared to the dark area of ​​the pixel edge (transmittance curve) in Figure 8B, that is, in the embodiment of this disclosure, the light efficiency of the pixel in the edge area is significantly improved (the L255 gray level is significantly increased), and the contrast ratio CR = L255 / L0 formula, the L0 of the two pixels is the same, the L255 brightness of the new pixel is significantly improved, so the contrast ratio is improved.

[0088] Optionally, the first conductive layer 20 can be a transparent conductive layer, and the second conductive layer 30 can be a transparent conductive layer; alternatively, the first conductive layer 20 can be a common electrode layer; the second conductive layer 30 can be a pixel electrode layer, and the second electrode 3 can be a pixel electrode. In this case, the first conductive layer is a common electrode layer as an example, but of course, the first conductive layer can also be a pixel electrode layer, and the second conductive layer can be a common electrode layer.

[0089] Optionally, the first electrode 2 can be a block structure, and the size of the first electrode 2 can be approximately equal to the size of the second electrode 3. Optionally, as shown in Figure 2D, the first conductive layer 20 also includes multiple first connecting lines 21, and multiple first electrodes 2 in the same row of first electrodes 2 can be connected into a single structure through the first connecting lines 21; Optionally, in the first conductive layer 20, each first electrode 2 in the same row of first electrodes 2 can also be an independent structure that is not connected to each other.

[0090] In one possible implementation, referring to Figures 2B-2D, at least one first corner portion A includes a first sharp corner A1; at least one second corner portion B includes a second sharp corner B1 disposed opposite to the first sharp corner A1; a first gap J1 exists between the orthographic projection of the first sharp corner A1 onto the substrate 1 and the orthographic projection of the second sharp corner B1 onto the substrate 1. In this embodiment of the present disclosure, for the first sharp corner A1 of the first corner portion A, the second corner portion B can be provided with a corresponding second sharp corner B, which can have a better electric field pulling balance effect, effectively increasing the horizontal electric field component between the two, thereby reducing the dark field ratio, improving the transmittance and contrast of the display panel, and at the same time, the "sharp-to-sharp" setting method can also avoid excessive pulling, which could lead to an imbalance between the two and cause a new dark field.

[0091] Optionally, the first apex A1 can be the included angle formed by two straight sides, and the included angle of the first apex A1 can be in the range of 0° to 90°; optionally, the second apex B1 can be the included angle formed by two straight sides, and the included angle of the second apex B1 can be in the range of 0° to 90°; optionally, the angles of the first apex A1 and the second apex B1 can be equal.

[0092] In one possible implementation, referring to Figures 2B-2D, at least one first corner portion A includes a first chamfer A2; at least one second corner portion B includes a second chamfer B2 disposed opposite to the first chamfer A2; a second gap J2 exists between the orthographic projection of the first chamfer A2 onto the substrate 1 and the orthographic projection of the second chamfer B2 onto the substrate 1. In this embodiment of the present disclosure, for the first chamfer A2 of the first corner portion A, the second corner portion B can be provided with a corresponding second chamfer B2, which can have a better electric field tension balance effect, effectively increasing the horizontal electric field component between the two, thereby reducing the proportion of dark field, improving the transmittance and contrast of the display panel, and at the same time, by setting up an "arc-to-arc", it can also avoid excessive tension, which could lead to an imbalance between the two and cause a new dark field.

[0093] Optionally, the first chamfer A2 can be understood as cutting the corner at the end of the slit F to form a bevel. Optionally, as shown in Figure 2D, the first chamfer A2 can have a bevel; optionally, in actual manufacturing, due to limitations in process precision, the first chamfer A2 can also have an arc edge, or it can also have a broken edge. Similarly, the second chamfer B2 can be understood as cutting the corner at the end of the first notch Q1 to form a bevel. Optionally, as shown in Figure 2C, the second chamfer B2 can have a bevel; optionally, in actual manufacturing, due to limitations in process precision, the second chamfer B2 can also have an arc edge, or it can also have a broken edge. The chamfer can be larger or gentler than a sharp corner.

[0094] Optionally, when both the first chamfer A2 and the second chamfer B2 have a hypotenuse, the hypotenuses can be parallel to each other. Optionally, when both the first chamfer A2 and the second chamfer B2 have an arc edge, the shapes of the arc edges can be the same.

[0095] Optionally, at least a portion of the first sharp angle A1 and at least a portion of the second sharp angle B1 can be centrally symmetric structures. Optionally, at least a portion of the first chamfer A2 and at least a portion of the second chamfer B2 can be centrally symmetric structures.

[0096] In one possible implementation, referring to Figures 2B-2D, for the same first notch Q1, the second chamfer B2 is opposite to the first chamfer A2 at the end of one of the slits F, and the second sharp corner B1 is opposite to the first sharp corner A1 at the end of the adjacent slit F. For example, referring to Figure 2B, for the first first notch Q1 in the top-to-bottom direction, its second chamfer B2 is opposite to the first chamfer A2 of the first slit F in the top-to-bottom direction, and its second sharp corner B1 is opposite to the first sharp corner A1 of the second slit F in the top-to-bottom direction. That is, the two corners of a first notch Q1 correspond to two slits respectively. In this way, the electric field at multiple corners of the slit F can be improved with a smaller number of first notches Q1, reducing the number of first notches Q1 required and the difficulty of setting them.

[0097] In one possible implementation, referring to Figures 2B-2D, the second electrode 3 includes: two first outer edges w1 extending along a first direction X, the extension direction of the first outer edges w1 being the same as the arrangement direction of the plurality of slits F; and the orthographic projection of the first notch Q1 onto the substrate 1 overlapping the orthographic projection of the first outer edges w1 onto the substrate 1. That is, in this embodiment of the present disclosure, the first notch Q1 can extend from the side of the first outer edge w1 away from the central region of the first electrode 2, across the first outer edge w1, towards the central region of the first electrode 2.

[0098] In one possible implementation, as shown in Figures 2B-2C, the first notch Q1 includes two first edges Qw1 disposed opposite to each other; the extending direction of the first edges Qw1 is parallel to the extending direction of the slit F, and the portion of the region between the extension lines of the two first edges Qw1 of the same first notch Q1 in the orthographic projection of the substrate 1 overlaps with the region between two adjacent slits F in the orthographic projection of the substrate 1.

[0099] Optionally, as shown in Figure 2B, the orthographic projection of the region between the extension lines of the two first edges Qw1 of the same first notch Q1 onto the substrate 1 partially overlaps with the orthographic projection of the region between two adjacent slits F onto the substrate 1, and partially overlaps with the orthographic projection of one of the slits F onto the substrate 1.

[0100] In one possible implementation, as shown in Figures 2B-2C, the first notch Q1 further includes a second edge Qw2, one end of which is connected to a first edge Qw1 and the other end of which is connected to another first edge Qw1.

[0101] The orthographic projection of the second edge Qw2 onto the substrate 1 and the orthographic projection of the slit F onto the substrate 1 are both located on the same side of the first outer edge w1; and the maximum distance a1 between the orthographic projection of the second edge Qw2 onto the substrate 1 and the orthographic projection of the first outer edge w1 onto the substrate 1 is less than or equal to the maximum distance a2 between the orthographic projection of the slit F onto the substrate 1 and the orthographic projection of the first outer edge w1 onto the substrate 1.

[0102] Optionally, referring to Figure 2C, the second edge Qw2 can be a broken line segment, which may include: a first sub-edge Qw21 and a second sub-edge Qw22. The first sub-edge Qw21 can extend along the first direction X, and the second sub-edge Qw22 can extend along the third direction Z. The first sub-edge Qw21 can form a second sharp angle B1 with one of the first edges Qw1, and the second sub-edge Qw22 can form a second chamfer B2 with the other first edge Qw1. The angle formed by the third direction Z and the first direction X can be in the range of 30° to 60°.

[0103] In one possible implementation, referring to Figures 2A, 2E-2I, the array substrate may further include a gate line layer 40 located between the first conductive layer 20 and the second conductive layer 30, an active layer 60 located between the gate line layer 40 and the second conductive layer 30, and a data line layer 50 located between the active layer 60 and the second conductive layer 30. The gate line layer 40 may include multiple gate lines 4 extending along the second direction Y, and multiple first traces 41 extending along the second direction Y. The orthographic projection of the first traces 41 onto the substrate 1 may coincide with the orthographic projection of the first connection line 21 onto the substrate 1. The first traces 41 may have no insulating layer between them and the first electrode layer 20, connecting the first electrodes 2 in the same row of the first electrode 2 into a single structure. At least a portion of the pattern in the active layer 60 may be the same as the pattern in the data line layer 50, and the active layer 60 may be formed in the same masking process as the data line layer 50. Some island structures are also formed on the gate line layer. For example, three island structures are shown in Figure 2F. The island structures can be of different sizes, and they overlap with the pixel electrodes in the direction perpendicular to the substrate. Some island structures are also formed in the data line layer. Optionally, at least some of the island structures formed in the data line layer and the island structures formed in the gate line layer overlap at least partially in the direction perpendicular to the substrate. Optionally, they can completely overlap, which can be used to prevent the support pillars of the display panel from sliding.

[0104] Optionally, as shown in Figure 2J, the display panel may have a black matrix layer 7, which may have multiple openings to enable light transmission at the openings.

[0105] In one possible implementation, referring to Figures 3A and 3B, where Figure 3B is an enlarged schematic diagram of Figure 3A at the dashed box S2, the edge of the first electrode 2 also has multiple second notches Q2; the second notches Q2 are located between two adjacent first notches Q1, and the orthographic projection of the second notches Q2 onto the substrate 1 is opposite to the orthographic projection of the first sharp corner A1 onto the substrate 1. Since the electric field at the first sharp corner A1 is strong, in this embodiment of the present disclosure, the edge of the first electrode 2 is further provided with second notches Q2 at the position corresponding to the first sharp corner A1, which can further increase the pulling balance effect of the electric field at the first sharp corner A1, increase the horizontal component of the electric field, and improve the edge dark field.

[0106] In one possible implementation, as shown in Figure 3B, the second notch Q2 has two third apex C1 on the side facing the slit F.

[0107] Optionally, the angle of the third apex C1 can be equal to the angle of the second apex B1. Optionally, referring to Figure 3B, in the first direction X, there is a gap between the first notch Q1 and the slit F; in the first direction X, the distance between the second notch Q2 and the slit F can be 0, that is, the extension line of the upper edge of the second notch Q2 can coincide with the upper edge of the slit F, and the two are set in an upper-aligned manner; in the second direction Y, the distance between the second notch Q2 and the slit F can be greater than 0, that is, the two have a gap in the second direction Y, so as to generate a horizontal electric field component.

[0108] In one possible implementation, referring to Figure 3B, the width b2 of the second notch Q2 in the first direction X is smaller than the width b1 of the first notch Q1 in the direction parallel to the first direction X, and the first direction X is the same as the arrangement direction of the slits; the length b4 of the second notch Q2 in the direction perpendicular to the first direction X can be equal to the length b3 of the first notch Q1 in the direction perpendicular to the first direction X.

[0109] In one possible implementation, referring to Figures 4A-4G, the first outer edge w1 has a break w0 at a partial location; the edge of the first electrode 2 also has a plurality of third notches Q3; the portion of the third notches Q3 projected onto the substrate 1 at least partially overlaps with the projection of the break w0 onto the substrate 1. In this embodiment, the first electrode 2 has a third notch Q3 at a location corresponding to the break w0 of the second electrode 3, which can improve the concentrated electric field formed at the break w0 due to its sharpness, thereby increasing the dark field ratio at the break w0 and improving the light efficiency and transmittance of the display panel.

[0110] In one possible implementation, referring to Figures 4B-4D, the second electrode 3 includes: a plurality of branches 31, with slits F located between adjacent branches 31; each branch 31 has a fourth sharp angle D1 at the fracture w0 location; the orthographic projection of the fourth sharp angle D1 onto the substrate 1 partially overlaps with the orthographic projection of the third notch Q3 onto the substrate 1; the third notch Q3 has a fifth sharp angle E1 disposed opposite to the fourth sharp angle D1. In this embodiment, the third notch Q3 having a fifth sharp angle E1 disposed opposite to the fourth sharp angle D1 can improve the concentrated electric field formed at the fourth sharp angle D1 of the fracture w0 due to its sharpness, thereby increasing the dark field ratio at the fracture w0 and improving the light efficiency and transmittance of the display panel.

[0111] In one possible implementation, as shown in Figures 4B-4D, the shape of the third notch Q3 is the same as the shape of the first notch Q1. This can improve the dark field at the edge of the display panel while simplifying the fabrication of the third electrode 3 and reducing the manufacturing cost of the display panel.

[0112] In one possible implementation, referring to Figure 4F, there are multiple branches 31 spaced apart between adjacent fracture surfaces w0; the fracture surfaces w0 of the two first outer edges w1 are staggered. That is, as shown in Figure 4F, the fracture surface w0 of the left first outer edge w1 and the fracture surface w0 of the right first outer edge w1 are not located on the same straight line parallel to the second direction Y, that is, the fracture surface w0 of the left first outer edge w1 and the fracture surface w0 of the right first outer edge w1 are not located on both sides of the same slit F.

[0113] In one possible implementation, referring to Figures 4E, 4F, and 4G, where Figure 4G is an enlarged schematic diagram of Figure 4E at the dashed box S4, the second electrode 3 includes: a first branch group 301 and a second branch group 302 arranged along the first direction X; both the first branch group 301 and the second branch group 302 include multiple branches 31; the extension directions of the branches of the first branch group 301 and the second branch group 302 are different; in the boundary area between the first branch group 301 and the second branch group 302, some branches 31 are broken, and have a sixth sharp angle F1 at the broken end;

[0114] The first electrode 2 further includes: a plurality of first hollows L1; the orthographic projection of the plurality of first hollows L1 onto the substrate 1 is the orthographic projection of the boundary region between the first branch group 301 and the second branch group 302 onto the substrate, and the orthographic projection of the first hollows L1 onto the substrate 1 does not overlap with the orthographic projection of the sixth sharp corner F1 onto the substrate 1; the first hollow L1 includes a first hollow end LA and a second hollow end LB, and in the direction from the first hollow end LA to the second hollow end LB, the width d of the first hollows L1 in the first direction X gradually decreases; wherein, the orthographic projection of the second hollow end LB onto the substrate 1 is opposite to the orthographic projection of the sixth sharp corner F1 onto the substrate 1.

[0115] In this embodiment, corresponding to the sixth sharp corner F1 in the middle region of the second electrode 3, the first electrode 2 can be provided with a first hollow L1, and the first hollow L1 and the sixth sharp corner F1 are set in a "point-to-point" manner to pull and balance the electric field generated by the accumulation of charge at the sixth sharp corner F1, thereby reducing the dark field at the sixth sharp corner F1 and improving the transmittance and contrast of the display panel.

[0116] In one possible implementation, as shown in FIG4A, the orthographic projection of the end of the sixth apex F1 along the extension line perpendicular to the first direction X onto the substrate overlaps with the orthographic projection of the first cutout L1 onto the substrate 1.

[0117] In one possible implementation, as shown in FIG4A, the orthographic projection of the first cutout L1 onto the substrate 1 is located within the orthographic projection of the slit F onto the substrate 1.

[0118] In one possible implementation, referring to FIG5, the second electrode 3 includes: a first branch group 301 and a second branch group 302 arranged along a first direction X; both the first branch group 301 and the second branch group 302 include a plurality of branches 31; the ends of each branch 31 of the first branch group 301 are disconnected from each other on a first side and connected to each other on a second side; the ends of each branch of the second branch group 302 are disconnected from each other on a second side and connected to each other on a first side; in the region where the first branch group 301 is located, the orthographic projection of each first notch Q1 on the substrate 1 is located on the second side; in the region where the second branch group 302 is located, the orthographic projection of each first notch Q1 on the substrate 1 is located on the first side. For example, referring to Figure 5, for the third second electrode 3 from left to right, the ends of each branch 31 of the first branch group 301 are disconnected on the left and connected to each other on the right. Then, the orthogonal projection of the first notch Q1 on the substrate 1 in the region corresponding to the first branch group 301 is located on the right. The ends of each branch 31 of the second branch group 302 are disconnected on the right and connected to each other on the left. Then, the orthogonal projection of the first notch Q1 on the substrate 1 in the region corresponding to the second branch group 302 is located on the left.

[0119] Optionally, for different second electrodes 3, the positions at which the ends of each branch 31 of the first branch group 301 are disconnected can be different. For example, as shown in Figure 5, for the third second electrode 3 from left to right, the ends of each branch 31 of the first branch group 301 are disconnected on the left side, and for the second second electrode 3 from left to right, the ends of each branch 31 of the first branch group 301 can be disconnected on the right side. Correspondingly, for different first electrodes 2, the position of the first gap Q1 in the region corresponding to the first branch group 301 can also be different. For example, as shown in Figure 5, for the third second electrode 3 from left to right, the position of the first gap Q1 in the region corresponding to the first branch group 301 can be located on the right side, and for the second second electrode 3 from left to right, the position of the first gap Q1 in the region corresponding to the first branch group 301 can be located on the left side. Optionally, the positions at which the ends of adjacent second electrodes 3 are disconnected and connected can be designed differently from each other, that is, at least for some sub-pixels, the disconnection positions and / or connection positions of adjacent second electrodes 3 are staggered.

[0120] Based on the same inventive concept, embodiments of this disclosure also provide a display panel, which includes an array substrate as provided in embodiments of this disclosure.

[0121] Display products in ADS mode suffer from low contrast and light leakage at side viewing angles. When backlight light spills into darker areas against backgrounds with significant brightness differences, a halo effect occurs. This can be understood as unwanted light overflowing into darker areas, creating an abnormal visual phenomenon. Halo has been a major weakness of ADS display products, hindering their competitiveness. The mechanism of halo formation is as follows: when light scatters in all directions, it causes uneven illumination and affects adjacent zones, resulting in halo. Interference between halos can even distort colors, significantly impacting image quality and color. Furthermore, ADS display products also suffer from washed-out appearance and reddish / bluish tint at wide viewing angles.

[0122] In view of this, embodiments of the present invention also provide a display panel, the display panel further comprising: a first polarizer attached to the light-emitting side of the display panel; referring to FIG10, the first polarizer 9 comprises: a liquid crystal layer 95, the long axis of the liquid crystal layer being perpendicular to the substrate. In this embodiment of the present disclosure, the first polarizer on the light-emitting side of the display panel comprises: a liquid crystal layer, wherein the long axis of the liquid crystal layer is perpendicular to the substrate, and the short axis can absorb light, that is, the long axis of the liquid crystal is arranged perpendicular to the film surface, relying on the light absorption characteristics of the short axis to reduce the amount of light transmitted in the side viewing angle direction, so as to reduce the halo and improve the large viewing angle color shift.

[0123] In one possible implementation, the liquid crystal layer comprises liquid crystal and a dichroic dye mixed in the liquid crystal. In this embodiment, a liquid crystal layer (as a light-reducing layer) can be added to a conventional polarizer. The liquid crystal layer comprises isooriented molecules of a dichroic dye, such as dye-like liquid crystal (DDLC) molecules, whose absorption field is parallel to their short axis and transparent in the direction parallel to their long axis. The long axis of the DDLC liquid crystal is aligned perpendicular to the film surface. Relying on its short-axis light absorption characteristics, it reduces the amount of light transmitted in the side viewing angle direction, thereby reducing halo and large-viewing-angle color shift, as shown in Figure 11. By adding a liquid crystal layer to a conventional polarizer, the light convergence of the first polarizer can be increased, thereby reducing the amount of light transmitted in the side viewing angle direction, thus achieving the purpose of reducing halo and large-viewing-angle color shift.

[0124] In one possible implementation, the liquid crystal layer comprises: liquid crystal, and a chiral additive mixed in the liquid crystal.

[0125] Optionally, the mass percentage of the dichroic dye in the liquid crystal layer can be greater than the mass percentage of the chiral additive in the liquid crystal layer. Optionally, both the mass percentage of the dichroic dye and the mass percentage of the chiral additive in the liquid crystal layer can be less than the mass percentage of the liquid crystal in the liquid crystal layer.

[0126] In one possible implementation, dichroic dyes include one or a combination of the following:

[0127] in, as well as It can be an azo dye; as well as It can be anthraquinone dye.

[0128] In one possible implementation, referring to FIG10, the first polarizer 9 further includes: a first substrate 91, and at least one of the following located on one side of the first substrate 91:

[0129] Polarizing layer 92;

[0130] Support layer 93;

[0131] First adhesive layer 94;

[0132] Second adhesive layer 96;

[0133] Second substrate 97;

[0134] Third adhesive layer 98;

[0135] The liquid crystal layer 95 may be located between the first adhesive layer 94 and the second adhesive layer 96; the third adhesive layer 98 may be used to bond the first polarizer 9 to the display panel. The material of the first substrate 91 may include polyethylene terephthalate (PET); the material of the second substrate 97 may include cyclic olefin polymer (COP); the material of at least one of the first adhesive layer 94, the second adhesive layer 96, the second substrate 97, and the third adhesive layer 98 may include a pressure-sensitive adhesive (PSA); and the material of the polarizer 92 may include polyvinyl alcohol (PVA).

[0136] In one possible implementation, the first polarizer further includes an alignment film layer in contact with the liquid crystal layer. Optionally, the alignment film layer may be located on at least one side of the liquid crystal layer and may be in direct contact with the liquid crystal layer.

[0137] Optionally, when forming the liquid crystal layer and the alignment film layer, an alignment film layer (PI) corresponding to the vertically aligned liquid crystal (VA) can be coated on the first substrate first, and then DDLC-type dichroic liquid crystal molecules can be coated on the alignment film layer and photo-aligned so that the DDLC liquid crystals are aligned perpendicular to the film surface.

[0138] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes a display panel as provided in embodiments of this disclosure.

[0139] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0140] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An array substrate, wherein, The application relates to a substrate, a first conductive layer on one side of the substrate, the first conductive layer comprising a plurality of first electrodes, a second conductive layer on the side of the first conductive layer away from the substrate and mutually insulated from the first conductive layer, the second conductive layer comprising a plurality of second electrodes, the second electrodes in orthographic projection on the substrate overlapping the first electrodes in orthographic projection on the substrate, the second electrodes having a plurality of slits, wherein the end of the slit has at least one first corner, the edge of the first electrode has a plurality of first notches, the first notch has at least one second corner on the side facing the slit, the first notch in orthographic projection on the substrate does not overlap the slit in orthographic projection on the substrate, and the second corner is arranged opposite the first corner. The at least one first corner comprises a first sharp corner, the at least one second corner comprises a second sharp corner arranged opposite the first sharp corner, and the first sharp corner in orthographic projection on the substrate has a first gap between the second sharp corner in orthographic projection on the substrate. The at least one first corner comprises a first chamfer, the at least one second corner comprises a second chamfer arranged opposite the first chamfer, and the first chamfer in orthographic projection on the substrate has a second gap between the second chamfer in orthographic projection on the substrate. The second corner of the same first notch is opposite the first chamfer of one end of the slit, and the second sharp corner is opposite the first sharp corner of the other end of the adjacent slit. The second electrode comprises two first outer edges extending in a first direction, the extending direction of the first outer edges is the same as the arrangement direction of the plurality of slits, and the first notch in orthographic projection on the substrate overlaps the first outer edge in orthographic projection on the substrate. The first notch comprises two first edges arranged oppositely, the extending direction of the first edges is parallel to the extending direction of the slits, and the area between the extension lines of the two first edges of the same first notch in orthographic projection on the substrate overlaps the area between the adjacent two slits in orthographic projection on the substrate.

2. The array substrate of claim 1, wherein, The first notch further comprises a second edge, one end of the second edge is connected with one first edge, and the other end of the second edge is connected with the other first edge.

3. The array substrate of claim 2, wherein, The second edge in orthographic projection on the substrate is on the same side of the slit in orthographic projection on the substrate, and the maximum distance between the second edge in orthographic projection on the substrate and the first outer edge in orthographic projection on the substrate is less than or equal to the maximum distance between the slit in orthographic projection on the substrate and the first outer edge in orthographic projection on the substrate.

4. The array substrate of claim 3, wherein, The edge of the first electrode further has a plurality of second notches, the second notch is located between the adjacent two first notches, and the second notch in orthographic projection on the substrate is opposite the first sharp corner in orthographic projection on the substrate.

5. The array substrate of any one of claims 1-4, wherein, The second notch has two third sharp corners on the side facing the slit.

6. The array substrate of claim 5, wherein, ​ 7. The array substrate of claim 5 or 6, wherein, ​ ​ 8. The array substrate of any one of claims 2-7, wherein, ​ 9. The array substrate of claim 8, wherein, ​ 10. The array substrate of claim 8 or 9, wherein, The second notch has a width in the first direction, which is smaller than a width of the first notch in a direction parallel to the first direction, the first direction being the same as a direction in which the slits are arranged; The second notch has a length in a direction perpendicular to the first direction, which is equal to a length of the first notch in a direction perpendicular to the first direction.

11. The array substrate of any of claims 5-10, wherein, The first outer edge has a break at a partial position; the edge of the first electrode further has a plurality of third notches; the third notches are at least partially overlapped with the break in the orthographic projection of the substrate.

12. The array substrate of claim 11, wherein, The second electrode comprises a plurality of branches, the slits being located between adjacent branches; the branches have fourth sharp corners at the break positions; the fourth sharp corners are overlapped with the third notches in the orthographic projection of the substrate. The third notches have fifth sharp corners arranged opposite to the fourth sharp corners.

13. The array substrate of claim 11 or 12, wherein, The third notches have the same shape as the first notches.

14. The array substrate of any one of claims 11-13, wherein, The branches are arranged between the breaks; the breaks of the two first outer edges are staggered.

15. The array substrate of any of claims 1-14, wherein, The second electrode comprises a first branch group and a second branch group arranged in a first direction; the first branch group and the second branch group each comprise a plurality of branches; the branches of the first branch group and the second branch group extend in different directions; at the boundary region of the first branch group and the second branch group, some of the branches are broken and have sixth sharp corners at the broken ends. The first electrode further comprises a plurality of first hollows; the plurality of first hollows are located in the orthographic projection of the substrate at the boundary region of the first branch group and the second branch group in the orthographic projection of the substrate, and the first hollows in the orthographic projection of the substrate are not overlapped with the sixth sharp corners in the orthographic projection of the substrate; the first hollows comprise first hollow ends and second hollow ends, and the width of the first hollows in the first direction gradually decreases in the direction from the first hollow ends to the second hollow ends; The second hollow ends in the orthographic projection of the substrate are arranged opposite to the sixth sharp corners in the orthographic projection of the substrate.

16. The array substrate of claim 15, wherein, The ends of the sixth sharp corners in the orthographic projection of the substrate along the extension line perpendicular to the first direction are overlapped with the first hollows in the orthographic projection of the substrate.

17. The array substrate of claim 15 or 16, wherein, The first hollows in the orthographic projection of the substrate are located within the slits in the orthographic projection of the substrate.

18. The array substrate of any one of claims 1-10, wherein, The second electrode comprises a first branch group and a second branch group arranged in a first direction; the first branch group and the second branch group each comprise a plurality of branches; the ends of the branches of the first branch group are disconnected with each other on a first side and connected with each other on a second side; the ends of the branches of the second branch group are disconnected with each other on the second side and connected with each other on the first side; In the region of the first branch group, the orthographic projection of each first notch in the substrate is located on the second side; in the region of the second branch group, the orthographic projection of each first notch in the substrate is located on the first side.

19. A display panel, wherein, The array substrate as claimed in any one of claims 1-18.

20. The display panel of claim 19, wherein, The display panel further comprises a first polarizer attached to the light exit side of the display panel; the first polarizer comprises a liquid crystal layer, a long axis of the liquid crystal layer being perpendicular to the substrate.

21. The display panel of claim 20, wherein, The liquid crystal layer comprises liquid crystal and dichroic dye mixed in the liquid crystal.

22. The display panel of claim 21, wherein, The dichroic dye comprises one or a combination of the following:

23. The display panel of any of claims 20-22, wherein, The first polarizer further comprises an alignment film layer in contact with the liquid crystal layer.

24. A display device comprising: The display panel as claimed in any one of claims 19-23.

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