Three-dimensional photomask transmission with kernel-based modeling

Abstract

A computing system is disclosed that simulates three-dimensional optical transmission in a near field of a lithographic mask using a thin mask approximation that designs a rasterized lithographic mask from a mask layout that describes the lithographic mask, and using a compact mask model that includes a plurality of directional nuclei that represent optical diffraction in the near field of the lithographic mask. The computing system may generate a wafer image or photoresist profile based on the simulated three-dimensional optical transmission in the near field of the lithographic mask and modify the mask layout design based on the wafer image or photoresist profile using an optical proximity correction (OPC) process. A lithographic mask corresponding to the mask layout design is configured for use in the fabrication of integrated circuits.

Description

Technical Field

[0001] This application generally relates to electronic design automation, and more specifically, to the use of kernel-based modeling for three-dimensional photomask transmission. Background Technology

[0002] In the design flow for manufacturing integrated circuits, the physical design of the integrated circuit can be described by specific geometric elements, often referred to as the placement design. These geometric elements (typically polygons) define the shape that will be created in various materials for manufacturing the integrated circuit. Typically, the designer selects groups of geometric elements representing circuit device components (e.g., contacts, gates, etc.) and places them in the design area. These groups of geometric elements can be custom-designed, selected from a library of previously created designs, or some combination of both. Once the groups of geometric elements representing the circuit device components are placed, geometric elements representing interconnecting lines are then placed between these geometric elements according to a predetermined route. These lines form the wiring for interconnecting electronic devices.

[0003] Descriptions of the physical design of integrated circuits can be provided in many different formats. The Graphical Data System II (GDSII) format is a popular format for transmitting and archiving two-dimensional (2D) graphical circuit layout data. Among its other features, it contains a hierarchical structure, with each structure containing layout elements (e.g., polygons, paths or polylines, circles, and text boxes). Other formats include open-source formats called Open Access, Milkyway, EDDM, and the Open Artwork System Interchange Standard (OASIS). These different industry formats are used to define geometric information in the layout design for manufacturing integrated circuits. Once the design is complete, the layout portion of the design can be used by manufacturing tools to fabricate the circuit using photolithography processes.

[0004] Many different manufacturing processes exist for creating circuits, but most involve a series of steps that deposit layers of different materials on a substrate, expose specific portions of each layer to radiation, and then etch away the exposed (or unexposed) portions of the layer. For example, a simple semiconductor device assembly can be fabricated using the following steps: First, a P-type epitaxial layer is grown on a silicon substrate via chemical vapor deposition. Next, a nitride layer is deposited on the epitaxial layer. Then, specific regions of the nitride layer are exposed to radiation and etched away, leaving exposed regions on the epitaxial layer (i.e., regions no longer covered by the nitride layer). The exposed regions are then subjected to a diffusion or ion implantation process, allowing dopants (such as phosphorus) to enter the exposed epitaxial layer and form charged traps. This process of depositing material layers on a substrate or subsequent material layers, then exposing specific patterns to radiation, etching, and doping or other diffused materials is repeated multiple times to create different physical layers of a circuit.

[0005] Each time a material layer is exposed to radiation, a mask is created to expose only the desired areas to the radiation while protecting other areas from exposure. The mask is created based on circuit layout data. That is, the geometric elements described in the layout design define the relative positions or areas of the circuit that will be exposed to radiation through the mask. A mask or photomask writing tool is used to create a mask based on the layout design, which can then be used in the photolithography process.

[0006] As designers and manufacturers continue to increase the number of circuit components in a given area and / or shrink the size of these components, the shapes reproduced on the substrate (and therefore in the mask) become smaller and more closely spaced. This reduction in feature size increases the difficulty of accurately reproducing the image intended for the layout design onto the substrate. Light diffraction effects often lead to defects—that is, the image intended during the photolithography process is not accurately printed onto the substrate, resulting in defects in the manufactured device. One or more resolution enhancement techniques (RETs) are typically used to improve the resolution of the image formed by the mask on the substrate during the photolithography process.

[0007] One of these resolution enhancement techniques—Optical Proximity Correction (OPC)—adjusts the amplitude of light traveling through a photolithographic mask by modifying the mask layout design data used to create the mask. For example, edges in the mask layout design can be adjusted to make certain portions of the geometry larger or smaller, depending on how much additional exposure (or lack thereof) is expected at certain points on the substrate. When these adjustments are properly calibrated, overall pattern fidelity can be increased.

[0008] A particular form of optical proximity correction, called model-based optical proximity correction, uses mask layout design data and one or more compact models (e.g., compact mask models, compact optical models, and / or compact photoresist models) to predict the printed image or photoresist profile produced on a substrate by exposure through one or more masks described by the mask layout design data, and then modifies the mask layout design data. Since most masks include Manhattan shapes, model-based optical proximity correction typically uses a compact mask model of the implementation domain decomposition (DDM) method to simulate the mask layout design data, which adds a one-dimensional signal corresponding to light transmission in the mask's near field. As optical proximity correction has evolved to allow the design of masks with non-Manhattan or curved shapes, model-based optical proximity correction using a compact mask model to add a one-dimensional signal may not accurately describe light transmission in the mask's near field, thus reducing the accuracy of wafer image simulation and any resulting modifications to the mask layout design data during optical proximity correction. Summary of the Invention

[0009] This application discloses a computational system that uses a compact mask model and an edge mesh associated with a lithographic mask to simulate three-dimensional light transmission in the near field of a lithographic mask. The computational system generates the edge mesh by rasterizing a mask layout design describing the lithographic mask into a mesh corresponding to a thin mask approximation of the lithographic mask, and then dividing the thin mask approximation into edge meshes representing the shapes of the edges in different directions within the thin mask approximation of the lithographic mask. The computational system generates the compact mask model by performing a three-dimensional simulation on a geometric mask pattern to determine the corresponding through-the-lens (TTL) target diffraction order of the geometric mask pattern, extracting the edge mesh from the geometric mask pattern, determining the TTL diffraction order of the edge mesh of the geometric mask pattern, and generating a direction kernel in the compact mask model based at least in part on the simulated TTL target diffraction order of the geometric mask pattern and the TTL diffraction order of the edge mesh of the geometric mask pattern.

[0010] The computational system can simulate 3D light transmission in the near field of a lithographic mask by convolving the edge mesh with the orientation kernel in the compact mask model based on the orientation associated with the edge mesh and the orientation kernel (which identifies directional light transmission at the edges of the thin mask approximation of the mask layout design). The computational system can then aggregate the thin mask approximation of the mask layout design with the directional light transmission at the edges of the thin mask approximation of the mask layout design to determine the simulated 3D light transmission in the near field of the lithographic mask.

[0011] The computing system can utilize three-dimensional light transport in the near field of a simulated lithographic mask in various ways. In some embodiments, the computing system can generate a wafer image or photoresist profile based at least in part on the simulated three-dimensional light transport in the near field of the lithographic mask. The computing system can implement an optical proximity correction (OPC) process to modify the mask layout design based on the wafer image and / or photoresist profile. The computing system can utilize the simulated three-dimensional light transport in the near field of the lithographic mask to train a compact photoresist model for simulating the photoresist profile, or to verify the mask layout design during OPC verification. Embodiments will be described in more detail below. Attached Figure Description

[0012] Figure 1 and Figure 2 Examples of computer systems of various types that can be used to implement various embodiments are shown.

[0013] Figure 3 Examples of manufacturing simulation systems 300 utilizing kernel-based modeling for three-dimensional photomask transmission are shown according to various embodiments.

[0014] Figure 4 A flowchart illustrating the calibration of an exemplary compact mask model is shown, based on various examples.

[0015] Figure 5 A flowchart illustrating an exemplary near-field simulation of a kernel-based compact mask model is shown, based on various examples. Detailed Implementation

[0016] Explanatory operating environment

[0017] Various examples can be implemented by executing software instructions using a computing device 101, such as a programmable computer. Therefore, Figure 1 An illustrative example of a computing device 101 is shown. As illustrated in the figure, the computing device 101 includes a computing unit 103 having a processing unit 105 and a system memory 107. The processing unit 105 can be any type of programmable electronic device for executing software instructions, but is conventionally a microprocessor. The system memory 107 may include a read-only memory (ROM) 109 and a random access memory (RAM) 111. As those skilled in the art will understand, both the read-only memory (ROM) 109 and the random access memory (RAM) 111 can store software instructions for execution by the processing unit 105.

[0018] Processing unit 105 and system memory 107 are connected directly or indirectly to one or more peripheral devices 115-123 via bus 113 or an alternative communication structure. For example, processing unit 105 or system memory 107 may be directly or indirectly connected to one or more additional storage devices, such as hard disk drive 117 (which may be magnetic and / or removable), removable optical disk drive 119, and / or flash memory card. Processing unit 105 and system memory 107 may also be directly or indirectly connected to one or more input devices 121 and one or more output devices 123. Input devices 121 may include, for example, a keyboard, pointing devices (e.g., mouse, touchpad, stylus, trackball, or joystick), scanner, camera, and microphone. Output devices 123 may include, for example, a monitor display, printer, and speaker. For various examples of computing device 101, one or more peripheral devices 115-123 may be housed internally with computing unit 103. Alternatively, one or more peripheral devices 115-123 may be external to the housing of computing unit 103 and connected to bus 113 via, for example, a Universal Serial Bus (USB) connection.

[0019] In some implementations, computing unit 103 may be directly or indirectly connected to network interface 115 for communication with other devices constituting the network. Network interface 115 may convert data and control signals from computing unit 103 into network messages according to one or more communication protocols, such as Transmission Control Protocol (TCP) and Internet Protocol (IP). Furthermore, network interface 115 may utilize any suitable connection proxy (or combination of proxies) to connect to the network, including, for example, a wireless transceiver, modem, or Ethernet connection. Such network interfaces and protocols are well known in the art and will not be discussed in detail here.

[0020] It should be understood that computing device 101 is illustrative only and is not intended to be limiting. Various embodiments may be implemented using one or more computing devices, including... Figure 1 The components of the computing device 101 shown include Figure 1 The components shown may be a subset of the components, or may include alternative combinations of components, including Figure 1 Components not shown. For example, various embodiments may be implemented using a multiprocessor computer, a network of multiple single-processor and / or multiprocessor computers, or some combination of both.

[0021] In some implementations, processor unit 105 may have more than one processor core. Therefore, Figure 2An example of a multi-core processor unit 105 that can be used in various embodiments is shown. As shown in the figure, the processor unit 105 includes a plurality of processor cores 201A and 201B. Each processor core 201A and 201B includes a computing engine 203A and a computing engine 203B, respectively, and a memory cache 205A and a memory cache 205B, respectively. As those skilled in the art will appreciate, the computing engines 203A and 203B may include logic devices for performing various computational functions, such as fetching software instructions and then performing actions specified in the fetched instructions. These actions may include, for example, adding, subtracting, multiplying, comparing numbers, performing logical operations such as AND, OR, NOR, and XOR, and retrieving data. Each computing engine 203A and 203B may then use its respective memory cache 205A and memory cache 205B to quickly store and retrieve data and / or instructions to be executed.

[0022] Each processor core 201A and 201B is connected to interconnect 207. The specific configuration of interconnect 207 can vary depending on the architecture of processor unit 105. For some processor cores 201A and 201B, such as the Cell microprocessors created by Sony, Toshiba, and IBM, interconnect 207 can be implemented as an interconnect bus. However, for other processor units 201A and 201B, such as the Opteron™ and Athlon™ dual-core processors offered by Advanced Micro Devices, Inc. of Sunnyvale, California, interconnect 207 can be implemented as a system request interface device. In any case, processor cores 201A and 201B communicate with input / output interface 209 and memory controller 210 via interconnect 207. Input / output interface 209 provides a communication interface with bus 113. Similarly, memory controller 210 controls the exchange of information with system memory 107. In some implementations, processor unit 105 may include additional components, such as a high-level cache memory that can be shared by processor cores 201A and 201B. It should also be understood that... Figure 1 and Figure 2 The description of the computer networks shown is provided by way of example only and is not intended to imply any limitation on the scope or functionality of alternative embodiments.

[0023] Transmission of 3D photomasks using kernel-based modeling

[0024] Figure 3 Examples of manufacturing simulation systems 300 utilizing kernel-based modeling for three-dimensional photomask transmission, according to various embodiments, are shown. (Refer to...) Figure 3The manufacturing simulation system 300 can receive a mask layout design 301 describing a photolithographic mask used for manufacturing integrated circuits. In some embodiments, the photolithographic mask described in the mask layout design 301 may include a non-Manhattan shape or a curved shape associated with the aperture or opening of the photolithographic mask. The manufacturing simulation system 300 can also receive optical system characterization data 302, which can describe a physical printing system used to manufacture integrated circuits using a photolithographic mask, including, for example, a description of the light source, the numerical aperture of the lens, a description of the mask material and thickness, a description of the photoresist material used on the semiconductor substrate, etc.

[0025] The manufacturing simulation system 300 may include a mask model calibration system 310 to create a compact mask model 311 for determining three-dimensional light transmission in the near field of a photolithographic mask described by the mask layout design 301. In some embodiments, the compact mask model 311 may include a plurality of direction nuclei representing light diffraction in fundamental directions in the near field of the photolithographic mask. Reference will be made below. Figure 4 A more detailed description of an embodiment of the creation of a compact mask model is provided.

[0026] Figure 4 A flowchart illustrating the calibration of an exemplary compact mask model is shown, based on various examples. References Figure 3 and Figure 4 In block 401, the mask model calibration system 310 can perform a three-dimensional simulation of a geometric mask pattern to determine the corresponding through-lens (TTL) target diffraction order of the geometric mask pattern. The geometric mask pattern may correspond to a two-dimensional pattern of one or more mask shapes with various curved edges. In some embodiments, the mask model calibration system 310 may include a simulator, such as a finite-difference time-domain (FDTD) simulator, to perform a three-dimensional simulation of light diffraction through the geometric mask pattern.

[0027] The mask model calibration system 310 can generate a target mesh for each geometric mask pattern using a three-dimensional simulation of light diffraction through the geometric mask pattern. In some embodiments, the mask model calibration system 310 can generate a target mesh for each geometric mask pattern by determining the difference between a thin mask approximation of the geometric mask pattern and the simulated light diffraction through the geometric mask pattern. The mask model calibration system 310 can generate a thin mask approximation of the geometric mask pattern by rasterizing the geometric mask pattern into a mesh with a pixel array, where the pixel values ​​correspond to the positions of the mask and aperture in the geometric mask pattern.

[0028] The mask model calibration system 310 can determine the through-lens (TTL) target diffraction order of a geometric mask pattern using a target grid representing the near-field light transmission of the mask in a fundamental direction for each geometric mask pattern. In some embodiments, the mask model calibration system 310 can perform a Fourier transform on the target grid to obtain a set of diffraction orders of transmitted light in the mask near field, eliminate one or more diffraction orders of transmitted light corresponding to light collected by lenses in a lithography system that will not be used to fabricate integrated circuits, and then perform an inverse Fourier transform on the modified set of diffraction orders of transmitted light. The modified set of diffraction orders of transmitted light can correspond to the through-lens (TTL) target diffraction order of the geometric mask pattern.

[0029] In box 402, the mask model calibration system 310 can extract edge meshes from a geometric mask pattern. In some embodiments, the mask model calibration system 310 can divide the thin mask approximation of the geometric mask pattern into edge meshes by identifying pixels with grayscale values ​​in the thin mask approximation and then separating the pixels with grayscale values ​​into different edge orientations in a basic direction (e.g., up, down, left, right, or north, south, east, west, etc.). The edge meshes may have pixel values ​​associated with the edges in the geometric mask pattern corresponding to the apertures of their respective edge orientations.

[0030] In block 403, the mask model calibration system 310 can determine the TTL diffraction orders of the edge grid of the geometric mask pattern. In some embodiments, the mask model calibration system 310 can perform a Fourier transform on the edge grid to obtain a set of diffraction orders of transmitted light in the near field of the mask, eliminate one or more diffraction orders of transmitted light corresponding to light collected by lenses in a lithography system that will not be used to fabricate integrated circuits, and then perform an inverse Fourier transform on the modified set of diffraction orders of the transmitted light. The modified set of diffraction orders of the transmitted light may correspond to the through-lens (TTL) diffraction orders of the edge grid.

[0031] In block 404, the mask model calibration system 310 can generate a direction kernel based on the TTL target diffraction order of the simulated geometric mask pattern and the TTL diffraction order of the edge mesh of the geometric mask pattern. In some embodiments, the mask model calibration system 310 can construct a matrix for the TTL diffraction order of the edge mesh and then use the matrix to generate the direction kernel. The matrix for the TTL diffraction order of the edge mesh can have a row-column format, where each row of the matrix corresponds to a specific target TTL diffraction order of a single geometry in the geometric mask pattern, each column of the matrix corresponds to a specific pairing of basis functions (e.g., Zernike coefficients) and the direction kernel, and each row-column intersection of the matrix corresponds to the product of the specific target TTL diffraction order of a single geometry with the specific pairing of basis functions and the direction kernel. The mask model calibration system 310 can generate the direction kernel by determining the complex basis function coefficients (e.g., Zernike coefficients) using a linear system including the TTL target diffraction order of the simulated geometric mask pattern and the matrix, and then summing a set of complex polynomials (e.g., Zernike polynomials) weighted by the complex coefficients to generate the direction kernel.

[0032] In block 405, mask model calibration system 310 can calibrate compact mask model 311 to include the orientation kernels. Mask model calibration system 310 can incorporate each orientation kernel into compact mask model 311, which can calibrate compact mask model 311 for use in manufacturing simulation system 300.

[0033] Return to reference Figure 3 The manufacturing simulation system 300 may include a mask near-field simulation system 320 to determine the mask near-field 321 of a photolithographic mask using a compact mask model 311. In some embodiments, the mask near-field simulation system 320 may determine the mask near-field 321 by simulating three-dimensional light transport in the near field of the photolithographic mask using a direction kernel in the compact mask model 311 and a mask layout design 301 for the photolithographic mask. Reference will be made below. Figure 5 An example of mask near-field simulation using a kernel-based compact mask model is described in more detail.

[0034] Figure 5 A flowchart illustrating exemplary near-field simulations of a kernel-based compact mask model is shown, illustrating various examples. References Figure 3 and Figure 5 The mask near-field simulation system 320 may include a rasterization system 322, in Figure 5 In block 501, the rasterization system 322 can rasterize the mask layout design 301 into a grid that approximately corresponds to the thin mask of the photomask. In some embodiments, the grid may correspond to pixelated data encoded in grayscale depending on whether the pixel corresponds to a portion of the photomask, an aperture or opening in the photomask, or a combination thereof.

[0035] The mask near-field simulation system 320 may include an edge mesh system 324, which, within block 502, can approximate the thin mask into multiple edge meshes, each edge mesh representing the edges of a shape in a different direction in the thin mask approximation of the lithographic mask. In some embodiments, the edge meshes may correspond to four basic directions, such as up, down, left, and right, or north, south, east, and west.

[0036] The mask near-field simulation system 320 may include a near-field simulator 326, located in block 503, which can simulate three-dimensional light transmission in the near field of a lithographic mask using a compact mask model 311 and edge meshes from a thin mask approximation of the lithographic mask. In some embodiments, the near-field simulator 326 can simulate three-dimensional light transmission in the near field of the lithographic mask in each fundamental direction, for example, by convolving each edge mesh with a corresponding orientation kernel in the compact mask model 311. For example, the near-field simulator 326 can identify edge meshes corresponding to a first fundamental direction, identify complex orientation kernels also corresponding to the first fundamental direction, and convolve them to determine light diffraction in the near field of the lithographic mask associated with the first fundamental direction. The near-field simulator 326 can repeat this convolution process for edge meshes and complex orientation kernels in other fundamental directions. In some embodiments, the near-field simulator 326 can perform a Fourier transform on the edge mesh and the complex orientation kernel, multiply the transformed edge mesh and the complex orientation kernel, and then perform an inverse Fourier transform to determine the light diffraction in the near field of the lithographic mask, instead of convolving the edge mesh and the complex orientation kernel.

[0037] The mask near-field simulation system 320 may include an aggregation system 328 for combining the simulated three-dimensional light transmission in the near field of the lithographic mask in each fundamental direction with the thin mask approximation of the lithographic mask. The combination of the simulated three-dimensional light transmission in the near field of the lithographic mask in each fundamental direction with the thin mask approximation of the lithographic mask can correspond to the mask near field 321 of the lithographic mask.

[0038] The manufacturing simulation system 300 may include an optical simulator 330, located in block 504, which can generate a wafer image 303 based at least in part on a mask near-field 321. The optical simulator 330 may receive a compact optical model 331 that models the optical characteristics of a physical printing system used to fabricate integrated circuits using a photolithographic mask. The optical simulator 330 can use the mask near-field 321 and the compact optical model 331 to predict the printed image produced on a substrate by exposure through one or more masks described by the mask layout design 301. The wafer image 303 may correspond to a light pattern displayed on a semiconductor wafer after passing through a lens of the photolithographic mask and the physical printing system.

[0039] Manufacturing simulation system 300 may include photoresist simulator 340, in block 504, which may generate photoresist profile 304 at least partially based on wafer image 303. Photoresist simulator 340 may receive compact photoresist model 341, which models the characteristics of photoresist when exposed to light in a physical printing system for fabricating integrated circuits using photomasks. Photoresist simulator 340 may use wafer image 303 and compact photoresist model 341 to predict the resulting profile in photoresist on a substrate produced by exposure through one or more masks described by mask layout design 301. In some embodiments, manufacturing simulation system 300 may include a calibration system for compact photoresist model 341, which may utilize mask near field 321 to create or modify compact photoresist model 341.

[0040] The wafer image 303 and photoresist outline 304 generated by the manufacturing simulation system 300 can be used by downstream design and analysis tools, such as an optical proximity correction tool 350, verification tools, mask or photomask writing tools, etc. In this example, the optical proximity correction tool 350 can receive the wafer image 303 and / or photoresist outline 304 from the manufacturing simulation system 300 and perform model-based optical proximity correction on the mask layout design 301. In block 505, this can at least partially modify the mask layout design 301 based on the wafer image 303 and / or photoresist outline 304 to increase overall pattern fidelity.

[0041] The systems and apparatuses described herein may use dedicated processor systems, microcontrollers, programmable logic devices, microprocessors, or any combination thereof to perform some or all of the operations described herein. Some of the operations described herein may be implemented in software, while others may be implemented in hardware. Any operations, processes, and / or methods described herein may be performed by apparatuses, devices, and / or systems substantially similar to those described herein and with reference to the accompanying drawings.

[0042] A processing device can execute instructions or "code" stored in memory. Memory can also store data. Processing devices can include, but are not limited to, analog processors, digital processors, microprocessors, multi-core processors, processor arrays, network processors, etc. A processing device can be part of an integrated control system or system manager, or it can be provided as a portable electronic device configured to interact with a networked system locally or remotely via wireless transmission.

[0043] Processor memory can be integrated with the processing device, such as RAM or FLASH memory housed within an integrated circuit microprocessor. In other examples, memory can include standalone devices, such as external disk drives, storage arrays, portable FLASH key disks, etc. Memory and processing devices can be operatively coupled together or communicate with each other, for example via I / O ports, network connections, etc., and the processing device can read files stored on the memory. The associated memory may be designed as "read-only" (ROM) with access permissions, or it may not be read-only. Other examples of memory may include, but are not limited to, WORM, EPROM, EEPROM, FLASH, etc., which can be implemented in solid-state semiconductor devices. Other memories may include moving parts, such as known spinning disk drives. All of these memories can be "machine-readable" and can be read by the processing device.

[0044] Operating instructions or commands can be implemented or embodied in the tangible form of stored computer software (also known as a "computer program" or "code"). The program or code can be stored in digital memory and can be read by a processing device. A "computer-readable storage medium" (or, alternatively, a "machine-readable storage medium") can include all of the aforementioned types of memory, as well as future technologies, provided that the memory is capable of storing digital information in the nature of a computer program or other data, at least temporarily, and that the stored information can be "read" by a suitable processing device. The term "computer-readable" may not be limited to the historical use of "computer" to imply a full range of mainframes, minicomputers, desktops, or even laptop computers. Rather, "computer-readable" can include storage media that can be read by a processor, processing device, or any computing system. Such media can be any available medium that can be accessed locally and / or remotely by a computer or processor, and can include volatile and non-volatile media, as well as removable and non-removable media, or any combination thereof.

[0045] A program stored in a computer-readable storage medium may include a computer program product. For example, a storage medium can be used as a convenient means of storing or transmitting a computer program. For convenience, operations may be described as various interconnected or coupled functional blocks or diagrams. However, there may be situations where these functional blocks or diagrams can be equivalently aggregated into a single logical device, program, or operation with unclear boundaries.

[0046] in conclusion

[0047] While this application describes specific examples of implementing embodiments of the invention, those skilled in the art will understand that many variations and arrangements of the above systems and techniques exist within the spirit and scope of the invention as set forth in the appended claims. For example, although specific terms have been used above to refer to electronic design automation processes, it should be understood that various examples of the invention can be implemented using any desired combination of electronic design automation processes.

[0048] Those skilled in the art will also recognize that the concepts taught herein can be tailored to specific applications in many other ways. In particular, those skilled in the art will recognize that the examples shown are merely one of many alternative implementations that will become apparent upon reading this disclosure.

[0049] Although the specification may refer to “one,” “another,” or “some” examples in multiple places, this does not necessarily mean that each such reference points to the same one or more examples, or that the feature applies only to a single example.

Claims

1. A method comprising: The computational system uses a thin mask approximation of the lithographic mask from the mask layout design and a compact mask model including multiple directional kernels representing light diffraction in the near field of the lithographic mask to simulate three-dimensional light transmission in the near field of the lithographic mask. The computing system generates a wafer image or photoresist profile based at least in part on the simulated three-dimensional light transmission in the near field of the photomask. as well as The computing system uses an optical proximity correction (OPC) process to modify the mask layout design, at least in part, based on the wafer image or the photoresist profile, wherein the photomask corresponding to the mask layout design is configured for use in the fabrication of integrated circuits.

2. The method according to claim 1, further comprising: The computing system rasterizes the mask layout design into a grid that approximately corresponds to the thin mask of the photolithography mask; as well as The computational system approximates the thin mask into multiple edge grids, which represent the edges of the shape in different directions in the thin mask approximation of the photolithography mask, wherein the simulation of the three-dimensional light transmission in the near field of the photolithography mask uses the edge grids representing the edges of the shape in the thin mask approximation of the photolithography mask.

3. The method according to claim 2, wherein, The simulation of the three-dimensional light transmission in the near field of the photolithographic mask further includes: Based on the orientation associated with the edge mesh and the orientation kernel, convolving the edge mesh with the orientation kernel identifies directional light transmission at the edges approximating the thin mask in the mask layout design; and The thin mask approximation of the mask layout design is combined with the directional light transmission at the edge of the thin mask approximation of the mask layout design to determine the three-dimensional light transmission in the near field of the simulated photolithography mask.

4. The method according to claim 1, further comprising: The compact mask model is generated by the computing system through the following steps: Perform a three-dimensional simulation on the geometric mask pattern to determine the corresponding through-lens (TTL) target diffraction order of the geometric mask pattern; Extract the edge mesh from the geometric mask pattern; Determine the TTL diffraction order of the edge mesh of the geometric mask pattern; as well as The orientation kernel of the compact mask model is generated based at least in part on the TTL target diffraction order of the simulated geometric mask pattern and the TTL diffraction order of the edge mesh of the geometric mask pattern.

5. The method according to claim 4, wherein, Generating the compact mask model further includes: The TTL diffraction order of the edge mesh of the geometric mask pattern is combined with the Zernike coefficients to generate a complex Zernike polynomial; and The directional kernels of the compact mask model are generated, at least in part, based on the TTL target diffraction order and the Fuzernik polynomial of the simulated geometric mask pattern, wherein each directional kernel in the compact mask model corresponds to the sum of the Fuzernik polynomials.

6. The method according to claim 1, wherein, Simulating the three-dimensional light transmission in the near field of the photolithographic mask further includes: determining the diffraction order of the light transmission through the photolithographic mask, and removing any diffraction orders of the light transmission that cannot be collected by lenses in an optical system used to manufacture the integrated circuit.

7. The method according to claim 1, further comprising: The compact photoresist model is calibrated by the computing system, at least in part, based on the simulated three-dimensional light transmission in the near field of the photomask.

8. A system comprising: The memory system is configured to store computer-executable instructions; as well as The computing system, in response to executing the computer-executable instructions, is configured to: A thin mask approximation of a photolithographic mask derived from a mask layout design is used, and a compact mask model comprising multiple directional cores representing light diffraction in the near field of the photolithographic mask is used to simulate three-dimensional light transmission in the near field of the photolithographic mask. A wafer image or photoresist profile is generated, based at least in part on the simulated three-dimensional light transmission in the near field of the photomask. as well as The mask layout design is modified, at least in part, based on the wafer image or the photoresist profile, using an optical proximity correction (OPC) process, wherein the photomask corresponding to the mask layout design is configured for use in the fabrication of integrated circuits.

9. The system according to claim 8, wherein, The computing system, in response to executing the computer-executable instructions, is further configured to: The mask layout design is rasterized into a grid that approximately corresponds to the thin mask of the photolithographic mask; and The thin mask is approximated by dividing it into multiple edge grids, which represent the edges of the shape in different directions in the thin mask approximation of the photolithography mask, wherein the simulation of the three-dimensional light transmission in the near field of the photolithography mask uses the edge grids representing the edges of the shape in the thin mask approximation of the photolithography mask.

10. The system according to claim 8, wherein, In response to executing the computer-executable instructions, the computing system is also configured to simulate the three-dimensional light transmission in the near field of the photolithographic mask by the following steps: Based on the orientation associated with the edge mesh and the orientation kernel, the edge mesh is convolved with the orientation kernel, which identifies directional light transmission at the edges approximating the thin mask in the mask layout design; as well as The thin mask approximation of the mask layout design is combined with the directional light transmission at the edge of the thin mask approximation of the mask layout design to determine the three-dimensional light transmission in the near field of the simulated photolithography mask.

11. The system according to claim 8, wherein, In response to executing the computer-executable instructions, the computing system is also configured to generate the compact mask model through the following steps: Perform a three-dimensional simulation on the geometric mask pattern to determine the corresponding through-lens (TTL) target diffraction order of the geometric mask pattern; Extract the edge mesh from the geometric mask pattern; Determine the TTL diffraction order of the edge mesh of the geometric mask pattern; as well as The orientation kernel of the compact mask model is generated based at least in part on the TTL target diffraction order of the simulated geometric mask pattern and the TTL diffraction order of the edge mesh of the geometric mask pattern.

12. The system according to claim 11, wherein, In response to executing the computer-executable instructions, the computing system is also configured to generate the compact mask model through the following steps: The TTL diffraction order of the edge mesh of the geometric mask pattern is combined with the Zernike coefficients to generate a complex Zernike polynomial. as well as The directional kernels of the compact mask model are generated, at least in part, based on the TTL target diffraction order and the Fuzernik polynomial of the simulated geometric mask pattern, wherein each directional kernel in the compact mask model corresponds to the sum of the Fuzernik polynomials.

13. The system according to claim 8, wherein, The computing system, in response to executing the computer-executable instructions, is further configured to: simulate the three-dimensional light transmission in the near field of the photolithographic mask by determining the diffraction orders of light transmission through the photolithographic mask and removing any diffraction orders of the light transmission that cannot be collected by lenses in an optical system used to manufacture the integrated circuit.

14. An apparatus comprising at least one computer-readable storage device storing instructions configured to cause one or more processing devices to perform operations, the operations including: A thin mask approximation of a photolithographic mask derived from a mask layout design is used, and a compact mask model comprising multiple directional cores representing light diffraction in the near field of the photolithographic mask is used to simulate three-dimensional light transmission in the near field of the photolithographic mask. A wafer image or photoresist profile is generated, based at least in part on the simulated three-dimensional light transmission in the near field of the photomask. as well as The mask layout design is modified, at least in part, based on the wafer image or the photoresist profile, using an optical proximity correction (OPC) process, wherein the photomask corresponding to the mask layout design is configured for use in the fabrication of integrated circuits.

15. The apparatus according to claim 14, wherein, The instructions are configured to cause one or more processing devices to perform an operation, the operation further comprising: The mask layout design is rasterized into a grid that approximately corresponds to the thin mask of the photolithographic mask; and The thin mask is approximated by dividing it into multiple edge grids, which represent the edges of the shape in different directions in the thin mask approximation of the photolithography mask, wherein the simulation of the three-dimensional light transmission in the near field of the photolithography mask uses the edge grids representing the edges of the shape in the thin mask approximation of the photolithography mask.

16. The apparatus according to claim 14, wherein, The instructions are configured to cause one or more processing devices to perform an operation, the operation further comprising simulating the three-dimensional light transmission in the near field of the photolithographic mask by means of the following steps: Based on the orientation associated with the edge mesh and the orientation kernel, the edge mesh is convolved with the orientation kernel, which identifies directional light transmission at the edges approximating the thin mask in the mask layout design; as well as The thin mask approximation of the mask layout design is combined with the directional light transmission at the edge of the thin mask approximation of the mask layout design to determine the three-dimensional light transmission in the near field of the simulated photolithography mask.

17. The apparatus of claim 14, wherein the instructions are configured to cause one or more processing devices to perform an operation, the operation further comprising generating the compact mask model by means of the following steps: Perform a three-dimensional simulation on the geometric mask pattern to determine the corresponding through-lens (TTL) target diffraction order of the geometric mask pattern; Extract the edge mesh from the geometric mask pattern; Determine the TTL diffraction order of the edge mesh of the geometric mask pattern; as well as The orientation kernel of the compact mask model is generated based at least in part on the TTL target diffraction order of the simulated geometric mask pattern and the TTL diffraction order of the edge mesh of the geometric mask pattern.

18. The apparatus according to claim 17, wherein, The instructions are configured to cause one or more processing devices to perform an operation, the operation further comprising generating the compact mask model through the following steps: The TTL diffraction order of the edge mesh of the geometric mask pattern is combined with the Zernike coefficients to generate a complex Zernike polynomial. as well as The directional kernels of the compact mask model are generated, at least in part, based on the TTL target diffraction order and the Fuzernik polynomial of the simulated geometric mask pattern, wherein each directional kernel in the compact mask model corresponds to the sum of the Fuzernik polynomials.

19. The apparatus according to claim 14, wherein, The instructions are configured to cause one or more processing devices to perform an operation, the operation further comprising: simulating the three-dimensional light transmission in the near field of the photolithographic mask by determining the diffraction order of light transmission through the photolithographic mask and removing any diffraction orders of the light transmission that cannot be collected by lenses in an optical system used to manufacture the integrated circuit.

20. The apparatus according to claim 14, wherein, The instructions are configured to cause one or more processing devices to perform an operation, the operation further comprising: calibrating a compact photoresist model based at least in part on three-dimensional light transmission in the near field of the simulated photomask.

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