Calculation device and data moving method

Abstract

A computing device (10) is provided with a plurality of PEs (12) arranged two-dimensionally, and each PE (12) is provided with a selector (24) that outputs input data in a set direction. A PE (12) performs data movement via a selector (24) between the PE (12) and another PE (12) not adjacent to the PE (12), such as data movement between the PE (12) and another PE (12) not adjacent to the PE (12) located in an inclined direction, or data movement via the selector (24) within the PE (12), by a single process of a selector setting command and an input / output command. For example, data is moved from a register (22) to an arithmetic circuit (20).

Description

[0001] Cross-referencing of related applications This application is based on Japanese Application No. 2023-136237, filed on August 24, 2023, the contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to computing devices and data movement methods. Background Technology

[0003] A computing device consisting of multiple processors arranged in an array (two-dimensional) was developed.

[0004] In such computing devices, there is a need to increase the data processing speed. For example, Patent Document 1 describes a computing device having a first plurality of processing cores arranged in an array and a second plurality of processing cores arranged in an array. A subset of the first plurality of processing cores of this computing device is configured between the data processing circuit and the second plurality of processing cores.

[0005] Existing technical documents Patent documents Patent Document 1: US Patent No. 11086574 Summary of the Invention

[0006] In this computing device where processors are arranged in an array, data input and output with the processors are performed, for example, using broadcasting or direct neighbors. Figure 31 As shown by the dashed lines in the illustrated computing device 10, broadcasting enables access to all processing elements (PEs) 102 and external memory 104. Directly adjacent elements are as follows: Figure 31 As shown by the solid line, access is possible between adjacent PE12 units in the top, bottom, left, and right directions.

[0007] Even if you want to use broadcasting and direct adjacent data input / output between two non-adjacent PE102s (top, bottom, left, and right), direct data input / output between two non-adjacent PE102s is not possible. For example, when moving data from PE102B to PE102C, it requires two separate processes, just like moving data from PE102B to PE102A and from PE102A to PE102C. Therefore, in data aggregation processing such as Sum processing or Max processing, data movement between PE102s takes time.

[0008] Furthermore, when data is moved within a PE102, such as between a register and an arithmetic circuit, multiple processing steps are sometimes required. In such cases, data movement within the PE102 also takes time.

[0009] The purpose of this disclosure is to provide a computing device and a data movement method that enable faster data movement within a processor.

[0010] This disclosure employs the following technical means to solve the aforementioned problems. The reference numerals in parentheses within the claims are examples indicating the correspondence with specific units described in the embodiments described later as an example, and do not limit the technical scope of this disclosure.

[0011] One aspect of the present disclosure is a computing device comprising a plurality of processors, each processor having a selector that outputs input data in a predetermined direction. The processor performs, through a single processing of a setting command of the selector and an input / output command of the data, movement of the data via the selector between non-adjacent processors, or movement of the data via the selector within the processor.

[0012] For example, sometimes processor B moves data towards processor C, which is not adjacent in the tilt direction. To do this, processor B outputs data to processor C via adjacent processor A. In this configuration, processor A, which receives the data, outputs the data from processor B to processor C according to the selector's setting command and the data input / output command; therefore, processor A does not actually perform any processing on the data. That is, data is essentially output directly from processor B to processor C. Furthermore, when focusing on processor B, data from the processor adjacent to the right is output to the processor adjacent to the lower side (D) according to the selector's setting command, and data is input from the processor adjacent to the upper side. In this way, by assigning the same selector setting command to all processors, data can be moved directly to processors in the tilt direction (other non-adjacent processors) simultaneously via all processors.

[0013] Furthermore, data movement within the processor is also performed via selectors. Data movement within the processor includes, for example, the movement of data between registers and arithmetic circuitry.

[0014] Furthermore, the movement of data to other non-adjacent processors, and the movement of data within a processor, is performed through a single processing of selector setting commands and data input / output commands.

[0015] This configuration enables faster data movement within the processor through movement processing via such a selector.

[0016] In the aforementioned computing device, the processor may also include a register connected to the selector and used to hold the data.

[0017] In the aforementioned computing device, the processor may also include multiple selectors.

[0018] In the aforementioned computing device, the processor may also include a computing circuit connected to the selector and performing calculations on the data. The processor performs data movement with the processor and calculations based on the computing circuit by processing the set command of the selector and the input / output command of the data.

[0019] In the aforementioned computing device, the computing circuit that performs specific processing may be located in a portion of the processor, and when performing the specific processing, data may be moved to the portion of the processor via the selector.

[0020] In the aforementioned computing device, the wiring used in data movement between the processor and the processor may also be provided at predetermined intervals for each of the processors.

[0021] In the aforementioned computing device, when performing sorting processing of score data representing the size held by a plurality of processors, the processor determines the size of the score data to be moved between adjacent processors via the selector, and performs an exchange process to move the score data to the other processor based on the size determination result, and repeatedly performs the exchange process with different combinations of adjacent processors.

[0022] Alternatively, the data input to the processor may be associated with score data representing the size of the data. The processor determines the size of the score data to be moved between adjacent processors via the selector, moves the score data to the other processor based on the size determination result, and maintains the move destination data representing the move destination of the score data. The processor moves the data between adjacent processors based on the move destination data.

[0023] In the aforementioned computing device, the data input to the processor may also be associated with score data representing the size of the data or index data representing the sorting order. The processor determines the size of the score data or index data to be moved between adjacent processors via the selector, moves the score data or index data to another processor based on the size determination result, and maintains the move destination data representing the move destination of the score data or index data. The processor moves the data between adjacent processors based on the move destination data.

[0024] In the aforementioned computing device, the relative address representing the destination of the data may be associated with the processor. The processor determines the size of the relative address to be moved between adjacent processors via the selector, and based on the size determination result, causes another processor to move the relative address, while maintaining the move destination data representing the move destination of the relative address. After the data and the moved relative address are established to correspond, the processor moves the data between adjacent processors based on the reverse order of the movement represented by the move destination data.

[0025] In the aforementioned computing device, it is also possible that, when the processor inputs data associated with the score data, the index data, or the relative address from external memory, the processor moves the data between adjacent processors based on the move destination data.

[0026] In the aforementioned computing device, the multiple processors may be virtually divided into a first group consisting of three or more adjacent processors. The size of multiple index data is determined for each first group. Based on the determination result, a first sorting process is performed to move the index data and the data associated with the index data. Then, the three or more adjacent processors are virtually divided into a second group different from the first group. The size of multiple index data is determined for each second group. Based on the determination result, a second sorting process is performed to move the index data and the data associated with the index data. The first sorting process and the second sorting process are repeated.

[0027] In the aforementioned computing device, when the number of data to be sorted is greater than the number of processors, one processor assigns a number to each plurality of data and maintains it, and multiple processor groups are virtually set up. The multiple processor groups are collections of multiple processors that maintain data with the same number. The multiple processor groups are set such that the processors constituting the processor groups are in reverse order in at least one of the row direction and column direction relative to the processor group that serves as the reference. After performing the first sorting process according to each first group divided within the processor group, the second sorting process is performed according to each second group that includes groups divided across multiple processor groups, and the first sorting process and the second sorting process are repeated.

[0028] In the aforementioned computing device, a first pre-processor may be provided adjacent to the outer edge processor located at the end of the processor arranged in a two-dimensional configuration. The first pre-processor is a processor for sorting the plurality of data held by the outer edge processor in the second sorting process.

[0029] In the aforementioned computing device, processing may also be performed on each of the data segments divided by the specified number of bits, among a plurality of processors that hold the input data in segments divided by the specified number of bits.

[0030] In the aforementioned computing device, the computing device may also include a preprocessor that does not have computing circuitry but has the selector and a register for holding the data, and the processor and the preprocessor move data via the selector.

[0031] In the aforementioned computing device, the actions for performing the functions required by the computing device may be preset for each processor or set by data, and different actions may be performed by each processor according to the requirements of the function.

[0032] One aspect of the data movement method disclosed herein is a data movement method of a computing device including multiple processors, wherein each processor has a selector that outputs input data in a set direction, and the processor performs data movement via the selector between non-adjacent processors or within the processor via the selector through a single processing of a setting command of the selector and an input / output command of the data.

[0033] According to this disclosure, data can be moved faster in the processor. Attached Figure Description

[0034] The foregoing and other objects, features, and advantages of this disclosure will become more apparent with reference to the accompanying drawings and through the following detailed description. The accompanying drawings are as follows: Figure 1 This is a schematic diagram of the PE included in the computing device of the embodiment.

[0035] Figure 2 This is a schematic diagram showing the data movement from the backoff register of a PE in one implementation to the registers of other non-adjacent PEs.

[0036] Figure 3 This is a schematic diagram showing the data movement from the register of a PE in one implementation to the backoff register of another non-adjacent PE.

[0037] Figure 4 It is a schematic diagram showing the data movement from one PE in an implementation to multiple other PEs in the same row.

[0038] Figure 5 It is a schematic diagram showing the data movement from one PE in the implementation to all other PEs.

[0039] Figure 6 This is a schematic diagram showing the transfer of data from the external memory of the implementation to a PE and the data movement from that PE to all PEs.

[0040] Figure 7 This is a schematic diagram showing the movement of data from the external memory of the implementation method according to each row.

[0041] Figure 8 This is a schematic diagram illustrating other embodiments of data movement from the external memory of the implementation to all PEs.

[0042] Figure 9 This is a schematic diagram showing the data movement during computational processing in the accompanying implementation of the arithmetic circuit.

[0043] Figure 10 This is a schematic diagram showing the data movement when the computing device of the embodiment performs a convolution operation.

[0044] Figure 11 This is a schematic diagram illustrating the data movement of the computing device in an embodiment where only a portion of the PEs have specific computing circuitry.

[0045] Figure 12 This is a schematic diagram illustrating the data movement of the computing device in an embodiment where only a portion of the PEs have specific computing circuitry.

[0046] Figure 13This is a schematic diagram showing the configuration of the wiring between PEs in an embodiment. (A) shows the arrangement of all wiring between adjacent PEs, and (B) shows the arrangement of omitting a portion of the wiring at intervals.

[0047] Figure 14 This is a schematic diagram illustrating the first processing of skewed data movement in the wiring method of the interval elimination implementation. (A) shows the data movement in four adjacent PEs, and (B) shows the positions of four adjacent PEs in the computing device with dashed lines. Figure 15 This is a schematic diagram of the second processing of skewed data movement in the manner in which wiring is periodically eliminated in the implementation method. (A) shows the data movement in four adjacent PEs, and (B) shows the positions of four adjacent PEs in the computing device with dashed lines.

[0048] Figure 16 This is a schematic diagram showing the data movement when sorting is performed using the computing device described in the embodiment.

[0049] Figure 17 This is a schematic diagram showing the data movement in the computing device when sorting the data in one row of the computing device in one processing step.

[0050] Figure 18 This is a schematic diagram showing the data movement between PEs when sorting the data in one row of the computing device of the embodiment in one processing step.

[0051] Figure 19 This is a schematic diagram showing the data movement when sorting multiple rows of data in the computing device of the implementation method.

[0052] Figure 20 This is a diagram showing the arrangement order of the index data associated with the sorting of the computing device in the implementation method before and after sorting. (A) is before sorting, and (B) is after sorting.

[0053] Figure 21 The diagram shows the movement of data associated with index data in the implementation method. (A) is the first or odd-numbered processing step, and (B) is the second or even-numbered processing step.

[0054] Figure 22 This diagram illustrates the relative addresses and input data sorted by the arithmetic unit during the sorting process of moving to a relative address position in the implementation method.

[0055] Figure 23 This is a diagram illustrating the sorting process of data for each group in the implementation method.

[0056] Figure 24This is a diagram illustrating the first sorting process when the amount of sorted data in the implementation method is greater than the number of PEs.

[0057] Figure 25 This is a diagram illustrating the second sorting process when the amount of sorted data in the implementation method is greater than the number of PEs.

[0058] Figure 26 This is a schematic diagram of a preparatory PE located adjacent to the outer edge of the PE in the embodiment.

[0059] Figure 27 This is a graph showing the relationship between the data used in the convolution operation in the implementation method and PE.

[0060] Figure 28 This is a schematic diagram of a computing device for a preparatory PE with an implementation method.

[0061] Figure 29 This is a diagram illustrating the one-dimensional sorting process accompanying the SIMD processing in the implementation method.

[0062] Figure 30 This is a diagram illustrating the sorting process in two dimensions accompanying the SIMD process in the implementation method.

[0063] Figure 31 This is a schematic diagram representing the data movement between PEs in existing computing devices. Detailed Implementation

[0064] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. Furthermore, the embodiments described below represent one example of implementing the present disclosure and are not intended to limit the present disclosure to the specific configurations described below. When implementing the present disclosure, specific configurations corresponding to the embodiments may be appropriately adopted.

[0065] Figure 1 This is a schematic diagram of the PE (Processing Element) 12, which is the processor included in the computing device 10 of this embodiment.

[0066] The computing device 10 includes a plurality of PE12. Furthermore, in Figure 1 In the example, four PE12s are arranged as in PE12A~12D, but the number of PE12s provided by the arithmetic device 10 can be multiple. In addition, multiple PE12s can be arranged not only in a two-dimensional (array) shape, but also in a multi-dimensional shape of three dimensions or more, as described later.

[0067] The PE12 constituting the arithmetic unit 10 is electrically connected via wiring 14 for data movement between adjacent PE12. Furthermore, in Figure 2In this embodiment, it is assumed that even if the wiring 14 between PE12s is omitted, adjacent PE12s are still connected by wiring 14. Furthermore, data movement in this embodiment also includes the concept of data replication.

[0068] In addition, the arithmetic unit 10 is capable of performing various processes such as data movement and calculation on each PE12. However, if the settings are configured according to each PE12 by a program, the amount of programming required will increase.

[0069] Therefore, the actions required by the computing device 10 can be preset or data-set for each PE12, and different actions can be performed for each PE12 according to the requirements of the function. Furthermore, this data is the setting data input to the PE12, which is different from the data for moving between PE12, etc. Thus, it is not necessary to set the actions of each PE12 through a program, reducing the amount of programming required to enable the computing device 10 to function.

[0070] The PE12 in this embodiment includes an arithmetic circuit 20, a register 22, a selector 24, and a backoff register 26.

[0071] The arithmetic circuit 20 is connected to the selector 24, and performs various arithmetic operations such as ==, ! =, >, >=, <, <=, >>, <<, or, and, min, max, clip, add, sub, mul, div, mod, and macc. The arithmetic circuit 20 performing the arithmetic operations can appropriately select the arithmetic device 10. In this embodiment, the arithmetic device 10 may also consist of a PE 12 equipped with multiple arithmetic circuits 20, which can select multiple arithmetic operations from different arithmetic operations or multiple identical arithmetic operations prepared by one PE 12 and perform the arithmetic operations simultaneously. Alternatively, each PE 12 may perform different arithmetic operations, and the arithmetic device 10 may perform multiple different arithmetic operations simultaneously.

[0072] Register 22 is a storage unit connected to selector 24 and holding (storing) data. For example, arithmetic circuit 20 performs arithmetic processing on the data held in register 22 and stores the result in register 22.

[0073] Selector 24 outputs the data input to PE12 in a set direction. The output direction of the data is either an adjacent PE12 or its own arithmetic circuit 20, register 22, backoff register 26, etc. Furthermore, in this embodiment, PE12 performs data movement with other non-adjacent PE12 via selector 24 through a single processing of the selector 24's setting command (hereinafter referred to as "selector setting command") and data input / output command (hereinafter referred to as "data input / output command").

[0074] Furthermore, the selector setting command is based on the setting of the output direction of the data from selector 24. For example, the selector setting command sets the direction of other PE12s that become the output destination of data, the direction of the arithmetic circuit 20, register 22, and backoff register 26 within the same PE12 that become the output destination of data. The data input / output command is a selection command for data that becomes the object of input / output via selector 24, and this data is held in register 22 or backoff register 26.

[0075] Furthermore, in this embodiment, PE12 moves data within PE12 via selector 24 through a single processing of selector setting commands and data input / output commands. Data movement within PE12 via selector 24 includes, for example, data movement between backoff register 26 and arithmetic circuit 20, data movement between arithmetic circuit 20 and register 22, and data movement between register 22 and backoff register 26.

[0076] Backoff register 26 is a register connected to selector 24 and temporarily holds data. In this embodiment, the storage capacity of backoff register 26 is smaller than that of register 22, for example, a storage capacity sufficient to hold one piece of data. Here, register 22 can hold multiple pieces of data for the processing program, therefore the address of the held data needs to be specified. On the other hand, backoff register 26 holds only one piece of data, therefore no address specification is required. Therefore, inputting data to and outputting data from backoff register 26 can be performed simply and quickly. Alternatively, a single PE12 may have multiple backoff registers 26, capable of holding multiple pieces of data.

[0077] As described above, in this embodiment, PE12 inputs and outputs data to / from the arithmetic circuit 20, register 22, and backoff register 26 via selector 24. Furthermore, data movement between PE12 is also performed via selector 24. This data movement between PE12 includes not only data movement between adjacent PE12, but also data movement between non-adjacent PE12, such as data movement towards PE12 in an inclined direction or data movement away from multiple PE12.

[0078] Reference Figure 1 This indicates the data movement via selector 24. Figure 1 The dashed line represents the path of data movement in the direction of the tilt. That is, in Figure 1 In the example shown by arrow A, the data movement from PE12B to PE12C is illustrated. This data movement from PE12B to PE12C is executed through a single processing step involving selector setting commands and data input / output commands.

[0079] More specifically, the data input to PE12B is held (input) to the backoff register 26 of PE12B via selector 24. Then, according to the new processing command, PE12B outputs the data held in backoff register 26, and the output data is output to PE12A via selector 24. PE12A controls selector 24 to output the data input from PE12B to PE12C. The control of selector 24 is performed according to the processing command described above. Furthermore, the control of selector 24 can be performed, for example, by the arithmetic circuit 20, or by a dedicated control circuit built into selector 24.

[0080] Then, PE12C holds (inputs) the data input from PE12B via PE12A to the backoff register 26 via selector 24. Furthermore, in Figure 1 In the example, the data held in the backoff register 26 of PE12C is output to the other adjacent PE12 via selector 24 according to the second processing command.

[0081] In this way, PE12A, which carries data, simply outputs data to PE12C via selector 24 without performing any processing on the data. Therefore, data is essentially output directly from PE12B to PE12C. Through this movement processing via selector 24, the computing device 10 of this embodiment can perform data movement between PE12 faster without increasing the wiring 14 between PE12.

[0082] Additionally, PE12B outputs data from the adjacent PE12 to its right to PE12D according to the selector setting command, causing the backoff register 26 to retain data from the adjacent PE12 above. In this way, by assigning the same selector setting command to all PE12, data can be moved directly to the PE12 in the tilt direction (other non-adjacent PE12) simultaneously in all PE12.

[0083] Furthermore, the single processing based on the selector setting command and input / output command described in this embodiment refers to the process up to the point where data output from storage units such as backoff register 26 or register 22 is re-inputted (held) to storage units such as backoff register 26 or register 22 via selector 24. As will be described later, a single processing command may also include an arithmetic processing command for causing the arithmetic circuit 20 to perform arithmetic processing on the data, together with the selector setting command and input / output command.

[0084] Furthermore, if the bit width for data movement between PE12 is, for example, 32 bits, and the data being moved is 8 bits, then four data bits are moved between PE12 at a time. Therefore, for example, when performing a skewed data movement such as moving data from PE12B to PE12C, skewed movements in four directions can be performed simultaneously. In this way, by taking into account the bit width of data movement between PE12 and the movement pattern of the number of data bits, data movement in multiple directions can be performed simultaneously.

[0085] Furthermore, a single PE12 can also have multiple selectors 24. By having multiple selectors 24 in a single PE12, data movement in multiple directions can be performed simultaneously. For example, in a PE12 with four selectors 24, data movement in four directions can be performed simultaneously. For example, a PE12 with multiple selectors 24 that move data in units of 1 byte can perform data movement independently for each byte. In the case of moving 4 bytes of data, the PE12 can use four selectors 24 to perform data movement simultaneously, thus enabling multiple data movements to be performed simultaneously.

[0086] Furthermore, when a PE12 has multiple selectors 24, the multiple selectors 24 can share a single wiring 14, or multiple wirings 14 can be provided between PE12 corresponding to each selector 24.

[0087] (Other examples of data movement between PEs) The following is for reference Figures 2-5 This illustrates other examples of data movement between PE12.

[0088] Figure 2 This is a schematic diagram showing the data movement from the backoff register 26 of PE12 to the register 22 of another non-adjacent PE12. Figure 2 In the example, the data held in backoff register 26 of PE12B is moved to register 22 of PE12C.

[0089] Additionally, PE12B outputs data from the adjacent PE12 to its right to PE12D according to the selector setting command, while register 22 retains data from the adjacent PE12 above. In this way, by assigning the same selector setting command to all PE12, data can be simultaneously moved directly to the PE12 in the tilt direction (other non-adjacent PE12) in all PE12.

[0090] Figure 3 This is a schematic diagram showing the data movement from register 22 of PE12 to backoff register 26 of other non-adjacent PE12s. Figure 3In the example, the data held in register 22 of PE12B is moved to backoff register 26 of PE12C.

[0091] Additionally, PE12B outputs data from the adjacent PE12 to its right to PE12D according to the selector setting command, causing the backoff register 26 to retain data from the adjacent PE12 above. In this way, by assigning the same selector setting command to all PE12, data can be moved directly to the PE12 in the tilt direction (other non-adjacent PE12) simultaneously in all PE12.

[0092] like Figure 2 , 3 As shown, the movement of data from register 22 or backoff register 26 of PE12 to register 22 or backoff register 26 of other PE12 is performed via selector 24.

[0093] Figure 4 This is a schematic diagram showing the movement of data from one PE12 to multiple other PE12s in the same row. As an example, Figure 4 This illustrates the output of data from PE12X (second column from the left) in the arithmetic unit 10 to other PE12s arranged in the same row. Thus, in... Figure 4 In the example, data is moved from PE12X to the left and right directions to other PE12s.

[0094] Figure 5 This is a schematic diagram showing the data movement from one PE12 to all other PE12s. As an example, Figure 5 This illustrates the output data from PE12X (second column from the left, second row from the top) in the arithmetic unit 10 to all other PE12s arranged in the same row. Figure 5 In the example, when PE12X outputs data to other PE12s in the same column, the PE12 that received the data outputs data to other PE12s in the same row. Thus, in Figure 5 In the example, data from other PE12s is moved upwards, downwards, leftwards, and rightwards, centered on PE12X.

[0095] In addition, Figure 4 , 5 In the example, the data input to PE12 is kept in backoff register 26, but it is not limited to this; the data can also be kept in register 22.

[0096] (An example of moving data from external storage to PE) The following is for reference Figures 6-8 This illustrates an example of data transfer from external memory 30 to PE12.

[0097] Figure 6 This is a schematic diagram illustrating the transfer of data from external memory 30 to a single PE12, and the data movement from that PE12 to all the PE12 constituting the arithmetic unit 10. Figure 6 In the example, data is transferred from external memory 30 to the top-left PE12A, and the same data is output from PE12A to all other PE12s. Figure 6 In this example, each PE12 holds data in register 22 via selector 24. Thus, data can be transferred from external memory 30 to all PE12 in a single process.

[0098] Figure 7 This is a schematic diagram showing the movement of data line by line starting from external memory 30. Figure 7 In the example, the same or different data is transferred from external memory 30 to PE12A, 12E, 12I, and 12M contained in the left-hand column, and data is moved from PE12A, 12E, 12I, and 12M to other PE12 in the same row. Figure 7 In this example, each PE12 holds data in register 22 via selector 24. Thus, data can be transferred from all external memories 30 to PE12 in a single process.

[0099] Alternatively, different data can be output from external memory 30 in stages, so that registers 22 of each PE12 hold different data. For example, in Figure 7 In the configuration, in the first process, data "1" is transferred from external memory 30 to PE12A. In the second process, data "2" is transferred from external memory 30 to PE12A, and data "1" is moved from PE12A to PE12B. In the third process, data "3" is transferred from external memory 30 to PE12A, and data "2" is moved from PE12A to PE12B, while data "1" is moved from PE12B to PE12C. In the fourth process, data "4" is transferred from external memory 30 to PE12A, and data "3" is moved from PE12A to PE12B, data "2" is moved from PE12B to PE12C, while data "1" is moved from PE12C to PE12D. Thus, in the four processes, data "4" is held in PE12A, data "3" is held in PE12B, data "2" is held in PE12C, and data "1" is held in PE12D.

[0100] Furthermore, when data is transmitted from external memory 30 to each PE12 via burst transmission, each PE12 receives data from external memory 30 only when necessary. Burst transmission may also transmit multiple data sets simultaneously, rather than transmitting data to each PE12 one by one.

[0101] In addition, when data at any address is transferred from external memory 30 to each PE12, each PE12 maintains a relative address, and only the data at its relative address is stored in register 22 of the PE12 in the data transferred from external memory 30.

[0102] Access circuitry to external memory 30 does not necessarily require all PE12s; for example, only the first column of PE12s or odd-numbered columns of PE12s may be required. Furthermore, PE12s transferring data from external memory 30 can simultaneously move data to other PE12s while other processes are in operation, and can also input data from other PE12s. Additionally, data can be compressed, and PE12s may have functions for decompressing compressed data and compressing data.

[0103] Alternatively, the PE12s at the ends of the column direction may have access circuits to the external memory 30, allowing data to be transferred from the external memory 30 column by column. Alternatively, the PE12s at the left and right ends of the row direction may have access circuits to the external memory 30, allowing data to be transferred from the external memory 30 to the PE12 simultaneously from the left and right sides of the row. This reduces data movement time. Similarly, the PE12s at the top and bottom of the column direction may have access circuits to the external memory 30, allowing data to be transferred from the external memory 30 to the PE12 simultaneously from the top and bottom of the column. Alternatively, data may be transferred from the external memory 30 to the PE12 located in the center of a row or column, from which data moves upwards, downwards, left, or right to the PE12.

[0104] Furthermore, such as Figure 8 As shown, two wirings 14 can also be provided between PE12 and other adjacent PE12s in the same row. PE12 and its adjacent PE12 can simultaneously move other data to two non-adjacent adjacent PE12s. This allows for faster data movement between PE12s. Furthermore, the wirings 14 between adjacent PE12s are described below as two doubled (multiplexed) wirings 14.

[0105] (Data movement accompanying computation) In this embodiment, PE12 connects to selector 24 and arithmetic circuit 20 to perform arithmetic processing on data moved from other PE12s via selector 24. That is, in this embodiment, PE12 can perform data movement between PE12s and arithmetic processing by arithmetic circuit 20 in a single processing of selector setting commands and data input / output commands. This speeds up the combined processing of arithmetic processing and data movement.

[0106] Figure 9 This is a schematic diagram illustrating the data movement during the computational processing of the arithmetic circuit 20 in this embodiment. Figure 9 The example shows the case where PE12B in the second column sums the results of the operations performed by each PE12A~12D constituting the row, and outputs the sum to the other PE12s. In addition, PE12B has two backoff registers, 26A and 26B.

[0107] First, in the initial processing, PE12A, 12C, and 12D perform calculations on the data stored in the backoff register 26 via the arithmetic circuit 20, and output the results to PE12B. That is, PE12B aggregates the calculation results from multiple other PE12s. Then, the arithmetic circuit 20 of PE12B sums the data input from PE12A, 12C, and 12D and stores it in the backoff register 26B.

[0108] In the second processing step, the arithmetic circuit 20 of PE12B sums the data stored in backoff register 26B and the data stored in backoff register 26A of PE12B. Then, PE12B outputs (expands) the summed result to the other PE12A, 12C, and 12D. The other PE12A, 12C, and 12D store the data input from PE12B in backoff register 26. Additionally, PE12B also stores the summed result in backoff register 26A.

[0109] In operations such as AND, OR, and SUM, to shorten the overall data movement distance, the data is concentrated at PE12 (located at the center in the row direction (left-right) or column direction (up-down)). Figure 9 In the example, the processing is done in the manner of PE12B. The result of the operation is obtained from the PE12 located at the center, so the distance the data moves is also shortened when the operation result is output (copied) to other PE12s.

[0110] The PE12, which collects data from top to bottom or left to right, sometimes uses 3 or 4 inputs instead of 2 inputs for processing. Therefore, the configuration of the PE12 for data collection can also be different from other PE12 configurations. Figure 9 In the example, the PE12B that collects data has two backoff registers 26A and 26B. Furthermore, the PE12 that collects data can also perform calculations multiple times, row by row and column by column. Therefore, the wiring 14 between PE12s can also be doubled, allowing for a single operation. Figure 9 As shown, there was a first gathering and a second unfolding.

[0111] Furthermore, PE12 may also have multiple arithmetic circuits 20. The arithmetic processing functions of the multiple arithmetic circuits 20 may be the same or different. PE12 with multiple arithmetic circuits 20 can also move data between the arithmetic circuits 20 via selector 24.

[0112] Figure 10 This is a schematic diagram illustrating the data movement when the computing device 10 of this embodiment performs a convolution operation. Figure 10 In the example, the 2×2 convolution operation is divided into four steps and performed repeatedly. Figure 10 In the diagram, the left side of each diagram represents a data movement in one PE12, and the right side diagram uses arrows to represent data movements in multiple PE12s provided by the computing device 10.

[0113] First, in the initial processing, data is copied from register 22 within PE12 to backoff register 26. This data is pre-multiplied by weights for the convolution operation.

[0114] In the second processing step, PE12 moves the data it holds in register 22 to the left of PE12. Therefore, PE12 moves data from PE12 on the right, and the arithmetic circuit 20 adds this moved data to the data held in backoff register 26. The result of this addition is held in backoff register 26.

[0115] In the third processing, PE12 moves the data it holds in register 22 upwards to PE12. Therefore, PE12 moves data from PE12 downwards, and the arithmetic circuit 20 adds the moved data to the data held in backoff register 26, and holds the sum in backoff register 26.

[0116] In the fourth processing step, PE12 moves the data it holds in register 22 to the upper left of PE12. Therefore, PE12 moves data from the lower right of PE12, and the arithmetic circuit 20 adds the moved data to the data held in backoff register 26, and holds the sum in backoff register 26.

[0117] Furthermore, by multiplexing the wiring 14 between PE12, the computing device 10 can perform convolution operations in fewer steps, or it can be configured to compute larger kernel sizes.

[0118] Next, refer to Figure 11 , 12This embodiment explains that the arithmetic device 10 performs data movement only when a portion of the PE12 has arithmetic circuits 20 for specific processing. When performing specific processing, data is moved to a portion of the PE12 via the selector 24. Having specific arithmetic circuits 20 only in a portion of the PE12 means, for example, not equipping all PE12 with arithmetic circuits 20 that are used relatively infrequently, such as exp, log, sin, asin, and floating-point calculations, but rather equipping them, for example, every other one in a row or column.

[0119] In addition, specific operational circuits 20 can also be distributed across PE12. For example, in order to ensure that the circuit size of PE12 does not deviate, the log operational circuit 20 only has odd-row, even-column PE12, and the sin operational circuit 20 only has even-row, odd-column PE12.

[0120] As an example, Figure 11 , 12 This refers to the case where only odd-numbered rows and columns of PE12A have an exp operation circuit 20, and PE12A performs exp operations on the data held in registers 22 of PE12A~12D.

[0121] First, in the initial processing, the PE12A performs an exp operation on the data stored in its own register 22 and stores the result in register 22.

[0122] In the second processing, PE12B moves data to PE12A via PE12D and PE12C. PE12A performs an exp operation on the data moved from PE12B, moving the result back to PE12B, which then stores the result in register 22.

[0123] In the third process, PE12C moves data to PE12A. PE12A performs an exp operation on the data moved from PE12C, and the result is moved back to PE12C via PE12B and PE12D. PE12C then stores the result in register 22.

[0124] In the fourth processing step, PE12D moves data to PE12A via PE12C. PE12A performs an exp operation on the data moved from PE12D, and moves the result back to PE12D via PE12B. PE12D then stores the result in register 22.

[0125] (Processing of each line) The arithmetic processing unit 10 in this embodiment can also assign multiple arithmetic operations to each row to process multiple rows at once. For example, the first row can be assigned as mul, the second row as add, the third row as rshift, and the fourth row as clip.

[0126] Furthermore, the arithmetic device 10 of this embodiment can also perform the same processing as a pipeline by reading (inputting) data and writing (outputting) data simultaneously with the arithmetic processing.

[0127] For example, in the first processing step, PE12 in the first row reads data 1 from external memory 30. In the second processing step, PE12 in the first row reads data 2 from external memory 30 while the arithmetic circuit 20 of PE12 in the first to fourth rows performs arithmetic processing on data 1, and simultaneously stores the result in register 22 of PE12 in the fourth row. In the third processing step, PE12 in the first row reads data 3 from external memory 30 while the arithmetic circuit 20 of PE12 in the first to fourth rows performs arithmetic processing on data 2, and simultaneously stores the result in register 22 of the fourth row. PE12 in the fourth row then writes the result of the arithmetic processing on data 1 back to external memory 30.

[0128] The arithmetic unit 10 repeatedly performs this series of processes through pipelined processing corresponding to the required data. Thus, it is possible to perform the processing from data processing to writing the processing result to the external memory 30 while reading data from the external memory 30.

[0129] Alternatively, PE12 may retrieve data from the register 22 of another PE12 that holds the processed data instead of from the external memory 30. Furthermore, the processed data may be output to the register 22 of a PE12 that does not have the arithmetic circuit 20, instead of to the external memory 30. This reduces the time required for data input and output when performing different processes consecutively. Additionally, in this case, the data capacity that the register 22 of the first and last rows of PE12 can hold can be increased. Furthermore, if the arithmetic processing is performed in the column direction, the data capacity that the register 22 of the first and last columns of PE12 can hold can also be increased.

[0130] Alternatively, a data storage unit may be provided outside the first row, outside the last row, outside the first column, and outside the last column, from which data is input to PE12 or from PE12 to the data storage unit.

[0131] Alternatively, if the number of rows to be processed is small, PE12 with increased capacity of register 22 can be provided every few rows, and data can be transferred from PE12 to external memory 30.

[0132] Furthermore, in cases where multiple processing steps are required to perform processing that should be performed due to insufficient number of rows in the PE12 of the arithmetic device 10, the following processing can be performed repeatedly: the first arithmetic processing performed by the PE12 from the first row to the last row is stored in the register 22 of the PE12 of the last row, and in the second arithmetic processing, the result of the arithmetic processing from the last row to the first row is stored in the register 22 of the PE12 of the first row.

[0133] In addition, when the operation is performed on PE12 of different columns, the operation can be performed while moving the data from PE12 of different columns.

[0134] Alternatively, data whose processing has ended in the final line can be moved to register 22 of the line above instead of being stored in the backoff register 26 of the final line for use in the next pipelined process. This eliminates the need for multiple backoff registers 26 in the final line, allowing subsequent processing to begin continuously from the line above. Furthermore, data can also be stored in the idle backoff registers 26 or 22 of other PE12s instead of in the backoff registers 26 or 22 of the PE12 that has finished processing.

[0135] (The configuration of a computing device that excludes a portion of the wiring between PEs) In this embodiment, the computing device 10 may also be provided with wiring 14 for data movement between PE12 at predetermined intervals between PE12. Figure 13 This is a schematic diagram showing the configuration of the wiring 14 between PE12. Figure 13 (A) indicates the usual practice of installing wiring 14 between all adjacent PE12s. Figure 13 (B) indicates that a portion of wiring 14 was removed at intervals.

[0136] exist Figure 13 In example (B), wiring 14 is provided between PE12 in the column direction every other PE12. That is, in Figure 13 In (B), the column-direction wiring 14 becomes half of the usual method. Furthermore, the spacing removal of wiring 14 can also be performed in the row direction.

[0137] Reference Figure 14 , 15 This indicates that the interval eliminated the skewed data movement in the wiring 14 method.

[0138] Figure 14 This indicates that the first processing step in the method of removing skewed data movement in wiring 14 was performed at intervals. Figure 15 This indicates the second processing step. Additionally, Figure 14 (A) Figure 15 (A) represents the data movement in four adjacent PE12s. Figure 14 (B) Figure 15 (B) is represented by dashed lines in the arithmetic unit 10. Figure 14 (A) Figure 15 The positions of the four adjacent PE12s are shown in (A). Figure 14 , 15 As shown, in the method of excluding wiring 14 by interval, as an example, four adjacent PE12 are grouped together to set the selector 24, and the data movement is carried out in two stages.

[0139] In addition, the method of intermittently removing wiring 14 is envisioned for use in arranging PE12 into multidimensional arrangements of three-dimensional, four-dimensional or higher dimensions.

[0140] The multidimensional arrangement represents PE12 in a multidimensional coordinate system that includes other directions (ZW direction, etc.) in addition to the two-dimensional directions (matrix direction, XY direction). In the multidimensional arrangement, PE12 can input and output data with adjacent PE12 in the XY direction, and can also input and output data with adjacent PE12 in other dimensions such as the ZW direction. With such a configuration of the computing device 10, the wiring 14 between PE12 required for data movement can be reduced.

[0141] If PE12 are arranged in a multidimensional or three-dimensional manner, each PE12 is connected to PE12 in the XY and ZW directions via wiring 40. However, the frequency of data movement between PE12 in the ZW direction is less than that between PE12 in the XY direction. Therefore, as described above, the circuit configuration can be simplified by periodically removing a portion of the wiring 14 in the ZW direction, which has a lower usage frequency.

[0142] (Sorting process) The sorting process of setting the values ​​held in registers 22 of multiple PE12 in ascending or descending order will be described. The sorting process involves repeatedly determining the size of the score data, representing the size held in registers 22 of two PE12, using the arithmetic circuit 20 of one PE12, and shifting the data according to the size relationship of the score data. For this purpose, the arithmetic circuit 20 functions as a switching circuit that changes the PE12 holding the score data according to the size relationship of the score data.

[0143] Figure 16This is a schematic diagram illustrating the movement of score data when sorting is performed by the computing device 10 of this embodiment. Furthermore, in this embodiment, the PEs 12 in the row direction are connected by two wiring 14, enabling input / output of score data from one PE 12 to another, as well as size determination and data movement corresponding to the size relationship of the score data, to be performed in a single process.

[0144] like Figure 16 As shown, in the first processing step, score data is exchanged between adjacent PE12A and PE12B. Specifically, the score data held in register 22 of PE12B is input to the arithmetic circuit 20 of PE12A via selector 24, and the score data held in register 22 of PE12A is input to the arithmetic circuit 20 of PE12A. The arithmetic circuit 20 of PE12A determines the size of the two input score data. Furthermore, the score data with the smaller value is held in the backoff register 26 of PE12A, and the score data with the larger value is held in the backoff register 26 of PE12B.

[0145] Similarly, the arithmetic circuit 20 of PE12C performs a size determination of the score data held in PE12C and the score data held in PE12D. The score data with the smaller value is held in the backoff register 26 of PE12C, and the score data with the larger value is held in the backoff register 26 of PE12D.

[0146] In the second processing, score data is exchanged between adjacent PE12 points in a different direction than in the first processing. Figure 16 In the example, the arithmetic circuit 20 of PE12B determines the size of the score data held in PE12B and the score data held in PE12C. The score data with the smaller value is held in the backoff register 26 of PE12B, and the score data with the larger value is held in the backoff register 26 of PE12C. Additionally, score data exchange is also performed between PE12A and the adjacent PE12 on the left. Furthermore, score data exchange is also performed between PE12D and the adjacent PE12 on the right.

[0147] Then, by repeatedly performing the first and second processing steps, the score data held in the computing device 10 is sorted.

[0148] Thus, in this embodiment, when performing sorting processing of score data held in multiple PEs 12, the arithmetic unit 10 determines the size of the score data that a PE 12 moves between with other adjacent PEs via the selector 24, and performs an exchange process based on the size determination result, moving the score data to the other PE 12. Then, the exchange process is repeatedly performed with different combinations of adjacent PEs 12. The arithmetic circuit 20 for determining the size of the score data can also be configured in the same way as the second time, using PEs 12B and PEs 12D, with the arithmetic circuit 20 for determining the size of the score data being removed at intervals.

[0149] Next, refer to Figure 17 , 18 This indicates cases where the number of sorted score data points is less than the number of PE12 values ​​in a single row. Figure 17 , 18 In the example, there are 8 PE12 values ​​in row 1, and we sort these 8 scores. That is, each PE12 in the first row retains one score. In this case, sorting can be done in a single process. Furthermore, Figure 17 This is an overall diagram of PE12, which constitutes the arithmetic unit 10. Figure 18 Indicates by Figure 17 Data movement within the 8 PE12s within the area enclosed by the dashed line.

[0150] like Figure 17 As shown, in the first row's PE12, the score data is compared between two adjacent PE12 values. Based on the result of this comparison, the score data is then swapped to the second row's PE12. (Refer to...) Figure 18 In PE12A and PE12B, the size of the two score data is determined. Based on the result of the size determination, the score data with the smaller value is moved from PE12A to PE12E, which is the second row adjacent in the column direction. The score data with the larger value is moved from PE12A to PE12F, which is the second row adjacent in the column direction of PE12B, via selector 24 of PE12B.

[0151] Similarly, the size of the two score data is determined in PE12C and PE12D. Based on the result of the size determination, the score data with the smaller value is moved from PE12C to PE12G, which is the second row adjacent in the column direction. The score data moved to PE12G is then moved to PE12F via selector 24. On the other hand, the score data with the larger value is moved from PE12C to PE12H, which is the second row adjacent in the column direction of PE12D, via selector 24 of PE12D.

[0152] PE12F determines the size of the two input score data. Based on the size determination result, PE12F moves the score data with the smaller value to PE12, which is the third row adjacent to PE12 in the column direction of PE12F, and moves the score data with the larger value to PE12, which is the third row adjacent to PE12 in the column direction of PE12G, via selector 24 of PE12G.

[0153] The score data moved to PE12E and PE12H are similarly compared with the score data of other adjacent PE12 in the row direction, and then moved to the PE12 in the third adjacent row in the column direction. Furthermore, the same swapping process as for the first and second rows is performed below the third row. Then, the score data is output from the final matrix in ascending or descending order. The output destination of the score data is, for example, external memory 30.

[0154] Here, refer to Figure 17 , 18 Explanation and reference Figure 16 The difference between the methods of multiple processing described above lies in that... Figure 16 During the process of exchanging score data between two adjacent PE12s, the score data is temporarily held in the backoff register 26, but... Figure 17 , 18 In the example, the score data that has undergone swapping is not kept in backoff register 26. That is, in Figure 17 , 18 In the example, instead of keeping the score data in the backoff register 26 each time a swap is performed, the process is repeated so that the score data is moved to the next row PE12 and swapped between the two adjacent PE12s in the next row.

[0155] Thus, in Figure 17 , 18 In the example, since the score data is not kept in backoff register 26 or register 22 during the sorting process, the sorting is completed in one process.

[0156] Next, refer to Figure 19 The data movement will be explained when sorting multiple rows of score data in the processing unit 10. That is, this example is the case where the number of score data to be sorted is greater than the number of PE12 rows.

[0157] exist Figure 19 In the example, the computing device 10 has 4 rows and 4 columns, totaling 16 PE12A~12P. Furthermore, each of these 16 PE12 stores score data. That is, Figure 19 This example illustrates how to sort 16 score data points using a 4x4 PE12 array.

[0158] In the first (odd-numbered) processing, the scores of two adjacent PE12s are swapped. That is, the first row swaps the scores of PE12A and PE12B, and swaps the scores of PE12C and PE12D. The second to fourth rows are processed in the same way.

[0159] In the second (even-numbered) processing, score data is exchanged between PE12B and PE12C in the same row, but score data is exchanged between PE12 at the ends of each row and other PE12 adjacent in the column direction. Figure 19 In the example, score data is swapped between PE12D and PE12H, between PE12E and PE12I, and between PE12L and PE12P. Then, the even-numbered and odd-numbered swaps are repeated until the sorting is complete.

[0160] In sorting the score data across multiple rows in the processing unit 10, the last PE12 of each row is considered virtually adjacent to the last PE12 of the next row in the row direction, and the first PE12 of each subsequent row is considered virtually adjacent to the first PE12 of the next row in the row direction. That is, the multiple rows of PE12 are virtually treated as a single row for sorting the score data. Figure 19 In the example, rows PE12A~12D, 12H, 12G, 12F, 12E, 12I~12L, 12P, 12D, 12N, and 12M are considered as one row. Therefore, even if the score data consists of multiple rows, sorting is still possible.

[0161] In addition, such as Figure 19 As illustrated, the PE12 at the end in the row direction is connected to the adjacent PE12 in the column direction via two wirings 14.

[0162] Additionally, in cases where there are more score data points than PE12, such as 64 score data points, the 16 PE12s, which are virtually considered a row, are each assigned four score data points, as described above. The four score data points assigned to each PE12 are distinguished by assigning the same identification number, such as "1", "2", "3", and "4". Then, Figure 19 The odd-numbered swap process shown is performed four times using the same identification number from the four score data points held in PE12, after which... Figure 19 The even-numbered exchange process shown is performed four times based on the score data with the same identification number among the four score data held in PE12.

[0163] Here, the ends of PE12, namely PE12A and PE12M, which are considered as a row, require the same exchange of score data within PE12 in even-numbered processing steps. In the example of 64 score data, in PE12M, the score data of identification number "1" and identification number "2" within the same PE12M are exchanged; in PE12A, the score data of identification number "2" and identification number "3" within the same PE12A are exchanged; and in PE12M, the score data of identification number "3" and identification number "4" within the same PE12M are exchanged. Thus, sorting is possible even when the number of score data is greater than the number of PE12.

[0164] Additionally, during exchange processing between adjacent PE12, the move destination data representing the move destination of the score data based on the score data exchange processing can be maintained, and other data can be moved in the same order as the score data based on this move destination data. Furthermore, the aforementioned other data is associated with the score data.

[0165] The moving destination data represents the movement of score data based on the results of the exchange processing corresponding to the magnitude of the score data. The moving destination data is maintained at the location where score data exchange processing takes place and the number of times score data exchange processing is performed. However, depending on the score data, sometimes no exchange occurs as the number of exchange processes progresses; therefore, in such cases, the exchange processing can be terminated midway.

[0166] In addition, as described above, if the PE12 of the computing device 10 is not a two-dimensional but a three-dimensional or four-dimensional multidimensional arrangement, it can also be arranged adjacent to the PE12 that is similarly considered to be located at the end of the three-dimensional or four-dimensional space in the row direction, so as to sort it with fewer processing times.

[0167] (Sorting based on index order) When sorting multiple data, in addition to determining the order of ascending or descending based on the size relationship of the score data representing the size, as mentioned above, sometimes the data is also sorted in a predetermined order.

[0168] Specifically, when the index data representing the order of the data is associated with each piece of data, the data held in each PE12 is sorted based on the arrangement order shown by the index data. Furthermore, the data associated with the index data will be referred to as input data below to distinguish it from the index data. Additionally, the index data represents the arrangement order of the data, and is therefore set as consecutive numbers such as "0", "1", "2", etc. Therefore, there are no PE12s, etc., assigned the same index data.

[0169] Figure 20 This is a graph showing the input data before and after sorting, which is associated with the index data. Figure 20 In the example shown in (A), the input data "a" to "h" are input into each PE12 of the arithmetic device 10 in the order of input data "a" to "h", and each input data "a" to "h" is associated with any one of the index data "7" to "0". The result of sorting the multiple input data in this way according to the index data "0" to "7" is... Figure 20 (B).

[0170] Next, refer to Figure 21 Explain the data movement between PE12. Figure 21 The data movement between PE12 shown is basically relative to Figure 17 , 18 The exchange process shown includes the concept of index data. Additionally, the input data associated with the index data is stored in register 22 of each PE12.

[0171] Figure 21 (A) is the first or odd-numbered processing. Based on the arrangement order shown by the index data, PE12 performs index data exchange processing with other adjacent PE12, maintaining the mobile destination data representing the mobile destination of the index data between adjacent PE12.

[0172] For example, the arithmetic circuit 20 of PE12A determines the size of the index data of PE12A and PE12B. Based on the result of the size determination, the index data with the smaller value is moved from PE12A to PE12E in the adjacent second row in the column direction. The index data with the larger value is moved from PE12A to PE12F in the adjacent second row in the column direction of PE12B via the selector 24 of PE12B. At this time, the arithmetic circuit 20 of PE12A generates the move destination data and stores it in the backoff register 26. Similarly, in PE12C and 12D, the index data is also exchanged between two adjacent PE12s, and the move destination data is stored in the backoff register 26. Then, the processing after the second row is performed in the same way as the processing of the first row, performing multi-row processing.

[0173] Figure 21 (B) is the second or even-numbered processing step. PE12 moves the input data between adjacent PE12s based on the moving destination data of the index data. That is, in the even-numbered processing step, the size relationship between the two input data is not determined, but the input data is moved based on the moving destination data representing the moving destination of the index data.

[0174] For example, the arithmetic circuit 20 of PE12A reads the move destination data from the backoff register 26 of PE12A, and based on the read move destination data, moves the input data of PE12A and the input data of PE12B. That is, the input data of PE12A and the input data of PE12B are moved to PE12E or PE12F in the same way as the index data represented by the move destination data. The processing in other PE12s is also performed in the same way. Then, the processing of the second row and thereafter is performed in the same way as the processing of the first row, performing multi-row processing at once.

[0175] As a result, Figure 20 As shown, the input data associated with the index data is sorted in the order indicated by the index data. Alternatively, multiple new input data sets associated with the index data can be input to the processing unit 10. If the input order is the same as the previous one, the input data is sorted using the previously generated destination data. That is, in this case, no further processing is performed. Figure 21 The processing of (A) is carried out. Figure 21 The treatment of (B).

[0176] Thus, when the input data to PE12 is associated with index data indicating the order of the input data, PE12 determines the size of the index data to be moved between adjacent PE12s via selector 24. Based on the size determination result, the index data is moved to the other PE12, while maintaining the move destination data indicating the move destination of the index data. Then, PE12 moves the input data between adjacent PE12s based on the move destination data.

[0177] As described above, when the arithmetic unit 10 inputs input data associated with index data from the external memory 30 to the PE12, the PE12 moves the input data between adjacent PE12s based on the destination data.

[0178] (Data swapping based on selector settings) In predetermined processes such as transposing data in rows and columns, the actions of selector 24 can also be preset to move data from one PE12 to other PE12.

[0179] Furthermore, when the data movement distance between PE12 becomes longer, data movement can also be achieved by bursting multiple data transfers from one or more PE12 to one or more PE12.

[0180] (The sorting of relative addresses used to move to relative address positions) Alternatively, by sorting the relative addresses, the arithmetic unit 10 can read data from the external memory 30 to the relative address location.

[0181] Figure 22 This diagram illustrates the relative addresses and input data sorted by the arithmetic unit 10 during the movement to relative address positions. The numbers on the left indicate the processing order. For example, the number of PE12 in the row direction is set to 8. That is, in the first processing, it indicates that a relative address has been input to each PE12 arranged in the row direction. Specifically, if PE12A, PE12B, ..., PE12H are designated from the left end of the row direction, then a relative address "5" is input to PE12A, a relative address "1" is input to PE12B, a relative address "0" is input to PE12C, a relative address "7" is input to PE12D, a relative address "8" is input to PE12E, a relative address "0" is input to PE12F, a relative address "5" is input to PE12G, and a relative address "-" is not input to PE12H.

[0182] Thus, in PE12 in the row direction, the input is the same relative address as the input to other PE12, or no relative address is input, or although a relative address is input, its relative address is not within the range of the input data.

[0183] In addition, Figure 22 In the example, relative address "8" is the ninth relative address, and it is not processed at the same timing as "0"~"7", but is a relative address outside the input range. Therefore, in the second processing, relative address "8" is converted to "+". In addition, the "-" input to PE12G is also outside the input range and is converted to "+".

[0184] In the third processing step, the relative addresses are sorted in ascending order from left to right. Furthermore, "+" values ​​outside the input range are considered the largest and shifted to the right. Additionally, data movement information based on this sorting is stored as move destination data 1 in the backoff register 26 of PE12.

[0185] In the fourth processing step, if the relative address is the same as the value on the left, the relative address is converted to "-". In this processing step, "+" is also converted to "-". In addition, the conversion information from "+" to "-" is stored in the backoff register 26 as mobile destination data 2.

[0186] In the fifth processing step, relative addresses greater than "0" are moved to PE12, the column corresponding to the same value. That is, PE12A is the first column, corresponding to "0", PE12B is the second column, corresponding to "1", and similarly, PE12H is the eighth column, therefore corresponding to "7". Thus, relative address "0" is moved to PE12A, relative address "1" to PE12B, relative address "5" to PE12F, and relative address "7" to PE12G. Furthermore, the data movement information from the fifth processing step is stored as move destination data 3 in the backoff register 26 of PE12.

[0187] Thus, through the first to fifth processing steps, the relative addresses are sorted in ascending order relative to PE12A~PE12H.

[0188] In the sixth process, input data is read from external memory 30 and sequentially input from PE12A to PE12H, and stored in each PE12. That is, the input data is input from external memory 30 to PE12 in an ascending order of relative addresses. Then, the input data is associated with the relative addresses stored in PE12. Furthermore, in this embodiment, input data is read from external memory 30, but it is not limited to this; the input data may also be stored in PE12 in advance. That is, through the sixth process, the input data is associated with the relative addresses sorted in ascending order through the first to fifth processes.

[0189] In the seventh process, the reverse conversion is performed using the mobile destination data 3, so that the row direction order of the input data maintained in each PE12 is the same as the order of the relative addresses in the fifth process.

[0190] In the eighth process, the input data held in each PE12 is reverse-converted using the mobile destination data 2 to correspond to the relative address in the fourth process.

[0191] In the ninth process, the input data held in each PE12 is reverse-converted using the mobile destination data 1 to correspond to the relative address in the third process.

[0192] Thus, in the sixth to ninth processes, the input data held by PE12 is moved and transformed by reversing and converting the relative address shift. As a result, the input data held by PE12 in the sixth process is maintained at the original relative address position (the relative address position at the time point of the first process) of PE12.

[0193] Thus, in this embodiment, when a relative address is associated with PE12, PE12 determines the size of the relative address to be moved between adjacent PE12 via selector 24, moves the relative address to the other PE12 based on the size determination result, and maintains the move destination data representing the move destination of the relative address. Then, after establishing a correspondence between the input data and the moved relative address, PE12 moves the input data between adjacent PE12 based on the reverse order of the movement shown by the move destination data.

[0194] As described above, when the arithmetic unit 10 inputs input data associated with a relative address from the external memory 30 to the PE12, the PE12 moves the input data between adjacent PE12s based on the move destination data.

[0195] also, Figure 22 The example involves processing relative addresses up to "0" to "7". Therefore, for relative addresses after "8", the arithmetic unit 10 performs the same processing while limiting the range as "8" to "15" and "16" to "23". Furthermore, if the values ​​and order of the relative addresses input to the arithmetic unit 10 are known in advance, the destination data can be pre-prepared before processing. Figure 22 In the case shown, only the inverse conversion is performed.

[0196] (Sorting the indexed data as two-dimensional data) In this embodiment, the index data of each PE12 constituting the computing device 10 is used as position information, and based on the one-dimensional index data, two-dimensional index data is specified for each PE12.

[0197] For example, let the columns be x, numbered 0, 1, 2, ... from left to right, and the rows be y, assigning two-dimensional index data to each PE12 in a consecutive order of 0, 1, 2, ... . Furthermore, when the number of columns in the two-dimensional arrangement of PE12 is set to 8, and the one-dimensional index data is a, the two-dimensional index data (x, y) becomes (the remainder of a divided by 8, and the quotient of a divided by 8). That is, when the one-dimensional index data is 21, the two-dimensional index data (x, y) is (5, 2). In this way, the multiple PE12s specifying the two-dimensional index data are virtually divided into multiple groups, and the data is sorted among the multiple PE12s according to each group.

[0198] The following is for reference Figure 23 The sorting process for data based on each group is explained. Furthermore, in Figure 23In the example, the data is moved between the four PE12s after grouping in one process for sorting. Therefore, the wiring 14 between PE12s can be reused as needed, or the operation circuits 20 of PE12 can be set to multiple.

[0199] First, in the first (odd-numbered) processing, multiple PE12s are virtually divided into a first group 40A consisting of three or more adjacent PE12s. For example, in Figure 23 In the example, four PE12s in two rows and two columns are set as a first group 40A.

[0200] Then, the size of multiple index data is determined according to each first group 40A, and a first sorting process is performed based on the determination result, shifting the index data and the input data associated with the index data. The sorting of data among the multiple PE12 constituting the group is the same as the sorting based on the exchange process described above. Additionally, in Figure 23 In the example, during row-wise swapping, data with smaller column positions in the two-dimensional index data is moved to PE12 on the left, while during column-wise swapping, data with smaller row positions in the two-dimensional index data is moved to PE12 on the top.

[0201] As a second (even-numbered) process following the first sorting process, three or more PE12s are virtually divided into multiple second groups 40B, different from the first group 40A. Figure 23 In the example, the PE12s located at the corners of the matrix do not form a group. The PE12s in the row direction at the ends are formed by two adjacent PE12s on the left and right, forming a second group 40B. The PE12s in the column direction at the ends are formed by two adjacent PE12s on the top and bottom, forming a second group 40B. The PE12s inside the matrix are formed by four PE12s in two rows and two columns, forming a second group 40B.

[0202] Then, in the even-numbered processing iterations, the size of multiple index data is determined for each second group 40B, and a second sorting process is performed based on the determination result, shifting the index data and the input data associated with the index data. The processing unit 10 repeatedly performs this first and second sorting process a necessary number of times. Furthermore, in Figure 23 In the example, the sorting is accomplished by repeating the square root of the data 8 times.

[0203] This method of sorting data among multiple PE12 groups can be applied not only to two-dimensional arrangements of PE12 in the matrix direction (xy direction) but also to multi-dimensional arrangements of PE12. In this method, even-numbered processing is performed in groups of PE12 arranged as elements in three or more dimensions (wz direction). Thus, sorting is completed with fewer processing steps.

[0204] Alternatively, if it is desired to sort each of the multiple data input to the arithmetic unit 10 in the same order, the destination data of the index data can be generated as described above and the PE12 can be kept, and the data can be moved based on the destination data.

[0205] (Sorting the index data into two-dimensional data when the number of data items is greater than the number of PE items) Next, refer to Figure 24 , 25 This describes the sorting process when the number of input data points is greater than the number of PE12 values, and the index data is set to two-dimensional sorting. Furthermore, Figure 24 This indicates the odd-numbered processing iterations. Figure 25 This indicates the even-numbered processing step, where x represents the column number and y represents the row number.

[0206] exist Figure 24 , 25 In the example, the arithmetic unit 10 has 16 PEs 12, but the number of input data input to the arithmetic unit 10 is 64, which is four times the number of input data. When the number of sorted input data is greater than the number of PEs 12, each PE 12 appends a number to each set of input data and maintains that number. Figure 24 , 25 In the example, each PE12 holds four input data and adds any one of the identification numbers from 1 to 4 to each input data.

[0207] Furthermore, multiple PE groups 42 are virtually configured as sets of multiple PE12 that retain data with the same appended number. Figure 24 In the example, PE group 42A corresponds to data number 1, PE group 42B corresponds to data number 2, PE group 42C corresponds to data number 3, and PE group 42D corresponds to data number 4.

[0208] Furthermore, multiple PE groups 42 are configured such that, relative to the reference PE group 42, at least one of the row direction and column direction of the PE12 constituting the PE group 42 is reversed. Figure 24 In the example, PE group 42A is the reference, PE group 42B is reversed in column direction relative to the reference, PE group 42C is reversed in row direction relative to the reference, and PE group 42D is reversed in both row and column directions relative to the reference. Therefore, PE groups 42B, 42C, and 42D are configured as PE12 folded upwards, downwards, left, right, or both directions relative to PE group 42A. To configure in reverse order, a selector setting command is performed during data input to reverse the data. Conversely, during data output, a selector setting command is performed to make the reversed data return to forward order. Alternatively, two wirings 14 can be provided between PE12 to allow data movement simultaneously in both forward and reverse directions.

[0209] Then, the arithmetic unit 10 performs a first sorting process according to each first group 40A divided within the PE group 42, and then performs a second sorting process according to each second group 40B that includes groups divided across multiple PE groups 42, and repeats the first sorting process and the second sorting process.

[0210] Figure 24 This corresponds to the odd-numbered processing step in the first sorting process. For example... Figure 24 As shown, each first group 40A exists within each PE group 42. The first sorting process determines the size of multiple index data according to each first group 40A, and performs an exchange process that moves the index data and the input data associated with the index data between PE12 based on the determination result.

[0211] Figure 25 This corresponds to the even-numbered iteration of the second sorting process. For example... Figure 25 As shown, a portion of the second group 40B spans multiple PE groups 42. The second sorting process determines the size of multiple index data points for each second group 40B, and performs an exchange process that moves the index data and associated input data between PEs 12 based on the determination result. Furthermore, in Figure 25 In the diagram, the dashed line representing the second group 40B, which is beyond PE groups 42B, 42C, and 42D, represents the second group 40B assuming the existence of a PE group 42 adjacent to PE groups 42B, 42C, and 42D.

[0212] Here, the xy coordinates of the PE12 located at the end of each PE group 42 are the same as those of the PE12 in the adjacent PE groups 42. That is, the input data of the second group 40B, which spans the PE groups 42, are input data with different numbers maintained by the same existing PE12. Moreover, the PE12 adjacent to the other PE groups 42 in each PE group 42 is the outer edge PE12X located at the end of the existing PE12. That is, the outer edge PE12X sorts the multiple input data it holds into the second group 40B in the second sorting process.

[0213] Therefore, the outer PE12X needs to sort the four input data within a single PE12. Thus, as... Figure 26 As shown, a first preparatory PE50 for sorting multiple input data held by itself in the second sorting process is provided on the outer side adjacent to the outer edge PE12X.

[0214] exist Figure 26In the diagram, the PE12 adjacent to the outer edge PE12X surrounded by dashed lines is the first backup PE50. The first backup PE50 is not virtual, but is actually installed on the PE12 of the computing device 10. The first backup PE50 is connected to the adjacent first backup PE50 and the outer edge PE12X through wiring 14.

[0215] In the second sorting process, the outer PE12X moves the input data it holds to the backoff register 26 of the first reserve PE50, and sorts the input data as the second group 40B between the outer PE12X and the first reserve PE50. Therefore, the first reserve PE50 has a selector 24, an arithmetic circuit 20, and a backoff register 26, but it may also not have a register 22.

[0216] In the group-based sorting where the amount of input data described above is greater than the number of PE12 elements, even when PE12 is set to multidimensional, the same process is performed: on the odd-numbered iterations, the even-numbered sequence numbers of each dimension and their next feature numbers are swapped a total of two power-of-dimensional data points. Then, on the even-numbered iterations, the odd-numbered feature numbers of each dimension and their next feature numbers are swapped a total of two power-of-dimensional data points.

[0217] (Using convolution operations with pre-defined PE) See reference Figure 27 , 28 This illustrates an example of convolution operation using the second pre-PE52. The second pre-PE52 does not have the arithmetic circuit 20, but has a selector 24 and a backoff register 26 or register 22. Then, PE12 and the second pre-PE52 perform data shifting via the selector 24.

[0218] Figure 27 This is a schematic diagram illustrating the relationship between the data used in the convolution operation of this embodiment and PE12. Figure 27 In this example, the computing device 10 has 16 (four rows and four columns) PE12s, and each PE12 holds multiple (nine) data. That is, in Figure 27 In this context, multiple PE12s represented by the same xy coordinates are the same PE12. Figure 27 This means that the nine distinct data points of each PE12 are arranged in a two-dimensional pattern. Furthermore, the group of data points where each (x, y) = (0, 0) ~ (3, 3) is considered a data set. For example, Figure 27 The top left data groups are “0”~“3”, “10”~“13”, “20”~“23”, and “30”~“33”. Moreover, the central data groups “44”~“47”, “54”~“57”, “64”~“67”, and “74”~“77” are the data of interest that become the objects of convolution operations.

[0219] The data around the central data group, indicated by shaded lines, virtually represents the data required for convolution operations on the data of interest (hereinafter referred to as "necessary data"). Furthermore, the necessary data is represented by coordinates x=-2, -1, 4, 5, y=-2, -1, 4, 5. Within this necessary data, the data within the outer dashed lines is the necessary data used in 5×5 convolution operations, and the data within the inner dashed lines is the necessary data used in 3×3 convolution operations. For example... Figure 27 As shown, the necessary data is the data that is maintained as a surrounding data group of the data of interest.

[0220] Therefore, in this embodiment, as Figure 28 As shown, the second preparation PE52 holds the necessary data so that it can be used as part of the data of interest. That is, by Figure 28 The coordinates x=-2, -1, 4, 5 and y=-2, -1, 4, 5 represent the PE, which is the second preparatory PE52. This second preparatory PE52 is an actual existing PE. Located from... Figure 28 The data within the dashed line at the rear end of the arrow pointing from PE12 toward the second preparatory PE52 is the necessary data held in the second preparatory PE52. Therefore, the second preparatory PE52 obtains the necessary data from the corresponding other PE12 via selector 24 and holds it in backoff register 26.

[0221] Then, when performing convolution operations on the data of interest, the second pre-processor PE52 is directed to PE12 via selector 24. Figure 28 The necessary data is output from the central PE12. This simplifies the movement of the necessary data to the PE12, enabling faster processing.

[0222] In addition, Figure 28 In the example, a second backup PE52 is configured outside each PE12, but it is not limited to this. For example, the arithmetic unit 10 may also include a second backup PE52 with a large storage capacity backoff register 26, in which necessary data is held. In addition, the second backup PE52 and PE12 may also be used to multiplex wiring 14 as needed.

[0223] (Sorting in SIMD processing) In this embodiment, among the multiple PE12s that hold input data divided into multiple data by each specified number of bits, processing is performed according to each data divided by the specified number of bits.

[0224] As an example, in this embodiment, the sorting process of the data among multiple PE12s, which is maintained by dividing the input data into multiple data sets at predetermined bit units, will be described. That is, the sorting process in this embodiment sorts the data in predetermined bit units. Furthermore, in order to simultaneously perform data size determination and movement on multiple sets of data within a single PE12, the sorting process in this embodiment performs parallel processing based on SIMD (Single Instruction Multiple Data) processing.

[0225] In this embodiment, as an example, 128 bits of input data are input to PE12. PE12 divides the input data into 32-bit segments and stores them in backoff register 26. That is, PE12 stores four 32-bit data segments in backoff register 26. Figure 29 In the example, a PE12 is shown to hold four data points. The PE12A on the left is the PE12 in the first row and first column. The PE12 are arranged in a two-dimensional shape in both the row and column directions.

[0226] Furthermore, each data stored in each PE12 is assigned a hold position in the backoff register 26 (hereinafter referred to as "data bit position") to distinguish it from other data. That is, "1", "2", ..., "0a", "0b" recorded in each PE12 represent data bit positions. Data bit positions are consecutively numbered across multiple PE12s.

[0227] In addition, Figure 29 Although the illustrations of register 22, arithmetic circuit 20, selector 24 and backoff register 26 are omitted, PE12 has them in the same manner as other embodiments.

[0228] Then, when the arithmetic unit 10 performs sorting processing on multiple data, firstly, the size of the data grouped within a PE12 is determined, and a first exchange process is performed to move the data within the PE12 based on the size determination result.

[0229] Figure 29 The odd-numbered sequence corresponds to the first exchange process. Within a PE12, the arithmetic circuit 20 determines the size relationship between the data at the even-numbered data bit position and the data at the odd-numbered data bit position (with 1 added to the even-numbered data bit position). That is, data bit positions "0" and "1" in PE12A are grouped together, and "2" and "3" are grouped together. Similarly, two groups are generated in PE12B and PE12C, and the size relationship of the data is determined within these groups.

[0230] Then, the data is moved within PE12 according to the size determination result. For example, if the data at bit position "0" is larger than the data at bit position "1", the data at bit position "0" is moved to bit position "1", and the data at bit position "1" is moved to bit position "0". Thus, the bit position of the data changes according to the size relationship of the data.

[0231] Additionally, the data size, in units of bits, is determined by outputting the data held in the backoff register 26 to the arithmetic circuit 20 via selector 24. Then, the data is output from the arithmetic circuit 20 to the backoff register 26 via the backoff register 26, and held at the data bit position corresponding to the size relationship.

[0232] Thus, in the first switching process, the size relationship of the data is determined only within one PE12, and the data movement is performed within the PE12. This data size determination and movement is performed simultaneously on multiple sets of data within one PE12. Therefore, this data size determination and movement is carried out within the PE12 through SIMD processing.

[0233] then, Figure 29 The even-numbered steps correspond to the second exchange process, generating a group different from the odd-numbered steps, determining the size relationship of the data, and moving the data within PE12. In the second exchange process of this embodiment, the size of the data that constitutes another group within a PE12 is determined, and the size of the data that moves between adjacent PE12s via selector 24 is also determined, and the data is moved according to the size determination result. Furthermore, other groups are combinations of multiple data that are different from the groups generated in the first exchange process.

[0234] In the second switching process, firstly, the data at the odd-numbered bit positions within a PE12 and the data at the even-numbered bit positions (after adding 1 to the odd-numbered bit position) are grouped together (another group). See reference... Figure 29 In the second switching process, data bit positions "1" and "2" of PE12A are grouped together, data bit positions "5" and "6" of PE12B are grouped together, and data bit positions "9" and "0a" of PE12C are grouped together. Thus, in the second switching process, other groups different from those in the first switching process are generated.

[0235] Furthermore, in the second switching process, data groups are also generated between adjacent PE12s. Therefore, data is moved between adjacent PE12s via selector 24. (See reference...) Figure 29Data bit position "3" of PE12A and data bit position "4" of PE12B are grouped together, and data bit positions "7" and "8" of PE12B are grouped together. Thus, in the second switching process, data is also grouped between adjacent PE12s. Furthermore, the data grouped between adjacent PE12s may be, for example, the data at the maximum value bit position of one PE12 and the data at the minimum value bit position of the other PE12.

[0236] In the second exchange process, the size relationship of the data in these groups is determined, and the data is moved according to the size determination result.

[0237] Then, the sorting process of this embodiment repeatedly performs the first swap process and the second swap process. Furthermore, in the sorting process of this embodiment, as referred to... Figure 19 As explained, PE12, which consists of multiple rows, is virtually treated as a single row for sorting the data.

[0238] Thus, in this embodiment, when data sorting is performed between multiple PE12s that hold input data divided into multiple data units of a predetermined number of bits, the size of multiple data units grouped within a PE12 is determined, and a first exchange process is performed to move the data within the PE12 based on the size determination result. Then, as a second exchange process, the size of multiple data units grouped within a PE12 is determined, and the size of data moved between adjacent PE12s via selector 24 is determined, and the data is moved based on the size determination result. The arithmetic unit 10 repeatedly performs this first exchange process and the second exchange process.

[0239] Figure 30 This is a schematic diagram illustrating the two-dimensional sorting process accompanying SIMD processing. Figure 30 In the example, the 128-bit input data is divided into eight 16-bit data segments, each stored in a 2x4 grid using PE12. Furthermore, the segmented data is as follows: Figure 30 As shown, data bit positions are specified by consecutive numbers in a way that allows for matrix processing across multiple PE12s.

[0240] exist Figure 30 In the sorting process of the example, in the odd-numbered first swap, the data is moved only within a single PE12 according to the size relationship of the data in every two rows and two columns. For example, in PE12A, data bit positions "0", "1", "10", and "11" are grouped together, and data bit positions "2", "3", "12", and "13" are grouped together. Then, the size of the four data in each group generated within PE12 is determined, and the data is moved according to the size determination result.

[0241] In the even-numbered iteration of the second exchange process, a group different from the one in the odd-numbered iterations is generated. The size relationship of the data is determined, and data movement is performed within PE12. Figure 30 In the even-numbered times, with Figure 29 Similarly, on the even-numbered times, groups of data are also generated between adjacent PE12. Therefore, data is moved between adjacent PE12 via selector 24.

[0242] exist Figure 30 In the example, for instance, the data at bit positions "1" and "2" in PE12A are grouped together. The size of these two data points is determined, and the data is moved according to the size determination result.

[0243] Additionally, data at bit position "10" of PE12A and data at bit position "20" of the adjacent PE12D are grouped together. Furthermore, data at bits "11" and "12" of PE12A and data at bits "21" and "22" of PE12D are grouped together. Finally, data at bit position "3" of PE12A and data at bit position "4" of PE12B are grouped together.

[0244] Furthermore, the data at bit position "13" of PE12A, the data at bit position "14" of PE12B, the data at bit position "23" of PE12D, and the data at bit position "24" of PE12E are grouped together. Additionally, PE12A and PE12E are not adjacent to each other, but PE12A and PE12E are adjacent to PE12B and PE12C respectively. In the second switching process, data groups are generated among these multiple PE12s.

[0245] Then, in the second switching process, the size relationship of multiple data sets grouped within and between multiple PE12s is determined, and the data is moved according to the size determination result. Furthermore, in Figure 30 The example also repeatedly performs the first swap and the second swap.

[0246] Furthermore, in this embodiment, the number of rows and columns of data within a PE12 can be arbitrarily determined based on the number of bits in the input data and the number of data segments, thereby constructing and determining various corresponding circuits.

[0247] Furthermore, the method of dividing data into multiple data points according to each specified number of bits is not limited to the sorting process described above. It can also be implemented as shown in other embodiments, by moving the multiple data points divided by each number of bits in a tilted direction, performing operations via selector 24, convolution operations, etc. Alternatively, the multiple data points divided by each number of bits can be restored to a single data point and moved and processed collectively.

[0248] The present disclosure has been described above using the embodiments described above, but the technical scope of the present disclosure is not limited to the scope described in the embodiments. Various changes or modifications can be made to the embodiments without departing from the spirit of the disclosure, and the manner in which such changes or modifications are made is also included in the technical scope of the present disclosure.

[0249] Next, the features of the invention will be shown as follows.

[0250] (Method 1) A computing device (10) includes multiple processors (12). The processor has a selector (24) that outputs input data in a set direction. The processor performs a single processing of the selector's setting command and the data input / output command, thereby moving the data via the selector between non-adjacent processors or within the processor itself.

[0251] (Method 2) The computing device according to method 1 The processor has registers (22, 26) connected to the selector and holding the data.

[0252] (Method 3) The computing device according to method 1 or 2 The processor has multiple selectors.

[0253] (Method 4) The arithmetic device according to any one of methods 1 to 3, The processor has an arithmetic circuit (20) connected to the selector and performing arithmetic processing on the data. Data movement between the processor and computational processing based on the arithmetic circuitry are performed through a single processing of the selector's setting commands and the data input / output commands.

[0254] (Method 5) The computing device according to method 4 The computational circuitry for performing specific processing is located in a portion of the processor. In the case of the specific processing, data is moved to the portion of the processor via the selector.

[0255] (Method 6) The arithmetic device according to any one of methods 1 to 5, The wiring used in data movement between the processors is provided at specified intervals for each of the processors.

[0256] (Method 7) The arithmetic device according to any one of methods 1 to 6, In the case of sorting score data that is maintained at the size of multiple processors, The processor determines the size of the score data to be moved between adjacent processors via the selector, and performs an exchange process to move the score data to the other processor based on the size determination result. The exchange process is repeated using different combinations of two adjacent processors.

[0257] (Method 8) The computing device according to method 1 The data input to the processor is associated with either score data representing the size of the data or index data representing the sorting order. The processor determines the size of the score data or index data to be moved between adjacent processors via the selector, moves the score data or index data to another processor based on the size determination result, and maintains the move destination data representing the move destination of the score data or index data. The processor moves the data between adjacent processors based on the mobile destination data.

[0258] (Method 9) The computing device according to method 1 This indicates that the relative address of the data's destination is associated with the processor. The processor determines the size of the relative address to be moved between adjacent processors via the selector, and based on the size determination, causes another processor to move the relative address, while maintaining the move destination data representing the move destination of the relative address. After establishing a correspondence between the data and the relative address after the move, the processor moves the data between itself and other adjacent processors based on the reverse order of the move represented by the destination data.

[0259] (Method 10) The computing device according to method 8 or 9 When the processor receives data associated with the score data, the index data, or the relative address from external memory (30), The processor moves the data between adjacent processors based on the mobile destination data.

[0260] (Method 11) The computing device according to method 8 The processors are virtually divided into a first group consisting of three or more adjacent processors. After determining the size of multiple index data sets for each of the first groups, and performing a first sorting process based on the determination results to move the index data and the data associated with the index data, the following steps are taken. The three or more adjacent processors are virtually divided into a second group, which is different from the first group. For each of the second groups, the size of multiple index data is determined, and based on the determination result, a second sorting process is performed to move the index data and the data associated with the index data. Repeat the first sorting process and the second sorting process.

[0261] (Method 12) The computing device according to method 11 When the amount of data to be sorted is greater than the number of processors, one processor appends a number to each plurality of data items and maintains it. Multiple processor groups are virtually configured, each being a collection of processors that maintain data items appended with the same number. The plurality of said processor groups are configured such that the processors constituting the processor groups are in reverse order, either in the row direction or the column direction, relative to the reference processor group. After performing the first sorting process according to each of the first groups separated within the processor groups, the second sorting process is performed according to each of the second groups comprising groups divided across multiple processor groups. Repeat the first sorting process and the second sorting process.

[0262] (Method 13) The computing device according to method 12 A first pre-processor is provided adjacent to the outer edge processor located at the end of the processor in the two-dimensionally configured processor. The first pre-processor is a processor for sorting the plurality of data held by the outer edge processor in the second sorting process.

[0263] (Method 14) The arithmetic device according to any one of methods 1 to 13, Processing is performed on each of the data segments divided into the specified number of bits, between the multiple processors that hold the input data and the processors that divide the input data into multiple data segments according to the specified number of bits.

[0264] (Method 15) The arithmetic device according to any one of methods 1 to 14, The computing device includes a preprocessor (52), which does not have computing circuitry but instead has the selector and a register for holding the data. The processor and the preprocessor move data via the selector.

[0265] (Method 16) The arithmetic device according to any one of methods 1 to 15, The actions required by the computing device to perform the functions are preset for each processor or set by data, and different actions are performed by each processor according to the requirements of the function.

[0266] (Method 17) A data movement method is a data movement method of a computing device including multiple processors. The processor includes a selector that outputs input data in a set direction. The processor performs a single processing of the selector's setting command and the data input / output command, thereby moving the data via the selector between non-adjacent processors or within the processor itself.

Claims

1. A computing device (10) comprising a plurality of processors (12), characterized in that, The processor has a selector (24) that outputs input data in a set direction. The processor performs a single processing of the selector's setting command and the data input / output command, thereby moving the data via the selector between non-adjacent processors or within the processor itself.

2. The computing device according to claim 1, characterized in that, The processor has registers (22, 26) connected to the selector and holding the data.

3. The computing device according to claim 1 or 2, characterized in that, The processor has multiple selectors.

4. The computing device according to claim 1 or 2, characterized in that, The processor has an arithmetic circuit (20) connected to the selector and performing arithmetic processing on the data. Data movement between the processor and computational processing based on the arithmetic circuitry are performed through a single processing of the selector's setting commands and the data input / output commands.

5. The computing device according to claim 4, characterized in that, The computational circuitry for performing specific processing is located in a portion of the processor. In the case of the specific processing, data is moved to the portion of the processor via the selector.

6. The computing device according to claim 1 or 2, characterized in that, For each of the processors at specified intervals, wiring is provided for data movement between the processors.

7. The computing device according to claim 1 or 2, characterized in that, In the case of sorting score data that is maintained at the size of multiple processors, The processor determines the size of the score data to be moved between adjacent processors via the selector, and performs an exchange process to move the score data to the other processor based on the size determination result. The exchange process is repeated using different combinations of two adjacent processors.

8. The computing device according to claim 1, characterized in that, The data input to the processor is associated with either score data representing the size of the data or index data representing the sorting order. The processor determines the size of the score data or index data to be moved between adjacent processors via the selector, moves the score data or index data to another processor based on the size determination result, and maintains the move destination data representing the move destination of the score data or index data. The processor moves the data between adjacent processors based on the mobile destination data.

9. The computing device according to claim 1, characterized in that, This indicates that the relative address of the data's destination is associated with the processor. The processor determines the size of the relative address to be moved between adjacent processors via the selector, and based on the size determination, causes another processor to move the relative address, while maintaining the move destination data representing the move destination of the relative address. After establishing a correspondence between the data and the relative address after the move, the processor moves the data between itself and other adjacent processors based on the reverse order of the move represented by the destination data.

10. The computing device according to claim 8 or 9, characterized in that, When the processor receives data associated with the score data, the index data, or the relative address from external memory (30), The processor moves the data between adjacent processors based on the mobile destination data.

11. The computing device according to claim 8, characterized in that, The processors are virtually divided into a first group consisting of three or more adjacent processors. After determining the size of multiple index data sets for each of the first groups, and performing a first sorting process based on the determination results to move the index data and the data associated with the index data, the process is repeated. The three or more adjacent processors are virtually divided into a second group, which is different from the first group. For each of the second groups, the size of multiple index data is determined, and based on the determination result, a second sorting process is performed to move the index data and the data associated with the index data. Repeat the first sorting process and the second sorting process.

12. The computing device according to claim 11, characterized in that, When the amount of data to be sorted is greater than the number of processors, one processor appends a number to each plurality of data items and maintains it. Multiple processor groups are virtually configured, each being a collection of multiple processors that maintain data items appended with the same number. The plurality of said processor groups are configured such that the processors constituting the processor groups are in reverse order, either in the row direction or the column direction, relative to the reference processor group. After performing the first sorting process according to each of the first groups divided within the processor groups, the second sorting process is performed according to each of the second groups, which includes groups divided across multiple processor groups. Repeat the first sorting process and the second sorting process.

13. The computing device according to claim 12, characterized in that, A first pre-processor is provided adjacent to the outer edge processor located at the end of the processor in the two-dimensionally configured processor. The first pre-processor is a processor for sorting the plurality of data held by the outer edge processor in the second sorting process.

14. The computing device according to claim 1 or 2, characterized in that, Processing is performed on each of the data segments divided into the specified number of bits, between the multiple processors that hold the input data and the processors that divide the input data into multiple data segments by each specified number of bits.

15. The computing device according to claim 1 or 2, characterized in that, The computing device includes a preprocessor (52), which does not have computing circuitry but instead has the selector and a register for holding the data. The processor and the preprocessor move data via the selector.

16. The computing device according to claim 1 or 2, characterized in that, The actions performed by the computing device to execute the required function are preset by each processor or set by data, and different actions are performed by each processor according to the requirements of the function.

17. A data movement method, comprising a computing device including multiple processors, characterized in that, The processor includes a selector that outputs input data in a set direction. The processor performs a single processing of the selector's setting command and the data input / output command, thereby moving the data via the selector between non-adjacent processors or within the processor itself.

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