Calculation method based on data flow diagram and related equipment

Abstract

The embodiment of the invention provides a calculation method based on a data flow graph (DFG) and a data flow microprocessor. The method comprises the steps that a first DFG is acquired, the first DFG comprises a plurality of operators and data transmitted among the plurality of operators, and the first DFG runs on the data flow microprocessor; the first DFG is optimized into a second DFG according to the connection relation of the operators in the first DFG and / or the data transmitted between the operators, and the second DFG runs on the data flow microprocessor; and executing the second DFG. The proposed techniques may improve the efficiency of a data stream microprocessor.

Description

Technical Field

[0001] The embodiments of this application relate to the field of data processing, and more specifically, to a method for computation based on a dataflow graph (DFG), and a related device for computation based on DFG. Background Technology

[0002] A data flow graph (DFG) is a graph that represents the data dependencies between multiple operations, which are software running in a dataflow microprocessor. An operator is a node representing a data transformation or computation, having one or more input ports and one or more output ports. Data flows from the input ports to the output ports, and the operator performs some transformation on the data as it flows.

[0003] To our knowledge, one of the main problems with dataflow microprocessors is the back-and-forth transfer of data between the microprocessor and RAM, which results in high latency and efficiency losses.

[0004] Therefore, improving the efficiency of dataflow microprocessors is a challenge. Summary of the Invention

[0005] Embodiments of this application provide a method for computation based on a data flow graph (DFG) and a data flow microprocessor. This technical solution can reduce the workload in the data flow microprocessor, thereby improving its efficiency.

[0006] According to a first aspect, embodiments of this application provide a method for computation based on DFG, wherein the method is applied to a dataflow microprocessor, and the method includes: A first DFG is obtained, wherein the first DFG includes multiple operators and data transmitted between the multiple operators, and the first DFG runs on the data stream microprocessor; Based on the connection relationships of the operators in the first DFG and / or the data transmitted between the operators, the first DFG is optimized into a second DFG, wherein the second DFG runs on the data stream microprocessor; Execute the second DFG.

[0007] According to the above method, based on the connection relationships of operators in the first DFG and / or the data transmitted between operators, the first DFG running in the dataflow microprocessor is optimized to obtain a second DFG, which is then run in the dataflow microprocessor. Since the second DFG is optimized relative to the first DFG, it can improve the execution efficiency of the dataflow microprocessor and reduce its latency.

[0008] In one possible design, optimizing the first DFG into a second DFG based on the connection relationships of the operators in the first DFG and / or the data transmitted between the operators includes: optimizing the first DFG into a second DFG by reducing the number of round trips between the operators in the first DFG and the random access memory (RAM).

[0009] According to the above method, compared with the first DFG, the second DFG reduces unnecessary round trips between the operators and RAM in the first DFG, thereby avoiding unnecessary interactions between the data stream microprocessor and RAM and improving the execution efficiency of the data stream microprocessor.

[0010] In one possible design, the first DFG includes a first operator, a second operator, a third operator, and a fourth operator, wherein the first operator outputs first data and sends the first data to the third operator, the third operator writes the first data into the RAM, the fourth operator retrieves the first data from the RAM and sends the first data to the second operator, and the second DFG includes the first operator and the second operator, wherein the first operator in the second DFG outputs the first data and sends the first data directly to the second operator in the second DFG.

[0011] According to the above method, compared with the first DFG, the second DFG reduces the number of operators, thereby improving the execution efficiency of the data stream microprocessor and reducing the latency of the data stream microprocessor.

[0012] In one possible design, the first DFG further includes a plurality of fifth operators, wherein the plurality of fifth operators respectively obtain second data from the second operator and send the second data to the RAM, and the second DFG further includes one of the fifth operators, wherein the fifth operator in the second DFG obtains the second data from the second operator in the second DFG and sends the second data to the RAM.

[0013] In one possible design, optimizing the first DFG into a second DFG based on the connection relationships of the operators in the first DFG and / or the data transmitted between the operators includes: optimizing the first DFG into a second DFG by calculating the data transmitted between the operators in the first DFG.

[0014] In one possible design, the first DFG further includes a sixth operator. The first operator in the first DFG also sends the first data to the sixth operator in the first DFG. The sixth operator in the first DFG obtains third data based on the first data and sends the third data to the third operator in the first DFG. The third operator in the first DFG also writes the third data into the RAM. The fourth operator in the first DFG also retrieves the third data from the RAM and sends the third data to the second operator in the first DFG. The first operator in the second DFG also obtains the third data based on the first data and sends the third data to the second operator in the second DFG.

[0015] In one possible design, the sixth operator in the first DFG is a decrementer.

[0016] In one possible design, the method is applied to a distribution advisor (DA) in the dataflow microprocessor.

[0017] According to a second aspect, embodiments of this application provide a dataflow microprocessor having the functionality to implement the method of the first aspect. The functionality can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the functionality.

[0018] According to a third aspect, embodiments of this application provide a computer-readable storage medium including instructions. When the instructions are executed on a computer, they cause the computer to perform the methods described in the first aspect or any possible design of the first aspect.

[0019] According to a fourth aspect, embodiments of this application provide a computing device including a processor, a memory, and a communication interface. The processor is connected to the memory and the communication interface. The memory is used to store instructions, the processor is used to execute the instructions, and the communication interface is used to communicate with other network elements under the control of the processor. When the processor executes the instructions stored in the memory, it causes the processor to perform the methods described in the first aspect or any possible design of the first aspect.

[0020] According to a fifth aspect, embodiments of this application provide a computing device cluster including at least one computing device, wherein the computing device includes a processor and a memory coupled to the processor, wherein the memory is used to store a computer program, and the processor is used to invoke and run the computer program stored in the memory to cause the computing device to perform the methods of the first aspect or any possible design of the first aspect.

[0021] According to a sixth aspect, a chip system is provided, wherein the chip system includes a memory and a processor, the memory being used to store a computer program, and the processor being used to invoke the computer program from the memory and run the computer program to cause a server on which the chip resides to perform the methods described in the first aspect or any possible design of the first aspect.

[0022] According to a seventh aspect, a computer program product is provided, wherein when the computer program product is run on a server, the server is caused to perform the methods described in the first aspect or any possible design of the first aspect. Attached Figure Description

[0023] One or more embodiments are illustrated by way of example with the accompanying drawings, which are not intended to limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings are not limited to scale, wherein: Figure 1 A pseudo-random number generator implemented in C++ is shown; Figure 2 A pseudo-random number generator implemented using EO is shown; Figure 3 It shows the representation Figure 2 A diagram showing the ownership relationships between objects in an EO program; Figure 4 It shows Figure 2 The project's data flow graph (DFG); Figure 5 It shows Figure 4 The data flow timeline (DFT) of the DFG. Figure 6 This is a schematic diagram of a method for calculation based on a data flow graph (DFG) provided in an embodiment of this application; Figure 7 A schematic diagram of a primitive architecture similar to a dataflow machine is shown; Figure 8 It shows Figure 6DFT evaluated by DFG in the middle; Figure 9 The architecture of the dataflow microprocessor is shown; Figure 10 An activity diagram showing the workflow of DA execution is provided. Figure 11 This illustrates another architecture for a dataflow microprocessor; Figure 12 An optimization of the rewriting rules for equation (1) is shown in an intuitive way; Figure 13 This demonstrates the operation on a simulator with an enable module. Figure 4 The DFT is evaluated using the DFG in the module, and the enabling module reproduces the functionality of the DA. Figure 14 An example DFG of the data flow procedure is shown, in which the edge from operator v1 to v3 can be deleted; Figure 15 An example DFG of a data stream procedure is shown, in which data is sent to only one writer w1; Figure 16 This is a schematic block diagram of a dataflow microprocessor provided in an embodiment of this application; Figure 17 This is a schematic block diagram of a computing device provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions in the embodiments of this application are clearly and completely described below with reference to the accompanying drawings. It is obvious that the described embodiments are merely some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this application.

[0025] In the specification, claims, and drawings of this application, the term "comprising" and any other variations thereof are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or apparatus that comprises a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to the process, method, system, product, or apparatus.

[0026] This application presents various aspects, embodiments, or features within the context of systems comprising multiple devices, components, modules, etc. It should be understood and appreciated that various systems may include additional devices, components, modules, etc., and / or may exclude all devices, components, modules, etc., discussed in conjunction with the accompanying drawings. Furthermore, combinations of these approaches may also be used.

[0027] Furthermore, in the embodiments of this application, the words "exemplary," "for example," etc., are used to indicate examples or illustrations. Any embodiment or design described as "exemplary" in this application should not be construed as a preferred or advantageous embodiment that is superior to other embodiments or designs. Rather, the word "exemplary" is used to present a concept in a specific manner.

[0028] In this application, "related" and "corresponding" can sometimes be used interchangeably. It should be noted that, without emphasizing the distinction, they have the same meaning.

[0029] The business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Even if the architecture evolves and new business scenarios emerge, the technical solutions provided by the embodiments of this application are still applicable to solving similar technical problems.

[0030] For ease of description, the following explains several concepts involved in the embodiments of this application.

[0031] A data flow graph (DFG) is a graph that represents the data dependencies between multiple operations, which are software operations running in a data flow microprocessor.

[0032] A surging object graph (SODG) is a graphical representation of an object-oriented program, where objects are vertices and their attributes are edges.

[0033] The data flow timeline (DFT) is the textual temporal representation of the DFG evaluation.

[0034] An operator is a node that represents data transformation or computation. It has one or more input ports and one or more output ports. Data flows from the input ports to the output ports, and the operator performs some kind of transformation on the data during the data flow.

[0035] An instruction cell (IC) is a small memory unit that stores instructions and their operands. It is responsible for controlling the execution of instructions and also provides operands to the functional units that perform the actual calculations.

[0036] An operation unit (OU) is a computing unit that performs specific operations on the data in an IC.

[0037] The distribution advisor (DA) is a hardware component of the dataflow microprocessor that is responsible for redirecting the IC to reduce the workload in the DFG.

[0038] Microarchitecture (also known as "microprocessor architecture") is the way a given instruction set architecture is implemented in a particular processor.

[0039] The central processing unit (CPU), also known as a microprocessor or simply a processor, is an electronic circuit that executes instructions, including computer programs.

[0040] Random access memory (RAM) is a form of computer memory that can be read and changed in any order, and is typically used to store working data and machine code.

[0041] Object-oriented programming (OOP) is a programming paradigm that treats data as objects that simultaneously possess state and behavior.

[0042] Mutability refers to the ability of an object to be changed after it has been created; a mutable object can be changed in situ without creating a new object; on the other hand, an immutable object cannot be changed after it has been created.

[0043] In OOP, an object is a self-contained entity with state and behavior. The state of an object is represented by its data attributes, and the behavior of an object is represented by its methods.

[0044] Dataflow architecture is a computer architecture that differs significantly from traditional von Neumann architecture or control flow architecture. The latter executes instructions sequentially, while the former does not have a program counter.

[0045] The main reason for creating a dataflow computing approach is that traditional von Neumann computers use a shared program counter and globally updatable memory, which are inherently unsuitable for leveraging parallelism.

[0046] A dataflow architecture represents a program as a data flow graph (DFG), where nodes are "operators" and directed edges between them are "channels" through which immutable data values ​​are transferred. Operators are evaluated when data is available on all input channels. Evaluation completes, making the resulting data available to operators at the end of the output channels. Therefore, the order of operator evaluation is unpredictable.

[0047] To our knowledge, one of the main problems with dataflow microprocessors is the back-and-forth transfer of data between the microprocessor and RAM, resulting in high latency and efficiency losses. This negative impact is particularly pronounced in programs that process massive amounts of data that require frequent transfers: neural networks, video and image processing, cryptography, databases, etc. Latency can also affect the performance of object-oriented programs converted to DFG.

[0048] exist Figure 1 The image shows C++ code implementing a pseudo-random number generator. First, the generator (an instance of the `Prng` struct) is initialized via a constructor that sets the struct's local field `last` to the provided "seed" value. Then, the `next()` method is called twice, calculating pseudo-random numbers using the "middle-square method" (proposed by John von Neumann in 1946). It's important to note that the `next()` method not only calculates the number but also modifies the value of the `last` field, which is then used in subsequent calls to the `next()` method.

[0049] It should be understood that, Figure 1 In this code, the Prng struct (whose instances are objects in C++) is mutable because its last property changes its value each time the next() method is called. The expected exit code returned after compilation and execution is 244, which is the lowest byte of the 756 (second random number) returned by the next() method.

[0050] exist Figure 2 The image shows a representation in EO (Object-Oriented Dataflow Programming Language). Figure 1 The program. Here, the prng object has two properties: (1) on line 19, the last property is a copy of the mutable memory object, similar to the mutable field on line 11; (2) on lines 20 to 27, the next property is a sub-object representing the pseudo-random number generation function, similar to the operation performed by the next() method on lines 4 to 9. The main object is an abstraction of the entire application; it consists of two properties: (1) on line 29, the g property is a reference to a copy of the prng object, whose only property is initialized to the data 42; (2) on lines 30 to 32, the @ property is a reference to a copy of the seq object, which implements the sequential evaluation of different numbers of objects. The implementation details of the next object are not important within the scope of this technical solution, but they work in the same way as the C++ code on lines 4 to 9.

[0051] It should be understood that Figure 2 A pseudo-random number generator implemented using EO (a dataflow programming language) is shown, making it very similar to... Figure 1 The code is written in C++. The Prng object includes a single mutable property named last, similar to the mutable class field last in C++ code.

[0052] exist Figure 3 middle, Figure 2The procedure is presented as a surging object di-graph (SODG). The vertex denoted by Φ is the root object of the graph from which evaluation begins. Edges between vertices represent ownership relationships between objects. Labels on the edges are the names of the attributes. The evaluation mechanism of the SODG is not explained here, so only the graph is shown to illustrate how objects are connected by attributes in the EO procedure. The implementation details of the last object are not visible in the graph because the v5 object is a macro operator.

[0053] exist Figure 3 In this context, the highest level of abstraction is the Φ vertex, and the other vertices are represented as follows: v1 represents the main object of the EO program, v2 represents Prng, v3 represents seq, v4 represents memory, v5 represents next, and v6 represents int.

[0054] exist Figure 4 middle, Figure 2 The program is represented as a DFG (Device-Based Graph). The vertices in the graph are operators that process data. The edges between vertices are channels through which data is transmitted. Edges are unidirectional, thus representing the mode of data transmission. Operators without incoming edges are evaluated at the start of the program because these operators do not require incoming data—there is only one operator of this type in the graph: r1. All other operators are "fired" only when data is available in all incoming edges. When the r1 operator (short for "read") is fired, it reads data (integer 42) from RAM and transmits it to the nxt1 operator. The nxt1 operator transforms 42 into 110, which is the next pseudo-random number, and transmits it to the w1 operator (short for "write"). The w1 operator saves the data to RAM and then sends a control token to the r2 operator (the control token is no different from a regular data token, but for better understanding of the data flow evaluation process, the control token is named k, and the data token is named d). When the k token arrives, the r2 operator reads data from RAM and sends it to the nxt2 operator. The nxt2 operator changes 110 to 756, which is the next pseudo-random number, and sends it to the seq operator and the w2 operator. Therefore, the memory object named last is represented in the DFG by four operators: r1, w1, r2, and w2.

[0055] Figure 4 yes Figure 2 In the project's DFG, the mutable object `last` is split into four operators to associate its stateful mechanism with the stateless `next` object. The `seq` operator is stateless because it does not send control flow tokens but only accepts data from the last operator in the operator chain: `nxt1` and `nxt2`.

[0056] exist Figure 5In this context, the data flow timeline (DFT) notation is used to present the data. Figure 4 The evaluation workflow of the data flow diagram. In the DFT, time is from left to right, and the vertical lines represent the counts (ticks) of the data flow microprocessors. The text lines on the right side of the bars describe the evaluation performed by the microprocessor for a particular count, likely in top-to-bottom chronological order. Figure 5 There are 5 counts, which are used for evaluation Figure 4 The diagram shown is necessary: ​​regardless of how many cores a microprocessor has, 5 counts is the minimum possible number.

[0057] It should be understood that, Figure 5 In this context, the names of the initiating operators precede the colon, and the operations performed by these operators follow the colon. The input channels of an operator are represented by the operator name, the point name, and the channel name; for example, w1.d is the input channel d of the w1 operator.

[0058] Here, the term "counting" refers to the complete cycle that propels the entire DFG to its next state: the IC is generated, processed, and then distributed to all operators with sufficient input data. This definition differs from the concept of "counting" in control flow microprocessors.

[0059] from Figure 4 As can be seen, multiple operators perform repetitive read and write operations on RAM, leading to high latency and efficiency losses, thus increasing the workload in the DFG. This negative impact is particularly noticeable in programs that process massive amounts of data that must be transferred frequently.

[0060] To address the aforementioned issues, embodiments of this application provide a method and an apparatus that can reduce the workload of DFG.

[0061] Figure 6 This is a schematic diagram of a method for computation based on a data flow graph (DFG). This method can be executed by a data flow microprocessor for DFG-based computation, or by a module or unit within that microprocessor. The method specifically includes the following steps.

[0062] For example, dataflow microprocessors include distributed advisors (DA). Figure 6 The methods described are applied to DA.

[0063] Step 610: Obtain the first DFG, wherein the first DFG includes multiple operators and data transmitted between the multiple operators.

[0064] In the implementation example of this application, the first DFG runs on a dataflow microprocessor.

[0065] For example, a data stream processor includes an OU, and a first DFG is software running in the OU. Specifically, the operators in the first DFG are software that runs in the OU.

[0066] Step 620: Based on the connection relationships of operators in the first DFG and / or the data transmitted between operators, optimize the first DFG into a second DFG.

[0067] In the implementation example of this application, the second DFG runs on a dataflow microprocessor.

[0068] For example, the second DFG is software running in Ou. Specifically, the operators in the second DFG are software that runs in Ou.

[0069] Step 630: Execute the second DFG on the data stream microprocessor.

[0070] According to the above method, based on the connection relationships of operators in the first DFG and / or the data transmitted between operators, the first DFG running in the dataflow microprocessor is optimized to obtain a second DFG, which is then run in the dataflow microprocessor. Since the second DFG is optimized relative to the first DFG, it can improve the execution efficiency of the dataflow microprocessor and reduce its latency.

[0071] In one possible implementation, the second DFG reduces the number of operators compared to the first DFG, thereby improving the execution efficiency of the data stream microprocessor while also reducing its latency.

[0072] For example, compared with the first DFG, the second DFG reduces unnecessary round trips between the operators and RAM in the first DFG, thereby avoiding unnecessary interactions between the data stream microprocessor and RAM and improving the execution efficiency of the data stream microprocessor.

[0073] In one possible design, the first DFG includes a first operator, a second operator, a third operator, and a fourth operator, wherein the first operator outputs first data and sends the first data to the third operator, the third operator writes the first data into the RAM, the fourth operator retrieves the first data from the RAM and sends the first data to the second operator, and the second DFG includes the first operator and the second operator, wherein the first operator in the second DFG outputs the first data and sends the first data directly to the second operator in the second DFG.

[0074] In another possible design, the first DFG further includes a plurality of fifth operators, wherein the plurality of fifth operators respectively obtain second data from the second operator and send the second data to the RAM, and the second DFG further includes one of the fifth operators, wherein the fifth operator in the second DFG obtains the second data from the second operator in the second DFG and sends the second data to the RAM.

[0075] In another possible design, the first DFG is optimized based on the data transmitted on each computing unit of the first DFG to obtain the second DFG.

[0076] For example, the first DFG further includes a sixth operator. The first operator in the first DFG also sends the first data to the sixth operator in the first DFG. The sixth operator in the first DFG obtains third data based on the first data and sends the third data to the third operator in the first DFG. The third operator in the first DFG also writes the third data into the RAM. The fourth operator in the first DFG also retrieves the third data from the RAM and sends the third data to the second operator in the first DFG. The first operator in the second DFG also obtains the third data based on the first data and sends the third data to the second operator in the second DFG.

[0077] For example, the sixth operator in the first DFG is a decrementer.

[0078] In the above technical solution, data flow is optimized within the microprocessor by leveraging the inherent semantics of operators such as memory writers and readers. This solution replaces single RAM round trips with direct data transfer to the receiving operator, subsequently establishing synthetic data flow edges at their locations. By detecting and eliminating unnecessary round trips to RAM, data routing efficiency is improved, thereby reducing the number of counts in the data flow microprocessor. Therefore, this solution achieves a substantial leap forward in pursuing higher efficiency and performance in data flow microprocessors.

[0079] The best way to demonstrate this solution is to use examples, where, Figure 4 DFG in the middle can be like Figure 7 The optimization shown is as follows: the functionality is retained, but the nxt1 operator sends data directly to the nxt2 operator instead of the w1 operator.

[0080] exist Figure 7In this approach, redundant round trips are eliminated by creating a new composite edge between the nxt1 and nxt2 operators. Data is not sent via the edge between the nxt1 and w1 operators, which is why the edge is no longer visible in the DFG.

[0081] This optimization results in a shorter evaluation timeline, such as Figure 8 As shown. Operators w1 and r2 do not receive data at all, therefore write and read operations do not use RAM.

[0082] exist Figure 8 middle, Figure 6 The DFT ratio of DFG evaluation in the middle Figure 5 The timeline is shorter because data is transferred directly from the nxt1 operator to the nxt2 operator without needing to travel back and forth to RAM.

[0083] In one possible implementation, Figure 9 The architecture of the dataflow microprocessor is illustrated, including: a distribution advisor (DA), a distribution network, a set of operators in the DFG, an arbitration network, and a set of computational units. The DA sits in front of the distribution network and makes additional distribution decisions regarding possible composite edges between operators.

[0084] It should be understood that the distributed network, arbitration network, and arithmetic units are all hardware. Operators contain information that helps create instruction units. The arbitration network uses this information to create instruction units. The arbitration network reads the DFG, which is uploaded to the microprocessor's memory by the programmer. The DFG is a set of operators. The arbitration network retrieves the next operator ready for evaluation, creates a new instruction unit, and sends it to the next available arithmetic unit (also called an ALU). The arithmetic unit performs the computation and adds more data to the instruction unit. The instruction unit then goes to the DA, where it decides whether to optimize the instruction unit. The DA then transmits the instruction unit to the distributed network, which determines where to place the data generated by the ALU. When a decision is made, data is placed into the new instruction unit, and these instruction units begin to be transmitted in the same cycle.

[0085] It should also be understood that operators are software components, like commands uploaded to a microprocessor, that run on the arithmetic unit. An instruction unit is a piece of data (20 to 50 bytes in length) created by the arbitration network and sent to the arithmetic unit, and then to the distributed network (DA).

[0086] In order to achieve from Figure 4 DFG to Figure 7 DFG optimization, in one possible implementation, Figure 9The paper proposes integrating an add-on component (DA) into a dataflow microprocessor. This component will be responsible for identifying unnecessary round trips to RAM and then creating shortcuts by synthesizing dataflow edges.

[0087] exist Figure 7 In a specific scenario, DA observes that data is intended to be transferred from operator nxt1 to operator w1, then back to operator nxt2 via RAM, and subsequently via operator r2. The semantics of operators w1 and r2 are known to DA: they are memory writers and readers, respectively. Knowing this, and also knowing that there are no other readers in this part of RAM, DA can decide that data can be directly sent to nxt2, thus forming a composite edge from nxt1 to nxt2.

[0088] It's important to note that while sending data directly from the nxt1 operator to the seq operator might be beneficial, DA will not do so because it doesn't understand the semantics of the nxt2 operator. The nxt2 operator is a macro-operator with an embedded control flow microprogram. Sending data directly from the nxt1 operator to the seq operator would be incorrect because this optimization would bypass the computation of the second pseudo-random number. Therefore, the program's evaluation result would be 110 (incorrect) instead of 756 (correct).

[0089] exist Figure 9 In different contexts, the applicability of DA in dataflow microprocessors may vary: 1. DA can implement different algorithms, rather than just focusing on reducing the number of round trips to RAM; 2. DA is not a separate component preceding the distribution network; it may be part of the distribution network, follow the distribution network, or even replace the distribution network.

[0090] 3. DA can not only redirect data, but also modify data to reduce the amount of computation performed by OU, such as... Figure 14 As shown.

[0091] 4. DA can accumulate information about data distribution into IC, and then use that information to make more effective decisions about data redirection.

[0092] 5. DA may play a similar role in multi-core or cluster architectures, redirecting data between DFGs, rather than just within a single DFG.

[0093] In one possible implementation, Figure 10 The activity graph shows the workflow that DA executes each time an IC arrives: determining whether redirection is possible, and then generating a new IC to replace the arriving IC.

[0094] In one possible implementation, Figure 11This illustrates another architecture for a dataflow microprocessor. Figure 11 The DA in the diagram can use additional OUs for arithmetic or other computations performed before the IC reaches the DN (these additional OUs are represented as AOUs in the diagram). The computational power of the AOU depends on the complexity of the computation the microprocessor needs to perform, and may even exceed the computational power of the OU. The central part of the diagram is... Figure 9 The content shown is simplified.

[0095] The following will list some implementation details.

[0096] While the implementation of DA may vary depending on the type of redirection decision DA makes, there are several mechanisms that can optimize for redundant round trips to RAM.

[0097] If we express DFG as a filtering function e(a, v1, v2), this filtering function holds when there exists a directed edge marked as leaving vertex v1 and reaching vertex v2, then Figure 6 The optimization decision can be expressed as a rewriting rule of equation (1). If the premise of the rule is true, then DFG can be modified so that the conclusion of the rule is also true.

[0098] (1) The filter function m(v, a) holds true if vertex v accesses the RAM portion located at address a. Both filter functions e and m are relatively easy to implement at the hardware level because filter function m is not the only expected function. It can only hold true if the semantics of the first parameter (vertex) are explicit and belong to one of two categories: a reader from RAM or a writer to RAM. If the semantics are unknown, the filter function may not hold true, or even hold falsely. Figure 12 The effect of equation (1) is shown intuitively.

[0099] The evaluation results of the e and m filtering functions can be cached by the CPU because they are constants: they do not change until the program execution ends. Furthermore, these evaluation results can be evaluated at the start of program execution, thus reducing the time required for the DA to make data redirection decisions at runtime.

[0100] exist Figure 12 The text intuitively demonstrates the optimization of the rewriting rule of equation (1). The DFG at (A) has only two edges, while DFG(B) obtains a new composite edge that leaves v1 and reaches v2, provided that... a : m(vw, a) ∧m(vr, a), where vw is the "writer" and vr is the "reader" at the same address in RAM.

[0101] One possible implementation uses a simulator for the dataflow machine in the Ruby programming language to verify the DA mechanism. The source code is hosted in a GitHub repository. Figure 5 and Figure 8 The DFT timeline in the image is rendered using this simulator. Furthermore, Figure 13 The timeline generated by the simulator when the DA function is enabled is shown. The lines in the second count that begin with the prefix "DA:" are generated by the DA module. The DA module redirects data destined for the w1 operator to the nxt2 operator. This decision is made by the DA module based on the mechanism of equation (1).

[0102] exist Figure 13 In the simulator with an enabled module that reproduces DA functionality, for Figure 4 The DFT used to evaluate the DFG in the dataset is written in the Ruby programming language.

[0103] One potential topic for future research is the development of a converter that can convert C++ programs (or programs from any other object-oriented language) into DFG format. The evaluation mechanism can then be verified using the simulator of this invention.

[0104] The following will explain the information that DA needs to know about DFG.

[0105] Data Analyzer (DA) can gain insights into operator semantics at compile time or runtime. During compile time, the compiler understands the semantics of each operator in the Data Flow Gradient (DFG). The compiler then provides this knowledge as supplemental metadata about the compiled program. At runtime, DA can preemptively analyze the DFG before the program runs or analyze it as needed. Given that the DFG size in macro-dataflow microprocessors is still relatively small, scanning the entire DFG is highly efficient. Importantly, DA does not need to know the complete semantics of every operator. DA only needs to know whether the operator reads / writes data from RAM and the unique location of the block it interacts with in RAM (absolute address values ​​are not required).

[0106] The following will explain why DFG cannot be optimized at compile time.

[0107] Some inefficiencies in DFG can be statically resolved at compile time, even before the DFG is scheduled to the microprocessor. However, certain dynamic details that are crucial for optimization decisions may not be accessible to the compiler, including (a) the frequency of use of certain operators, (b) the size of data transferred through edges, and (c) the completion status of ICs.

[0108] The differences between DA and JIT compilers will be explained below.

[0109] The role of Data Optimizer (DA) is somewhat similar to that of the Just-In-Time (JIT) compiler, a component of the Java™ Virtual Machine that improves the performance of Java applications by translating bytecode into native machine code in real time. While technically this translation to native machine code could be performed by the compiler for the entire application, it is deferred to runtime for various reasons. Interestingly, these reasons echo the motivations behind delegating DFG optimizations to DA.

[0110] The following will explain how data size affects DA's decisions.

[0111] The data transfer capability between operators in a DFG is constrained by the CPU's physical architecture. A cautious assumption is that, in modern CPUs, DFG edges may not be suitable for megabyte-scale data transfers. Under this constraint, DA must calibrate its redirection selection: avoiding redirection when the data size exceeds a certain threshold.

[0112] The following will explain how much computing power DA can provide.

[0113] Figure 14 This demonstrates how Data Analyzers (DAs) perform mathematical decrementing on integers to save CPU counts. DAs can perform more complex operations, including multiplication, division, bit shifting, and other traditional data operations available in control-flow CPUs. DAs themselves can act as coprocessors, helping dataflow microprocessors optimize evaluation flows and minimize the number of counts required. Furthermore, DAs can employ supplementary OUs, delegating a portion of the workload to these OUs, such as... Figure 11 As shown.

[0114] exist Figure 14 In this context, if the semantics of operator v2 are known, and it is a "decreasing" operator for data arrival (a typical pattern in loops and recursion), then data can be directly sent to the arriving operator, thus reducing the CPU count by one. Edges from operator v1 to operator v2 can be removed to avoid data redundancy.

[0115] The following will explain the minimum DFG pattern that can be optimized.

[0116] The optimizations performed by DA are only meaningful when three or more operators are involved, for example... Figure 14 Explanation: The "originating" operator, "receiving" operator, and "substitute" operator that replaces the receiving operator are filled in the IC. Figure 15 A segment of a DFG is shown, in which a data token from operator v1 is transferred to two operators w1 and w2, both of which are written to the same location in RAM. It is clear that the double write to the same portion of RAM can be simplified to a single write, thus skipping the data transfer to operator w2 (e.g.).

[0117] exist Figure 15 In segment (A), operator v1 sends the same data to two writers w1 and w2 connected to the same location in RAM. Segment (B) is modified by DA so that data is sent to only one writer w1, which reduces the number of counts in the microprocessor.

[0118] For some DFGs, the following dual positive effects can be achieved due to the use of DA in the dataflow microprocessor architecture: 1. It can reduce the number of round trips to RAM; 2. It can reduce the number of CPU cycles.

[0119] The ultimate result of this dual effect is a reduction in the time required to evaluate the entire DFG or some of its subgraphs.

[0120] The primary objective of this invention is to design a dataflow microprocessor for general-purpose programming languages ​​such as C++ or Java. Previous attempts have yielded microprocessors specifically designed to execute object-oriented programs. However, to our knowledge, none of these approaches have utilized the principles of dataflow architecture. It is anticipated that a dataflow microprocessor equipped with this invention and executing a C++ program (pre-converted to EO) ​​can exhibit significantly higher performance than a controlflow architecture running the same C++ program.

[0121] This invention falls under the field of internal design of microprocessor architectures (“G06F7” IPC category). Due to the microscopic nature of microprocessors, it is virtually impossible to decompose competing solutions and prove that their dataflow architecture includes DA. However, there are some possible implicit metrics that may be helpful: 1. If a program with a certain number of stateful operators makes fewer round trips to RAM than theoretically should, this can be a clear indicator of good performance in microprocessor DA (Data Access). Round trips can be calculated by scanning the memory bus. However, CPU caches can interfere by reducing the number of round trips to RAM.

[0122] 2. If a program with a certain number of operators produces fewer counts than it should theoretically produce, this may be an indicator of using DA.

[0123] 3. If the binary workload output by the compiler includes supplemental metadata about the semantics of the DFG operators, specifically detailing the memory readers / writers and their interactions with RAM, this may indicate the use of DA.

[0124] Determining whether a competitor's dataflow microprocessor architecture includes Data Controller (DA) using publicly available product documentation (such as user manuals, white papers, and videos) can be challenging, but achievable. Metrics may include: 1. If optimizations guarantee that an object-oriented program with stateful (mutable) objects may run faster than expected due to the processor’s internal optimizations, then it is very likely that these optimizations will be achieved by using DA.

[0125] 2. If optimizations ensure that specific DFG optimizations are performed by the processor at runtime, and the compiler does not provide these optimizations, then such optimizations are likely performed by the DA located before the distribution network.

[0126] 3. If optimizations ensure reduced inefficiencies caused by memory read / write operations at runtime, then these optimizations likely refer to the presence of DA (Data Access Optimization).

[0127] Figure 16 This is a schematic block diagram of a dataflow microprocessor 1600 provided in an embodiment of this application. Figure 16 As shown, the data flow microprocessor 1600 includes: an acquisition unit 1601, an optimization unit 1602, and an execution unit 1603.

[0128] As an example, the dataflow microprocessor 1600 is used to perform calculations based on a data flow graph (DFG). An acquisition unit 1601 is used to acquire a first DFG, wherein the first DFG includes multiple operators and data transmitted between the multiple operators, and the first DFG runs on the dataflow microprocessor. An optimization unit 1602 is used to optimize the first DFG into a second DFG based on the connection relationships of the operators in the first DFG and / or the data transmitted between the operators, wherein the second DFG runs on the dataflow microprocessor. An execution unit 1603 is used to execute the second DFG.

[0129] In some embodiments, the optimization unit is specifically used to optimize the first DFG into the second DFG by reducing the number of round trips between the operator in the first DFG and the random access memory (RAM).

[0130] In some embodiments, the first DFG includes a first operator, a second operator, a third operator, and a fourth operator, wherein the first operator outputs first data and sends the first data to the third operator, the third operator writes the first data into the RAM, and the fourth operator retrieves the first data from the RAM and sends the first data to the second operator. The second DFG includes the first operator and the second operator, wherein the first operator in the second DFG outputs the first data and directly sends the first data to the second operator in the second DFG.

[0131] In some embodiments, the first DFG further includes a plurality of fifth operators, wherein the plurality of fifth operators respectively obtain second data from the second operator and send the second data to the RAM, and the second DFG further includes one of the fifth operators, wherein the fifth operator in the second DFG obtains the second data from the second operator in the second DFG and sends the second data to the RAM.

[0132] In some embodiments, the optimization unit is specifically configured to optimize the first DFG into the second DFG by calculating the data transmitted between the operators in the first DFG.

[0133] In some embodiments, the first DFG further includes a sixth operator, the first operator in the first DFG also sends the first data to the sixth operator in the first DFG, the sixth operator in the first DFG obtains third data based on the first data and sends the third data to the third operator in the first DFG, the third operator in the first DFG also writes the third data into the RAM, the fourth operator in the first DFG also retrieves the third data from the RAM and sends the third data to the second operator in the first DFG, and the first operator in the second DFG also obtains the third data based on the first data and sends the third data to the second operator in the second DFG.

[0134] In some embodiments, the sixth operator is a decrementer.

[0135] In some embodiments, the data flow microprocessor 1600 further includes a understanding unit for understanding the semantics of a plurality of operators in the first DFG.

[0136] like Figure 17 As shown, computing device 1700 may include transceiver 1701, processor 1702, and memory 1703. Memory 1703 may be used to store code, instructions, etc., executed by processor 1702.

[0137] It should be understood that the processor 1702 in the computing device 1700 may correspond to the data stream microprocessor 1600.

[0138] It should be understood that the processor 1702 can be an integrated circuit chip with signal processing capabilities. In implementation, the various steps of the above method embodiments can be completed by hardware integrated logic circuits in the processor or by software instructions. The processor can be a general-purpose processor, a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), a system-on-chip (SoC), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. A general-purpose processor can be a microprocessor, or it can be any common processor. The steps of the methods disclosed in the embodiments of this application can be directly executed by a hardware decoding processor, or executed using a combination of hardware and software modules in the decoding processor. The software modules can be located in storage media that are well-established in the field, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. The storage medium is located in memory, and the processor reads information from the memory and, in conjunction with the hardware in the processor, completes the steps of the above methods.

[0139] It is understood that the memory 1703 in the embodiments of this application can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM) used as an external cache. By way of example, but not limitation, many forms of RAM can be used, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0140] It should be noted that the memory of the systems and methods described in this specification includes, but is not limited to, these memories and any other suitable types of memory.

[0141] Embodiments of this application also provide a system-on-a-chip (SoC), which includes an input / output interface, at least one processor, at least one memory, and a bus. The at least one memory is used to store instructions, and the at least one processor is used to invoke the instructions from the at least one memory to perform the operations of the methods described above.

[0142] Embodiments of this application also provide a computer storage medium, wherein the computer storage medium can store program instructions to execute any of the methods described above.

[0143] Alternatively, the storage medium may specifically be memory 1703.

[0144] Those skilled in the art will recognize that the various examples described in conjunction with the embodiments disclosed in this specification, the units and algorithm steps, can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but this implementation should not be considered beyond the scope of the invention.

[0145] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the above-described systems, devices, and units can be referred to the corresponding processes in the above method embodiments. Further details will not be repeated here.

[0146] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the described apparatus embodiments are merely exemplary. For example, the unit division is only a logical functional division, and other division methods may be used in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not performed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed can be implemented through some interfaces. Indirect coupling or communication connection between devices or units can be implemented electronically, mechanically, or otherwise.

[0147] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; they may be located in one place or distributed across multiple network units. Some or all of the units can be selected based on actual needs to achieve the purpose of the embodiment.

[0148] In addition, the functional units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0149] When these functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes any medium capable of storing program code, such as a USB flash drive, a removable hard disk, read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0150] The above description is merely a specific implementation of this application and is not intended to limit the scope of protection of this application. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for calculation based on a data flow graph (DFG), characterized in that, The method is applied to a dataflow microprocessor, and the method includes: A first DFG is obtained, wherein the first DFG includes multiple operators and data transmitted between the multiple operators, and the first DFG runs on the data stream microprocessor; Based on the connection relationships of the operators in the first DFG and / or the data transmitted between the operators, the first DFG is optimized into a second DFG, wherein the second DFG runs on the data stream microprocessor; Execute the second DFG.

2. The method according to claim 1, characterized in that, Optimizing the first DFG into a second DFG based on the connection relationships of the operators in the first DFG and / or the data transmitted between the operators includes: The first DFG is optimized into the second DFG by reducing the number of round trips between the operator in the first DFG and the random access memory (RAM).

3. The method according to claim 2, characterized in that, The first DFG includes a first operator, a second operator, a third operator, and a fourth operator. The first operator outputs first data and sends the first data to the third operator. The third operator writes the first data into the RAM. The fourth operator retrieves the first data from the RAM and sends the first data to the second operator. The second DFG includes the first operator and the second operator. The first operator in the second DFG outputs the first data and sends the first data directly to the second operator in the second DFG.

4. The method according to claim 3, characterized in that, The first DFG further includes a plurality of fifth operators, wherein the plurality of fifth operators respectively obtain second data from the second operator and send the second data to the RAM. The second DFG further includes one of the fifth operators, wherein the fifth operator in the second DFG obtains the second data from the second operator in the second DFG and sends the second data to the RAM.

5. The method according to any one of claims 1 to 4, characterized in that, Optimizing the first DFG into a second DFG based on the connection relationships of the operators in the first DFG and / or the data transmitted between the operators includes: The first DFG is optimized into the second DFG by calculating the data transmitted between the operators in the first DFG.

6. The method according to claim 5, characterized in that, The first DFG further includes a sixth operator. The first operator in the first DFG also sends the first data to the sixth operator in the first DFG. The sixth operator in the first DFG obtains third data based on the first data and sends the third data to the third operator in the first DFG. The third operator in the first DFG also writes the third data into the RAM. The fourth operator in the first DFG also retrieves the third data from the RAM and sends the third data to the second operator in the first DFG. The first operator in the second DFG also obtains the third data based on the first data and sends the third data to the second operator in the second DFG.

7. The method according to claim 6, characterized in that, The sixth operator in the first DFG is a decrementer.

8. The method according to any one of claims 1 to 7, characterized in that, The method further includes: Understand the semantics of the plurality of operators in the first DFG.

9. The method according to any one of claims 1 to 8, characterized in that, The method is applied to the distribution advisor (DA) in the dataflow microprocessor.

10. A dataflow microprocessor that performs computations based on a data flow graph (DFG), characterized in that, The data stream microprocessor includes: An acquisition unit is configured to acquire a first DFG, wherein the first DFG includes multiple operators and data transmitted between the multiple operators, and the first DFG runs on the data stream microprocessor; An optimization unit is configured to optimize the first DFG into a second DFG based on the connection relationship of the operators in the first DFG and / or the data transmitted between the operators, wherein the second DFG runs on the data stream microprocessor; An execution unit is used to execute the second DFG.

11. The data stream microprocessor according to claim 10, characterized in that, The optimization unit is specifically used to optimize the first DFG into the second DFG by reducing the number of round trips between the operator in the first DFG and the random access memory (RAM).

12. The data stream microprocessor according to claim 10 or 11, characterized in that, The first DFG includes a first operator, a second operator, a third operator, and a fourth operator. The first operator outputs first data and sends the first data to the third operator. The third operator writes the first data into the RAM. The fourth operator retrieves the first data from the RAM and sends the first data to the second operator. The second DFG includes the first operator and the second operator. The first operator in the second DFG outputs the first data and sends the first data directly to the second operator in the second DFG.

13. The dataflow microprocessor according to claim 12, characterized in that, The first DFG further includes a plurality of fifth operators, wherein the plurality of fifth operators respectively obtain second data from the second operator and send the second data to the RAM. The second DFG further includes one of the fifth operators, wherein the fifth operator in the second DFG obtains the second data from the second operator in the second DFG and sends the second data to the RAM.

14. The data stream microprocessor according to any one of claims 10 to 13, characterized in that, The optimization unit is specifically used to optimize the first DFG into the second DFG by calculating the data transmitted between the operators in the first DFG.

15. The data stream microprocessor according to claim 14, characterized in that, The first DFG further includes a sixth operator. The first operator in the first DFG also sends the first data to the sixth operator in the first DFG. The sixth operator in the first DFG obtains third data based on the first data and sends the third data to the third operator in the first DFG. The third operator in the first DFG also writes the third data into the RAM. The fourth operator in the first DFG also retrieves the third data from the RAM and sends the third data to the second operator in the first DFG. The first operator in the second DFG also obtains the third data based on the first data and sends the third data to the second operator in the second DFG.

16. The dataflow microprocessor according to claim 15, characterized in that, The sixth operator in the first DFG is a decrementer.

17. The data stream microprocessor according to any one of claims 10 to 16, characterized in that, The data stream microprocessor also includes: The understanding unit is used to understand the semantics of the plurality of operators in the first DFG.

18. A computer-readable storage medium for storing instructions, characterized in that, When the instruction is executed on the server, it causes the server to perform the method according to any one of claims 1 to 9.

19. A computing device cluster, characterized in that, The device includes at least one computing device, wherein the computing device includes a processor and a memory coupled to the processor, wherein the memory is used to store a computer program, and the processor is used to invoke and run the computer program stored in the memory to cause the computing device to perform the method according to any one of claims 1 to 9.

20. A computer program product, characterized in that, When the computer program product is run on the server, the server performs the method according to any one of claims 1 to 9.

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