Window-type out-of-order execution in processing unit as side-channel attack countering

Abstract

Systems and techniques for secure processing are provided. For example, a process may include receiving a plurality of instructions for execution; receiving an indication that the plurality of instructions are independent instructions; randomly reordering the plurality of instructions; executing the plurality of instructions which are randomly reordered; and outputting a plurality of results corresponding to the plurality of instructions.

Description

Technical Field

[0001] This disclosure relates to secure computing in general. For example, aspects of this disclosure relate to systems and techniques for enhancing security protection by using window-type out-of-order execution in a processing unit as a countermeasure against side-channel attacks. Background Technology

[0002] Computing devices can utilize firmware or operating system software to store sensitive data owned by users or businesses. To help protect computing devices, firmware or software may include security measures to protect them from various security threats, such as brute-force attacks, disabling secure boot / trusted boot, and / or preventing side-channel attacks on the computing device.

[0003] Side-channel attacks are a type of attack targeting computing devices that attempts to exploit certain physical characteristics of the device to obtain information. These characteristics can include timing, power consumption, thermal emission, electromagnetic emission, and acoustic emission. Therefore, techniques to help mitigate or detect potential side-channel attacks can be useful. Summary of the Invention

[0004] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Accordingly, the following outline presents certain concepts in a simplified form relating to one or more aspects of the mechanisms disclosed herein, preceding the detailed description that follows.

[0005] Systems, methods, apparatuses, and computer-readable media for out-of-order execution in processing units as countermeasures against side-channel attacks are disclosed. In one exemplary example, an apparatus for secure processing is provided. The apparatus includes: a memory including instructions; and a processor coupled to the memory. The processor is configured to: receive a plurality of instructions for execution; receive an indication that the plurality of instructions are independent instructions; randomly reorder the plurality of instructions; execute the randomly reordered plurality of instructions; and output a plurality of results corresponding to the plurality of instructions.

[0006] For example, a method for secure processing is provided. The method includes: receiving a plurality of instructions for execution; receiving an indication that the plurality of instructions are independent instructions; randomly reordering the plurality of instructions; executing the randomly reordered plurality of instructions; and outputting a plurality of results corresponding to the plurality of instructions.

[0007] For example, an apparatus for secure processing is provided. The apparatus includes: a component for receiving a plurality of instructions for execution; a component for receiving an indication that the plurality of instructions are independent instructions; a component for randomly reordering the plurality of instructions; a component for executing the randomly reordered plurality of instructions; and a component for outputting a plurality of results corresponding to the plurality of instructions.

[0008] In some aspects, one or more of the devices described herein are, are a part of, or include the following: mobile devices (e.g., mobile phones or so-called "smartphones," tablet computers, or other types of mobile devices), wearable devices, extended reality devices (e.g., virtual reality (VR) devices, augmented reality (AR) devices, or mixed reality (MR) devices), personal computers, laptop computers, video servers, television sets (e.g., network-connected television sets), vehicles (or computing devices or systems of vehicles), or other devices. In some aspects, the device includes at least one camera for capturing one or more images or video frames. For example, the device may include one or more cameras (e.g., an RGB camera) for capturing one or more images and / or one or more videos including video frames. In some aspects, the device includes a display for displaying one or more images, videos, notifications, or other displayable data. In some aspects, the device includes a transmitter configured to transmit one or more video frames and / or syntax data to at least one device via a transmission medium. In some aspects, the processor includes a neural processing unit (NPU), a central processing unit (CPU), a graphics processing unit (GPU), or other processing devices or components.

[0009] The features and technical advantages of the examples according to this disclosure have been summarized rather extensively above in order to better understand the detailed description below. Additional features and advantages will be described below. The disclosed concepts and specific examples can be readily used as the basis for modifying or designing other structures for achieving the same purpose as this disclosure. Such equivalent constructions do not depart from the scope of the appended claims. The characteristics of the concepts disclosed herein, in both their organization and manner of operation, and the associated advantages, will be better understood by considering the following description in conjunction with the accompanying drawings. Each of the drawings provided is for illustrative and descriptive purposes and not as a definition of limitation of the claims.

[0010] While aspects are described herein by way of example, those skilled in the art will understand that such aspects can be implemented in many different arrangements and scenarios. The techniques described herein can be implemented using different platform types, devices, systems, shapes, sizes, and / or package arrangements. For example, some aspects can be implemented via integrated chip implementations or other devices based on non-modular components (e.g., end-user equipment, vehicles, communication equipment, computing devices, industrial equipment, retail / shopping devices, medical devices, and / or artificial intelligence devices). Aspects can be implemented in chip-level components, modular components, non-modular components, non-chip-level components, device-level components, and / or system-level components. Devices incorporating the described aspects and features may include additional components and features for implementing and practicing the claimed and described aspects. For example, the transmission and reception of wireless signals may include one or more components (e.g., hardware elements including antennas, radio frequency (RF) chains, power amplifiers, modulators, buffers, processors, interleavers, adders, and / or summers) for analog and digital purposes. The aspects described herein are intended to be practiced in a wide variety of devices, components, systems, distributed arrangements, and / or end-user equipment of various sizes, shapes, and configurations.

[0011] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0012] Examples of specific implementations are described in detail below with reference to the accompanying figures: Figure 1 This is a diagram illustrating example wireless devices based on some examples; Figure 2 This is a block diagram illustrating the execution of processor instructions during a window used for out-of-order execution according to various aspects of this disclosure; Figure 3A Examples of assembly code based on various aspects of this disclosure illustrate special instructions that indicate multiple independent instructions that can be executed in a random order; Figure 3B Examples of assembly code based on various aspects of this disclosure illustrate special instructions that indicate multiple independent instructions that can be executed in a random order; Figure 4 It is a flowchart of a process for secure handling based on various aspects of this disclosure; Figure 5 This is a block diagram illustrating an example of a wireless communication network based on some examples; Figure 6These are illustrations of designs for base stations and user equipment (UE) based on some examples, which enable the transmission and processing of signals exchanged between the UE and the base station; and Figure 7 This is a diagram illustrating examples of computing systems according to various aspects of this disclosure. Detailed Implementation

[0013] Certain aspects and embodiments of this disclosure are provided below. Some of these aspects and embodiments may be applied independently, and some may be combined, as will be apparent to those skilled in the art. Specific details are set forth in the following description for purposes of explanation in order to provide a thorough understanding of the various embodiments of this application. However, it will be apparent, however, that the various embodiments may be practiced without these specific details. The accompanying drawings and descriptions are not intended to be limiting.

[0014] The following description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the subsequent description of exemplary embodiments will provide those skilled in the art with enabling descriptions for implementing the exemplary embodiments. It should be understood that various changes may be made to the function and arrangement of the elements without departing from the spirit and scope of this application as set forth in the appended claims.

[0015] In some cases, computing devices may be able to perform operations where additional security can be expected. Computing devices can be wireless devices (e.g., user equipment (UE) in 3GPP systems, such as 4G LTE networks or 5G New Radio (NR) networks), base stations (e.g., LTE eNodeB (eNB), 5G / NR gNodeB (gNB), etc.), server equipment, or other computing devices. Examples of wireless devices include mobile devices (e.g., mobile phones), extended reality (XR) devices (such as virtual reality (VR) devices or augmented reality (AR) devices), vehicles or components or systems of vehicles, Internet of Things (IoT) devices, network-connected wearable devices (such as watches), or other types of computing devices.

[0016] For example, a computing device can be used to generate private keys that can be used to protect important assets such as blockchain wallets, digital certificates, and digital signatures. The computing device can also be used to access such important assets. To help allow for such security actions, the computing device may include a secure processing unit. This secure processing unit can be configured or designed (or “hardened”) to resist attacks such as side-channel attacks, which can make the secure processing unit less suitable for general use.

[0017] Side-channel attacks are a type of physical attack on computing devices in which an attacker gains access to the device and can perform non-destructive attempts to extract information from it. For example, an attacker might measure the device's power consumption while performing certain tasks (such as inducing errors, like bit flips or inducing power failures) to help uncover subtle physical differences that might occur during certain operations. For instance, an attacker might measure the device's power consumption or electromagnetic radiation during the execution of an encryption algorithm to extract the encryption key from the device.

[0018] To help strengthen processors against side-channel attacks, processors can execute certain instructions in a randomized order. In some cases, these instructions can be independent machine code instructions used to perform cryptographic operations (e.g., instructions that can be executed out of order). Executing instructions in a randomized order or shuffling instructions helps make it more difficult for attackers to correlate data obtained via a side channel with what is being executed, which in turn makes developing side-channel attacks more difficult. While shuffling can be implemented in software, the software implementation of shuffling can vary in quality across different software applications and may generate machine code / assembly code with large jumps in the code, which could be identified by attackers using machine learning techniques.

[0019] This document describes systems, apparatuses, electronic devices, methods (also referred to as processes), and computer-readable media (collectively, “Systems and Technologies”) for using window-type out-of-order execution in a processing unit to combat side-channel attacks. In some cases, special-purpose instructions (e.g., opcodes, opcodes, instruction codes, assembly instructions, etc.) or flags (e.g., flags, voltages applied to pins, bits set in registers, etc.) may be added to the processor to indicate the presence of multiple instructions that can be executed in a random order. This special-purpose instruction or flag can be used to trigger an out-of-order execution (e.g., speculative execution) pipeline in the processor. For example, based on this indication, the execution order of the multiple instructions that can be executed in a random order can be randomized, and then the multiple instructions are executed in a random order. The randomized multiple instructions can then be placed on a reordering buffer of the out-of-order execution pipeline and the randomized multiple instructions are executed. In some cases, the special-purpose instruction may indicate the number of subsequent instructions that can be executed in a random order. In other cases, the special-purpose instruction may indicate the start and end of the multiple instructions that can be executed in a random order. In other cases, the flag may indicate when the multiple instructions that can be executed in a random order are received.

[0020] Additional aspects of this disclosure are described in more detail below.

[0021] Figure 1 This is a diagram illustrating an example wireless device 100 that can be used to perform the techniques described herein. Wireless device 100 may include client devices, such as user equipment (UE) (e.g., those described below). Figure 5UE 504, UE 552, or UE 590) or other types of devices that can be used by an end user (e.g., a station (STA) configured to communicate using a Wi-Fi interface). For example, wireless device 100 may include mobile phones, vehicles or vehicle computing systems or devices, routers, tablet computers, laptop computers, tracking devices, wearable devices (e.g., smartwatches, glasses, etc.), extended reality (XR) devices (e.g., virtual reality (VR), augmented reality (AR), or mixed reality (MR) devices, Internet of Things (IoT) devices, access points, point-of-sale devices, and / or another device configured to communicate via a wireless communication network.

[0022] As shown in the figure, wireless device 100 may include one or more local area network (LAN) transceivers 106 that can be connected to one or more antennas 102. The one or more LAN transceivers 106 include features for communicating with network devices within the network (e.g., Figure 5 The access point (AP) 550 communicates with and / or detects signals to / from the network device and / or directly with other wireless devices within the network (e.g., Figure 5 Suitable equipment, circuitry, hardware and / or software for UE 552 communication.

[0023] In some implementations, the wireless device 100 may also include one or more wide area network (WAN) transceivers 104 that can be connected to one or more antennas 102. The WAN transceiver 104 may include interfaces for communication with one or more other devices or systems within the network (e.g., Figure 5 The base station (BS) 502, AP 550, millimeter-wave (mmW) base station (BS) 580 communicates with and / or detects signals from one or more other devices or systems and / or directly communicates with other wireless devices within the network (e.g., Figure 5 Suitable equipment, circuitry, hardware, and / or software for communication with UE 552. In some embodiments, the WAN transceiver 104 may include a CDMA communication system suitable for communicating with a CDMA network of a wireless base station. In some embodiments, the wireless communication system may include other types of cellular telephone networks, such as, for example, TDMA, GSM, WCDMA, LTE, NR, etc. Additionally, any other type of wireless networking technology may be used, including, for example, WiMax (802.16), Wi-Fi (802.11), etc.

[0024] Processor (also referred to as controller) 110 can be connected to local area network transceiver 106 and wide area network transceiver 104. Processor 110 may include one or more microprocessors, microcontrollers, and / or digital signal processors that provide processing functions as well as other computing and control functions. Processor 110 may be coupled to storage medium (e.g., memory) 114 for storing data and software instructions for executing programmed functions within a mobile device. Memory 114 may be onboard on processor 110 (e.g., within the same IC package), and / or memory may be external memory of the processor and functionally coupled via a data bus.

[0025] In some cases, processor 110 may be coupled to position sensor 160. Position sensor 160 can provide information about the location of wireless device 100. In some cases, position sensor 160 may include a Global Navigation Satellite System (GNSS) receiver or transceiver for determining the location of wireless device 100. In some cases, position sensor 160 may be based, for example, on information from one or more wireless nodes (such as...). Figure 5 The location of wireless device 100 is estimated by using the wireless signals received by BS 502, AP 550, mmW BS 580 (as shown).

[0026] Multiple software engines and data tables can reside in memory 114 and can be utilized by processor 110 for management of remote devices / nodes (such as... Figure 5 The communication between BS 502, AP 550, and mmW BS 580 (shown) performs location determination functionality and / or device control functionality. In some embodiments, memory 114 may include application engine 118 and secure communication engine 126. It should be noted that the functionality of modules and / or data structures can be combined, separated, and / or constructed in different ways depending on the specific implementation of wireless device 100.

[0027] Application engine 118 may include a process running on processor 110 of wireless device 100, which can request data from one of the other modules of wireless device 100. Applications typically run at higher layers of the software architecture and can be implemented in the rich execution environment of wireless device 100, and may include indoor navigation applications, shopping applications, financial services applications, social media applications, location-aware service applications, etc. Applications in application engine 118 can utilize access tokens to request data from remote servers (such as…). Figure 5 The content is obtained from the service provider server 574.

[0028] The secure communication engine 126 may be a process configured to manage the storage and access of access tokens, encryption keys, authentication information, etc. The secure communication engine 126 may execute on a processor component of a trusted execution environment 180 and / or a secure element 190, wherein the wireless device 100 includes such a component. The functionality of the secure communication engine 126 discussed herein may also be implemented as hardware or a combination of hardware and software. The secure communication engine 126 may be implemented as one or more application-specific integrated circuits (ASICs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), or other electronic units or combinations thereof designed to perform the functions described herein.

[0029] The wireless device 100 may also include a user interface 150 that provides a suitable interface system allowing users to interact with the wireless device 100, such as a microphone / speaker 152, a keypad 154, and a display 156. The microphone / speaker 152 provides voice communication services (e.g., using a wide area network transceiver 104 and / or a local area network transceiver 106). The keypad 154 may include suitable buttons for user input. The display 156 may include a suitable display, such as, for example, a backlit LCD display, and may also include a touchscreen display for additional user input modes.

[0030] Processor 110 may also include a Trusted Execution Environment 180. The Trusted Execution Environment 180 may be implemented as a secure area of ​​processor 110 that can be used to process sensitive data and store such sensitive data in an environment isolated from the Rich Execution Environment, where an operating system and / or applications (such as applications of application engine 118) can execute. The Trusted Execution Environment 180 may be configured to execute trusted applications that provide end-to-end security for sensitive data by implementing confidentiality, integrity, and protection on the sensitive data stored therein. The Trusted Execution Environment 180 may be used to store encryption keys, access tokens, and other sensitive data.

[0031] Wireless device 100 may include a secure element 190 (also referred to herein as a trusted component). As a complement to or alternative to the trusted execution environment 180, wireless device 100 may include secure element 190. Secure element 190 may include autonomous and tamper-proof hardware that can be used to execute secure applications and confidential data associated with such applications. Secure element 190 may be used to store encryption keys, access tokens, and other sensitive data. Secure element 190 may include a near-field communication (NFC) tag, a subscriber identity module (SIM) card, or other types of hardware devices that can be used to securely store data. Secure element 190 may be integrated with the hardware of wireless device 100 in a permanent or semi-permanent manner, or in some implementations, may be a movable or external component of wireless device 100 that can be used to securely store data and / or provide a secure execution environment for applications.

[0032] In some cases, to help reduce the attack surface against side-channel attacks, some security applications can execute within a secure processing unit (such as a trusted execution environment 180 and / or a secure element 190) without being aware of other components in their operating environment, such as wide area networks / local area networks, sensors (such as position sensors 160), and / or certain components of the user interface (such as microphones / speakers 152). In some cases, security applications may require certain components (such as keypads 154 and / or displays 156), for example, to provide passwords to encrypt / decrypt data using keys.

[0033] To help harden the processor (such as Secure Element 190, Trusted Execution Environment 180, Processor 110, etc.), independent instructions for execution on the processor can be executed in a random order (e.g., mixed order). By executing independent instructions in a random order, an attacker may be unable to determine what instructions are being executed at a given time, which may make it more difficult for an attacker to correlate data obtained via side channels with what is being executed. It is worth noting that not all instructions can be executed out of order by the processor. Interdependent instructions (e.g., one instruction uses the output written by another instruction) may not be executed out of order. However, instructions that are independent of each other (e.g., independent, so that changing the execution order will not change the result) can be executed out of order. For example, the first instruction that multiplies the contents of register A and register B and outputs them to register C can be independent of the second instruction that adds the contents of register D and register E and outputs them to register F. However, the first instruction that multiplies the contents of register A and register B and outputs them to register C is not independent of the second instruction that adds the contents of register C and register E and outputs them to register F, because the second instruction uses the result of the first instruction. It is worth noting that the term “random” as used in this paper should be interpreted to encompass both true random numbers (e.g., based on physical processes known to have statistical random noise (e.g., entropy)) and pseudo-random numbers.

[0034] Traditionally, shuffling individual instructions into a random order can be implemented in software. However, such implementations can be slow and / or more prone to implementation errors or variations in implementation quality across different software applications. For example, assembly code generated using such shuffling techniques may include multiple jumps in the assembly language, and attackers can use machine learning techniques to identify these jumps. Conversely, having hardware implementations for triggering instruction shuffling—such as dedicated instructions (e.g., instructions specifically designed to trigger instruction shuffling), settings, patterns—can be useful. Such hardware implementations for instruction shuffling are particularly useful in hardware designed to be hardened against attacks, such as Secure Element 190, Trusted Execution Environment 180, etc.

[0035] In some cases, special-purpose instructions (e.g., opcodes, opcodes, instruction codes, assembly instructions, etc.) or tags can be added to the processor to indicate the presence of independent instructions that can be executed in a random order. These special-purpose instructions or tags can be used to trigger an out-of-order execution (e.g., speculative execution) pipeline in the processor. For example, the processor may include a speculative execution pipeline that includes a reordering buffer. In typical use, the processor may execute an instruction branch out of order (e.g., speculatively) and before the non-speculative instructions executed on the main branch. The result of the instruction executed in the speculative branch can then be stored in the reordering buffer along with the instruction. The instruction executed in the main branch can then be compared with the instruction executed in the speculative branch, and if the instructions match, the result of the instruction can be used without re-executing the instruction in the main branch.

[0036] like Figure 2As shown, signals 202 (e.g., indications), such as machine instructions, flags, register settings, etc., can indicate that multiple instructions can be executed out of order. During this window, processor 204 can receive multiple independent instructions to be executed, such as instruction A 206, instruction B 208, and instruction C 210. Processor 204 can randomly reorder the multiple instructions and load them into a reorder buffer 212 (e.g., a memory for storing reordered instructions) in a random order, and then processor 204 can execute 214 the multiple instructions in that random order. For example, the processor can apply a random permutation to the execution order of the multiple instructions (e.g., randomly or pseudo-randomly reorder the multiple instructions), load the multiple instructions into the reorder buffer 212 based on the random permutation of the execution order, and execute the multiple instructions in a manner similar to speculative execution. The results of the executed multiple instructions can be stored in the reorder buffer 212. In some cases, instruction A 206, instruction B 208, and instruction C 210 can also be loaded into the main branch in a random order. Instructions in the main branch can then be matched with multiple instructions in reorder buffer 220, and the results of the execution of multiple instructions from reorder buffer 212 (e.g., output, actual writes to specified registers / memory / caches, etc.) can be used. In some cases, the use of multiple instruction indications can be based on commands in a higher-level programming language that can be compiled into assembly / machine instructions (e.g., machine code, opcodes, etc.).

[0037] Figure 3A This is an example of assembly code 300 according to various aspects of this disclosure, which illustrates a special instruction indicating a plurality of independent instructions that can be executed in a random order. Assembly code 300 includes the special instruction "mix-up" in the first line, which instructs the processor to execute a plurality of instructions following a mix-up instruction in a random order. In this example, the mix-up instruction has a parameter, here 3, which indicates the number of instructions that can be executed in a random order after the mix-up instruction.

[0038] Figure 3B This is an example of assembly code 350 based on various aspects of this disclosure, which executors a special instruction indicating a plurality of independent instructions that can be executed in a random order. Similar to assembly code 300, assembly code 350 also includes the special instruction "mix-up" in the first line. In this example, the mix-up instruction takes a binary parameter (true or false), where true indicates that instructions following the mix-up true instruction (e.g., the start position of a plurality of instructions that can be executed in a random order) can be executed in a random order. The mix-up false instruction can then indicate the end of the plurality of instructions that can be executed in a random order. In other examples, multiple special instructions may be used. For example, a first instruction can indicate that subsequent instructions can be executed in a random order, while a second instruction can indicate the end of the plurality of instructions that can be executed in a random order.

[0039] In some cases, mechanisms other than explicit instructions can be used to provide the processor with indications for independent instructions. For example, indications for independent instructions can be based on set flags, applied pin voltages, bits set in registers, etc. In some cases, the presence of such indications can indicate that the received instruction can be executed independently of the next instruction. The removal of indications for independent instructions can be referenced above. Figure 3B The described approach corresponds to the final independent instruction.

[0040] In some cases, dummy instructions may be included as part of independent instructions. A dummy instruction can be a valid instruction that performs some operation, the result of which may be discarded. In some cases, dummy instructions may be randomly inserted along with independent instructions.

[0041] Figure 4 This is a flowchart of a process 400 for secure processing according to various aspects of this disclosure. Process 400 may be performed by a computing device (or apparatus) or components of that computing device (e.g., chipset, codec, etc.). Figure 1 Processor 110 Figure 1 TEE180 Figure 1 Safety Component 190 Figure 2 Processor 204 Figure 7 The processor (such as 710) is used to execute the operation. Examples of computing devices may include... Figure 1 Wireless devices 100 Figure 5 UE 504, UE 552, and / or UE 590. The computing device can be a mobile device (e.g., a mobile phone), an extended reality (XR) device (such as a virtual reality (VR) device or an augmented reality (AR) device), a vehicle or a component or system of a vehicle, a network-connected wearable device (such as a watch), or other types of computing devices. In another example, it may be a device with… Figure 7 The computing device of the computing system 700 shown executes process 400. The operation of process 400 can be implemented as a software component that executes and runs on one or more processors. In some cases, the computing device may include instructions (such as configuration) that the UE can use to enhance privacy technologies (such as those discussed in various aspects of this disclosure).

[0042] At box 402, the computing device (or a component thereof) may receive a plurality of instructions (e.g., assembly code 300) for execution.

[0043] At box 404, the computing device (or a component thereof) may receive an indication that the plurality of instructions are independent instructions. For example, this indication of independent instructions may be based on a dedicated instruction, a set flag, a voltage applied to a pin, a bit set in a register, etc. In some cases, the indication includes a dedicated instruction. In some cases, the dedicated instruction indicates the number of subsequent instructions (see, for example, assembly code 300) for execution. In some cases, the dedicated instruction includes a parameter indicating that the subsequent instruction is an instruction within the plurality of instructions (see, for example, assembly code 350) for execution. In some cases, the parameter of the dedicated instruction indicates the end of the plurality of instructions (see, for example, assembly code 350) for execution. In some cases, the indication includes at least one of a flag, a register setting, or a voltage on a pin.

[0044] At box 406, the computing device (or a component thereof) may randomly reorder the plurality of instructions. In some cases, the computing device (or a component thereof) may randomly reorder the plurality of instructions by applying a random (or pseudo-random) permutation (e.g., random shuffling) to the execution order of the plurality of instructions. In some cases, the computing device (or a component thereof) may randomly reorder the plurality of instructions by loading the plurality of instructions into a reordering buffer (e.g., reordering buffer 212) based on a random permutation of the execution order.

[0045] At box 408, the computing device (or a component thereof) may execute multiple instructions for the random reordering. In some cases, the computing device (or a component thereof) may execute multiple random reorderings, executing multiple instructions for the random reordering loaded into the reordering buffer.

[0046] At box 410, the computing device (or a component thereof) may output multiple results corresponding to the multiple instructions.

[0047] As described in this article, wireless devices (e.g., Figure 1The wireless device 100 can communicate via one or more wireless networks. The wireless networks are deployed to provide various communication services, such as voice, video, packet data, message sending and receiving, broadcasting, etc. The wireless networks can support two access links for communication between the wireless devices. An access link can refer to any communication link between a client device (e.g., a user equipment (UE), a station (STA), or other client device) and a base station (e.g., a 3GPP gNodeB (gNB) for 5G / NR, a 3GPP eNodeB (eNB) for LTE, a Wi-Fi access point (AP), or other base station) or any communication link between the client device and components of a disaggregated base station (e.g., a central unit, a distributed unit, and / or a radio unit). In one example, the access link between the UE and the 3GPP gNB can be via the Uu interface. In some cases, the access link can support uplink signaling, downlink signaling, connection procedures, etc.

[0048] In some aspects, wireless communication networks can be implemented using one or more modulation schemes. For example, wireless communication networks can be implemented using quadrature amplitude modulation (QAM) schemes such as 16QAM, 32QAM, 64QAM, etc.

[0049] As used herein, the terms “User Equipment” (UE) and “Network Entity” are not intended to be specific to or otherwise limited to any particular Radio Access Technology (RAT) unless otherwise specified. In general, a UE can be any wireless communication device (e.g., mobile phone, router, tablet computer, laptop computer, and / or tracking device, etc.) used by a user to communicate over a wireless communication network, wearable devices (e.g., smartwatches, smart glasses, wearable rings, etc.), XR devices (e.g., VR headsets, AR headsets or glasses, or MR headsets), vehicles (e.g., cars, motorcycles, bicycles, etc.), and / or IoT devices, etc. A UE can be mobile or can (e.g., at certain times) be stationary and can communicate with a Radio Access Network (RAN). As used herein, the term “UE” can be interchangeably referred to as “Access Terminal” or “AT”, “Client Equipment”, “Wireless Equipment”, “Subscriber Equipment”, “Subscriber Terminal”, “Subscriber Station”, “User Terminal” or “UT”, “Mobile Equipment”, “Mobile Terminal”, “Mobile Station”, or variations thereof. Generally speaking, a UE can communicate with the core network via the RAN, and through the core network, the UE can connect to external networks such as the Internet and other UEs. Of course, other mechanisms for connecting to the core network and / or the Internet are also possible for the UE, such as through wired access networks, wireless local area network (WLAN) networks (e.g., based on the IEEE 802.11 communication standard), etc.

[0050] Network entities can be implemented in a converged or monolithic base station architecture, or alternatively, in a decomposed base station architecture, and may include one or more of a central unit (CU), a distributed unit (DU), a radio unit (RU), a near real-time (near RT) RAN intelligent controller (RIC), or a non-real-time (non-RT) RIC. A base station (e.g., with a converged / monolithic or decomposed base station architecture) may operate according to one of several RATs communicating with the UE (depending on the network in which it is deployed), and may alternatively be referred to as an access point (AP), network node, NodeB (NB), evolved NodeB (eNB), next-generation eNB (ng-eNB), new radio (NR) NodeB (also known as gNB or gNodeB), etc. The base station may primarily be used to support the UE's radio access, including supporting data, voice, and / or signaling connections for the supported UE. In some systems, the base station may provide edge node signaling functions, while in others, it may provide additional control and / or network management functions. The communication link through which a UE transmits signals to a base station is called an uplink (UL) channel (e.g., reverse traffic channel, reverse control channel, access channel, etc.). The communication link through which a base station transmits signals to a UE is called a downlink (DL) or forward link channel (e.g., paging channel, control channel, broadcast channel, or forward traffic channel, etc.). As used herein, the term traffic channel (TCH) can refer to uplink, reverse or downlink, and / or forward traffic channel.

[0051] The terms "network entity" or "base station" (e.g., having a converged / monolithic base station architecture or a decomposed base station architecture) can refer to a single physical transmit / receive point (TRP) or multiple physical TRPs that may be co-located or non-co-located. For example, when the term "network entity" or "base station" refers to a single physical TRP, the physical TRP may be a base station antenna corresponding to a cell (or several cell sectors) of the base station. When the term "network entity" or "base station" refers to multiple co-located physical TRPs, these physical TRPs may be an antenna array of the base station (e.g., as in a multiple-input multiple-output (MIMO) system or where the base station employs beamforming). When the term "base station" refers to multiple non-co-located physical TRPs, the physical TRPs may be a distributed antenna system (DAS) (a network of spatially separated antennas connected via a transmission medium to a common source) or a remote radio headend (RRH) (a remote base station connected to a serving base station). Alternatively, a non-co-located physical TRP may be a serving base station receiving measurement reports from a UE and a neighboring base station where the UE is measuring its reference radio frequency (RF) signal (or simply "reference signal"). As used in this article, a TRP is the point by which a base station transmits and receives wireless signals, so any mention of transmitting from or receiving at a base station should be understood as referring to a specific TRP of the base station.

[0052] In some specific implementations supporting UE positioning, network entities or base stations may not support the UE's radio access (e.g., may not support data, voice, and / or signaling connections regarding the UE), but instead may transmit reference signals to the UE for measurement, and / or receive and measure signals transmitted by the UE. Such a base station may be referred to as a positioning beacon (e.g., in the case of transmitting signals to the UE) and / or as a location measurement unit (e.g., in the case of receiving and measuring signals from the UE).

[0053] RF signals comprise electromagnetic waves of a given frequency that transmit information across the space between a transmitter and a receiver. As used herein, a transmitter may send a single “RF signal” or multiple “RF signals” to a receiver. However, due to the propagation characteristics of RF signals through multipath channels, a receiver may receive multiple “RF signals” corresponding to each transmitted RF signal. The same transmitted RF signal on different paths between the transmitter and receiver may be referred to as a “multipath” RF signal. As used herein, where the context clearly indicates that the term “signal” refers to a wireless signal or RF signal, an RF signal may also be referred to as a “wireless signal” or simply a “signal.”

[0054] According to various aspects, Figure 5 Examples are shown of what can be done to wireless devices (e.g., Figure 1Examples of wireless communication systems 500 that provide network access include wireless devices 100. Wireless communication system 500 (also referred to as a wireless wide area network (WWAN)) may include various base stations 502 and various UEs 504. Figure 1 The wireless device 100 is an example of UE 504. In some aspects, base station 502 may also be referred to as a "network entity" or "network node". One or more base stations in base station 502 may be implemented in an aggregated or monolithic base station architecture. Additionally or alternatively, one or more base stations in base station 502 may be implemented in a decomposed base station architecture and may include one or more of a central unit (CU), a distributed unit (DU), a radio unit (RU), a near real-time (near RT) RAN intelligent controller (RIC), or a non-real-time (non-RT) RIC. Base station 502 may include macro cell base stations (high-power cellular base stations) and / or small cell base stations (low-power cellular base stations). In one aspect, macro cell base stations may include eNB and / or ng-eNB (where wireless communication system 500 corresponds to a Long Term Evolution (LTE) network), or gNB (where wireless communication system 500 corresponds to an NR network) or a combination of both, and small cell base stations may include femtocells, picocells, microcells, etc.

[0055] Base station 502 can collectively form a RAN and interface with core network 570 (e.g., evolved packet core (EPC) or 5G core (5GC)) via backhaul link 522, and interface with one or more location servers 572 (which may be part of core network 570 or external to core network 570) via core network 570. UE 504 may be able to access one or more remote servers, such as service provider server 574, via base station 502 and core network 570, and in some cases via other networks such as the Internet. Among other functions, base station 502 may perform functions related to one or more of the following: delivering user data, radio channel encryption and decryption, integrity protection, header compression, mobility control functions (e.g., handover, dual connectivity), inter-cell interference coordination, connection establishment and release, load balancing, distribution of non-access stratum (NAS) messages, NAS node selection, synchronization, RAN sharing, multimedia broadcast multicast service (MBMS), subscriber and equipment tracking, RAN information management (RIM), paging, location, and warning message delivery. Base stations 502 can communicate with each other directly or indirectly (e.g., via EPC or 5GC) via backhaul link 534 (which can be wired and / or wireless).

[0056] Base station 502 can wirelessly communicate with UE 504. Each base station in base station 502 can provide communication coverage for a corresponding geographical coverage area 510. In one aspect, base station 502 in each coverage area 510 can support one or more cells. A “cell” is a logical communication entity used to communicate with a base station (e.g., on a frequency resource, referred to as a carrier frequency, component carrier, carrier, frequency band, etc.) and can be associated with an identifier (e.g., Physical Cell Identifier (PCI), Virtual Cell Identifier (VCI), Cell Global Identifier (CGI)) to distinguish cells operating via the same or different carrier frequencies. In some cases, different cells can be configured according to different protocol types that can provide access for different types of UEs (e.g., Machine Type Communication (MTC), Narrowband IoT (NB-IoT), Enhanced Mobile Broadband (eMBB), or other protocol types). Because a cell is supported by a specific base station, the term “cell” can refer to either or both of the logical communication entity and the base station supporting the logical communication entity, depending on the context. Furthermore, since the TRP is typically the physical transmission point of the cell, the terms “cell” and “TRP” can be used interchangeably. In some cases, the term "cell" may also refer to the geographical coverage area of ​​a base station (e.g., a sector), provided that a carrier frequency can be detected within a portion of the geographical coverage area 510 and that carrier frequency is used for communication within that portion.

[0057] While the geographic coverage areas 510 of adjacent macro cell base stations 502 may partially overlap (e.g., in a handover area), some areas within geographic coverage areas 510 may substantially overlap with larger geographic coverage areas 510. For example, a small cell base station 502' may have a coverage area 510' that substantially overlaps with the coverage areas 510 of one or more macro cell base stations 502. A network that includes both small cell base stations and macro cell base stations may be referred to as a heterogeneous network. A heterogeneous network may also include a home eNB (HeNB) that can provide service to a restricted group referred to as a Closed Subscriber Group (CSG).

[0058] The communication link 520 between base station 502 and UE 504 may include uplink (also known as reverse link) transmission from UE 504 to base station 502 and / or downlink (also known as forward link) transmission from base station 502 to UE 504. The communication link 520 may use MIMO antenna techniques, including spatial multiplexing, beamforming, and / or transmit diversity. The communication link 520 may use one or more carrier frequencies. Carrier allocation may be asymmetric for the downlink and uplink (e.g., more or fewer carriers may be allocated to the downlink compared to the uplink).

[0059] The wireless communication system 500 may also include a WLAN AP 550 communicating with a WLAN station (STA) 552 via a communication link 554 in unlicensed spectrum (e.g., 5 GHz). When communicating in unlicensed spectrum, the WLAN STA 552 and / or WLAN AP 550 may perform a Free Channel Assessment (CCA) or Listen-After-Talk (LBT) process before communication to determine if the channel is available. In some examples, the wireless communication system 500 may include devices (e.g., UEs, etc.) that communicate with one or more UEs 504, base stations 502, APs 550, etc., using ultra-wideband (UWB) spectrum. The UWB spectrum may range from 3.1 GHz to 10.5 GHz.

[0060] Small cell base station 502' can operate in licensed and / or unlicensed spectrum. When operating in unlicensed spectrum, small cell base station 502' can employ LTE or NR technologies and use the same 5 GHz unlicensed spectrum as WLAN AP 550. Small cell base station 502' employing LTE and / or 5G in unlicensed spectrum can improve coverage of the access network and / or increase the capacity of the access network. NR in unlicensed spectrum can be referred to as NR-U. LTE in unlicensed spectrum can be referred to as LTE-U, Licensed Assisted Access (LAA), or MulteFire.

[0061] The wireless communication system 500 may also include a millimeter-wave (mmW) base station 580, which can operate at mmW and / or near-mmW frequencies to communicate with the UE 582. The mmW base station 580 may be implemented in a converged or monolithic base station architecture, or alternatively, in a decomposed base station architecture (e.g., including one or more of a CU, DU, RU, near-RT RIC, or non-RT RIC). Extremely high frequency (EHF) is a portion of the electromagnetic spectrum that contains radio frequency (RF). EHF has a range of 30 GHz to 300 GHz, with wavelengths between 1 mm and 10 mm. Radio waves in this band are referred to as millimeter waves. Near-mmW extends down to frequencies of 3 GHz with wavelengths of 100 mm. Ultra-high frequency (SHF) bands extend between 3 GHz and 30 GHz, and are also referred to as centimeter waves. Communication using mmW and / or near-mmW radio bands has high path loss and relatively short range. mmW base station 580 and UE 582 can utilize beamforming (transmit and / or receive) on mmW communication link 584 to compensate for extremely high path loss and short range. Furthermore, it should be understood that in alternative configurations, one or more base stations 502 may also use mmW or near-mmW and beamforming for transmission. Therefore, it should be understood that the foregoing illustrations are merely examples and should not be construed as limiting the various aspects disclosed herein.

[0062] In some aspects related to 5G, the spectrum operated by wireless network nodes or entities (e.g., base stations 502 / 580, UE 504 / 582) is divided into multiple frequency ranges: FR1 (from 450 MHz to 6000 MHz), FR2 (from 24250 MHz to 52600 MHz), FR3 (above 52600 MHz), and FR4 (between FR1 and FR2). In multi-carrier systems such as 5G, one of the carrier frequencies is referred to as the "primary carrier," "anchor carrier," "primary serving cell," or "PCell," and the remaining carrier frequencies are referred to as "secondary carriers," "secondary serving cells," or "SCell." In carrier aggregation, the anchor carrier is the carrier operating on the primary frequency (e.g., FR1) utilized by UE 504 / 582 and the cell, where UE 504 / 582 performs an initial radio resource control (RRC) connection establishment procedure or initiates an RRC connection re-establishment procedure in that cell. The primary carrier carries all common control channels as well as UE-specific control channels and can be a carrier on a licensed frequency (however, this is not always the case). The secondary carrier is a carrier operating on a second frequency (e.g., FR2) that can be configured and used to provide additional radio resources once an RRC connection is established between the UE 504 and the anchor carrier. In some cases, the secondary carrier can be a carrier on an unlicensed frequency. The secondary carrier may contain only the necessary signaling information and signals; for example, since the primary uplink and primary downlink carriers are typically UE-specific, those UE-specific signaling information and signals may not be present in the secondary carrier. This means that different UEs 504 / 582 in a cell can have different downlink primary carriers. The same applies to the uplink primary carrier. The network can change the primary carrier of any UE 504 / 582 at any time. This is done, for example, to balance the load on different carriers. Because a “serving cell” (whether PCell or SCell) corresponds to the carrier frequency and / or component carriers through which some base stations are communicating, the terms “cell,” “serving cell,” “component carrier,” “carrier frequency,” etc., can be used interchangeably.

[0063] For example, still refer to Figure 5One of the frequencies used by macro cell base station 502 can be an anchor carrier (or "PCell"), and the other frequencies used by macro cell base station 502 and / or mmW base station 580 can be secondary carriers ("SCell"). In carrier aggregation, each carrier of base station 502 and / or UE 504 can use a spectrum with a bandwidth of up to Y MHz (e.g., 5 MHz, 10 MHz, 15 MHz, 20 MHz, 100 MHz), with up to a total of Yx MHz (x component carriers) for transmission in each direction. Component carriers may or may not be adjacent to each other in the spectrum. Carrier allocation may be asymmetric with respect to downlink and uplink (e.g., more or fewer carriers may be allocated to downlink compared to uplink). Simultaneous transmission and / or reception on multiple carriers allows UE 504 / 582 to significantly increase its data transmission rate and / or data reception rate. For example, two aggregated 20 MHz carriers in a multi-carrier system would theoretically result in a doubling of the data rate (i.e., 40 MHz) compared to the data rate obtained by a single 20 MHz carrier.

[0064] To operate on multiple carrier frequencies, base station 502 and / or UE 504 may be equipped with multiple receivers and / or transmitters. For example, UE 504 may have two receivers, namely "Receiver 1" and "Receiver 2", where "Receiver 1" is a multi-band receiver that can be tuned to band "X" or band "Y", and "Receiver 2" is a single-band receiver that can be tuned to band "Z" only. In this example, if UE 504 is being served in band "X", then band "X" will be referred to as PCell or active carrier frequency, and "Receiver 1" will need to tune from band "X" to band "Y" (SCell) to measure band "Y" (and vice versa). In contrast, regardless of whether UE 504 is being served in band "X" or band "Y", since "Receiver 2" is independent, UE 504 can measure band "Z" without interrupting service on band "X" or band "Y".

[0065] The wireless communication system 500 may also include a UE 564, which can communicate with a macro cell base station 502 on a communication link 520 and / or with an mmW base station 580 on an mmW communication link 584. For example, the macro cell base station 502 may support a PCell and one or more SCells for the UE 564, and the mmW base station 580 may support one or more SCells for the UE 564.

[0066] The wireless communication system 500 may also include one or more UEs, such as UE 590, which are indirectly connected to one or more communication networks via one or more device-to-device (D2D) peer-to-peer (P2P) links (referred to as "side links"). Figure 5 In the example, UE 590 has a D2D P2P link 592 with one of UEs 504 in one of the base stations 502 (e.g., UE 590 can indirectly obtain cellular connectivity through this D2D P2P link), and has a D2D P2P link 594 with a WLANSTA 552 connected to WLAN AP 550 (UE 590 can indirectly obtain WLAN-based Internet connectivity through this D2D P2P link). In the example, D2D P2P links 592 and 594 can use any known D2D RAT (such as LTE Direct (LTE-D), Wi-Fi Direct (Wi-Fi-D), Bluetooth). ® (etc.) to support.

[0067] Figure 6 A block diagram of a base station 506 and a UE 504 designed according to some aspects of this disclosure is shown, which enables the transmission and processing of signals exchanged between the UE and the base station. Design 600 includes components of base station 502 and UE 504, which may be... Figure 5 The base station 502 is a base station and the UE 504 is a UE. The base station 502 may be equipped with T antennas 634a to 634t, and the UE 504 may be equipped with R antennas 652a to 652r, wherein typically T≥1 and R≥1.

[0068] At base station 502, transmitting processor 620 can receive data for one or more UEs from data source 612, select one or more modulation and decoding schemes (MCS) for each UE based at least in part on channel quality indicators (CQI) received from the UE, process (e.g., encode and modulate) the data for each UE based at least in part on the MCS selected for the UE, and provide data symbols for all UEs. Transmitting processor 620 can also process system information (e.g., semi-static resource allocation information (SRPI), etc.) and control information (e.g., CQI requests, grants, and / or upper-layer signaling, etc.), and provide overhead symbols and control symbols. Transmitting processor 620 can also generate reference symbols for reference signals (e.g., cell-specific reference signals (CRS)) and synchronization signals (e.g., primary synchronization signal (PSS) and secondary synchronization signal (SSS)). The transmit (TX) multiple-input multiple-output (MIMO) processor 630 can perform spatial processing (e.g., pre-decoding) on ​​data symbols, control symbols, overhead symbols, and / or reference symbols, where applicable, and can provide T output symbol streams to T modulators (MODs) 632a to 632t. The modulators 632a to 632t are shown as combined modulator-demodulator (MOD-DEMOD). In some cases, the modulator and demodulator can be separate components. Each modulator in 632a to 632t can process a corresponding output symbol stream (e.g., for an orthogonal frequency division multiplexing (OFDM) scheme, etc.) to obtain an output sample stream. Each modulator in 632a to 632t can further process (e.g., convert to analog, amplify, filter, and up-convert) the output sample stream to obtain a downlink signal. The T downlink signals can be transmitted from the modulators 632a to 632t via T antennas 634a to 634t, respectively. Based on some aspects described in more detail below, position coding can be used to generate synchronization signals to transmit additional information.

[0069] At UE 504, antennas 652a to 652r can receive downlink signals from base station 502 and / or other base stations and can provide the received signals to demodulators (DEMODs) 654a to 654r respectively. Demodulators 654a to 654r are shown as combined modulator-demodulators (MOD-DEMODs). In some cases, the modulator and demodulator can be separate components. Each demodulator in 654a to 654r can condition (e.g., filter, amplify, down-convert, and digitize) the received signal to obtain an input sample. Each demodulator in 654a to 654r can further process the input sample (e.g., for OFDM, etc.) to obtain the received symbols. MIMO detector 656 can obtain the received symbols from all R demodulators 654a to 654r, perform MIMO detection on these received symbols where applicable, and provide the detected symbols. The receiver processor 658 can process (e.g., demodulate and decode) the detected symbols, provide the decoded data for UE 504 to the data sink 660, and provide the decoded control information and system information to the controller / processor 680. The channel processor can determine the Reference Signal Received Power (RSRP), Received Signal Strength Indicator (RSSI), Reference Signal Received Quality (RSRQ), and / or Channel Quality Indicator (CQI), etc.

[0070] On the uplink, at UE 504, the transmitting processor 664 can receive and process data from data source 662 and control information from controller / processor 680 (e.g., reports including RSRP, RSSI, RSRQ, CQI, etc.). The transmitting processor 664 can also generate reference symbols for one or more reference signals (e.g., based at least in part on β values ​​or sets of β values ​​associated with the one or more reference signals). The symbols from the transmitting processor 664 can be pre-decoded by the TX MIMO processor 666, further processed by modulators 654a to 654r (e.g., for DFT-s-OFDM and / or CP-OFDM, etc.), and transmitted to base station 502. At base station 502, uplink signals from UE 504 and other UEs can be received by antennas 634a to 634t, processed by demodulators 632a to 632t, detected by MIMO detector 636 where applicable, and further processed by receiver processor 638 to obtain decoded data and control information transmitted by UE 504. Receiver processor 638 can provide the decoded data to data sink 639 and the decoded control information to controller (processor) 640. Base station 502 may include communication unit 644 and communicates with network controller 631 via communication unit 644. Network controller 631 may include communication unit 694, controller / processor 690, and memory 692.

[0071] In some respects, one or more components of UE 504 may be included in the housing. These include the controller 640 of base station 502, the controller / processor 680 of UE 504, and / or Figure 6 Any other component may perform one or more techniques associated with the determination of implicit UCI β values ​​for NR.

[0072] Memory 642 and 682 may store data and program code for base station 502 and UE 504, respectively. Scheduler 646 may schedule UE for data transmission on downlink, uplink and / or sidelink.

[0073] In some respects, the deployment of communication systems (such as 5G New Radio (NR) systems) can involve a variety of components or constituent parts. In a 5G NR system or network, network nodes, network entities, network mobility elements, radio access network (RAN) nodes, core network nodes, network elements or network equipment (such as base stations (BS)) or one or more units (or components) performing base station functionality can be implemented in aggregated or decomposed architectures. For example, BSs (such as Node B (NB), evolved NB (eNB), NR BS, 5G NB, access point (AP), transmit / receive point (TRP), or cell, etc.) can be implemented as aggregated base stations (also known as standalone BS or monolithic BS) or decomposed base stations.

[0074] Aggregated base stations can be configured to utilize a radio protocol stack that is physically or logically integrated within a single RAN node. Decentralized base stations can be configured to utilize a protocol stack that is physically or logically distributed across two or more units, such as one or more central or centralized units (CUs), one or more distributed units (DUs), or one or more radio units (RUs). In some respects, the CU may be implemented within a RAN node, and one or more DUs may co-located with the CU, or alternatively, may be geographically or virtually distributed across one or more other RAN nodes. DUs may be implemented to communicate with one or more RUs. Each of the CUs, DUs, and RUs may also be implemented as a virtual unit, namely a virtual central unit (VCU), a virtual distributed unit (VDU), or a virtual radio unit (VRU).

[0075] Base station type operation or network design can take into account the aggregation characteristics of base station functionality. For example, decomposed base stations can be utilized in Integrated Access Backhaul (IAB) networks, Open Radio Access Networks (O-RAN (such as network configurations advocated by the O-RAN Alliance)), or Virtualized Radio Access Networks (vRAN, also known as Cloud Radio Access Networks (C-RAN)). Decomposition can include distributing functionality across two or more units in various physical locations, as well as virtually distributing the functionality of at least one unit, which enables flexibility in network design. Individual units in a decomposed base station or decomposed RAN architecture can be configured to communicate wirelessly with at least one other unit.

[0076] Figure 7 This is a diagram illustrating an example of a system used to implement certain aspects of this technology. Specifically, Figure 7 An example of a computing system 700 is illustrated. This computing system can be any computing device, such as an internal computing system, a remote computing system, a camera, or any component thereof, wherein the components of the system communicate with each other using a connection 705. Connection 705 can be a physical connection using a bus, or a signal connection to a processor 710 (such as in a chipset architecture). Connection 705 can also be a virtual connection, a networking connection, or a logical connection.

[0077] In some embodiments, computing system 700 is a distributed system, wherein the functions described herein may be distributed across a data center, multiple data centers, a peer-to-peer network, etc. In some embodiments, one or more system components described represent a plurality of such components that each perform some or all of the functions described for which the component is used. In some embodiments, the component may be a physical device or a virtual device.

[0078] Example system 700 includes at least one processing unit (CPU or processor) 710 and a connection 705 that communicatively couples various system components, including system memories 715 such as read-only memory (ROM) 720 and random access memory (RAM) 725, to processor 710. Computing system 700 may include a cache 712 of high-speed memory that is directly connected to, close to, or integrated into processor 710.

[0079] Processor 710 may include any general-purpose processor and hardware or software services, such as services 732, 734, and 736 stored in storage device 730, which are configured to control processor 710 and dedicated processors in which software instructions are incorporated into the actual processor design. Processor 710 can essentially be a completely independent computing system containing multiple cores or processors, buses, memory controllers, caches, etc. Multi-core processors can be symmetric or asymmetric.

[0080] To enable user interaction, the computing system 700 includes an input device 745 that can represent any number of input mechanisms, such as a microphone for voice, a touch-sensitive screen for gesture or graphic input, a keyboard, a mouse, motion input, voice input, etc. The computing system 700 may also include an output device 735 that can be one or more of a plurality of output mechanisms. In some cases, a multimodal system allows the user to provide multiple types of input / output to communicate with the computing system 700.

[0081] The computing system 700 may include a communication interface 740, which typically controls and manages user input and system output. The communication interface may perform or facilitate the receiving and / or transmitting of wired or wireless communications using wired and / or wireless transceivers, including utilizing audio jacks / plugs, microphone jacks / plugs, Universal Serial Bus (USB) ports / plugs, Apple... ™ Lightning ™ Ports / plugs, Ethernet ports / plugs, fiber optic ports / plugs, dedicated wired ports / plugs, 3G, 4G, 5G and / or other cellular data network wireless signal transmission, Bluetooth ™ Wireless signal transmission, Bluetooth ™ Low-power (BLE) wireless signal transmission, IBEACON ™Wireless signal transmission, including radio frequency identification (RFID) wireless signal transmission, near field communication (NFC) wireless signal transmission, dedicated short range communication (DSRC) wireless signal transmission, 802.11 Wi-Fi wireless signal transmission, wireless local area network (WLAN) signal transmission, visible light communication (VLC), global microwave access interoperability (WiMAX), infrared (IR) wireless signal transmission, public switched telephone network (PSTN) signal transmission, integrated services digital network (ISDN) signal transmission, ad hoc network signal transmission, radio wave signal transmission, microwave signal transmission, infrared signal transmission, visible light signal transmission, ultraviolet light signal transmission, wireless signal transmission along the electromagnetic spectrum, or some combination thereof. The communication interface 740 may also include one or more Global Navigation Satellite System (GNSS) receivers or transceivers for determining the location of the computing system 700 based on one or more signals received from one or more satellites associated with one or more GNSS systems. GNSS systems include, but are not limited to, the U.S. Global Positioning System (GPS), Russia's Global Navigation Satellite System (GLONASS), China's BeiDou Navigation Satellite System (BDS), and Europe's Galileo GNSS. There are no limitations on operation on any particular hardware configuration, and therefore the underlying features here can be easily replaced to obtain improved hardware or firmware configurations as they are developed.

[0082] Storage device 730 may be one or more non-volatile and / or non-transitory and / or computer-readable storage devices, and may be a hard disk or other type of computer-readable medium capable of storing data accessible by a computer, such as magnetic tape, flash memory cards, solid-state storage devices, digital multifunction disks, cartridges, floppy disks, hard disks, magnetic tapes, magnetic stripes, any other magnetic storage media, flash memory, memristor memory, any other solid-state storage, CD-ROM, rewritable CD, DVD, Blu-ray Disc, holographic disc, another optical medium, secure digital (SD) card, microSD card, Memory Stick. ®Cards, smart card chips, EMV chips, Subscriber Identity Module (SIM) cards, mini / micro / nano / micro SIM cards, another integrated circuit (IC) chip / card, random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash EPROM, cache memory (e.g., layer 1 (L1) cache, layer 2 (L2) cache, layer 3 (L3) cache, layer 4 (L4) cache, layer 5 (L5) cache, or other (L#) cache), resistive random access memory (RRAM / ReRAM), phase change memory (PCM), spin-transfer torque RAM (STT-RAM), another memory chip or card and / or combinations thereof.

[0083] Storage device 730 may include software services, servers, services, etc., which enable the system to perform functions when the code defining such software is executed by processor 710. In some embodiments, hardware services performing specific functions may include software components for performing functions stored in a computer-readable medium connected to necessary hardware components such as processor 710, connection 705, output device 735, etc. The term "computer-readable medium" includes, but is not limited to, portable or non-portable storage devices, optical storage devices, and various other media capable of storing, containing, or carrying instructions and / or data. Computer-readable media may include non-transitory media in which data can be stored and which does not include carrier waves and / or transient electronic signals propagated wirelessly or via a wired connection. Examples of non-transitory media may include, but are not limited to, magnetic disks or magnetic tapes, optical storage media such as compact discs (CDs) or digital versatile discs (DVDs), flash memory, memory, or memory devices. Computer-readable media may store code and / or machine-executable instructions thereon, which may represent procedures, functions, subroutines, programs, routines, subroutines, modules, software packages, classes, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or hardware circuitry by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, forwarded, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0084] Specific details have been provided in the foregoing description to offer a thorough understanding of the various embodiments and examples presented herein, but those skilled in the art will recognize that this application is not limited thereto. Therefore, although exemplary embodiments of this application have been described in detail herein, it is to be understood that the inventive concept can be embodied and adopted in a variety of other ways, and the appended claims are intended to be construed as including such variations, unless limited by prior art. Various features and aspects of the applications described above may be used individually or in combination. Furthermore, without departing from the broader scope of this specification, the embodiments can be used in any number of environments and applications beyond those described herein. Therefore, the specification and drawings should be considered illustrative rather than restrictive. For illustrative purposes, the methods are described in a particular order. It should be understood that in alternative embodiments, the methods may be performed in a different order than described.

[0085] For clarity, in some instances, this technology may be presented as comprising various functional blocks, which include devices, device components, steps, or routines embodied in a method, either in software or a combination of hardware and software. Additional components may be used in addition to those shown in the figures and / or described herein. For example, circuits, systems, networks, processes, and other components may be shown as components in block diagram form to avoid obscuring these embodiments with unnecessary detail. In other cases, well-known circuits, processes, algorithms, structures, and techniques may be shown without necessary detail to avoid obscuring the embodiments.

[0086] Furthermore, those skilled in the art will understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in connection with the aspects disclosed herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, various exemplary components, blocks, modules, circuits, and steps have been described above in general terms of their functionality. Whether such functionality is implemented as hardware or software depends on the specific application and the design constraints imposed on the overall system. Those skilled in the art may implement the described functionality in different ways for each specific application; however, such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0087] Individual implementations may be described above as processes or methods depicted as flowcharts, flow diagrams, data flow diagrams, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation may be executed in parallel or concurrently. Furthermore, the order of operations may be rearranged. A process terminates when its operations are completed, but a process may have additional steps not included in the accompanying drawings. A process may correspond to a method, function, procedure, subroutine, subroutine, etc. When a process corresponds to a function, the termination of the process may correspond to the function returning to the calling function or the main function.

[0088] The processes and methods described in the examples above can be implemented using stored computer-executable instructions or computer-executable instructions otherwise available from a computer-readable medium. Such instructions may include, for example, instructions and data that configure, or otherwise configure, a general-purpose computer, special-purpose computer, or processing device to perform a function or group of functions. The portion may be accessible via a network of the computer resources used. The computer-executable instructions may be, for example, binary, intermediate format instructions such as assembly language, firmware, or source code. Examples of computer-readable media that can be used to store the instructions, the information used, and / or information created during the methods according to the described examples include disks or optical discs, flash memory, USB devices with non-volatile memory, networked storage devices, etc.

[0089] In some implementations, computer-readable storage devices, media, and memories may include cables or wireless signals containing bit streams, etc. However, when referred to, non-transitory computer-readable storage media explicitly exclude media such as energy, carrier signals, electromagnetic waves, and the signals themselves.

[0090] Those skilled in the art will understand that information and signals can be represented using any of a variety of different techniques and arts. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referred to throughout the above description may, in some cases, be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, depending in part on the specific application, in part on the desired design, in part on the corresponding technology, etc.

[0091] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein can be implemented or executed using hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof, and can take any form factor of various form factors. When implemented in software, firmware, middleware, or microcode, program code or code segments (e.g., computer program products) for performing necessary tasks can be stored in a computer-readable or machine-readable medium. A processor can perform the necessary tasks. Examples of form factors include: laptop computers, smartphones, mobile phones, tablet devices, or other small form factor personal computers, personal digital assistants, rack-mounted devices, self-contained devices, etc. The functionality described herein can also be embodied in peripheral devices or interlocking cards. By further example, such functionality can also be implemented on circuit boards in different chips or different processes running on a single device.

[0092] Instructions, media for delivering such instructions, computing resources for executing them, and other structures for supporting such computing resources are example components for providing the functionality described in this disclosure.

[0093] The techniques described herein can also be implemented in electronic hardware, computer software, firmware, or any combination thereof. Such techniques can be implemented in any of a variety of devices, such as general-purpose computers, wireless communication devices (mobile phones), or integrated circuit devices with multiple uses, including applications in wireless communication devices (mobile phones) and other devices. Any feature described as a module or component can be implemented together in an integrated logic device or separately as discrete but interoperable logic devices. If implemented in software, these techniques can be implemented at least in part by a computer-readable data storage medium comprising program code including instructions that, when executed by one or more processors, perform one or more of the methods, algorithms, and / or operations described above. The computer-readable data storage medium can form part of a computer program product, which may include packaging materials. Computer-readable media and / or memory systems may include any memory or data storage medium, such as random access memory (RAM) (such as synchronous dynamic random access memory (SDRAM)), read-only memory (ROM), non-volatile random access memory (NVRAM), electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic or optical data storage media, memory 615, read-only memory (ROM) 620, random access memory (RAM) 625, storage device 630, etc., and computer-readable media may include multiple memory or data storage media. Additionally or alternatively, the technology may be implemented at least in part by a computer-readable communication medium that carries or conveys program code in the form of instructions or data structures that can be accessed, read, and / or executed by a computer, such as propagated signals or waves.

[0094] The program code can be executed by a processor system, which may include one or more processors, such as one or more digital signal processors (DSPs), general-purpose microprocessors, application-specific integrated circuits (ASICs), field-programmable arrays (FPGAs), or other equivalent integrated or discrete logic circuits. Such processor systems can be configured to perform any of the techniques described in this disclosure. A general-purpose processor may be a microprocessor; however, in alternatives, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor system may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration. Therefore, as used herein, the term "processor system" may refer to any of the foregoing structures, any combination of the foregoing structures, or any other structure or means suitable for implementing the techniques described herein.

[0095] Those skilled in the art will understand that, without departing from the scope of this description, the less than (“<”) sign and greater than (“>”) sign or terms used herein may be represented by less than or equal to (“>”) respectively. The sign "") and greater than or equal to (" The symbol ) is used instead.

[0096] When a component is described as being “configured” to perform certain operations, such configuration can be achieved, for example, by designing electronic circuits or other hardware to perform the operations, by programming programmable electronic circuits (e.g., microprocessors or other suitable electronic circuits) to perform the operations, or any combination thereof.

[0097] The phrase “coupled to” or “communicatively coupled to” means that any component is physically connected directly or indirectly to another component, and / or that any component is in communication with another component directly or indirectly (e.g., connected to that other component via a wired or wireless connection and / or other suitable communication interface).

[0098] Claim language or other languages ​​that state "at least one of" and / or "one or more of" in a set indicate that one member of the set or multiple members of the set (in any combination) satisfy the claim. For example, claim language stating "at least one of A and B" or "at least one of A or B" means A, B, or A and B. In another example, claim language stating "at least one of A, B, and C" or "at least one of A, B, or C" means A, B, C, or A and B, or A and C, or B and C, A and B and C, or any repetition is information or data (e.g., A and A, B and B, C and C, A and A and B, etc.), or any other ordering, repetition, or combination of A, B, and C. The language "at least one of" and / or "one or more of" in a set does not limit the set to the items listed in the set. For example, the language of a claim stating "at least one of A and B" or "at least one of A or B" may refer to A, B, or A and B, and may additionally include items not listed in the set of A and B. The phrases "at least one" and "one or more" are used interchangeably herein.

[0099] Claims using phrases such as "at least one processor, the at least one processor being configured to," "at least one processor being configured to," "one or more processors, the one or more processors being configured to," or "one or more processors being configured to," or other languages, indicate that one or more processors (in any combination) are capable of performing associated operations. For example, a claim using the phrase "at least one processor, the at least one processor being configured to: X, Y, and Z" means that a single processor can be used to perform operations X, Y, and Z; or that multiple processors are each assigned a specific subset of tasks to perform operations X, Y, and Z, such that the multiple processors together perform X, Y, and Z; or that a group of multiple processors work together to perform operations X, Y, and Z. In another example, a claim using the phrase "at least one processor, the at least one processor being configured to: X, Y, and Z" could mean that any single processor can perform only at least one subset of operations X, Y, and Z.

[0100] When referring to one or more elements that perform functions (e.g., steps of a method), one element may perform all functions, or more than one element may jointly perform these functions. When more than one element jointly performs these functions, each function does not need to be performed by every single element (e.g., different functions may be performed by different elements), and / or each function does not need to be performed by only one element as a whole (e.g., different elements may perform different sub-functions of a function). Similarly, when referring to one or more elements configured to cause another element (e.g., a device) to perform functions, one element may be configured to cause another element to perform all functions, or more than one element may be jointly configured to cause another element to perform these functions.

[0101] When referring to an entity that performs or is configured to perform functions (e.g., steps of a method) (e.g., any entity or device described herein), the entity may be configured to cause one or more elements (individually or collectively) to perform those functions. One or more components of the entity may include at least one memory, at least one processor, at least one communication interface, another component configured to perform one or more of those functions, and / or any combination thereof. When referring to an entity that performs functions, the entity may be configured to cause one component to perform all functions, or to cause more than one component to perform those functions collectively. When the entity is configured to cause more than one component to perform those functions collectively, each function does not need to be performed by every single component (e.g., different functions may be performed by different components), and / or each function does not need to be performed by only one component as a whole (e.g., different components may perform different sub-functions of a function).

[0102] The exemplary aspects of this disclosure include: Aspect 1. An apparatus for secure processing, the apparatus comprising: a memory including instructions; and a processor coupled to the memory, wherein the processor is configured to: receive a plurality of instructions for execution; receive an indication that the plurality of instructions are independent instructions; randomly reorder the plurality of instructions; execute the randomly reordered plurality of instructions; and output a plurality of results corresponding to the plurality of instructions.

[0103] Aspect 2. The apparatus according to aspect 1, wherein the indication includes a dedicated instruction.

[0104] Aspect 3. The apparatus according to aspect 2, wherein the dedicated instructions indicate the number of subsequent instructions including the plurality of instructions for execution.

[0105] Aspect 4. The apparatus according to any one of Aspects 2 or 3, wherein the dedicated instruction includes a parameter indicating that a subsequent instruction is one of the plurality of instructions for execution.

[0106] Aspect 5. The apparatus according to aspect 4, wherein the parameter of the dedicated instruction indicates the end of the plurality of instructions to be executed.

[0107] Aspect 6. The apparatus according to any one of Aspects 1 to 5, wherein the indication includes at least one of a flag, a register setting, or a voltage on a pin.

[0108] Aspect 7. The apparatus according to any one of Aspects 1 to 6, wherein, in order to randomly reorder the plurality of instructions, the processor is configured to apply a random permutation to the execution order of the plurality of instructions.

[0109] Aspect 8. The apparatus according to aspect 7, the apparatus further comprising a reordering buffer, and wherein, in order to randomly reorder the plurality of instructions, the processor is further configured to load the plurality of instructions into the reordering buffer based on the random permutation of the execution order.

[0110] Aspect 9. The apparatus according to aspect 8, wherein, in order to execute the plurality of instructions for random reordering, the processor is further configured to execute the plurality of instructions for random reordering loaded into the reordering buffer.

[0111] Aspect 10. A method for secure processing, the method comprising: receiving a plurality of instructions for execution; receiving an indication that the plurality of instructions are independent instructions; randomly reordering the plurality of instructions; executing the randomly reordered plurality of instructions; and outputting a plurality of results corresponding to the plurality of instructions.

[0112] Aspect 11. The method according to aspect 10, wherein the instruction includes a dedicated command.

[0113] Aspect 12. The method according to aspect 11, wherein the dedicated instruction indicates the number of subsequent instructions including the plurality of instructions for execution.

[0114] Aspect 13. The method according to any one of Aspects 11 or 12, wherein the special instruction includes a parameter indicating that a subsequent instruction is an instruction among the plurality of instructions for execution.

[0115] Aspect 14. The method according to aspect 13, wherein the parameter of the dedicated instruction indicates the end of the plurality of instructions to be executed.

[0116] Aspect 15. The method according to any one of aspects 10 to 14, wherein the indication includes at least one of a flag, a register setting, or a voltage on a pin.

[0117] Aspect 16. The method according to any one of Aspects 10 to 15, wherein random reordering of the plurality of instructions comprises: applying a random permutation to the execution order of the plurality of instructions.

[0118] Aspect 17. The method according to aspect 16, wherein randomly reordering the plurality of instructions comprises: loading the plurality of instructions into a reordering buffer based on the random permutation of the execution order.

[0119] Aspect 18. The method according to aspect 17, wherein the plurality of instructions for performing random reordering includes: performing the plurality of instructions for random reordering loaded into the reordering buffer.

[0120] Aspect 19. An apparatus for secure processing, the apparatus comprising: means for receiving a plurality of instructions for execution; means for receiving an indication that the plurality of instructions are independent instructions; means for randomly reordering the plurality of instructions; means for executing the randomly reordered plurality of instructions; and means for outputting a plurality of results corresponding to the plurality of instructions.

[0121] Aspect 20. The apparatus according to aspect 19, wherein the indication includes dedicated instructions.

[0122] Aspect 21. The apparatus according to aspect 20, wherein the dedicated instructions indicate the number of subsequent instructions including the plurality of instructions for execution.

[0123] Aspect 22. The apparatus according to any one of Aspects 20 or 21, wherein the dedicated instruction includes a parameter indicating that a subsequent instruction is one of the plurality of instructions for execution.

[0124] Aspect 23. The apparatus according to aspect 22, wherein the parameter of the dedicated instruction indicates the end of the plurality of instructions to be executed.

[0125] Aspect 24. The apparatus according to any one of aspects 19 to 23, wherein the indication includes at least one of a flag, a register setting, or a voltage on a pin.

[0126] Aspect 25. The apparatus according to any one of aspects 19 to 24, wherein randomly reordering the plurality of instructions comprises: applying a random arrangement to the execution order of the plurality of instructions.

[0127] Aspect 26. The apparatus according to aspect 25, wherein random reordering of the plurality of instructions comprises: loading the plurality of instructions into a reordering buffer based on the random permutation of the execution order.

[0128] Aspect 27. The apparatus according to aspect 26, wherein the plurality of instructions for performing random reordering includes: performing the plurality of instructions for random reordering loaded into the reordering buffer.

[0129] Aspect 28. A non-transitory computer-readable medium having instructions stored thereon, which, when executed by one or more processors, cause the one or more processors to perform any one of aspects 10 to 18.

Claims

1. An apparatus for secure handling, the apparatus comprising: Memory, the memory including instructions; and A processor, coupled to the memory, wherein the processor is configured to: Receives multiple instructions for execution; Receiving the multiple instructions is an indication that they are independent instructions; Randomly reorder the multiple instructions; Execute the plurality of instructions for random reordering; as well as Output multiple results corresponding to the multiple instructions.

2. The apparatus of claim 1, wherein the instruction includes a dedicated command.

3. The apparatus of claim 2, wherein the dedicated instruction indicates the number of subsequent instructions including the plurality of instructions for execution.

4. The apparatus of claim 2, wherein the dedicated instruction includes a parameter indicating that a subsequent instruction is one of the plurality of instructions for execution.

5. The apparatus of claim 4, wherein the parameter of the dedicated instruction indicates the end of the plurality of instructions to be executed.

6. The apparatus of claim 1, wherein the indication includes at least one of a flag, a register setting, or a voltage on a pin.

7. The apparatus according to claim 1, wherein, In order to randomly reorder the plurality of instructions, the processor is configured to apply a random arrangement to the execution order of the plurality of instructions.

8. The apparatus of claim 7, further comprising a reordering buffer, wherein, In order to randomly reorder the plurality of instructions, the processor is further configured to load the plurality of instructions into the reordering buffer based on the random permutation of the execution order.

9. The apparatus according to claim 8, wherein, In order to execute the plurality of instructions for random reordering, the processor is further configured to execute the plurality of instructions for random reordering loaded into the reordering buffer.

10. A method for secure processing, the method comprising: Receives multiple instructions for execution; Receiving the multiple instructions is an indication that they are independent instructions; Randomly reorder the multiple instructions; Execute the plurality of instructions for random reordering; as well as Output multiple results corresponding to the multiple instructions.

11. The method of claim 10, wherein the instruction includes a dedicated command.

12. The method of claim 11, wherein the dedicated instruction indicates the number of subsequent instructions including the plurality of instructions for execution.

13. The method of claim 11, wherein the special instruction includes a parameter indicating that a subsequent instruction is one of the plurality of instructions for execution.

14. The method of claim 13, wherein the parameter of the special instruction indicates the end of the plurality of instructions to be executed.

15. The method of claim 10, wherein the indication includes at least one of a flag, a register setting, or a voltage on a pin.

16. The method of claim 10, wherein randomly reordering the plurality of instructions comprises: The execution order of the multiple instructions is randomly arranged.

17. The method of claim 16, wherein randomly reordering the plurality of instructions comprises: The plurality of instructions are loaded into the reordering buffer based on the random arrangement of the execution order.

18. The method of claim 17, wherein the plurality of instructions for performing random reordering comprises: Execute the plurality of instructions for random reordering loaded into the reordering buffer.

19. An apparatus for secure handling, the apparatus comprising: A component for receiving multiple instructions for execution; A component for receiving indications that the plurality of instructions are independent instructions; A component for randomly reordering the plurality of instructions; A component for executing the plurality of instructions for random reordering; and A component for outputting multiple results corresponding to the multiple instructions.

20. The apparatus of claim 19, wherein the instruction includes a dedicated command.

21. The apparatus of claim 20, wherein the dedicated instructions indicate the number of subsequent instructions including the plurality of instructions for execution.

22. The apparatus of claim 20, wherein the dedicated instruction includes a parameter indicating that a subsequent instruction is one of the plurality of instructions for execution.

23. The apparatus of claim 22, wherein the parameter of the dedicated instruction indicates the end of the plurality of instructions to be executed.

24. The apparatus of claim 19, wherein the indication includes at least one of a flag, a register setting, or a voltage on a pin.

25. The apparatus of claim 19, wherein randomly reordering the plurality of instructions comprises: The execution order of the multiple instructions is randomly arranged.

26. The apparatus of claim 25, wherein randomly reordering the plurality of instructions comprises: The plurality of instructions are loaded into the reordering buffer based on the random arrangement of the execution order.

27. The apparatus of claim 26, wherein the plurality of instructions for performing random reordering comprises: Execute the plurality of instructions for random reordering loaded into the reordering buffer.

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