Pixel circuit and display device

Abstract

The invention provides a pixel circuit and a display device. The pixel circuit comprises a light-emitting circuit, a light-emitting control circuit (11), a first control circuit (12) and a switch control circuit, the light-emitting control circuit (11) controls communication between a control voltage input end (11) and the light-emitting circuit under the control of a light-emitting control signal, and the light-emitting circuit emits light according to control voltage provided by the control voltage input end (11). The first control circuit (12) controls a switch control signal according to a data voltage under the control of a scanning signal, the switch control circuit comprises N switch control ends, N light-emitting control voltage ends and N switch control sub-circuits, and the nth switch control sub-circuit controls the N light-emitting control voltage ends according to the data voltage under the control of the nth switch control signal. The nth light-emitting control voltage end is controlled to be communicated with the control voltage input end (11), N is an integer larger than 1, and n is a positive integer smaller than or equal to N. High PPI can be achieved, and low-gray-scale display uniformity is improved.

Description

Pixel circuit and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit and a display device. Background Art

[0002] Micro LEDs (micro light-emitting diodes) and Mini LEDs (sub-millimeter light-emitting diodes) have great potential in the display field due to their high brightness, long lifespan, and compact size. In related technologies, sub-millimeter LEDs are approximately 100μm to 300μm in size, while micro LEDs are less than 100μm in size.

[0003] Currently, Micro LED display panels and Mini LED display panels cannot achieve high PPI (Pixels Per Inch, pixel density) display, and the low grayscale display uniformity is poor.

[0004] Summary of the Invention

[0005] In one aspect, an embodiment of the present disclosure provides a pixel circuit, comprising a light emitting circuit, a light emitting control circuit, a first control circuit, and a switch control circuit;

[0006] The light-emitting control circuit is electrically connected to the light-emitting control terminal, the control voltage input terminal and the light-emitting circuit respectively, and is used to control the connection between the control voltage input terminal and the light-emitting circuit under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0007] The light emitting circuit is used to emit light according to the control voltage provided by the control voltage input terminal;

[0008] The first control circuit is electrically connected to at least two data voltage terminals, at least two scan terminals, and N switch control terminals, respectively, and is configured to control the switch control signals provided to the switch control terminals according to the data voltages provided by the data voltage terminals under the control of the scan signals provided by the scan terminals; N is an integer greater than 1;

[0009] The switch control circuit includes N switch control terminals, N light-emitting control voltage terminals and N switch control sub-circuits; n is a positive integer less than or equal to N;

[0010] The nth switch control subcircuit is electrically connected to the nth switch control terminal, the nth light-emitting control voltage terminal and the control voltage input terminal respectively, and is used to control the connection between the nth light-emitting control voltage terminal and the control voltage input terminal under the control of the nth switch control signal provided by the nth switch control terminal.

[0011] Optionally, the light-emitting control voltage provided by the light-emitting control voltage terminal is a DC voltage, and the light-emitting control voltages provided by the N light-emitting control voltage terminals are different from each other.

[0012] Optionally, the light-emitting control voltage provided by the light-emitting control voltage terminal is a square wave voltage signal, and the duty cycles of the light-emitting control voltages provided by the N light-emitting control voltage terminals are different from each other.

[0013] Optional, N equals 2 a , a is a positive integer.

[0014] Optionally, the first control circuit includes a first data writing circuit, a second data writing circuit and a first control sub-circuit;

[0015] The first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the first data access terminal respectively, and is used to write the first data voltage provided by the first data voltage terminal into the first data access terminal under the control of the first scanning signal provided by the first scanning terminal;

[0016] The second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the second data access terminal respectively, and is used to write the second data voltage provided by the second data voltage terminal into the second data access terminal under the control of the second scanning signal provided by the second scanning terminal;

[0017] The first control subcircuit is electrically connected to the first data access terminal, the second data access terminal and N switch control terminals, respectively, and is used to control the provision of corresponding switch control signals to the N switch control terminals according to the potential of the first data access terminal and the potential of the second data access terminal.

[0018] Optionally, the first control subcircuit includes a first latch, a second latch, a third latch, a fourth latch, a first control switch, and a second control switch; N is equal to 4;

[0019] The input end of the first latch is electrically connected to the first data access end, and the output end of the first latch is electrically connected to the control end of the first control switch. The first latch is used to latch the voltage signal input by the first data access end and output a first output voltage. The first output voltage is in opposite phase to the voltage signal input by the first data access end.

[0020] The input end of the second latch is electrically connected to the second data access end, and the output end of the second latch is electrically connected to the control end of the second control switch. The second latch is used to latch the voltage signal input by the second data access end and output a second output voltage. The second output voltage is inversely proportional to the voltage signal input by the second data access end.

[0021] The input end of the third latch is electrically connected to the first end of the first control switch, and the output end of the third latch is electrically connected to the first switch control end. The third latch is used to latch the voltage signal input to the input end and output a third output voltage. The third output voltage is inversely proportional to the voltage signal input to the input end of the third latch.

[0022] The input end of the fourth latch is electrically connected to the first end of the second control switch, and the output end of the fourth latch is electrically connected to the third switch control end. The fourth latch is used to latch the voltage signal input to the input end and output a fourth output voltage. The fourth output voltage is inversely proportional to the voltage signal input to the input end of the fourth latch.

[0023] The control end of the first control switch is electrically connected to the output end of the first latch, and the second end of the first control switch is electrically connected to the output end of the second latch, and the first control switch is used to control the connection or disconnection between the first end of the first control switch and the second end of the first control switch under the control of the potential of the control end;

[0024] The control end of the second control switch is electrically connected to the input end of the first latch, and the second end of the second control switch is electrically connected to the input end of the second latch. The second control switch is used to control the connection or disconnection between the first end of the second control switch and the second end of the second control switch under the control of the potential of the control end;

[0025] The first switch control terminal is electrically connected to the output terminal of the third latch, and the second switch control terminal is electrically connected to the input terminal of the third latch;

[0026] The third switch control terminal is electrically connected to the output terminal of the fourth latch, and the fourth switch control terminal is electrically connected to the input terminal of the fourth latch.

[0027] Optionally, the first latch includes a first inverter and a second inverter;

[0028] An input terminal of the first inverter is electrically connected to an input terminal of the first latch, and an output terminal of the first inverter is electrically connected to an output terminal of the first latch;

[0029] The input end of the second inverter is electrically connected to the output end of the first inverter, and the output end of the second inverter is electrically connected to the input end of the first inverter;

[0030] The second latch includes a third inverter and a fourth inverter;

[0031] The input end of the third inverter is electrically connected to the input end of the second latch, and the output end of the third inverter is electrically connected to the output end of the second latch;

[0032] The input end of the fourth inverter is electrically connected to the output end of the third inverter, and the output end of the fourth inverter is electrically connected to the input end of the third inverter;

[0033] The third latch includes a fifth inverter and a sixth inverter;

[0034] The input end of the fifth inverter is electrically connected to the input end of the third latch, and the output end of the fifth inverter is electrically connected to the output end of the third latch;

[0035] The input end of the sixth inverter is electrically connected to the output end of the fifth inverter, and the output end of the sixth inverter is electrically connected to the input end of the fifth inverter;

[0036] The fourth latch includes a seventh inverter and an eighth inverter;

[0037] The input end of the seventh inverter is electrically connected to the input end of the fourth latch, and the output end of the seventh inverter is electrically connected to the output end of the fourth latch;

[0038] The input end of the eighth inverter is electrically connected to the output end of the seventh inverter, and the output end of the eighth inverter is electrically connected to the input end of the seventh inverter.

[0039] Optionally, the first control switch is a first control transistor, and the second control switch is a second control transistor;

[0040] The control electrode of the first control transistor is electrically connected to the output terminal of the first latch, the first electrode of the first control transistor is electrically connected to the input terminal of the third latch, and the second electrode of the first control transistor is electrically connected to the output terminal of the second latch;

[0041] The control electrode of the second control transistor is electrically connected to the input end of the first latch, the first electrode of the second control transistor is electrically connected to the input end of the fourth latch, and the second electrode of the second control transistor is electrically connected to the input end of the second latch.

[0042] Optionally, the first data writing circuit includes a first writing transistor, and the second data writing circuit includes a second writing transistor;

[0043] The control electrode of the first write transistor is electrically connected to the first scan terminal, the first electrode of the first write transistor is electrically connected to the first data voltage terminal, and the second electrode of the first write transistor is electrically connected to the first data access terminal;

[0044] The control electrode of the second write transistor is electrically connected to the second scan end, the first electrode of the second write transistor is electrically connected to the second data voltage end, and the second electrode of the second write transistor is electrically connected to the second data access end.

[0045] Optionally, the first control circuit includes a first data writing circuit, a second data writing circuit, a third data writing circuit, a fourth data writing circuit and a second control sub-circuit;

[0046] The first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the first data access terminal respectively, and is used to write the first data voltage provided by the first data voltage terminal into the first data access terminal under the control of the first scanning signal provided by the first scanning terminal;

[0047] The second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the second data access terminal respectively, and is used to write the second data voltage provided by the second data voltage terminal into the second data access terminal under the control of the second scanning signal provided by the second scanning terminal;

[0048] The third data writing circuit is electrically connected to the third scanning terminal, the third data voltage terminal and the third data access terminal respectively, and is used to write the third data voltage provided by the third data voltage terminal into the third data access terminal under the control of the third scanning signal provided by the third scanning terminal;

[0049] The fourth data writing circuit is electrically connected to the fourth scanning terminal, the fourth data voltage terminal and the fourth data access terminal respectively, and is used to write the fourth data voltage provided by the fourth data voltage terminal into the fourth data access terminal under the control of the fourth scanning signal provided by the fourth scanning terminal;

[0050] The second control subcircuit is electrically connected to the first data access terminal, the second data access terminal, the third data access terminal, the fourth data access terminal, and N switch control terminals, respectively, and is configured to control the provision of corresponding switch control signals to the N switch control terminals, respectively, based on the potential of the first data access terminal, the potential of the second data access terminal, the potential of the third data access terminal, and the potential of the fourth data access terminal.

[0051] Optionally, the second control subcircuit includes a first latch, a second latch, a third latch, a fourth latch, a fifth latch, a sixth latch, a seventh latch, an eighth latch, a ninth latch, a tenth latch, a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, and a sixth control switch; N is equal to 8;

[0052] The input end of the first latch is electrically connected to the first data access end, and the output end of the first latch is electrically connected to the control end of the first control switch. The first latch is used to latch the voltage signal input by the first data access end and output a first output voltage. The first output voltage is in opposite phase to the voltage signal input by the first data access end.

[0053] The input end of the second latch is electrically connected to the second data access end, and the output end of the second latch is electrically connected to the control end of the second control switch. The second latch is used to latch the voltage signal input by the second data access end and output a second output voltage. The second output voltage is inversely proportional to the voltage signal input by the second data access end.

[0054] The input end of the third latch is electrically connected to the first end of the first control switch, and the output end of the third latch is electrically connected to the control end of the third control switch. The third latch is used to latch the voltage signal input to the input end and output a third output voltage, and the third output voltage is inversely proportional to the voltage signal input to the input end of the third latch;

[0055] The input end of the fourth latch is electrically connected to the first end of the second control switch, and the output end of the fourth latch is electrically connected to the control end of the fifth control switch. The fourth latch is used to latch the voltage signal input to the input end and output a fourth output voltage, and the fourth output voltage is inversely proportional to the voltage signal input to the input end of the fourth latch.

[0056] The input end of the fifth latch is electrically connected to the first end of the third control switch, and the output end of the fifth latch is electrically connected to the second switch control end. The fifth latch is used to latch the voltage signal input to the input end and output a fifth output voltage. The fifth output voltage is inversely proportional to the voltage signal input to the input end of the fifth latch.

[0057] The input end of the sixth latch is electrically connected to the third data access end, and the output end of the sixth latch is electrically connected to the second end of the third control switch. The sixth latch is used to latch the voltage signal input to the input end and output a sixth output voltage, and the sixth output voltage is inversely proportional to the voltage signal input to the input end of the sixth latch.

[0058] The input end of the seventh latch is electrically connected to the first end of the fourth control switch, and the output end of the seventh latch is electrically connected to the fourth switch control end. The seventh latch is used to latch the voltage signal input to the input end and output a seventh output voltage. The seventh output voltage is inversely proportional to the voltage signal input to the input end of the seventh latch.

[0059] The input end of the eighth latch is electrically connected to the first end of the fifth control switch, and the output end of the eighth latch is electrically connected to the sixth switch control end. The eighth latch is used to latch the voltage signal input to the input end and output an eighth output voltage. The eighth output voltage is inversely proportional to the voltage signal input to the input end of the eighth latch.

[0060] The input end of the ninth latch is electrically connected to the fourth data access end, and the output end of the ninth latch is electrically connected to the second end of the fifth control switch. The ninth latch is used to latch the voltage signal input to the input end and output a ninth output voltage, and the ninth output voltage is inversely proportional to the voltage signal input to the input end of the ninth latch.

[0061] The input terminal of the tenth latch is electrically connected to the first terminal of the sixth control switch, and the output terminal of the tenth latch is electrically connected to the eighth switch control terminal. The tenth latch is used to latch the voltage signal input to the input terminal and output a tenth output voltage, and the tenth output voltage is inversely proportional to the voltage signal input to the input terminal of the tenth latch.

[0062] The control end of the first control switch is electrically connected to the output end of the first latch, and the second end of the first control switch is electrically connected to the output end of the second latch, and the first control switch is used to control the connection or disconnection between the first end of the first control switch and the second end of the first control switch under the control of the potential of the control end;

[0063] The control end of the second control switch is electrically connected to the input end of the first latch, and the second end of the second control switch is electrically connected to the input end of the second latch. The second control switch is used to control the connection or disconnection between the first end of the second control switch and the second end of the second control switch under the control of the potential of the control end;

[0064] The control end of the third control switch is electrically connected to the output end of the third latch, and the third control switch is used to control the connection or disconnection between the input end of the fifth latch and the output end of the sixth latch under the control of the potential of the control end;

[0065] The control end of the fourth control switch is electrically connected to the input end of the third latch, and the fourth control switch is used to control the connection or disconnection between the input end of the seventh latch and the input end of the sixth latch under the control of the potential of the control end;

[0066] The control end of the fifth control switch is electrically connected to the output end of the fourth latch, and the fifth control switch is used to control the input end of the eighth latch to be electrically connected to the output end of the ninth latch under the control of the potential of the control end;

[0067] The control end of the sixth control switch is electrically connected to the input end of the fourth latch, and the sixth control switch is used to control the connection between the input end of the tenth latch and the input end of the ninth latch under the control of the potential of the control end;

[0068] The first switch control terminal is electrically connected to the input terminal of the fifth latch, and the seventh switch control terminal is electrically connected to the input terminal of the tenth latch.

[0069] Optionally, the first latch includes a first inverter and a second inverter;

[0070] An input terminal of the first inverter is electrically connected to an input terminal of the first latch, and an output terminal of the first inverter is electrically connected to an output terminal of the first latch;

[0071] The input end of the second inverter is electrically connected to the output end of the first inverter, and the output end of the second inverter is electrically connected to the input end of the first inverter;

[0072] The second latch includes a third inverter and a fourth inverter;

[0073] The input end of the third inverter is electrically connected to the input end of the second latch, and the output end of the third inverter is electrically connected to the output end of the second latch;

[0074] The input end of the fourth inverter is electrically connected to the output end of the third inverter, and the output end of the fourth inverter is electrically connected to the input end of the third inverter;

[0075] The third latch includes a fifth inverter and a sixth inverter;

[0076] The input end of the fifth inverter is electrically connected to the input end of the third latch, and the output end of the fifth inverter is electrically connected to the output end of the third latch;

[0077] The input end of the sixth inverter is electrically connected to the output end of the fifth inverter, and the output end of the sixth inverter is electrically connected to the input end of the fifth inverter;

[0078] The fourth latch includes a seventh inverter and an eighth inverter;

[0079] The input end of the seventh inverter is electrically connected to the input end of the fourth latch, and the output end of the seventh inverter is electrically connected to the output end of the fourth latch;

[0080] The input end of the eighth inverter is electrically connected to the output end of the seventh inverter, and the output end of the eighth inverter is electrically connected to the input end of the seventh inverter;

[0081] The fifth latch includes a ninth inverter and a tenth inverter;

[0082] The input end of the ninth inverter is electrically connected to the input end of the fifth latch, and the output end of the ninth inverter is electrically connected to the output end of the fifth latch;

[0083] The input end of the tenth inverter is electrically connected to the output end of the ninth inverter, and the output end of the tenth inverter is electrically connected to the input end of the ninth inverter;

[0084] The sixth latch includes an eleventh inverter and a twelfth inverter;

[0085] The input end of the eleventh inverter is electrically connected to the input end of the sixth latch, and the output end of the eleventh inverter is electrically connected to the output end of the sixth latch;

[0086] The input end of the twelfth inverter is electrically connected to the output end of the eleventh inverter, and the output end of the twelfth inverter is electrically connected to the input end of the eleventh inverter;

[0087] The seventh latch includes a thirteenth inverter and a fourteenth inverter;

[0088] The input end of the thirteenth inverter is electrically connected to the input end of the seventh latch, and the output end of the thirteenth inverter is electrically connected to the output end of the seventh latch;

[0089] The input end of the fourteenth inverter is electrically connected to the output end of the thirteenth inverter, and the output end of the fourteenth inverter is electrically connected to the input end of the thirteenth inverter;

[0090] The eighth latch includes a fifteenth inverter and a sixteenth inverter;

[0091] The input end of the fifteenth inverter is electrically connected to the input end of the eighth latch, and the output end of the fifteenth inverter is electrically connected to the output end of the eighth latch;

[0092] The input end of the sixteenth inverter is electrically connected to the output end of the fifteenth inverter, and the output end of the sixteenth inverter is electrically connected to the input end of the fifteenth inverter;

[0093] The ninth latch includes a seventeenth inverter and an eighteenth inverter;

[0094] The input end of the seventeenth inverter is electrically connected to the input end of the ninth latch, and the output end of the seventeenth inverter is electrically connected to the output end of the ninth latch;

[0095] The input end of the eighteenth inverter is electrically connected to the output end of the seventeenth inverter, and the output end of the eighteenth inverter is electrically connected to the input end of the seventeenth inverter;

[0096] The tenth latch includes a nineteenth inverter and a twentieth inverter;

[0097] The input end of the nineteenth inverter is electrically connected to the input end of the tenth latch, and the output end of the nineteenth inverter is electrically connected to the output end of the tenth latch;

[0098] The input terminal of the 20th inverter is electrically connected to the output terminal of the 19th inverter, and the output terminal of the 20th inverter is electrically connected to the input terminal of the 19th inverter.

[0099] Optionally, the first control switch is a first control transistor, the second control switch is a second control transistor; the third control switch is a third control transistor, the fourth control switch is a fourth control transistor; the fifth control switch is a fifth control transistor, and the sixth control switch is a sixth control transistor;

[0100] The control electrode of the first control transistor is electrically connected to the output terminal of the first latch, the first electrode of the first control transistor is electrically connected to the input terminal of the third latch, and the second electrode of the first control transistor is electrically connected to the output terminal of the second latch;

[0101] The control electrode of the second control transistor is electrically connected to the input terminal of the first latch, the first electrode of the second control transistor is electrically connected to the input terminal of the fourth latch, and the second electrode of the second control transistor is electrically connected to the input terminal of the second latch;

[0102] The control electrode of the third control transistor is electrically connected to the output terminal of the third latch, the first electrode of the third control transistor is electrically connected to the input terminal of the fifth latch, and the second electrode of the third control transistor is electrically connected to the output terminal of the sixth latch;

[0103] The control electrode of the fourth control transistor is electrically connected to the input terminal of the third latch, the first electrode of the fourth control transistor is electrically connected to the input terminal of the seventh latch, and the second electrode of the fourth control transistor is electrically connected to the input terminal of the sixth latch;

[0104] The control electrode of the fifth control transistor is electrically connected to the output terminal of the fourth latch, the first electrode of the fifth control transistor is electrically connected to the input terminal of the eighth latch, and the second electrode of the fifth control transistor is electrically connected to the output terminal of the ninth latch;

[0105] The control electrode of the sixth control transistor is electrically connected to the input end of the fourth latch, the first electrode of the sixth control transistor is electrically connected to the input end of the tenth latch, and the second electrode of the sixth control transistor is electrically connected to the input end of the ninth latch.

[0106] Optionally, the first data writing circuit includes a first writing transistor, the second data writing circuit includes a second writing transistor, the third data writing circuit includes a third writing transistor, and the fourth data writing circuit includes a fourth writing transistor;

[0107] The control electrode of the first write transistor is electrically connected to the first scan terminal, the first electrode of the first write transistor is electrically connected to the first data voltage terminal, and the second electrode of the first write transistor is electrically connected to the first data access terminal;

[0108] The control electrode of the second write transistor is electrically connected to the second scan terminal, the first electrode of the second write transistor is electrically connected to the second data voltage terminal, and the second electrode of the second write transistor is electrically connected to the second data access terminal;

[0109] The control electrode of the third write transistor is electrically connected to the third scan terminal, the first electrode of the third write transistor is electrically connected to the third data voltage terminal, and the second electrode of the third write transistor is electrically connected to the third data access terminal;

[0110] The control electrode of the fourth write transistor is electrically connected to the fourth scan end, the first electrode of the fourth write transistor is electrically connected to the fourth data voltage end, and the second electrode of the fourth write transistor is electrically connected to the fourth data access end.

[0111] Optionally, the light emitting circuit includes a light emitting element;

[0112] The light emitting control circuit is electrically connected to the first electrode of the light emitting element, and is used to control the connection between the control voltage input terminal and the first electrode of the light emitting element under the control of the light emitting control signal;

[0113] The second electrode of the light emitting element is electrically connected to the first voltage end.

[0114] Optionally, the light emitting circuit includes an amplitude control subcircuit, a driving subcircuit, a first on / off control subcircuit, and a light emitting element; the first terminal of the driving subcircuit is electrically connected to the second voltage terminal;

[0115] The amplitude control subcircuit is used to control the driving current generated by the driving subcircuit according to the display data voltage;

[0116] The light emitting control circuit is used to control the connection between the control voltage input terminal and the control terminal of the first on-off control subcircuit under the control of the light emitting control signal;

[0117] The control end of the first on-off control subcircuit is electrically connected to the light-emitting control circuit, the first end of the first on-off control subcircuit is electrically connected to the second end of the driving subcircuit, and the second end of the first on-off control subcircuit is electrically connected to the light-emitting element; the first on-off control subcircuit is used to control the connection between the driving subcircuit and the light-emitting element under the control of the potential of its control end.

[0118] Optionally, the amplitude control subcircuit includes a data writing subcircuit, an energy storage subcircuit and a reset subcircuit;

[0119] The data writing sub-circuit is electrically connected to the first scan line, the data line and the control terminal of the driving sub-circuit respectively, and is used to write the data voltage provided by the data line into the control terminal of the driving sub-circuit under the control of the first scan signal provided by the first scan line;

[0120] The reset sub-circuit is electrically connected to the first scan line, the reset voltage terminal and the second terminal of the driving sub-circuit respectively, and is used to control the reset voltage provided by the reset voltage terminal to be written into the second terminal of the driving sub-circuit under the control of the first scan signal;

[0121] The energy storage subcircuit is electrically connected to the control terminal of the driving subcircuit and the second terminal of the driving subcircuit respectively, and is used for storing electrical energy;

[0122] The driving sub-circuit is used to generate a driving current under the control of the potential of its control terminal.

[0123] Optionally, the amplitude control subcircuit includes a data writing subcircuit and an energy storage subcircuit;

[0124] The data writing sub-circuit is electrically connected to the scan line, the data line and the control terminal of the driving sub-circuit respectively, and the data writing sub-circuit is used to write the voltage of the data provided by the data line into the control terminal of the driving sub-circuit under the control of the scan signal provided by the scan line;

[0125] The energy storage subcircuit is electrically connected to the control terminal and the first common electrode terminal of the driving subcircuit respectively, and is used for storing electric energy;

[0126] The driving sub-circuit is used to generate a driving current under the control of the potential of its control terminal.

[0127] Optionally, the scan line includes a second scan line and a third scan line;

[0128] The data writing sub-circuit includes a first data writing transistor and a second data writing transistor;

[0129] The control electrode of the first data writing transistor is electrically connected to the second scan line, the first electrode of the first data writing transistor is electrically connected to the data line, and the second electrode of the first data writing transistor is electrically connected to the control terminal of the driving sub-circuit;

[0130] The control electrode of the second data writing transistor is electrically connected to the third scan line, the first electrode of the second data writing transistor is electrically connected to the data line, and the second electrode of the second data writing transistor is electrically connected to the control terminal of the driving sub-circuit;

[0131] The first data writing transistor is an n-type transistor, and the second data writing transistor is a p-type transistor.

[0132] Optionally, the nth switch control subcircuit includes an nth switch control transistor;

[0133] The control electrode of the nth switch control transistor is electrically connected to the nth switch control terminal, the first electrode of the nth switch control transistor is electrically connected to the nth light emitting control voltage terminal, and the second electrode of the nth switch control transistor is electrically connected to the control voltage input terminal.

[0134] Optionally, the light emitting control circuit includes a light emitting control transistor;

[0135] The control electrode of the light emitting control transistor is electrically connected to the light emitting control terminal, the first electrode of the light emitting control transistor is electrically connected to the control voltage input terminal, and the second electrode of the light emitting control transistor is electrically connected to the light emitting circuit.

[0136] Optionally, the light-emitting element included in the light-emitting circuit is a micro light-emitting diode or a sub-millimeter light-emitting diode; the first pole of the light-emitting element is an anode, and the second pole of the light-emitting element is a cathode.

[0137] In a second aspect, embodiments of the present disclosure further provide a display device, comprising a display panel;

[0138] The display area of ​​the display panel has a plurality of sub-pixels, and the above-mentioned pixel circuit is arranged in each sub-pixel.

[0139] Optionally, the display panel includes a silicon substrate;

[0140] The pixel circuit is arranged on the silicon substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0141] FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0142] FIG2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0143] FIG3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0144] FIG4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0145] FIG5 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0146] FIG6 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG5 ;

[0147] FIG7 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0148] FIG8 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0149] FIG9 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0150] FIG10 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG9 ;

[0151] FIG11 is a structural diagram of at least one embodiment of a light emitting circuit;

[0152] FIG12 is a structural diagram of at least one embodiment of the light emitting circuit;

[0153] FIG13 is a structural diagram of at least one embodiment of the light emitting circuit;

[0154] FIG14 is a structural diagram of at least one embodiment of the light emitting circuit;

[0155] FIG15 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0156] FIG16 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0157] FIG17 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0158] FIG18 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0159] FIG19 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0160] FIG20 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0161] FIG21 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0162] FIG. 22 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0163] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0164] The transistors used in all embodiments of the present disclosure may be triodes, thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor other than the control electrode, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0165] In actual operation, when the transistor is a triode, the control electrode may be a base, the first electrode may be a collector, and the second electrode may be an emitter; or, the control electrode may be a base, the first electrode may be an emitter, and the second electrode may be a collector.

[0166] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode can be a gate, the first electrode can be a drain, and the second electrode can be a source; or, the control electrode can be a gate, the first electrode can be a source, and the second electrode can be a drain.

[0167] The pixel circuit according to the embodiment of the present disclosure includes a light emitting circuit, a light emitting control circuit, a first control circuit and a switch control circuit;

[0168] The light-emitting control circuit is electrically connected to the light-emitting control terminal, the control voltage input terminal and the light-emitting circuit respectively, and is used to control the connection between the control voltage input terminal and the light-emitting circuit under the control of the light-emitting control signal provided by the light-emitting control terminal;

[0169] The light emitting circuit is used to emit light according to the control voltage provided by the control voltage input terminal;

[0170] The first control circuit is electrically connected to at least two data voltage terminals, at least two scan terminals, and N switch control terminals, respectively, and is configured to control the switch control signals provided to the switch control terminals according to the data voltages provided by the data voltage terminals under the control of the scan signals provided by the scan terminals; N is an integer greater than 1;

[0171] The switch control circuit includes N switch control terminals, N light-emitting control voltage terminals and N switch control sub-circuits; n is a positive integer less than or equal to N;

[0172] The nth switch control subcircuit is electrically connected to the nth switch control terminal, the nth light-emitting control voltage terminal and the control voltage input terminal respectively, and is used to control the connection between the nth light-emitting control voltage terminal and the control voltage input terminal under the control of the nth switch control signal provided by the nth switch control terminal.

[0173] When the pixel circuit described in the embodiment of the present disclosure is in operation, the first control circuit controls the switch control signal according to the data voltage under the control of the scanning signal, and each switch control sub-circuit controls the connection between the corresponding light-emitting control voltage terminal and the control voltage input terminal under the control of the corresponding switch control signal to control the light-emitting brightness of the light-emitting circuit.

[0174] In a specific implementation, the light-emitting circuit may include a light-emitting element, and the light-emitting control circuit is electrically connected to the first pole of the light-emitting element, and is used to control the connection between the control voltage input terminal and the first pole of the light-emitting element under the control of the light-emitting control signal, and the second pole of the light-emitting element is electrically connected to the first voltage terminal; at this time, the pixel circuit described in the embodiment of the present disclosure can realize the control of the light-emitting brightness without the need for a storage capacitor, and can reduce the number of masks, thereby reducing costs. Moreover, when the pixel circuit described in the embodiment of the present disclosure is working, there is no capacitor charging and discharging function, which greatly reduces power consumption.

[0175] Optionally, the light-emitting element included in the light-emitting circuit may be a micro light-emitting diode or a sub-millimeter light-emitting diode, the first electrode of the light-emitting element is an anode, and the second electrode of the light-emitting element is a cathode, but the present invention is not limited thereto.

[0176] When the light-emitting circuit only includes a light-emitting element, at least one embodiment of the present disclosure provides a MIP (Memory In Pixel) Micro LED (micro light-emitting diode) pixel circuit, which can be suitable for application scenarios with a small number of grayscales, such as watches.

[0177] In at least one embodiment of the present disclosure, the light emitting circuit may include an amplitude control subcircuit, a driving subcircuit, a first on-off control subcircuit, and a light emitting element;

[0178] The amplitude control subcircuit is used to control the driving current generated by the driving subcircuit according to the display data voltage;

[0179] The light emitting control circuit is used to control the connection between the control voltage input terminal and the control terminal of the first on-off control subcircuit under the control of the light emitting control signal;

[0180] The control end of the first on-off control subcircuit is electrically connected to the light-emitting control circuit, the first end of the first on-off control subcircuit is electrically connected to the second end of the driving subcircuit, and the second end of the first on-off control subcircuit is electrically connected to the light-emitting element; the first on-off control subcircuit is used to control the connection between the driving subcircuit and the light-emitting element under the control of the potential of its control end, so that the control voltage connected to the control end of the first on-off control subcircuit (the control voltage can be a square wave voltage signal) can be controlled to control the light-emitting duration of the light-emitting element to control the light-emitting brightness of the light-emitting element, thereby improving the uniformity of low grayscale display.

[0181] In at least one embodiment of the present disclosure, when the light-emitting circuit includes an amplitude control subcircuit, a driving subcircuit, a first on-off control subcircuit and a light-emitting element, the on-off time of the first on-off control subcircuit can be controlled by the light-emitting control circuit, the first control circuit and the switch control circuit to control the light-emitting duration of the light-emitting element, and the driving circuit generates a driving current according to the display data voltage to achieve multi-grayscale display, which can be applied to various multi-grayscale display scenarios.

[0182] In at least one embodiment of the present disclosure, the nth switch control subcircuit includes an nth switch control transistor;

[0183] The control electrode of the nth switch control transistor is electrically connected to the nth switch control terminal, the first electrode of the nth switch control transistor is electrically connected to the nth light emitting control voltage terminal, and the second electrode of the nth switch control transistor is electrically connected to the control voltage input terminal.

[0184] Optionally, the light emitting control circuit includes a light emitting control transistor;

[0185] The control electrode of the light emitting control transistor is electrically connected to the light emitting control terminal, the first electrode of the light emitting control transistor is electrically connected to the control voltage input terminal, and the second electrode of the light emitting control transistor is electrically connected to the first electrode of the light emitting element.

[0186] In at least one embodiment of the present disclosure, N is taken as 4 or 8 as an example.

[0187] In at least one embodiment of the present disclosure, N may be equal to 2 a , a is a positive integer, but is not limited to this.

[0188] In a preferred embodiment, a may be a positive integer greater than 1, so as to increase the number of control voltages that can be provided to the control voltage input terminal I1 and increase the number of displayed grayscales.

[0189] Optionally, the first voltage end may be a low voltage end, but is not limited thereto.

[0190] As shown in FIG1 , the pixel circuit according to at least one embodiment of the present disclosure includes a light-emitting element 10 , a light-emitting control circuit 11 , a first control circuit 12 , and a switch control circuit;

[0191] The light emitting control circuit 11 is electrically connected to the light emitting control terminal EM, the control voltage input terminal I1, and the first electrode of the light emitting element 10, respectively, and is used to control the connection between the control voltage input terminal I1 and the first electrode of the light emitting element 10 under the control of the light emitting control signal provided by the light emitting control terminal EM; the second electrode of the light emitting element 10 is electrically connected to the first voltage terminal V1;

[0192] The first control circuit 12 is electrically connected to the first data voltage terminal D1, the second data voltage terminal D2, the first scan terminal G1, the second scan terminal G2, the first switch control terminal A, the second switch control terminal B, the third switch control terminal C, and the fourth switch control terminal D, respectively, and is configured to control, under the control of a first scan signal provided by the first scan terminal G1 and a second scan signal provided by the second scan terminal G2, a first switch control signal provided to the first switch control terminal A, a second switch control signal provided to the second switch control terminal B, a third switch control signal provided to the third switch control terminal C, and a fourth switch control signal provided to the fourth switch control terminal D according to a first data voltage Vdata1 provided by the first data voltage terminal D1 and a second data voltage Vdata2 provided by the second data voltage terminal D2;

[0193] The switch control circuit includes a first switch control terminal A, a second switch control terminal B, a third switch control terminal C, a fourth switch control terminal D, a first light-emitting control voltage terminal VC1, a second light-emitting control voltage terminal VC2, a third light-emitting control voltage terminal VC3, a fourth light-emitting control voltage terminal VC4, a first switch control sub-circuit 131, a second switch control sub-circuit 132, a third switch control sub-circuit 133 and a fourth switch control sub-circuit 134;

[0194] The first switch control sub-circuit 131 is electrically connected to the first switch control terminal A, the first light-emitting control voltage terminal VC1, and the control voltage input terminal I1, respectively, and is configured to control the connection between the first light-emitting control voltage terminal VC1 and the control voltage input terminal I1 under the control of a first switch control signal provided by the first switch control terminal A;

[0195] The second switch control sub-circuit 132 is electrically connected to the second switch control terminal B, the second light-emitting control voltage terminal VC2, and the control voltage input terminal I1, respectively, and is configured to control the communication between the second light-emitting control voltage terminal VC2 and the control voltage input terminal I1 under the control of a second switch control signal provided by the second switch control terminal B;

[0196] The third switch control sub-circuit 133 is electrically connected to the third switch control terminal C, the third light-emitting control voltage terminal VC3, and the control voltage input terminal I1, respectively, and is configured to control the communication between the third light-emitting control voltage terminal VC3 and the control voltage input terminal I1 under the control of a third switch control signal provided by the third switch control terminal C;

[0197] The fourth switch control subcircuit 134 is electrically connected to the fourth switch control terminal D, the fourth light-emitting control voltage terminal VC4 and the control voltage input terminal I1, respectively, and is used to control the connection between the fourth light-emitting control voltage terminal VC4 and the control voltage input terminal I1 under the control of the fourth switch control signal provided by the fourth switch control terminal D.

[0198] When at least one embodiment of the pixel circuit shown in FIG1 of the present disclosure is in operation, the first control circuit 12 controls the provision of a first switch control signal, a second switch control signal, a third switch control signal, and a fourth switch control signal; the first switch control subcircuit 131, under the control of the first switch control signal, controls the first light-emitting control voltage terminal VC1 to provide a first light-emitting control voltage to the control voltage input terminal I1; the second switch control subcircuit 132, under the control of the second switch control signal, controls the second light-emitting control voltage terminal VC2 to provide a second light-emitting control voltage to the control voltage input terminal I1; the third switch control subcircuit 133, under the control of the second switch control signal, controls the second light-emitting control voltage terminal VC2 to provide a second light-emitting control voltage to the control voltage input terminal I1; Under the control of the third switch control signal, the third light-emitting control voltage terminal VC3 is controlled to provide a third light-emitting control voltage to the control voltage input terminal I1; under the control of the fourth switch control signal, the fourth switch control sub-circuit 134 controls the fourth light-emitting control voltage terminal VC4 to provide a fourth light-emitting control voltage to the control voltage input terminal I1; under the control of the light-emitting control signal, the light-emitting control circuit 11 controls the connection between the control voltage input terminal I1 and the first pole of the light-emitting element 10 to control the light-emitting element 10 to emit light, and can control the light-emitting brightness of the light-emitting element 10 according to the light-emitting control voltage provided by the control voltage terminal.

[0199] As shown in FIG2 , the pixel circuit according to at least one embodiment of the present disclosure includes a light-emitting element 10 , a light-emitting control circuit 11 , a first control circuit 12 , and a switch control circuit;

[0200] The light emitting control circuit 11 is electrically connected to the light emitting control terminal EM, the control voltage input terminal I1, and the first electrode of the light emitting element 10, respectively, and is used to control the connection between the control voltage input terminal I1 and the first electrode of the light emitting element 10 under the control of the light emitting control signal provided by the light emitting control terminal EM; the second electrode of the light emitting element 10 is electrically connected to the first voltage terminal V1;

[0201] The first control circuit 12 is electrically connected to the first data voltage terminal D1, the second data voltage terminal D2, the third data voltage terminal D3, the fourth data voltage terminal D4, the first scan terminal G1, the second scan terminal G2, the third scan terminal G3, the fourth scan terminal G4, the first switch control terminal A, the second switch control terminal B, the third switch control terminal C, the fourth switch control terminal D, the fifth switch control terminal E, the sixth switch control terminal F, the seventh switch control terminal G and the eighth switch control terminal H, respectively, and is configured to generate a first data voltage Vdat provided by the first data voltage terminal D1 under the control of a first scan signal provided by the first scan terminal G1, a second scan signal provided by the second scan terminal G2, a third scan signal provided by the third scan terminal G3 and a fourth scan signal provided by the fourth scan terminal G4. a1, a second data voltage Vdata2 provided by the second data voltage terminal D2, a third data voltage Vdata3 provided by the third data voltage terminal D3, and a fourth data voltage Vdata4 provided by the fourth data voltage terminal D4, controlling a first switch control signal provided to the first switch control terminal A, a second switch control signal provided to the second switch control terminal B, a third switch control signal provided to the third switch control terminal C, a fourth switch control signal provided to the fourth switch control terminal D, a fifth switch control signal provided to the fifth switch control terminal E, a sixth switch control signal provided to the sixth switch control terminal F, a seventh switch control signal provided to the seventh switch control terminal G, and an eighth switch control signal provided to the eighth switch control terminal H;

[0202] The switch control circuit includes a first switch control terminal A, a second switch control terminal B, a third switch control terminal C, a fourth switch control terminal D, a fifth switch control terminal E, a sixth switch control terminal F, a seventh switch control terminal G, an eighth switch control terminal H, a first light-emitting control voltage terminal VC1, a second light-emitting control voltage terminal VC2, a third light-emitting control voltage terminal VC3, a fourth light-emitting control voltage terminal VC4, a fifth light-emitting control voltage terminal VC5, a sixth light-emitting control voltage terminal VC6, a seventh light-emitting control voltage terminal VC7, an eighth light-emitting control voltage terminal VC8, a first switch control sub-circuit 131, a second switch control sub-circuit 132, a third switch control sub-circuit 133, a fourth switch control sub-circuit 134, a fifth switch control sub-circuit 135, a sixth switch control sub-circuit 136, a seventh switch control sub-circuit 137, and an eighth switch control sub-circuit 138;

[0203] The first switch control sub-circuit 131 is electrically connected to the first switch control terminal A, the first light-emitting control voltage terminal VC1, and the control voltage input terminal I1, respectively, and is configured to control the connection between the first light-emitting control voltage terminal VC1 and the control voltage input terminal I1 under the control of a first switch control signal provided by the first switch control terminal A;

[0204] The second switch control sub-circuit 132 is electrically connected to the second switch control terminal B, the second light-emitting control voltage terminal VC2, and the control voltage input terminal I1, respectively, and is configured to control the communication between the second light-emitting control voltage terminal VC2 and the control voltage input terminal I1 under the control of a second switch control signal provided by the second switch control terminal B;

[0205] The third switch control sub-circuit 133 is electrically connected to the third switch control terminal C, the third light-emitting control voltage terminal VC3, and the control voltage input terminal I1, respectively, and is configured to control the communication between the third light-emitting control voltage terminal VC3 and the control voltage input terminal I1 under the control of a third switch control signal provided by the third switch control terminal C;

[0206] The fourth switch control sub-circuit 134 is electrically connected to the fourth switch control terminal D, the fourth light-emitting control voltage terminal VC4, and the control voltage input terminal I1, respectively, and is configured to control the communication between the fourth light-emitting control voltage terminal VC4 and the control voltage input terminal I1 under the control of a fourth switch control signal provided by the fourth switch control terminal D;

[0207] The fifth switch control sub-circuit 135 is electrically connected to the fifth switch control terminal E, the second light-emitting control voltage terminal VC2, and the control voltage input terminal I1, respectively, and is configured to control the communication between the fifth light-emitting control voltage terminal VC5 and the control voltage input terminal I1 under the control of a fifth switch control signal provided by the fifth switch control terminal E;

[0208] The sixth switch control sub-circuit 136 is electrically connected to the sixth switch control terminal F, the sixth light-emitting control voltage terminal VC6, and the control voltage input terminal I1, respectively, and is configured to control the communication between the sixth light-emitting control voltage terminal VC6 and the control voltage input terminal I1 under the control of a sixth switch control signal provided by the sixth switch control terminal F;

[0209] The seventh switch control sub-circuit 137 is electrically connected to the seventh switch control terminal G, the seventh light-emitting control voltage terminal VC7, and the control voltage input terminal I1, respectively, and is configured to control the seventh light-emitting control voltage terminal VC7 to be connected to the control voltage input terminal I1 under the control of a seventh switch control signal provided by the seventh switch control terminal G;

[0210] The eighth switch control sub-circuit 138 is electrically connected to the eighth switch control terminal H, the eighth light-emitting control voltage terminal VC8 and the control voltage input terminal I1, respectively, and is used to control the connection between the eighth light-emitting control voltage terminal VC8 and the control voltage input terminal I1 under the control of the eighth switch control signal provided by the eighth switch control terminal H.

[0211] In at least one embodiment of the pixel circuit shown in FIG2 of the present disclosure, when working, the first control circuit 12 controls the provision of a first switch control signal, a second switch control signal, a third switch control signal, a fourth switch control signal, a fifth switch control signal, a sixth switch control signal, a seventh switch control signal, and an eighth switch control signal; the first switch control subcircuit 131, under the control of the first switch control signal, controls the first light-emitting control voltage terminal VC1 to provide a first light-emitting control voltage to the control voltage input terminal I1; the second switch control subcircuit 132, under the control of the second switch control signal, controls the second light-emitting control voltage terminal VC2 to provide a second light-emitting control voltage to the control voltage input terminal I1; the third switch control subcircuit 133, under the control of the third switch control signal, controls the third light-emitting control voltage terminal VC3 to provide a third light-emitting control voltage to the control voltage input terminal I1; the fourth switch control subcircuit 134, under the control of the fourth switch control signal, controls the fourth light-emitting control voltage terminal VC4 to provide a fourth light-emitting control voltage to the control voltage input terminal I1. input terminal I1; the fifth switch control sub-circuit 135, under the control of the fifth switch control signal, controls the fifth light-emitting control voltage terminal VC5 to provide a fifth light-emitting control voltage to the control voltage input terminal I1; the sixth switch control sub-circuit 136, under the control of the sixth switch control signal, controls the sixth light-emitting control voltage terminal VC6 to provide a sixth light-emitting control voltage to the control voltage input terminal I1; the seventh switch control sub-circuit 137, under the control of the seventh switch control signal, controls the seventh light-emitting control voltage terminal VC7 to provide a seventh light-emitting control voltage to the control voltage input terminal I1; the eighth switch control sub-circuit 138, under the control of the eighth switch control signal, controls the eighth light-emitting control voltage terminal VC8 to provide an eighth light-emitting control voltage to the control voltage input terminal I1; the light-emitting control circuit 11, under the control of the light-emitting control signal, controls the connection between the control voltage input terminal I1 and the first electrode of the light-emitting element 10 to control the light-emitting element 10 to emit light, and can control the light-emitting brightness of the light-emitting element 10 according to the light-emitting control voltage provided by the control voltage terminal.

[0212] In at least one embodiment of the pixel circuit shown in FIG2 of the present disclosure, when working, the first control circuit 12 controls the provision of a first switch control signal, a second switch control signal, a third switch control signal, a fourth switch control signal, a fifth switch control signal, a sixth switch control signal, a seventh switch control signal and an eighth switch control signal; the first switch control subcircuit 131, under the control of the first switch control signal, controls the first light-emitting control voltage terminal VC1 to provide a first light-emitting control voltage to the control voltage input terminal I1; the second switch control subcircuit 132, under the control of the second switch control signal, controls the second light-emitting control voltage terminal VC2 to provide a second light-emitting control voltage to the control voltage input terminal I1; the third switch control subcircuit 133, under the control of the third switch control signal, controls the third light-emitting control voltage terminal VC3 to provide a third light-emitting control voltage to the control voltage input terminal I1; the fourth switch control subcircuit 134, under the control of the fourth switch control signal, controls the fourth light-emitting control voltage terminal VC4 to provide a fourth light-emitting control voltage to the control voltage input terminal I1; the fifth switch control subcircuit 135, under the control of the fifth switch control signal, controls the fifth light-emitting control voltage terminal VC5 to provide a fifth light-emitting control voltage to the control voltage input terminal I1; the sixth switch control subcircuit 136, under the control of the sixth switch control signal, controls the sixth light-emitting control voltage terminal VC6 to provide a sixth light-emitting control voltage to the control voltage input terminal I1; the seventh switch control subcircuit 137, under the control of the seventh switch control signal, controls the seventh light-emitting control voltage terminal VC7 to provide a seventh light-emitting control voltage to the control voltage input terminal I1; the eighth switch control subcircuit 138, under the control of the eighth switch control signal, controls the eighth light-emitting control voltage terminal VC8 to provide an eighth light-emitting control voltage to the control voltage input terminal I1; the light-emitting control circuit 11, under the control of the light-emitting control signal, controls the connection between the control voltage input terminal I1 and the first electrode of the light-emitting element 10 to control the light-emitting element 10 to emit light, and can control the light-emitting brightness of the light-emitting element 10 according to the light-emitting control voltage provided by the control voltage terminal.

[0213] Optionally, the light-emitting control voltage provided by the light-emitting control voltage terminal is a DC voltage, and the light-emitting control voltages provided by the N light-emitting control voltage terminals are different from each other.

[0214] In a specific implementation, the light-emitting control voltage may be a DC voltage. By adjusting the voltage value of the light-emitting control voltage, the light-emitting brightness of the light-emitting element may be controlled.

[0215] Optionally, the light-emitting control voltage provided by the light-emitting control voltage terminal is a square wave voltage signal, and the duty cycles of the light-emitting control voltages provided by the N light-emitting control voltage terminals are different from each other.

[0216] In a specific implementation, the light-emission control voltage may be a square wave voltage signal, and the duty cycles of the N light-emission control voltages are different. When the light-emission control voltage is a square wave voltage signal, since the square wave voltage signal has better low-grayscale brightness uniformity, display uniformity can be improved by adding high voltage and light-emission duration control.

[0217] Optionally, the first control circuit includes a first data writing circuit, a second data writing circuit and a first control sub-circuit;

[0218] The first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the first data access terminal respectively, and is used to write the first data voltage provided by the first data voltage terminal into the first data access terminal under the control of the first scanning signal provided by the first scanning terminal;

[0219] The second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the second data access terminal respectively, and is used to write the second data voltage provided by the second data voltage terminal into the second data access terminal under the control of the second scanning signal provided by the second scanning terminal;

[0220] The first control subcircuit is electrically connected to the first data access terminal, the second data access terminal and N switch control terminals, respectively, and is used to control the provision of corresponding switch control signals to the N switch control terminals according to the potential of the first data access terminal and the potential of the second data access terminal.

[0221] In a specific implementation, the first control circuit may include a first data writing circuit, a second data writing circuit and a first control sub-circuit. The first data writing circuit writes a first data voltage to a first data access terminal under the control of a first scanning signal, and the second data writing circuit writes a second data voltage to the second data access terminal under the control of a second scanning signal. The first control sub-circuit controls the provision of corresponding switch control signals to the N switch control terminals respectively according to the potential of the first data access terminal and the potential of the second data access terminal.

[0222] In at least one embodiment of the present disclosure, as shown in FIG3 , based on at least one embodiment of the pixel circuit shown in FIG1 , the first control circuit includes a first data writing circuit 31 , a second data writing circuit 32 and a first control sub-circuit 33 ;

[0223] The first data writing circuit 31 is electrically connected to the first scanning terminal G1, the first data voltage terminal D1 and the first data access terminal DI1, and is configured to write the first data voltage Vdata1 provided by the first data voltage terminal D1 into the first data access terminal DI1 under the control of the first scanning signal provided by the first scanning terminal G1;

[0224] The second data writing circuit 32 is electrically connected to the second scanning terminal G2, the second data voltage terminal D2 and the second data access terminal DI2, respectively, and is configured to write the second data voltage Vdata2 provided by the second data voltage terminal D2 into the second data access terminal DI2 under the control of the second scanning signal provided by the second scanning terminal G2;

[0225] The first control sub-circuit 33 is electrically connected to the first data access terminal DI1, the second data access terminal DI2, the first switch control terminal A, the second switch control terminal B, the third switch control terminal C and the fourth switch control terminal D, respectively, and is used to control the provision of a first switch control signal to the first switch control terminal A, the provision of a second switch control signal to the second switch control terminal B, the provision of a third switch control signal to the third switch control terminal C, and the provision of a fourth switch control signal to the fourth switch control terminal D according to the potential of the first data access terminal DI1 and the potential of the second data access terminal DI2.

[0226] Optionally, the first control subcircuit includes a first latch, a second latch, a third latch, a fourth latch, a first control switch, and a second control switch; N is equal to 4;

[0227] The input end of the first latch is electrically connected to the first data access end, and the output end of the first latch is electrically connected to the control end of the first control switch. The first latch is used to latch the voltage signal input by the first data access end and output a first output voltage. The first output voltage is in opposite phase to the voltage signal input by the first data access end.

[0228] The input end of the second latch is electrically connected to the second data access end, and the output end of the second latch is electrically connected to the control end of the second control switch. The second latch is used to latch the voltage signal input by the second data access end and output a second output voltage. The second output voltage is inversely proportional to the voltage signal input by the second data access end.

[0229] The input end of the third latch is electrically connected to the first end of the first control switch, and the output end of the third latch is electrically connected to the first switch control end. The third latch is used to latch the voltage signal input to the input end and output a third output voltage. The third output voltage is inversely proportional to the voltage signal input to the input end of the third latch.

[0230] The input end of the fourth latch is electrically connected to the first end of the second control switch, and the output end of the fourth latch is electrically connected to the third switch control end. The fourth latch is used to latch the voltage signal input to the input end and output a fourth output voltage. The fourth output voltage is inversely proportional to the voltage signal input to the input end of the fourth latch.

[0231] The control end of the first control switch is electrically connected to the output end of the first latch, and the second end of the first control switch is electrically connected to the output end of the second latch, and the first control switch is used to control the connection or disconnection between the first end of the first control switch and the second end of the first control switch under the control of the potential of the control end;

[0232] The control end of the second control switch is electrically connected to the input end of the first latch, and the second end of the second control switch is electrically connected to the input end of the second latch. The second control switch is used to control the connection or disconnection between the first end of the second control switch and the second end of the second control switch under the control of the potential of the control end;

[0233] The first switch control terminal is electrically connected to the output terminal of the third latch, and the second switch control terminal is electrically connected to the input terminal of the third latch;

[0234] The third switch control terminal is electrically connected to the output terminal of the fourth latch, and the fourth switch control terminal is electrically connected to the input terminal of the fourth latch.

[0235] In a specific implementation, the first control subcircuit may include a first latch, a second latch, a third latch, a fourth latch, a first control switch, and a second control switch. The first latch latches a voltage signal input to the first data access terminal and outputs a first output voltage, which is inversely proportional to the voltage signal input to the first data access terminal. The second latch latches a voltage signal input to the second data access terminal and outputs a second output voltage, which is inversely proportional to the voltage signal input to the second data access terminal. The third latch latches a voltage signal input to its input terminal and outputs a third output voltage, which is inversely proportional to the voltage signal input to the input terminal of the third latch. The fourth latch latches a voltage signal input to its input terminal and outputs a fourth output voltage, which is inversely proportional to the voltage signal input to the input terminal of the fourth latch. The first control switch controls the connection or disconnection between the first terminal of the first control switch and the second terminal of the first control switch under the control of the potential of its control terminal. The second control switch controls the connection or disconnection between the first terminal of the second control switch and the second terminal of the second control switch under the control of the potential of its control terminal.

[0236] As shown in FIG4 , based on at least one embodiment of the pixel circuit shown in FIG3 , the first control subcircuit includes a first latch S1, a second latch S2, a third latch S3, a fourth latch S4, a first control switch K1, and a second control switch K2;

[0237] The input end of the first latch S1 is electrically connected to the first data access end DI1, and the output end of the first latch S1 is electrically connected to the control end of the first control switch K1. The first latch S1 is used to latch the voltage signal input to the first data access end DI1 and output a first output voltage Vo1 through the output end of the first latch S1. The first output voltage Vo1 is in opposite phase to the voltage signal input to the first data access end DI1.

[0238] The input end of the second latch S2 is electrically connected to the second data access end DI2, and the output end of the second latch S2 is electrically connected to the control end of the second control switch K2. The second latch S2 is used to latch the voltage signal input to the second data access end DI2 and output a second output voltage Vo2 through the output end of the second latch S2. The second output voltage Vo2 is in opposite phase to the voltage signal input to the second data access end DI2.

[0239] The input end of the third latch S3 is electrically connected to the first end of the first control switch K1, and the output end of the third latch S3 is electrically connected to the first switch control end A. The third latch S3 is used to latch the voltage signal input to its input end and output a third output voltage Vo3 through the output end of the third latch S3. The third output voltage Vo3 is inversely proportional to the voltage signal input to the input end of the third latch S3.

[0240] The input end of the fourth latch S4 is electrically connected to the first end of the second control switch K2, and the output end of the fourth latch S4 is electrically connected to the third switch control end C. The fourth latch S4 is used to latch the voltage signal input to the input end and output a fourth output voltage Vo4. The fourth output voltage Vo4 is inversely proportional to the voltage signal input to the input end of the fourth latch S4.

[0241] The control end of the first control switch K1 is electrically connected to the output end of the first latch S1, and the second end of the first control switch K1 is electrically connected to the output end of the second latch S2. The first control switch K1 is used to control the connection or disconnection between the first end of the first control switch K1 and the second end of the first control switch K1 under the control of the potential of the control end;

[0242] The control end of the second control switch K2 is electrically connected to the input end of the first latch S1, and the second end of the second control switch K2 is electrically connected to the input end of the second latch S2. The second control switch K2 is used to control the connection or disconnection between the first end of the second control switch K2 and the second end of the second control switch K2 under the control of the potential of the control end;

[0243] The first switch control terminal A is electrically connected to the output terminal of the third latch S3, and the second switch control terminal B is electrically connected to the input terminal of the third latch S3;

[0244] The third switch control terminal C is electrically connected to the output terminal of the fourth latch S4 , and the fourth switch control terminal D is electrically connected to the input terminal of the fourth latch S4 .

[0245] In a specific implementation, the first control subcircuit may include a first latch, a second latch, a third latch, a fourth latch, a first control switch, and a second control switch. The first latch latches a voltage signal input to the first data access terminal and outputs a first output voltage, which is inversely proportional to the voltage signal input to the first data access terminal. The second latch latches a voltage signal input to the second data access terminal and outputs a second output voltage, which is inversely proportional to the voltage signal input to the second data access terminal. The third latch latches a voltage signal input to its input terminal and outputs a third output voltage, which is inversely proportional to the voltage signal input to the input terminal of the third latch. The fourth latch latches a voltage signal input to its input terminal and outputs a fourth output voltage, which is inversely proportional to the voltage signal input to the input terminal of the fourth latch. The first control switch controls the connection or disconnection between the first terminal of the first control switch and the second terminal of the first control switch under the control of the potential of its control terminal. The second control switch controls the connection or disconnection between the first terminal of the second control switch and the second terminal of the second control switch under the control of the potential of its control terminal.

[0246] In at least one embodiment of the present disclosure, the first latch includes a first inverter and a second inverter;

[0247] An input terminal of the first inverter is electrically connected to an input terminal of the first latch, and an output terminal of the first inverter is electrically connected to an output terminal of the first latch;

[0248] The input end of the second inverter is electrically connected to the output end of the first inverter, and the output end of the second inverter is electrically connected to the input end of the first inverter;

[0249] The second latch includes a third inverter and a fourth inverter;

[0250] The input end of the third inverter is electrically connected to the input end of the second latch, and the output end of the third inverter is electrically connected to the output end of the second latch;

[0251] The input end of the fourth inverter is electrically connected to the output end of the third inverter, and the output end of the fourth inverter is electrically connected to the input end of the third inverter;

[0252] The third latch includes a fifth inverter and a sixth inverter;

[0253] The input end of the fifth inverter is electrically connected to the input end of the third latch, and the output end of the fifth inverter is electrically connected to the output end of the third latch;

[0254] The input end of the sixth inverter is electrically connected to the output end of the fifth inverter, and the output end of the sixth inverter is electrically connected to the input end of the fifth inverter;

[0255] The fourth latch includes a seventh inverter and an eighth inverter;

[0256] The input end of the seventh inverter is electrically connected to the input end of the fourth latch, and the output end of the seventh inverter is electrically connected to the output end of the fourth latch;

[0257] The input end of the eighth inverter is electrically connected to the output end of the seventh inverter, and the output end of the eighth inverter is electrically connected to the input end of the seventh inverter.

[0258] Optionally, the first control switch is a first control transistor, and the second control switch is a second control transistor;

[0259] The control electrode of the first control transistor is electrically connected to the output terminal of the first latch, the first electrode of the first control transistor is electrically connected to the input terminal of the third latch, and the second electrode of the first control transistor is electrically connected to the output terminal of the second latch;

[0260] The control electrode of the second control transistor is electrically connected to the input end of the first latch, the first electrode of the second control transistor is electrically connected to the input end of the fourth latch, and the second electrode of the second control transistor is electrically connected to the input end of the second latch.

[0261] Optionally, the first data writing circuit includes a first writing transistor, and the second data writing circuit includes a second writing transistor;

[0262] The control electrode of the first write transistor is electrically connected to the first scan terminal, the first electrode of the first write transistor is electrically connected to the first data voltage terminal, and the second electrode of the first write transistor is electrically connected to the first data access terminal;

[0263] The control electrode of the second write transistor is electrically connected to the second scan end, the first electrode of the second write transistor is electrically connected to the second data voltage end, and the second electrode of the second write transistor is electrically connected to the second data access end.

[0264] As shown in FIG5 , based on at least one embodiment of the pixel circuit shown in FIG4 , the light emitting element is a micro light emitting diode M1 ;

[0265] The first latch S1 includes a first inverter F1 and a second inverter F2;

[0266] The input end of the first inverter F1 is electrically connected to the input end of the first latch S1, and the output end of the first inverter F1 is electrically connected to the output end of the first latch S1;

[0267] The input end of the second inverter F2 is electrically connected to the output end of the first inverter F1, and the output end of the second inverter F2 is electrically connected to the input end of the first inverter F1;

[0268] The second latch S2 includes a third inverter F3 and a fourth inverter F4;

[0269] The input end of the third inverter F3 is electrically connected to the input end of the second latch S2, and the output end of the third inverter F3 is electrically connected to the output end of the second latch S2;

[0270] The input end of the fourth inverter F4 is electrically connected to the output end of the third inverter F3, and the output end of the fourth inverter F4 is electrically connected to the input end of the third inverter F3;

[0271] The third latch S3 includes a fifth inverter F5 and a sixth inverter F6;

[0272] The input end of the fifth inverter F5 is electrically connected to the input end of the third latch S3, and the output end of the fifth inverter F5 is electrically connected to the output end of the third latch S3;

[0273] The input end of the sixth inverter F6 is electrically connected to the output end of the fifth inverter F5, and the output end of the sixth inverter F6 is electrically connected to the input end of the fifth inverter F5;

[0274] The fourth latch S4 includes a seventh inverter F7 and an eighth inverter F8;

[0275] The input end of the seventh inverter F7 is electrically connected to the input end of the fourth latch S4, and the output end of the seventh inverter F7 is electrically connected to the output end of the fourth latch S4;

[0276] The input end of the eighth inverter F8 is electrically connected to the output end of the seventh inverter F7, and the output end of the eighth inverter F8 is electrically connected to the input end of the seventh inverter F7;

[0277] The first control switch is a first control transistor TC1, and the second control switch is a second control transistor TC2;

[0278] The gate of the first control transistor TC1 is electrically connected to the output terminal of the first latch S1, the drain of the first control transistor TC1 is electrically connected to the input terminal of the third latch S3, and the source of the first control transistor TC1 is electrically connected to the output terminal of the second latch;

[0279] The gate of the second control transistor TC2 is electrically connected to the input terminal of the first latch S1, the drain of the second control transistor TC2 is electrically connected to the input terminal of the fourth latch S4, and the source of the second control transistor TC2 is electrically connected to the input terminal of the second latch S2;

[0280] The first data writing circuit 31 includes a first writing transistor TW1, and the second data writing circuit 32 includes a second writing transistor TW2;

[0281] The gate of the first write transistor TW1 is electrically connected to the first scan terminal G1, the drain of the first write transistor TW1 is electrically connected to the first data voltage terminal D1, and the source of the first write transistor TW1 is electrically connected to the first data access terminal DI1;

[0282] The gate of the second write transistor TW2 is electrically connected to the second scan terminal G2, the drain of the second write transistor TW2 is electrically connected to the first data voltage terminal D1, and the source of the second write transistor TW2 is electrically connected to the second data access terminal DI2;

[0283] The first switch control sub-circuit 131 includes a first switch control transistor TK1;

[0284] The gate of the first switch control transistor TK1 is electrically connected to the first switch control terminal A, the drain of the first switch control transistor TK1 is electrically connected to the first light emission control voltage terminal VC1, and the source of the first switch control transistor TK1 is electrically connected to the control voltage input terminal I1;

[0285] The second switch control sub-circuit 132 includes a second switch control transistor TK2;

[0286] The gate of the second switch control transistor TK2 is electrically connected to the second switch control terminal B, the drain of the second switch control transistor TK2 is electrically connected to the second light emitting control voltage terminal VC2, and the source of the second switch control transistor TK2 is electrically connected to the control voltage input terminal I1;

[0287] The third switch control sub-circuit 133 includes a third switch control transistor TK3;

[0288] The gate of the third switch control transistor TK3 is electrically connected to the third switch control terminal C, the drain of the third switch control transistor TK3 is electrically connected to the third light emitting control voltage terminal VC2, and the source of the third switch control transistor TK3 is electrically connected to the control voltage input terminal I1;

[0289] The fourth switch control sub-circuit 134 includes a fourth switch control transistor TK4;

[0290] The gate of the fourth switch control transistor TK4 is electrically connected to the fourth switch control terminal D, the drain of the fourth switch control transistor TK4 is electrically connected to the fourth light emitting control voltage terminal VC4, and the source of the fourth switch control transistor TK4 is electrically connected to the control voltage input terminal I1;

[0291] The light emitting control circuit 11 includes a light emitting control transistor TE;

[0292] The gate of the light emitting control transistor TE is electrically connected to the light emitting control terminal EM, the drain of the light emitting control transistor TE is electrically connected to the control voltage input terminal I1, the source of the light emitting control transistor TE is electrically connected to the anode of M1, and the cathode of M1 is electrically connected to the low voltage terminal VSS.

[0293] In at least one embodiment shown in FIG. 5 , the first data voltage terminal D1 and the second data voltage terminal are the same data voltage terminal.

[0294] In at least one embodiment of the pixel circuit shown in FIG. 5 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0295] As shown in FIG6 , when at least one embodiment of the pixel circuit shown in FIG5 of the present disclosure is in operation, a display cycle includes a first writing phase tw1 , a second writing phase tw2 , and a light emitting phase te that are sequentially arranged;

[0296] In the first writing phase tw1, G1 provides a high voltage signal, D1 provides a first data voltage Vdata1, and TW1 is turned on to write Vdata1 into the input terminal of S1;

[0297] In the second writing phase tw2, G2 provides a high voltage signal, D1 provides a second data voltage Vdata2, and TW2 is turned on to write Vdata2 into the input terminal of S2;

[0298] When Vdata1 is a low voltage signal and Vdata2 is a low voltage signal, S1 outputs a high voltage signal, S2 outputs a high voltage signal, TC1 is turned on, TC2 is turned off, the input end of S3 is connected to a high voltage signal, the first switch control end A is connected to a low voltage signal, the second switch control end B is connected to a high voltage signal, the potential of the third switch control end C and the potential of the fourth switch control end D are low voltage, TK1 is turned off, TK2 is turned on, TK3 and TK4 are turned off, and I1 is connected to the second light-emitting control voltage; in the light-emitting stage te, TE is turned on, and the drain of TE is connected to the second light-emitting control voltage to drive M1 to emit light;

[0299] When Vdata1 is a low voltage signal and Vdata2 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a low voltage signal, TC1 is turned on, TC2 is turned off, the input end of S3 is connected to a low voltage signal, the first switch control end A is connected to a high voltage signal, the second switch control end B is connected to a low voltage signal, the potential of the third switch control end C and the potential of the fourth switch control end D are low voltage, TK1 is turned on, TK2 is turned off, TK3 and TK4 are turned off, and I1 is connected to the first light-emitting control voltage; in the light-emitting stage te, TE is turned on, and the drain of TE is connected to the first light-emitting control voltage to drive M1 to emit light;

[0300] When Vdata1 is a high voltage signal and Vdata2 is a low voltage signal, S1 outputs a low voltage signal, S2 outputs a high voltage signal, TC1 is turned off, TC2 is turned on, the input end of S4 is connected to a low voltage signal, the third switch control end C is connected to a high voltage signal, the fourth switch control end D is connected to a low voltage signal, the potential of the first switch control end A and the potential of the second switch control end B are low voltage, TK3 is turned on, TK4 is turned off, TK1 and TK2 are turned off, and I1 is connected to the third light-emitting control voltage; in the light-emitting stage te, TE is turned on, and the drain of TE is connected to the third light-emitting control voltage to drive M1 to emit light;

[0301] When Vdata1 is a high voltage signal and Vdata2 is a high voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, TC1 is turned off, TC2 is turned on, the input end of S4 is connected to a high voltage signal, the third switch control end C is connected to a low voltage signal, the fourth switch control end D is connected to a high voltage signal, the potential of the first switch control end A and the potential of the second switch control end B are low voltages, TK4 is turned on, TK3 is turned off, TK1 and TK2 are turned off, and I1 is connected to the fourth light-emitting control voltage; in the light-emitting stage te, TE is turned on, and the drain of TE is connected to the fourth light-emitting control voltage to drive M1 to emit light.

[0302] In at least one embodiment of the present disclosure, the first control circuit includes a first data writing circuit, a second data writing circuit, a third data writing circuit, a fourth data writing circuit, and a second control sub-circuit;

[0303] The first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the first data access terminal respectively, and is used to write the first data voltage provided by the first data voltage terminal into the first data access terminal under the control of the first scanning signal provided by the first scanning terminal;

[0304] The second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the second data access terminal respectively, and is used to write the second data voltage provided by the second data voltage terminal into the second data access terminal under the control of the second scanning signal provided by the second scanning terminal;

[0305] The third data writing circuit is electrically connected to the third scanning terminal, the third data voltage terminal and the third data access terminal respectively, and is used to write the third data voltage provided by the third data voltage terminal into the third data access terminal under the control of the third scanning signal provided by the third scanning terminal;

[0306] The fourth data writing circuit is electrically connected to the fourth scanning terminal, the fourth data voltage terminal and the fourth data access terminal respectively, and is used to write the fourth data voltage provided by the fourth data voltage terminal into the fourth data access terminal under the control of the fourth scanning signal provided by the fourth scanning terminal;

[0307] The second control subcircuit is electrically connected to the first data access terminal, the second data access terminal, the third data access terminal, the fourth data access terminal, and N switch control terminals, respectively, and is configured to control the provision of corresponding switch control signals to the N switch control terminals, respectively, based on the potential of the first data access terminal, the potential of the second data access terminal, the potential of the third data access terminal, and the potential of the fourth data access terminal.

[0308] As shown in FIG7 , based on at least one embodiment of the pixel circuit shown in FIG2 , the first control circuit includes a first data writing circuit 71 , a second data writing circuit 72 , a third data writing circuit 73 , a fourth data writing circuit 74 and a second control sub-circuit 75 ;

[0309] The first data writing circuit 71 is electrically connected to the first scanning terminal G1, the first data voltage terminal D1 and the first data access terminal DI1, and is configured to write the first data voltage Vdata1 provided by the first data voltage terminal D1 into the first data access terminal DI1 under the control of the first scanning signal provided by the first scanning terminal G1;

[0310] The second data writing circuit 72 is electrically connected to the second scanning terminal G2, the second data voltage terminal D2 and the second data access terminal DI2, respectively, and is configured to write the second data voltage Vdata2 provided by the second data voltage terminal D2 into the second data access terminal DI2 under the control of the second scanning signal provided by the second scanning terminal G2;

[0311] The third data writing circuit 73 is electrically connected to the third scanning terminal G3, the third data voltage terminal D3, and the third data access terminal DI3, respectively, and is configured to write the third data voltage Vdata3 provided by the third data voltage terminal D3 into the third data access terminal DI3 under the control of the third scanning signal provided by the third scanning terminal G3;

[0312] The fourth data writing circuit 74 is electrically connected to the fourth scanning terminal G4, the fourth data voltage terminal D4, and the fourth data access terminal DI4, respectively, and is configured to write the fourth data voltage Vdata4 provided by the fourth data voltage terminal D4 into the fourth data access terminal DI4 under the control of the fourth scanning signal provided by the fourth scanning terminal G4;

[0313] The second control sub-circuit 75 is electrically connected to the first data access terminal DI1, the second data access terminal DI2, the third data access terminal DI3, the fourth data access terminal DI4, the first switch control terminal A, the second switch control terminal B, the third switch control terminal C, the fourth switch control terminal D, the fifth switch control terminal E, the sixth switch control terminal F, the seventh switch control terminal G, and the eighth switch control terminal H, respectively, and is configured to control the provision of a first switch control signal to the first switch control terminal A, a second switch control signal to the second switch control terminal B, a third switch control signal to the third switch control terminal C, a fourth switch control signal to the fourth switch control terminal D, a fifth switch control signal to the fifth switch control terminal E, a sixth switch control signal to the sixth switch control terminal F, a seventh switch control signal to the seventh switch control terminal G, and an eighth switch control signal to the eighth switch control terminal H, based on the potential of the first data access terminal DI1, the potential of the second data access terminal DI2, the potential of the third data access terminal DI3, and the potential of the fourth data access terminal DI4.

[0314] Optionally, the second control subcircuit includes a first latch, a second latch, a third latch, a fourth latch, a fifth latch, a sixth latch, a seventh latch, an eighth latch, a ninth latch, a tenth latch, a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, and a sixth control switch; N is equal to 8;

[0315] The input end of the first latch is electrically connected to the first data access end, and the output end of the first latch is electrically connected to the control end of the first control switch. The first latch is used to latch the voltage signal input by the first data access end and output a first output voltage. The first output voltage is in opposite phase to the voltage signal input by the first data access end.

[0316] The input end of the second latch is electrically connected to the second data access end, and the output end of the second latch is electrically connected to the control end of the second control switch. The second latch is used to latch the voltage signal input by the second data access end and output a second output voltage. The second output voltage is inversely proportional to the voltage signal input by the second data access end.

[0317] The input end of the third latch is electrically connected to the first end of the first control switch, and the output end of the third latch is electrically connected to the control end of the third control switch. The third latch is used to latch the voltage signal input to the input end and output a third output voltage, and the third output voltage is inversely proportional to the voltage signal input to the input end of the third latch;

[0318] The input end of the fourth latch is electrically connected to the first end of the second control switch, and the output end of the fourth latch is electrically connected to the control end of the fifth control switch. The fourth latch is used to latch the voltage signal input to the input end and output a fourth output voltage, and the fourth output voltage is inversely proportional to the voltage signal input to the input end of the fourth latch.

[0319] The input end of the fifth latch is electrically connected to the first end of the third control switch, and the output end of the fifth latch is electrically connected to the second switch control end. The fifth latch is used to latch the voltage signal input to the input end and output a fifth output voltage. The fifth output voltage is inversely proportional to the voltage signal input to the input end of the fifth latch.

[0320] The input end of the sixth latch is electrically connected to the third data access end, and the output end of the sixth latch is electrically connected to the second end of the third control switch. The sixth latch is used to latch the voltage signal input to the input end and output a sixth output voltage, and the sixth output voltage is inversely proportional to the voltage signal input to the input end of the sixth latch.

[0321] The input end of the seventh latch is electrically connected to the first end of the fourth control switch, and the output end of the seventh latch is electrically connected to the fourth switch control end. The seventh latch is used to latch the voltage signal input to the input end and output a seventh output voltage. The seventh output voltage is inversely proportional to the voltage signal input to the input end of the seventh latch.

[0322] The input end of the eighth latch is electrically connected to the first end of the fifth control switch, and the output end of the eighth latch is electrically connected to the sixth switch control end. The eighth latch is used to latch the voltage signal input to the input end and output an eighth output voltage. The eighth output voltage is inversely proportional to the voltage signal input to the input end of the eighth latch.

[0323] The input end of the ninth latch is electrically connected to the fourth data access end, and the output end of the ninth latch is electrically connected to the second end of the fifth control switch. The ninth latch is used to latch the voltage signal input to the input end and output a ninth output voltage, and the ninth output voltage is inversely proportional to the voltage signal input to the input end of the ninth latch.

[0324] The input terminal of the tenth latch is electrically connected to the first terminal of the sixth control switch, and the output terminal of the tenth latch is electrically connected to the eighth switch control terminal. The tenth latch is used to latch the voltage signal input to the input terminal and output a tenth output voltage, and the tenth output voltage is inversely proportional to the voltage signal input to the input terminal of the tenth latch.

[0325] The control end of the first control switch is electrically connected to the output end of the first latch, and the second end of the first control switch is electrically connected to the output end of the second latch, and the first control switch is used to control the connection or disconnection between the first end of the first control switch and the second end of the first control switch under the control of the potential of the control end;

[0326] The control end of the second control switch is electrically connected to the input end of the first latch, and the second end of the second control switch is electrically connected to the input end of the second latch. The second control switch is used to control the connection or disconnection between the first end of the second control switch and the second end of the second control switch under the control of the potential of the control end;

[0327] The control end of the third control switch is electrically connected to the output end of the third latch, and the third control switch is used to control the connection or disconnection between the input end of the fifth latch and the output end of the sixth latch under the control of the potential of the control end;

[0328] The control end of the fourth control switch is electrically connected to the input end of the third latch, and the fourth control switch is used to control the connection or disconnection between the input end of the seventh latch and the input end of the sixth latch under the control of the potential of the control end;

[0329] The control end of the fifth control switch is electrically connected to the output end of the fourth latch, and the fifth control switch is used to control the input end of the eighth latch to be electrically connected to the output end of the ninth latch under the control of the potential of the control end;

[0330] The control end of the sixth control switch is electrically connected to the input end of the fourth latch, and the sixth control switch is used to control the connection between the input end of the tenth latch and the input end of the ninth latch under the control of the potential of the control end;

[0331] The first switch control terminal is electrically connected to the input terminal of the fifth latch, and the seventh switch control terminal is electrically connected to the input terminal of the tenth latch.

[0332] As shown in FIG8 , based on at least one embodiment of the pixel circuit shown in FIG7 , the second control subcircuit includes a first latch S1, a second latch S2, a third latch S3, a fourth latch S4, a fifth latch S5, a sixth latch S6, a seventh latch S7, an eighth latch S8, a ninth latch S9, a tenth latch S10, a first control switch K1, a second control switch K2, a third control switch K3, a fourth control switch K4, a fifth control switch K5, and a sixth control switch K6; N is equal to 8;

[0333] The input end of the first latch S1 is electrically connected to the first data access end DI1, and the output end of the first latch S1 is electrically connected to the control end of the first control switch K1. The first latch S1 is used to latch the voltage signal input to the first data access end DI1 and output a first output voltage Vo1 through the output end of the first latch S1. The first output voltage Vo1 is in opposite phase to the voltage signal input to the first data access end DI1.

[0334] The input end of the second latch S2 is electrically connected to the second data access end DI2, and the output end of the second latch S2 is electrically connected to the control end of the second control switch K2. The second latch S2 is used to latch the voltage signal input to the second data access end DI2 and output a second output voltage Vo2 through the output end of the second latch S2. The second output voltage Vo2 is in opposite phase to the voltage signal input to the second data access end DI2.

[0335] The input end of the third latch S3 is electrically connected to the first end of the first control switch K1, and the output end of the third latch S3 is electrically connected to the control end of the third control switch K3. The third latch S3 is used to latch the voltage signal input to its input end and output a third output voltage Vo3 through the output end of the third latch S3. The third output voltage Vo3 is in opposite phase to the voltage signal input to the input end of the third latch S3.

[0336] The input end of the fourth latch S4 is electrically connected to the first end of the second control switch K2, and the output end of the fourth latch S4 is electrically connected to the control end of the fifth control switch K5. The fourth latch S4 is used to latch the voltage signal input to its input end and output a fourth output voltage Vo4 through the output end of the fourth latch S4. The fourth output voltage Vo4 is in opposite phase to the voltage signal input to the input end of the fourth latch S4.

[0337] The input end of the fifth latch S5 is electrically connected to the first end of the third control switch K3, and the output end of the fifth latch S5 is electrically connected to the second switch control end B. The fifth latch S5 is used to latch the voltage signal input to its input end and output a fifth output voltage Vo5 through the output end of the fifth latch S5. The fifth output voltage Vo5 is inversely proportional to the voltage signal input to the input end of the fifth latch S5.

[0338] The input end of the sixth latch S6 is electrically connected to the third data access end DI3, and the output end of the sixth latch S6 is electrically connected to the second end of the third control switch K3. The sixth latch S6 is used to latch the voltage signal input to its input end and output a sixth output voltage Vo6 through the output end of the sixth latch S6. The sixth output voltage Vo6 is in opposite phase to the voltage signal input to the input end of the sixth latch S6.

[0339] The input end of the seventh latch S7 is electrically connected to the first end of the fourth control switch K4, and the output end of the seventh latch S7 is electrically connected to the fourth switch control end D. The seventh latch S7 is used to latch the voltage signal input to the input end thereof and output a seventh output voltage Vo7 through the seventh latch S7. The seventh output voltage Vo7 is inversely proportional to the voltage signal input to the input end of the seventh latch S7.

[0340] The input end of the eighth latch S8 is electrically connected to the first end of the fifth control switch K5, and the output end of the eighth latch S8 is electrically connected to the sixth switch control end F. The eighth latch S8 is used to latch the voltage signal input to its input end and output an eighth output voltage Vo8 through the output end of the eighth latch S8. The eighth output voltage Vo8 is inversely proportional to the voltage signal input to the input end of the eighth latch S8.

[0341] The input end of the ninth latch S9 is electrically connected to the fourth data access end DI4, and the output end of the ninth latch S9 is electrically connected to the second end of the fifth control switch K5. The ninth latch S9 is used to latch the voltage signal input to its input end and output a ninth output voltage Vo9 through the ninth latch S9. The ninth output voltage Vo9 is in opposite phase to the voltage signal input to the input end of the ninth latch S9.

[0342] The input terminal of the tenth latch S10 is electrically connected to the first terminal of the sixth control switch K6, and the output terminal of the tenth latch S10 is electrically connected to the eighth switch control terminal H. The tenth latch S10 is used to latch the voltage signal input to the input terminal thereof and output a tenth output voltage Vo10 through the output terminal of the tenth latch S10. The tenth output voltage V10 is in opposite phase to the voltage signal input to the input terminal of the tenth latch S10.

[0343] The control end of the first control switch K1 is electrically connected to the output end of the first latch S1, and the second end of the first control switch K1 is electrically connected to the output end of the second latch S2. The first control switch K1 is used to control the connection or disconnection between the first end of the first control switch K1 and the second end of the first control switch K1 under the control of the potential of the control end;

[0344] The control end of the second control switch K2 is electrically connected to the input end of the first latch S1, and the second end of the second control switch K2 is electrically connected to the input end of the second latch S2. The second control switch K2 is used to control the connection or disconnection between the first end of the second control switch K2 and the second end of the second control switch K2 under the control of the potential of the control end;

[0345] The control end of the third control switch K3 is electrically connected to the output end of the third latch S3. The third control switch K3 is used to control the connection or disconnection between the input end of the fifth latch S5 and the output end of the sixth latch S6 under the control of the potential of the control end.

[0346] The control end of the fourth control switch K4 is electrically connected to the input end of the third latch S3. The fourth control switch K4 is used to control the connection or disconnection between the input end of the seventh latch S7 and the input end of the sixth latch S6 under the control of the potential of the control end.

[0347] The control end of the fifth control switch K5 is electrically connected to the output end of the fourth latch S4. The fifth control switch K5 is used to control the input end of the eighth latch S8 to be electrically connected to the output end of the ninth latch S9 under the control of the potential of the control end thereof;

[0348] The control end of the sixth control switch K6 is electrically connected to the input end of the fourth latch S4. The sixth control switch K6 is used to control the connection between the input end of the tenth latch S10 and the input end of the ninth latch S9 under the control of the potential of the control end.

[0349] The first switch control terminal A is electrically connected to the input terminal of the fifth latch S5, and the seventh switch control terminal G is electrically connected to the input terminal of the tenth latch S10;

[0350] The third switch control terminal C is electrically connected to the input terminal of the seventh latch S7, and the fifth switch control terminal E is electrically connected to the input terminal of the eighth latch S8.

[0351] When at least one embodiment of the pixel circuit shown in FIG8 of the present disclosure is in operation,

[0352] When Vdata1 is a low voltage signal, Vdata2 is a low voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a low voltage signal, the gate of K1 is connected to a high voltage signal, the gate of K2 is connected to a low voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to a high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input end of S7 is connected to a low voltage signal, and S7 outputs a high voltage signal to the fourth switch control end D;

[0353] When Vdata1 is a high voltage signal, Vdata2 is a low voltage signal, Vata3 is a low voltage signal, and Vdata4 is a low voltage signal, S1 outputs a low voltage signal, K1 is turned off, S2 outputs a high voltage signal, K2 is turned on, the input end of S4 is connected to the low voltage signal, the control end of K5 is connected to the high voltage signal, K5 is turned on, K6 is turned off, the input end of S9 is connected to the low voltage signal, S9 outputs a high voltage signal, and provides the high voltage signal to the fifth switch control end E through K5;

[0354] When Vdata1 is a low voltage signal, Vdata2 is a high voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a low voltage signal, S1 outputs a high voltage signal, K1 is turned on, K2 is turned off, S2 outputs a low voltage signal, the input end of S3 is connected to the low voltage signal, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, S6 outputs a high voltage signal, and S6 provides the high voltage signal to the first switch control terminal A through the turned-on K3;

[0355] When Vdata1 is a low voltage signal, Vdata2 is a low voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a low voltage signal, S1 outputs a high voltage signal, S2 provides a high voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to the high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input end of S7 is connected to the high voltage signal, and the high voltage signal is written to the third switch control terminal C;

[0356] When Vdata1 is a low voltage signal, Vdata2 is a low voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a high voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to a high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input end of S6 is connected to a low voltage signal, the input end of S7 is connected to a low voltage signal, and S7 outputs a high voltage signal to the fourth switch control end D;

[0357] When Vdata1 is a high voltage signal, Vdata2 is a high voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a low voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to a high voltage signal, S4 outputs a low voltage signal, K7 is turned off, K8 is turned on, the input end of S9 is connected to a low voltage signal, the input end of S10 is connected to a low voltage signal, and S10 outputs a high voltage signal to the eighth switch control terminal H;

[0358] When Vdata1 is a high voltage signal, Vdata2 is a high voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a high voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to a high voltage signal, S4 outputs a low voltage signal, K7 is turned off, K8 is turned on, the input end of S9 is connected to a high voltage signal, the input end of S10 is connected to a high voltage signal, and S10 outputs a low voltage signal, so as to write the high voltage signal to the seventh switch control terminal G;

[0359] When Vdata1 is a high voltage signal, Vdata2 is a high voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a low voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, K1 is turned off, and K2 is turned on; the input end of S4 is connected to a high voltage signal, S4 outputs a low voltage signal, K7 is turned off, K8 is turned on, the input end of S9 is connected to a low voltage signal, S9 outputs a high voltage signal, the input end of S10 is connected to a low voltage signal, and S10 outputs a high voltage signal to the eighth switch control terminal H;

[0360] When Vdata1 is a high voltage signal, Vdata2 is a high voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a high voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, K1 is turned off, K2 is turned on, the input terminal of S4 is connected to the high voltage signal, S4 outputs a low voltage signal, K7 is turned off, K8 is turned on, the input terminal of S9 is connected to the high voltage signal, S9 outputs a low voltage signal, the input terminal of S10 is connected to the high voltage signal, S10 outputs a low voltage signal, so as to provide a high voltage signal to the seventh switch control terminal G;

[0361] When Vdata1 is a high voltage signal, Vdata2 is a low voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a high voltage signal, S1 outputs a low voltage signal, S2 outputs a high voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to the low voltage signal, S4 outputs a high voltage signal, K7 is turned on, K8 is turned off, the input end of S9 is connected to the high voltage signal, S9 outputs a low voltage signal to the input end of S8, and S8 outputs a high voltage signal to the sixth switch control end F;

[0362] When Vdata1 is a high voltage signal, Vdata2 is a low voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a high voltage signal, S1 outputs a low voltage signal, S2 provides a high voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to the low voltage signal, S4 outputs a high voltage signal, K7 is turned on, K8 is turned off, the input end of S9 is connected to the high voltage signal, S9 outputs a low voltage signal to the input end of S8, and S8 outputs a high voltage signal to the sixth switch control end F;

[0363] When Vdata1 is a high voltage signal, Vdata2 is a low voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a low voltage signal, S1 outputs a low voltage signal, S2 provides a high voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to the low voltage signal, S4 outputs a high voltage signal, K7 is turned on, K8 is turned off, the input end of S9 is connected to the low voltage signal, S9 outputs a high voltage signal to the input end of S8, S8 outputs a low voltage signal, and S9 outputs a high voltage signal to the fifth switch control terminal E;

[0364] When Vdata1 is a low voltage signal, Vdata2 is a high voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a low voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to a low voltage signal, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, the input end of S6 is connected to a high voltage signal, S6 outputs a low voltage signal, the input end of S5 is connected to a low voltage signal, and S5 outputs a high voltage signal to the second switch control terminal B;

[0365] When Vdata1 is a low voltage signal, Vdata2 is a high voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a low voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to the low voltage signal, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, the input end of S6 is connected to the low voltage signal, and S6 outputs a high voltage signal to the first switch control terminal A;

[0366] When Vdata1 is a low voltage signal, Vdata2 is a high voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a low voltage signal, S1 outputs a high voltage signal, S2 outputs a low voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to the low voltage signal, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, the input end of S6 is connected to the high voltage signal, S6 outputs a low voltage signal to the input end of S5, and S5 outputs a high voltage signal to the second switch control end B;

[0367] When Vdata1 is a low voltage signal, Vdata2 is a low voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a high voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to the high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input end of S6 is connected to the high voltage signal, the input end of S7 is connected to the high voltage signal, S7 outputs a low voltage signal, and provides the high voltage signal to the third switch control terminal C.

[0368] In at least one embodiment of the present disclosure, the first latch includes a first inverter and a second inverter;

[0369] An input terminal of the first inverter is electrically connected to an input terminal of the first latch, and an output terminal of the first inverter is electrically connected to an output terminal of the first latch;

[0370] The input end of the second inverter is electrically connected to the output end of the first inverter, and the output end of the second inverter is electrically connected to the input end of the first inverter;

[0371] The second latch includes a third inverter and a fourth inverter;

[0372] The input end of the third inverter is electrically connected to the input end of the second latch, and the output end of the third inverter is electrically connected to the output end of the second latch;

[0373] The input end of the fourth inverter is electrically connected to the output end of the third inverter, and the output end of the fourth inverter is electrically connected to the input end of the third inverter;

[0374] The third latch includes a fifth inverter and a sixth inverter;

[0375] The input end of the fifth inverter is electrically connected to the input end of the third latch, and the output end of the fifth inverter is electrically connected to the output end of the third latch;

[0376] The input end of the sixth inverter is electrically connected to the output end of the fifth inverter, and the output end of the sixth inverter is electrically connected to the input end of the fifth inverter;

[0377] The fourth latch includes a seventh inverter and an eighth inverter;

[0378] The input end of the seventh inverter is electrically connected to the input end of the fourth latch, and the output end of the seventh inverter is electrically connected to the output end of the fourth latch;

[0379] The input end of the eighth inverter is electrically connected to the output end of the seventh inverter, and the output end of the eighth inverter is electrically connected to the input end of the seventh inverter;

[0380] The fifth latch includes a ninth inverter and a tenth inverter;

[0381] The input end of the ninth inverter is electrically connected to the input end of the fifth latch, and the output end of the ninth inverter is electrically connected to the output end of the fifth latch;

[0382] The input end of the tenth inverter is electrically connected to the output end of the ninth inverter, and the output end of the tenth inverter is electrically connected to the input end of the ninth inverter;

[0383] The sixth latch includes an eleventh inverter and a twelfth inverter;

[0384] The input end of the eleventh inverter is electrically connected to the input end of the sixth latch, and the output end of the eleventh inverter is electrically connected to the output end of the sixth latch;

[0385] The input end of the twelfth inverter is electrically connected to the output end of the eleventh inverter, and the output end of the twelfth inverter is electrically connected to the input end of the eleventh inverter;

[0386] The seventh latch includes a thirteenth inverter and a fourteenth inverter;

[0387] The input end of the thirteenth inverter is electrically connected to the input end of the seventh latch, and the output end of the thirteenth inverter is electrically connected to the output end of the seventh latch;

[0388] The input end of the fourteenth inverter is electrically connected to the output end of the thirteenth inverter, and the output end of the fourteenth inverter is electrically connected to the input end of the thirteenth inverter;

[0389] The eighth latch includes a fifteenth inverter and a sixteenth inverter;

[0390] The input end of the fifteenth inverter is electrically connected to the input end of the eighth latch, and the output end of the fifteenth inverter is electrically connected to the output end of the eighth latch;

[0391] The input end of the sixteenth inverter is electrically connected to the output end of the fifteenth inverter, and the output end of the sixteenth inverter is electrically connected to the input end of the fifteenth inverter;

[0392] The ninth latch includes a seventeenth inverter and an eighteenth inverter;

[0393] The input end of the seventeenth inverter is electrically connected to the input end of the ninth latch, and the output end of the seventeenth inverter is electrically connected to the output end of the ninth latch;

[0394] The input end of the eighteenth inverter is electrically connected to the output end of the seventeenth inverter, and the output end of the eighteenth inverter is electrically connected to the input end of the seventeenth inverter;

[0395] The tenth latch includes a nineteenth inverter and a twentieth inverter;

[0396] The input end of the nineteenth inverter is electrically connected to the input end of the tenth latch, and the output end of the nineteenth inverter is electrically connected to the output end of the tenth latch;

[0397] The input terminal of the 20th inverter is electrically connected to the output terminal of the 19th inverter, and the output terminal of the 20th inverter is electrically connected to the input terminal of the 19th inverter.

[0398] Optionally, the first control switch is a first control transistor, the second control switch is a second control transistor; the third control switch is a third control transistor, the fourth control switch is a fourth control transistor; the fifth control switch is a fifth control transistor, and the sixth control switch is a sixth control transistor;

[0399] The control electrode of the first control transistor is electrically connected to the output terminal of the first latch, the first electrode of the first control transistor is electrically connected to the input terminal of the third latch, and the second electrode of the first control transistor is electrically connected to the output terminal of the second latch;

[0400] The control electrode of the second control transistor is electrically connected to the input terminal of the first latch, the first electrode of the second control transistor is electrically connected to the input terminal of the fourth latch, and the second electrode of the second control transistor is electrically connected to the input terminal of the second latch;

[0401] The control electrode of the third control transistor is electrically connected to the output terminal of the third latch, the first electrode of the third control transistor is electrically connected to the input terminal of the fifth latch, and the second electrode of the third control transistor is electrically connected to the output terminal of the sixth latch;

[0402] The control electrode of the fourth control transistor is electrically connected to the input terminal of the third latch, the first electrode of the fourth control transistor is electrically connected to the input terminal of the seventh latch, and the second electrode of the fourth control transistor is electrically connected to the input terminal of the sixth latch;

[0403] The control electrode of the fifth control transistor is electrically connected to the output terminal of the fourth latch, the first electrode of the fifth control transistor is electrically connected to the input terminal of the eighth latch, and the second electrode of the fifth control transistor is electrically connected to the output terminal of the ninth latch;

[0404] The control electrode of the sixth control transistor is electrically connected to the input end of the fourth latch, the first electrode of the sixth control transistor is electrically connected to the input end of the tenth latch, and the second electrode of the sixth control transistor is electrically connected to the input end of the ninth latch.

[0405] Optionally, the first data writing circuit includes a first writing transistor, the second data writing circuit includes a second writing transistor, the third data writing circuit includes a third writing transistor, and the fourth data writing circuit includes a fourth writing transistor;

[0406] The control electrode of the first write transistor is electrically connected to the first scan terminal, the first electrode of the first write transistor is electrically connected to the first data voltage terminal, and the second electrode of the first write transistor is electrically connected to the first data access terminal;

[0407] The control electrode of the second write transistor is electrically connected to the second scan terminal, the first electrode of the second write transistor is electrically connected to the second data voltage terminal, and the second electrode of the second write transistor is electrically connected to the second data access terminal;

[0408] The control electrode of the third write transistor is electrically connected to the third scan terminal, the first electrode of the third write transistor is electrically connected to the third data voltage terminal, and the second electrode of the third write transistor is electrically connected to the third data access terminal;

[0409] The control electrode of the fourth write transistor is electrically connected to the fourth scan end, the first electrode of the fourth write transistor is electrically connected to the fourth data voltage end, and the second electrode of the fourth write transistor is electrically connected to the fourth data access end.

[0410] As shown in FIG9 , based on at least one embodiment of the pixel circuit shown in FIG8 , the first latch includes a first inverter F1 and a second inverter F2;

[0411] The input end of the first inverter F1 is electrically connected to the input end of the first latch, and the output end of the first inverter F1 is electrically connected to the output end of the first latch;

[0412] The input end of the second inverter F2 is electrically connected to the output end of the first inverter F1, and the output end of the second inverter F2 is electrically connected to the input end of the first inverter F1;

[0413] The second latch includes a third inverter F3 and a fourth inverter F4;

[0414] The input end of the third inverter F3 is electrically connected to the input end of the second latch, and the output end of the third inverter F3 is electrically connected to the output end of the second latch;

[0415] The input end of the fourth inverter F4 is electrically connected to the output end of the third inverter F3, and the output end of the fourth inverter F4 is electrically connected to the input end of the third inverter F3;

[0416] The third latch includes a fifth inverter F5 and a sixth inverter F6;

[0417] The input end of the fifth inverter F5 is electrically connected to the input end of the third latch, and the output end of the fifth inverter F5 is electrically connected to the output end of the third latch;

[0418] The input end of the sixth inverter F6 is electrically connected to the output end of the fifth inverter F5, and the output end of the sixth inverter F6 is electrically connected to the input end of the fifth inverter F5;

[0419] The fourth latch includes a seventh inverter F7 and an eighth inverter F8;

[0420] The input end of the seventh inverter F7 is electrically connected to the input end of the fourth latch, and the output end of the seventh inverter F7 is electrically connected to the output end of the fourth latch;

[0421] The input end of the eighth inverter F8 is electrically connected to the output end of the seventh inverter F7, and the output end of the eighth inverter F8 is electrically connected to the input end of the seventh inverter F7;

[0422] The fifth latch includes a ninth inverter F9 and a tenth inverter F10;

[0423] The input end of the ninth inverter F9 is electrically connected to the input end of the fifth latch, and the output end of the ninth inverter F9 is electrically connected to the output end of the fifth latch;

[0424] The input end of the tenth inverter F10 is electrically connected to the output end of the ninth inverter F9, and the output end of the tenth inverter F10 is electrically connected to the input end of the fifth inverter F5;

[0425] The sixth latch includes an eleventh inverter F11 and a twelfth inverter F12;

[0426] The input end of the eleventh inverter F11 is electrically connected to the input end of the sixth latch, and the output end of the eleventh inverter F11 is electrically connected to the output end of the sixth latch;

[0427] The input end of the twelfth inverter F12 is electrically connected to the output end of the eleventh inverter F11, and the output end of the twelfth inverter F12 is electrically connected to the input end of the eleventh inverter F11;

[0428] The seventh latch includes a thirteenth inverter F13 and a fourteenth inverter F14;

[0429] The input end of the thirteenth inverter F13 is electrically connected to the input end of the seventh latch, and the output end of the thirteenth inverter F13 is electrically connected to the output end of the seventh latch;

[0430] The input end of the fourteenth inverter F14 is electrically connected to the output end of the thirteenth inverter F13, and the output end of the fourteenth inverter F14 is electrically connected to the input end of the thirteenth inverter F13;

[0431] The eighth latch includes a fifteenth inverter F15 and a sixteenth inverter F16;

[0432] The input end of the fifteenth inverter F15 is electrically connected to the input end of the eighth latch, and the output end of the fifteenth inverter F15 is electrically connected to the output end of the eighth latch;

[0433] The input end of the sixteenth inverter F16 is electrically connected to the output end of the fifteenth inverter F15, and the output end of the sixteenth inverter F16 is electrically connected to the input end of the fifteenth inverter F15;

[0434] The ninth latch includes a seventeenth inverter F17 and an eighteenth inverter F18;

[0435] The input end of the seventeenth inverter F17 is electrically connected to the input end of the ninth latch, and the output end of the seventeenth inverter F17 is electrically connected to the output end of the ninth latch;

[0436] The input end of the eighteenth inverter F18 is electrically connected to the output end of the seventeenth inverter F17, and the output end of the eighteenth inverter F18 is electrically connected to the input end of the seventeenth inverter F17;

[0437] The tenth latch includes a nineteenth inverter F19 and a twentieth inverter F20;

[0438] The input end of the nineteenth inverter F19 is electrically connected to the input end of the tenth latch, and the output end of the nineteenth inverter S19 is electrically connected to the output end of the tenth latch;

[0439] The input end of the 20th inverter F20 is electrically connected to the output end of the 19th inverter F19, and the output end of the 20th inverter F20 is electrically connected to the input end of the 19th inverter F19;

[0440] The first control switch is a first control transistor TC1, the second control switch is a second control transistor TC2; the third control switch is a third control transistor TC3, the fourth control switch is a fourth control transistor TC4; the fifth control switch is a fifth control transistor TC5, and the sixth control switch is a sixth control transistor TC6;

[0441] The gate of the first control transistor TC1 is electrically connected to the output terminal of the first latch S1, the drain of the first control transistor TC1 is electrically connected to the input terminal of the third latch S3, and the source of the first control transistor TC1 is electrically connected to the output terminal of the second latch S2;

[0442] The gate of the second control transistor TC2 is electrically connected to the input terminal of the first latch S1, the drain of the second control transistor TC2 is electrically connected to the input terminal of the fourth latch S4, and the source of the second control transistor TC2 is electrically connected to the input terminal of the second latch S2;

[0443] The gate of the third control transistor TC3 is electrically connected to the output terminal of the third latch S3, the drain of the third control transistor TC3 is electrically connected to the input terminal of the fifth latch S5, and the source of the third control transistor TC3 is electrically connected to the output terminal of the sixth latch S6;

[0444] The gate of the fourth control transistor TC4 is electrically connected to the input terminal of the third latch S3, the drain of the fourth control transistor TC4 is electrically connected to the input terminal of the seventh latch S7, and the source of the fourth control transistor TC4 is electrically connected to the input terminal of the sixth latch S6;

[0445] The gate of the fifth control transistor TC5 is electrically connected to the output terminal of the fourth latch S4, the drain of the fifth control transistor TC5 is electrically connected to the input terminal of the eighth latch S8, and the source of the fifth control transistor TC5 is electrically connected to the output terminal of the ninth latch S9;

[0446] The gate of the sixth control transistor TC6 is electrically connected to the input terminal of the fourth latch S4, the drain of the sixth control transistor TC6 is electrically connected to the input terminal of the tenth latch S10, and the source of the sixth control transistor TC6 is electrically connected to the input terminal of the ninth latch S9;

[0447] The first data write circuit includes a first write transistor TW1, the second data write circuit includes a second write transistor TW2, the third data write circuit includes a third write transistor TW3, and the fourth data write circuit includes a fourth write transistor TW4;

[0448] The gate of the first write transistor TW1 is electrically connected to the first scan terminal G1, the drain of the first write transistor TW1 is electrically connected to the first data voltage terminal D1, and the source of the first write transistor TW1 is electrically connected to the first data access terminal DI1;

[0449] The gate of the second write transistor TW2 is electrically connected to the second scan terminal G2, the drain of the second write transistor TW2 is electrically connected to the second data voltage terminal D2, and the source of the second write transistor TW2 is electrically connected to the second data access terminal DI2;

[0450] The gate of the third write transistor TW3 is electrically connected to the third scan terminal G3, the drain of the third write transistor TW3 is electrically connected to the third data voltage terminal D3, and the source of the third write transistor TW3 is electrically connected to the third data access terminal DI3;

[0451] The gate of the fourth write transistor TW4 is electrically connected to the fourth scan terminal G4, the drain of the fourth write transistor TW4 is electrically connected to the fourth data voltage terminal D4, and the source of the fourth write transistor TW4 is electrically connected to the fourth data access terminal DI4;

[0452] The first switch control subcircuit includes a first switch control transistor TK1;

[0453] The gate of the first switch control transistor TK1 is electrically connected to the first switch control terminal A, the drain of the first switch control transistor TK1 is electrically connected to the first light emission control voltage terminal VC1, and the source of the first switch control transistor TK1 is electrically connected to the control voltage input terminal I1;

[0454] The second switch control subcircuit includes a second switch control transistor TK2;

[0455] The gate of the second switch control transistor TK2 is electrically connected to the second switch control terminal B, the drain of the second switch control transistor TK2 is electrically connected to the second light emitting control voltage terminal VC2, and the source of the second switch control transistor TK2 is electrically connected to the control voltage input terminal I1;

[0456] The third switch control subcircuit includes a third switch control transistor TK3;

[0457] The gate of the third switch control transistor TK3 is electrically connected to the third switch control terminal C, the drain of the third switch control transistor TK3 is electrically connected to the third light emitting control voltage terminal VC2, and the source of the third switch control transistor TK3 is electrically connected to the control voltage input terminal I1;

[0458] The fourth switch control subcircuit includes a fourth switch control transistor TK4;

[0459] The gate of the fourth switch control transistor TK4 is electrically connected to the fourth switch control terminal D, the drain of the fourth switch control transistor TK4 is electrically connected to the fourth light emitting control voltage terminal VC4, and the source of the fourth switch control transistor TK4 is electrically connected to the control voltage input terminal I1;

[0460] The fifth switch control sub-circuit includes a fifth switch control transistor TK5;

[0461] The gate of the fifth switch control transistor TK5 is electrically connected to the fifth switch control terminal E, the drain of the fifth switch control transistor TK5 is electrically connected to the fifth light-emitting control voltage terminal VC5, and the source of the fifth switch control transistor TK5 is electrically connected to the control voltage input terminal I1;

[0462] The sixth switch control sub-circuit includes a sixth switch control transistor TK6;

[0463] The gate of the sixth switch control transistor TK6 is electrically connected to the sixth switch control terminal F, the drain of the sixth switch control transistor TK6 is electrically connected to the sixth light-emitting control voltage terminal VC6, and the source of the sixth switch control transistor TK6 is electrically connected to the control voltage input terminal I1;

[0464] The seventh switch control sub-circuit includes a seventh switch control transistor TK7;

[0465] A gate of the seventh switch control transistor TK7 is electrically connected to the seventh switch control terminal G, a drain of the seventh switch control transistor TK7 is electrically connected to the seventh light-emitting control voltage terminal VC7, and a source of the seventh switch control transistor TK7 is electrically connected to the control voltage input terminal I1;

[0466] The eighth switch control sub-circuit includes an eighth switch control transistor TK8;

[0467] The gate of the eighth switch control transistor TK8 is electrically connected to the eighth switch control terminal H, the drain of the eighth switch control transistor TK8 is electrically connected to the eighth light emitting control voltage terminal VC8, and the source of the eighth switch control transistor TK8 is electrically connected to the control voltage input terminal I1;

[0468] The light emitting control circuit includes a light emitting control transistor TE;

[0469] The gate of the light emitting control transistor TE is electrically connected to the light emitting control terminal EM, the drain of the light emitting control transistor TE is electrically connected to the control voltage input terminal I1, the source of the light emitting control transistor TE is electrically connected to the anode of M1, and the cathode of M1 is electrically connected to the low voltage terminal VSS.

[0470] In at least one embodiment of the pixel circuit shown in FIG. 9 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0471] When at least one embodiment of the pixel circuit shown in FIG9 of the present disclosure is in operation, as shown in FIG10 , a display cycle may include a first writing phase tw1 , a second writing phase tw2 , a third writing phase tw3 , a fourth writing phase tw4 and a light emitting phase te which are sequentially arranged;

[0472] In the first writing phase tw1 , G1 provides a high voltage signal, G2 , G3 , and G4 all provide low voltage signals, and D1 provides a first data voltage Vdata1 to the first data access terminal DI1 ;

[0473] In the second writing phase tw2, G2 provides a high voltage signal, G1, G3 and G4 all provide low voltage signals, and D2 provides a second data voltage Vdata2 to the second data access terminal DI2;

[0474] In the third writing phase tw3, G3 provides a high voltage signal, G1, G2 and G4 all provide low voltage signals, and D3 provides a third data voltage Vdata3 to the third data access terminal DI3;

[0475] In the fourth writing phase tw4, G4 provides a high voltage signal, G1, G2 and G3 all provide low voltage signals, and D4 provides a fourth data voltage Vdata4 to the fourth data access terminal DI4;

[0476] When Vdata1 is a low voltage signal, Vdata2 is a low voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a low voltage signal, the gate of K1 is connected to a high voltage signal, the gate of K2 is connected to a low voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to a high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input end of S7 is connected to a low voltage signal, and S7 outputs a high voltage signal to the fourth switch control end D; in the light-emitting stage te, TK4 is turned on, TE is turned on, the drain of TE is connected to the fourth light-emitting control voltage, and M1 emits light;

[0477] When Vdata1 is a high voltage signal, Vdata2 is a low voltage signal, Vata3 is a low voltage signal, and Vdata4 is a low voltage signal, S1 outputs a low voltage signal, K1 is turned off, S2 outputs a high voltage signal, K2 is turned on, the input end of S4 is connected to the low voltage signal, the control end of K5 is connected to the high voltage signal, K5 is turned on, K6 is turned off, the input end of S9 is connected to the low voltage signal, S9 outputs a high voltage signal, and provides the high voltage signal to the fifth switch control end E through K5; in the light-emitting stage te, TK5 is turned on, TE is turned on, the drain of TE is connected to the fifth light-emitting control voltage, and M1 emits light;

[0478] When Vdata1 is a low voltage signal, Vdata2 is a high voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a low voltage signal, S1 outputs a high voltage signal, K1 is turned on, K2 is turned off, S2 outputs a low voltage signal, the input end of S3 is connected to the low voltage signal, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, S6 outputs a high voltage signal, and S6 provides the high voltage signal to the first switch control terminal A through the turned-on K3; in the light-emitting stage te, TK1 is turned on, TE is turned on, the drain of TE is connected to the first light-emitting control voltage, and M1 emits light;

[0479] When Vdata1 is a low voltage signal, Vdata2 is a low voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a low voltage signal, S1 outputs a high voltage signal, S2 provides a high voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to the high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input end of S7 is connected to the high voltage signal, and the high voltage signal is written to the third switch control end C; in the light-emitting stage te, TK3 is turned on, TE is turned on, the drain of TE is connected to the third light-emitting control voltage, and M1 emits light;

[0480] When Vdata1 is a low voltage signal, Vdata2 is a low voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a high voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to a high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input end of S6 is connected to a low voltage signal, the input end of S7 is connected to a low voltage signal, and S7 outputs a high voltage signal to the fourth switch control end D; in the light-emitting stage te, TK4 is turned on, TE is turned on, the drain of TE is connected to the fourth light-emitting control voltage, and M1 emits light;

[0481] When Vdata1 is a high voltage signal, Vdata2 is a high voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a low voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to a high voltage signal, S4 outputs a low voltage signal, K7 is turned off, K8 is turned on, the input end of S9 is connected to a low voltage signal, the input end of S10 is connected to a low voltage signal, and S10 outputs a high voltage signal to the eighth switch control terminal H; in the light-emitting stage te, TK8 is turned on, TE is turned on, the drain of TE is connected to the eighth light-emitting control voltage, and M1 emits light;

[0482] When Vdata1 is a high voltage signal, Vdata2 is a high voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a high voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to a high voltage signal, S4 outputs a low voltage signal, K7 is turned off, K8 is turned on, the input end of S9 is connected to a high voltage signal, the input end of S10 is connected to a high voltage signal, and S10 outputs a low voltage signal, so as to write the high voltage signal into the seventh switch control end G; in the light-emitting stage te, TK7 is turned on, TE is turned on, the drain of TE is connected to the seventh light-emitting control voltage, and M1 emits light;

[0483] When Vdata1 is a high voltage signal, Vdata2 is a high voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a low voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, K1 is turned off, and K2 is turned on; the input end of S4 is connected to a high voltage signal, S4 outputs a low voltage signal, K7 is turned off, K8 is turned on, the input end of S9 is connected to a low voltage signal, S9 outputs a high voltage signal, the input end of S10 is connected to a low voltage signal, and S10 outputs a high voltage signal to the eighth switch control terminal H; in the light-emitting stage te, TK8 is turned on, TE is turned on, the drain of TE is connected to the eighth light-emitting control voltage, and M1 emits light;

[0484] When Vdata1 is a high voltage signal, Vdata2 is a high voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a high voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to the high voltage signal, S4 outputs a low voltage signal, K7 is turned off, K8 is turned on, the input end of S9 is connected to the high voltage signal, S9 outputs a low voltage signal, the input end of S10 is connected to the high voltage signal, S10 outputs a low voltage signal, so as to provide the high voltage signal to the seventh switch control end G; in the light-emitting stage te, TK7 is turned on, TE is turned on, the drain of TE is connected to the seventh light-emitting control voltage, and M1 emits light;

[0485] When Vdata1 is a high voltage signal, Vdata2 is a low voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a high voltage signal, S1 outputs a low voltage signal, S2 outputs a high voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to the low voltage signal, S4 outputs a high voltage signal, K7 is turned on, K8 is turned off, the input end of S9 is connected to the high voltage signal, S9 outputs a low voltage signal to the input end of S8, and S8 outputs a high voltage signal to the sixth switch control end F; in the light-emitting stage te, TK6 is turned on, TE is turned on, the drain of TE is connected to the sixth light-emitting control voltage, and M1 emits light;

[0486] When Vdata1 is a high voltage signal, Vdata2 is a low voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a high voltage signal, S1 outputs a low voltage signal, S2 provides a high voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to the low voltage signal, S4 outputs a high voltage signal, K7 is turned on, K8 is turned off, the input end of S9 is connected to the high voltage signal, S9 outputs a low voltage signal to the input end of S8, and S8 outputs a high voltage signal to the sixth switch control end F; in the light-emitting stage te, TK6 is turned on, TE is turned on, the drain of TE is connected to the sixth light-emitting control voltage, and M1 emits light;

[0487] When Vdata1 is a high voltage signal, Vdata2 is a low voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a low voltage signal, S1 outputs a low voltage signal, S2 provides a high voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to the low voltage signal, S4 outputs a high voltage signal, K7 is turned on, K8 is turned off, the input end of S9 is connected to the low voltage signal, S9 outputs a high voltage signal to the input end of S8, S8 outputs a low voltage signal, and S9 outputs a high voltage signal to the fifth switch control end E; in the light-emitting stage te, TK5 is turned on, TE is turned on, the drain of TE is connected to the fifth light-emitting control voltage, and M1 emits light;

[0488] When Vdata1 is a low voltage signal, Vdata2 is a high voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a low voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to a low voltage signal, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, the input end of S6 is connected to a high voltage signal, S6 outputs a low voltage signal, the input end of S5 is connected to a low voltage signal, and S5 outputs a high voltage signal to the second switch control end B; in the light-emitting stage te, TK2 is turned on, TE is turned on, the drain of TE is connected to the second light-emitting control voltage, and M1 emits light;

[0489] When Vdata1 is a low voltage signal, Vdata2 is a high voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a low voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to the low voltage signal, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, the input end of S6 is connected to the low voltage signal, and S6 outputs a high voltage signal to the first switch control end A; in the light-emitting stage te, TK1 is turned on, TE is turned on, the drain of TE is connected to the first light-emitting control voltage, and M1 emits light;

[0490] When Vdata1 is a low voltage signal, Vdata2 is a high voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a low voltage signal, S1 outputs a high voltage signal, S2 outputs a low voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to a low voltage signal, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, the input end of S6 is connected to a high voltage signal, S6 outputs a low voltage signal to the input end of S5, and S5 outputs a high voltage signal to the second switch control end B; in the light-emitting stage te, TK2 is turned on, TE is turned on, the drain of TE is connected to the second light-emitting control voltage, and M1 emits light;

[0491] When Vdata1 is a low voltage signal, Vdata2 is a low voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a high voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to the high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input end of S6 is connected to the high voltage signal, the input end of S7 is connected to the high voltage signal, S7 outputs a low voltage signal, and the high voltage signal is provided to the third switch control end C; in the light-emitting stage te, TK3 is turned on, TE is turned on, the drain of TE is connected to the third light-emitting control voltage, and M1 emits light.

[0492] In at least one embodiment of the present disclosure, the light emitting circuit may include an amplitude control subcircuit, a driving subcircuit, a first on / off control subcircuit, and a light emitting element; the first terminal of the driving subcircuit is electrically connected to the second voltage terminal;

[0493] The amplitude control subcircuit is used to control the driving current generated by the driving subcircuit according to the display data voltage;

[0494] The light emitting control circuit is used to control the connection between the control voltage input terminal and the control terminal of the first on-off control subcircuit under the control of the light emitting control signal;

[0495] The control end of the first on-off control subcircuit is electrically connected to the light-emitting control circuit, the first end of the first on-off control subcircuit is electrically connected to the second end of the driving subcircuit, and the second end of the first on-off control subcircuit is electrically connected to the light-emitting element; the first on-off control subcircuit is used to control the connection between the driving subcircuit and the light-emitting element under the control of the potential of its control end.

[0496] In at least one embodiment of the present disclosure, the second voltage terminal may be a high voltage terminal, but is not limited thereto.

[0497] Optionally, the amplitude control subcircuit includes a data writing subcircuit, an energy storage subcircuit and a reset subcircuit;

[0498] The data writing sub-circuit is electrically connected to the first scan line, the data line and the control terminal of the driving sub-circuit respectively, and is used to write the data voltage provided by the data line into the control terminal of the driving sub-circuit under the control of the first scan signal provided by the first scan line;

[0499] The reset sub-circuit is electrically connected to the first scan line, the reset voltage terminal and the second terminal of the driving sub-circuit respectively, and is used to control the reset voltage provided by the reset voltage terminal to be written into the second terminal of the driving sub-circuit under the control of the first scan signal;

[0500] The energy storage subcircuit is electrically connected to the control terminal of the driving subcircuit and the second terminal of the driving subcircuit respectively, and is used for storing electrical energy;

[0501] The driving sub-circuit is used to generate a driving current under the control of the potential of its control terminal.

[0502] Optionally, the amplitude control subcircuit includes a data writing subcircuit and an energy storage subcircuit;

[0503] The data writing sub-circuit is electrically connected to the scan line, the data line and the control terminal of the driving sub-circuit respectively, and the data writing sub-circuit is used to write the voltage of the data provided by the data line into the control terminal of the driving sub-circuit under the control of the scan signal provided by the scan line;

[0504] The energy storage subcircuit is electrically connected to the control terminal and the first common electrode terminal of the driving subcircuit respectively, and is used for storing electric energy;

[0505] The driving sub-circuit is used to generate a driving current under the control of the potential of its control terminal.

[0506] As shown in FIG11 , at least one embodiment of the light-emitting circuit may include an amplitude control subcircuit 110, a driving subcircuit 111, a first on / off control subcircuit 112, and a light-emitting element 10; a first terminal of the driving subcircuit 111 is electrically connected to the second voltage terminal V2;

[0507] The amplitude control subcircuit 110 is electrically connected to the driving subcircuit 111 and is used to control the driving current generated by the driving subcircuit 111 according to the display data voltage;

[0508] The light emitting control circuit 11 is used to control the connection between the control voltage input terminal I1 and the control terminal of the first on-off control subcircuit 112 under the control of the light emitting control signal;

[0509] The control end of the first on-off control subcircuit 112 is electrically connected to the light emitting control circuit 11, the first end of the first on-off control subcircuit 112 is electrically connected to the second end of the driving subcircuit 111, and the second end of the first on-off control subcircuit 112 is electrically connected to the first electrode of the light emitting element 10; the first on-off control subcircuit 112 is configured to control the communication between the driving subcircuit 111 and the light emitting element 10 under the control of the potential of the control end thereof;

[0510] The second electrode of the light emitting element 10 is electrically connected to the first voltage terminal V1 .

[0511] Optionally, the first voltage terminal V1 may be a low voltage terminal.

[0512] As shown in FIG12 , based on at least one embodiment of the light emitting circuit shown in FIG11 , the amplitude control subcircuit may include a data writing subcircuit 121 , an energy storage subcircuit 122 , and a reset subcircuit 123 ;

[0513] The data writing sub-circuit 121 is electrically connected to the first scan line GT1, the data line DA, and the control terminal of the driving sub-circuit 111, respectively, and is used to write the data voltage provided by the data line DA into the control terminal of the driving sub-circuit 111 under the control of the first scan signal provided by the first scan line GT1; the data line DA is used to provide a display data voltage;

[0514] The reset sub-circuit 123 is electrically connected to the first scan line GT1, the reset voltage terminal R1 and the second terminal of the driving sub-circuit 111 respectively, and is used to control the reset voltage provided by the reset voltage terminal R1 to be written into the second terminal of the driving sub-circuit 111 under the control of the first scan signal;

[0515] The energy storage subcircuit 122 is electrically connected to the control terminal of the driving subcircuit 111 and the second terminal of the driving subcircuit 111 respectively, and is used to store electrical energy;

[0516] The driving sub-circuit 111 is configured to generate a driving current under the control of the potential of its control terminal.

[0517] As shown in FIG13 , based on at least one embodiment shown in FIG11 , the amplitude control subcircuit may include a data writing subcircuit 121 and an energy storage subcircuit 122 ;

[0518] The data writing sub-circuit 121 is electrically connected to the scan line GT, the data line DA and the control terminal of the driving sub-circuit 111 respectively. The data writing sub-circuit 121 is used to write the voltage of the data provided by the data line DA into the control terminal of the driving sub-circuit 111 under the control of the scan signal provided by the scan line GT;

[0519] The energy storage sub-circuit 122 is electrically connected to the control terminal and the first common electrode terminal VM1 of the driving sub-circuit 111 respectively, and is used to store electrical energy;

[0520] The driving sub-circuit 111 is configured to generate a driving current under the control of the potential of its control terminal.

[0521] As shown in FIG14 , based on at least one embodiment shown in FIG13 , the amplitude control subcircuit may further include a second on-off control subcircuit 141 ;

[0522] The second on-off control subcircuit is electrically connected to the light-emitting control terminal EM, the second voltage terminal V2 and the first terminal of the driving subcircuit 111 respectively, and is used to control the connection between the second voltage terminal V2 and the first terminal of the driving subcircuit 111 under the control of the light-emitting control signal provided by the light-emitting control terminal EM.

[0523] As shown in FIG15 , based on at least one embodiment shown in FIG1 , the light emitting element 10 is replaced with at least one embodiment of the light emitting circuit shown in FIG11 ;

[0524] The light emitting control circuit 11 is electrically connected to a control terminal of the first on / off control subcircuit 112 .

[0525] As shown in FIG16 , based on at least one embodiment shown in FIG2 , the light emitting element 10 is replaced with at least one embodiment of the light emitting circuit shown in FIG11 ;

[0526] The light emitting control circuit 11 is electrically connected to a control terminal of the first on / off control subcircuit 112 .

[0527] As shown in FIG17 , based on at least one embodiment shown in FIG5 , the micro-LED M1 is replaced with at least one embodiment of the light-emitting circuit shown in FIG11 ;

[0528] The source of the light emitting control transistor TE is electrically connected to the control terminal of the first on-off control sub-circuit 112 .

[0529] When at least one embodiment of the pixel circuit of the present disclosure as shown in FIG17 is in operation, a display cycle includes a first writing phase, a second writing phase, and a light emitting phase which are arranged in sequence;

[0530] In the first writing phase, G1 provides a high voltage signal, D1 provides a first data voltage Vdata1, and TW1 is turned on to write Vdata1 into the input terminal of S1;

[0531] In the second writing phase, G2 provides a high voltage signal, D1 provides a second data voltage Vdata2, and TW2 is turned on to write Vdata2 into the input terminal of S2;

[0532] When Vdata1 is a low voltage signal and Vdata2 is a low voltage signal, S1 outputs a high voltage signal, S2 outputs a high voltage signal, TC1 is turned on, TC2 is turned off, the input end of S3 is connected to a high voltage signal, the first switch control end A is connected to a low voltage signal, the second switch control end B is connected to a high voltage signal, the potential of the third switch control end C and the potential of the fourth switch control end D are low voltage, TK1 is turned off, TK2 is turned on, TK3 and TK4 are turned off, and I1 is connected to the second light-emitting control voltage; in the light-emitting stage, TE is turned on, and the drain of TE is connected to the second light-emitting control voltage;

[0533] When Vdata1 is a low voltage signal and Vdata2 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a low voltage signal, TC1 is turned on, TC2 is turned off, the input end of S3 is connected to a low voltage signal, the first switch control end A is connected to a high voltage signal, the second switch control end B is connected to a low voltage signal, the potential of the third switch control end C and the potential of the fourth switch control end D are low voltage, TK1 is turned on, TK2 is turned off, TK3 and TK4 are turned off, and I1 is connected to the first light-emitting control voltage; in the light-emitting stage, TE is turned on, and the drain of TE is connected to the first light-emitting control voltage;

[0534] When Vdata1 is a high voltage signal and Vdata2 is a low voltage signal, S1 outputs a low voltage signal, S2 outputs a high voltage signal, TC1 is turned off, TC2 is turned on, the input end of S4 is connected to a low voltage signal, the third switch control end C is connected to a high voltage signal, the fourth switch control end D is connected to a low voltage signal, the potential of the first switch control end A and the potential of the second switch control end B are low voltage, TK3 is turned on, TK4 is turned off, TK1 and TK2 are turned off, and I1 is connected to the third light-emitting control voltage; in the light-emitting stage, TE is turned on, and the drain of TE is connected to the third light-emitting control voltage;

[0535] When Vdata1 is a high voltage signal and Vdata2 is a high voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, TC1 is turned off, TC2 is turned on, the input end of S4 is connected to a high voltage signal, the third switch control end C is connected to a low voltage signal, the fourth switch control end D is connected to a high voltage signal, the potential of the first switch control end A and the potential of the second switch control end B are low voltages, TK4 is turned on, TK3 is turned off, TK1 and TK2 are turned off, and I1 is connected to the fourth light-emitting control voltage; in the light-emitting stage, TE is turned on and the drain of TE is connected to the fourth light-emitting control voltage.

[0536] In at least one embodiment of the pixel circuit of the present disclosure, as shown in FIG17 , when in operation, the first light-emitting control voltage, the second light-emitting control voltage, the third light-emitting control voltage, and the fourth light-emitting control voltage can all be square wave voltage signals, with the duty cycles of the first light-emitting control voltage, the second light-emitting control voltage, the third light-emitting control voltage, and the fourth light-emitting control voltage being different. This allows the on-time of the first on-off control subcircuit to be controlled to be different, resulting in different light-emitting durations of the light-emitting element, thereby enabling low-grayscale display of different grayscale values ​​and improving the uniformity of low-grayscale display. As shown in FIG18 , based on at least one embodiment shown in FIG9 , the micro-LED M1 is replaced with at least one embodiment of the light-emitting circuit shown in FIG11 .

[0537] The source of the light emitting control transistor TE is electrically connected to the control terminal of the first on-off control sub-circuit 112 .

[0538] When at least one embodiment of the pixel circuit shown in FIG18 of the present disclosure is in operation, a display cycle may include a first writing phase, a second writing phase, a third writing phase, a fourth writing phase, and a light emitting phase, which are arranged in sequence;

[0539] In the first writing phase, G1 provides a high voltage signal, G2, G3 and G4 all provide low voltage signals, and D1 provides a first data voltage Vdata1 to the first data access terminal DI1;

[0540] In the second writing phase, G2 provides a high voltage signal, G1, G3 and G4 all provide low voltage signals, and D2 provides a second data voltage Vdata2 to the second data access terminal DI2;

[0541] In the third writing phase, G3 provides a high voltage signal, G1, G2 and G4 all provide low voltage signals, and D3 provides a third data voltage Vdata3 to the third data access terminal DI3;

[0542] In the fourth writing phase, G4 provides a high voltage signal, G1, G2 and G3 all provide low voltage signals, and D4 provides a fourth data voltage Vdata4 to the fourth data access terminal DI4;

[0543] When Vdata1 is a low voltage signal, Vdata2 is a low voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a low voltage signal, the gate of K1 is connected to a high voltage signal, the gate of K2 is connected to a low voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to a high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input end of S7 is connected to a low voltage signal, and S7 outputs a high voltage signal to the fourth switch control end D; in the light-emitting stage, TK4 is turned on, TE is turned on, and the drain of TE is connected to the fourth light-emitting control voltage;

[0544] When Vdata1 is a high voltage signal, Vdata2 is a low voltage signal, Vata3 is a low voltage signal, and Vdata4 is a low voltage signal, S1 outputs a low voltage signal, K1 is turned off, S2 outputs a high voltage signal, K2 is turned on, the input end of S4 is connected to the low voltage signal, the control end of K5 is connected to the high voltage signal, K5 is turned on, K6 is turned off, the input end of S9 is connected to the low voltage signal, S9 outputs a high voltage signal, and provides the high voltage signal to the fifth switch control end E through K5; in the light-emitting stage, TK5 is turned on, TE is turned on, and the drain of TE is connected to the fifth light-emitting control voltage;

[0545] When Vdata1 is a low voltage signal, Vdata2 is a high voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a low voltage signal, S1 outputs a high voltage signal, K1 is turned on, K2 is turned off, S2 outputs a low voltage signal, the input end of S3 is connected to the low voltage signal, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, S6 outputs a high voltage signal, and S6 provides the high voltage signal to the first switch control terminal A through the turned-on K3; in the light-emitting stage, TK1 is turned on, TE is turned on, and the drain of TE is connected to the first light-emitting control voltage;

[0546] When Vdata1 is a low voltage signal, Vdata2 is a low voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a low voltage signal, S1 outputs a high voltage signal, S2 provides a high voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to the high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input end of S7 is connected to the high voltage signal, and the high voltage signal is written to the third switch control terminal C; in the light-emitting stage, TK3 is turned on, TE is turned on, and the drain of TE is connected to the third light-emitting control voltage;

[0547] When Vdata1 is a low voltage signal, Vdata2 is a low voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a high voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to a high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input end of S6 is connected to a low voltage signal, the input end of S7 is connected to a low voltage signal, and S7 outputs a high voltage signal to the fourth switch control end D; in the light-emitting stage, TK4 is turned on, TE is turned on, and the drain of TE is connected to the fourth light-emitting control voltage;

[0548] When Vdata1 is a high voltage signal, Vdata2 is a high voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a low voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to a high voltage signal, S4 outputs a low voltage signal, K7 is turned off, K8 is turned on, the input end of S9 is connected to a low voltage signal, the input end of S10 is connected to a low voltage signal, and S10 outputs a high voltage signal to the eighth switch control terminal H; in the light-emitting stage, TK8 is turned on, TE is turned on, and the drain of TE is connected to the eighth light-emitting control voltage;

[0549] When Vdata1 is a high voltage signal, Vdata2 is a high voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a high voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to a high voltage signal, S4 outputs a low voltage signal, K7 is turned off, K8 is turned on, the input end of S9 is connected to a high voltage signal, the input end of S10 is connected to a high voltage signal, and S10 outputs a low voltage signal, so as to write the high voltage signal into the seventh switch control end G; in the light-emitting stage, TK7 is turned on, TE is turned on, and the drain of TE is connected to the seventh light-emitting control voltage;

[0550] When Vdata1 is a high voltage signal, Vdata2 is a high voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a low voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, K1 is turned off, and K2 is turned on; the input end of S4 is connected to a high voltage signal, S4 outputs a low voltage signal, K7 is turned off, K8 is turned on, the input end of S9 is connected to a low voltage signal, S9 outputs a high voltage signal, the input end of S10 is connected to a low voltage signal, and S10 outputs a high voltage signal to the eighth switch control terminal H; in the light-emitting stage, TK8 is turned on, TE is turned on, and the drain of TE is connected to the eighth light-emitting control voltage;

[0551] When Vdata1 is a high voltage signal, Vdata2 is a high voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a high voltage signal, S1 outputs a low voltage signal, S2 outputs a low voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to the high voltage signal, S4 outputs a low voltage signal, K7 is turned off, K8 is turned on, the input end of S9 is connected to the high voltage signal, S9 outputs a low voltage signal, the input end of S10 is connected to the high voltage signal, S10 outputs a low voltage signal, so as to provide the high voltage signal to the seventh switch control terminal G; in the light-emitting stage, TK7 is turned on, TE is turned on, and the drain of TE is connected to the seventh light-emitting control voltage;

[0552] When Vdata1 is a high voltage signal, Vdata2 is a low voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a high voltage signal, S1 outputs a low voltage signal, S2 outputs a high voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to the low voltage signal, S4 outputs a high voltage signal, K7 is turned on, K8 is turned off, the input end of S9 is connected to the high voltage signal, S9 outputs a low voltage signal to the input end of S8, and S8 outputs a high voltage signal to the sixth switch control end F; in the light-emitting stage, TK6 is turned on, TE is turned on, and the drain of TE is connected to the sixth light-emitting control voltage;

[0553] When Vdata1 is a high voltage signal, Vdata2 is a low voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a high voltage signal, S1 outputs a low voltage signal, S2 provides a high voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to the low voltage signal, S4 outputs a high voltage signal, K7 is turned on, K8 is turned off, the input end of S9 is connected to the high voltage signal, S9 outputs a low voltage signal to the input end of S8, and S8 outputs a high voltage signal to the sixth switch control end F; in the light-emitting stage, TK6 is turned on, TE is turned on, and the drain of TE is connected to the sixth light-emitting control voltage;

[0554] When Vdata1 is a high voltage signal, Vdata2 is a low voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a low voltage signal, S1 outputs a low voltage signal, S2 provides a high voltage signal, K1 is turned off, K2 is turned on, the input end of S4 is connected to the low voltage signal, S4 outputs a high voltage signal, K7 is turned on, K8 is turned off, the input end of S9 is connected to the low voltage signal, S9 outputs a high voltage signal to the input end of S8, S8 outputs a low voltage signal, and S9 outputs a high voltage signal to the fifth switch control end E; in the light-emitting stage, TK5 is turned on, TE is turned on, and the drain of TE is connected to the fifth light-emitting control voltage;

[0555] When Vdata1 is a low voltage signal, Vdata2 is a high voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a low voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to a low voltage signal, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, the input end of S6 is connected to a high voltage signal, S6 outputs a low voltage signal, the input end of S5 is connected to a low voltage signal, and S5 outputs a high voltage signal to the second switch control terminal B; in the light-emitting stage, TK2 is turned on, TE is turned on, and the drain of TE is connected to the second light-emitting control voltage;

[0556] When Vdata1 is a low voltage signal, Vdata2 is a high voltage signal, Vdata3 is a low voltage signal, and Vdata4 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a low voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to the low voltage signal, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, the input end of S6 is connected to the low voltage signal, and S6 outputs a high voltage signal to the first switch control terminal A; in the light-emitting stage, TK1 is turned on, TE is turned on, and the drain of TE is connected to the first light-emitting control voltage;

[0557] When Vdata1 is a low voltage signal, Vdata2 is a high voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a low voltage signal, S1 outputs a high voltage signal, S2 outputs a low voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to the low voltage signal, S3 outputs a high voltage signal, K3 is turned on, K4 is turned off, the input end of S6 is connected to the high voltage signal, S6 outputs a low voltage signal to the input end of S5, and S5 outputs a high voltage signal to the second switch control end B; in the light-emitting stage, TK2 is turned on, TE is turned on, and the drain of TE is connected to the second light-emitting control voltage;

[0558] When Vdata1 is a low voltage signal, Vdata2 is a low voltage signal, Vdata3 is a high voltage signal, and Vdata4 is a high voltage signal, S1 outputs a high voltage signal, S2 outputs a high voltage signal, K1 is turned on, K2 is turned off, the input end of S3 is connected to the high voltage signal, S3 outputs a low voltage signal, K3 is turned off, K4 is turned on, the input end of S6 is connected to the high voltage signal, the input end of S7 is connected to the high voltage signal, S7 outputs a low voltage signal, and the high voltage signal is provided to the third switch control end C; in the light-emitting stage, TK3 is turned on, TE is turned on, and the drain of TE is connected to the third light-emitting control voltage.

[0559] In at least one embodiment of the pixel circuit of the present disclosure as shown in Figure 18, when working, the first light-emitting control voltage, the second light-emitting control voltage, the third light-emitting control voltage, the fourth light-emitting control voltage, the fifth light-emitting control voltage, the sixth light-emitting control voltage, the seventh light-emitting control voltage and the eighth light-emitting control voltage can all be square wave voltage signals, and the duty cycle of the first light-emitting control voltage, the duty cycle of the second light-emitting control voltage, the duty cycle of the third light-emitting control voltage, the duty cycle of the fourth light-emitting control voltage, the duty cycle of the fifth light-emitting control voltage, the duty cycle of the sixth light-emitting control voltage, the duty cycle of the seventh light-emitting control voltage and the duty cycle of the eighth light-emitting control voltage are different, so that the conduction time of the first on-off control subcircuit can be controlled to be different, thereby realizing low grayscale display of different grayscale values ​​and improving the uniformity of low grayscale display.

[0560] As shown in FIG19 , based on at least one embodiment of the pixel circuit shown in FIG17 , the amplitude control subcircuit may include a data writing subcircuit, an energy storage subcircuit, and a reset subcircuit;

[0561] The data writing subcircuit includes a first data writing transistor T1; the energy storage subcircuit includes a storage capacitor C1; the reset subcircuit includes a reset transistor T3; the driving subcircuit includes a driving transistor T0; the first on-off control circuit includes a first on-off control transistor T4; and the light emitting element is a micro light emitting diode M1;

[0562] The source of TE is electrically connected to the gate of T4;

[0563] The gate of T1 is electrically connected to the scan line GT, the drain of T1 is electrically connected to the data line DA, and the source of T1 is electrically connected to the gate of T0;

[0564] The drain of T0 is electrically connected to the high voltage terminal VDD, the source of T0 is electrically connected to the drain of T4, the source of T4 is electrically connected to the anode of M1, and the cathode of M1 is electrically connected to the low voltage terminal VSS;

[0565] A first end of C1 is electrically connected to the gate of T0 , and a second end of C1 is electrically connected to the source of T0 .

[0566] In at least one embodiment shown in FIG. 19 , each transistor is an n-type transistor, but the present invention is not limited thereto.

[0567] When at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure is in operation, GT first provides

[0568] A high voltage signal is provided, turning on T1 and T3 to write the display data voltage provided by DA to the gate of T0 and the reset voltage provided by R1 to the source of T0. Subsequently, EM provides a high voltage signal, turning on TE, and the first, second, third, or fourth light-emitting control voltages are connected to the gate of T4 to control T4 to turn on or off. When T4 is turned on, T0 drives M1 to emit light. As shown in FIG20 , based on at least one embodiment of the pixel circuit shown in FIG17 , the amplitude control subcircuit may include a data writing subcircuit and an energy storage subcircuit.

[0569] The data writing subcircuit includes a first data writing transistor T1 and a second data writing transistor T2; the energy storage subcircuit includes a storage capacitor C1; the driving subcircuit includes a driving transistor T0; the first on-off control circuit includes a first on-off control transistor T4; the light emitting element is a micro light emitting diode M1;

[0570] The source of TE is electrically connected to the gate of T4;

[0571] The first end of C1 is electrically connected to the gate of T0, and the second end of C2 is electrically connected to the first common electrode terminal VM1;

[0572] The gate of T1 is electrically connected to the first scan line GT1, the drain of T1 is electrically connected to the data line DA, the source of T1 is electrically connected to the gate of T0; the drain of T0 is electrically connected to the high voltage terminal VDD;

[0573] The gate of T2 is electrically connected to the second scan line GT2, the source of T2 is electrically connected to the data line DA, and the drain of T2 is electrically connected to the gate of T0;

[0574] The source of T0 is electrically connected to the drain of T4 , the source of T4 is electrically connected to the anode of M1 , and the cathode of M1 is electrically connected to the low voltage terminal VSS.

[0575] In at least one embodiment shown in FIG. 20 , T1 is an n-type transistor and T2 is a p-type transistor, so as to expand the voltage range of the display data voltage provided by the data line DA that can be written into the gate of T0 .

[0576] In at least one embodiment shown in FIG. 20 , T0 and T4 are n-type transistors.

[0577] When at least one embodiment of the pixel circuit of the present disclosure as shown in Figure 20 is in operation, first GT1 provides a high voltage signal or GT2 provides a low voltage signal, and T1 or T2 is turned on to write the display data voltage provided by DA into the gate of T0; then, EM provides a high voltage signal, TE is turned on, and the first light-emitting control voltage, the second light-emitting control voltage, the third light-emitting control voltage or the fourth light-emitting control voltage is connected to the gate of T4 to control T4 to be turned on or off. When T4 is turned on, T0 drives M1 to emit light.

[0578] As shown in FIG21 , based on at least one embodiment of the pixel circuit shown in FIG18 , the amplitude control subcircuit may include a data writing subcircuit, an energy storage subcircuit, and a reset subcircuit;

[0579] The data writing subcircuit includes a first data writing transistor T1; the energy storage subcircuit includes a storage capacitor C1; the reset subcircuit includes a reset transistor T3; the driving subcircuit includes a driving transistor T0; the first on-off control circuit includes a first on-off control transistor T4; and the light emitting element is a micro light emitting diode M1;

[0580] The source of TE is electrically connected to the gate of T4;

[0581] The gate of T1 is electrically connected to the scan line GT, the drain of T1 is electrically connected to the data line DA, and the source of T1 is electrically connected to the gate of T0;

[0582] The drain of T0 is electrically connected to the high voltage terminal VDD, the source of T0 is electrically connected to the drain of T4, the source of T4 is electrically connected to the anode of M1, and the cathode of M1 is electrically connected to the low voltage terminal VSS;

[0583] A first end of C1 is electrically connected to the gate of T0 , and a second end of C1 is electrically connected to the source of T0 .

[0584] In at least one embodiment shown in FIG. 21 , each transistor is an n-type transistor, but the present invention is not limited thereto.

[0585] When at least one embodiment of the pixel circuit of the present disclosure as shown in Figure 21 is working, first GT provides a high voltage signal, T1 and T3 are turned on, so as to write the display data voltage provided by DA into the gate of T0, and write the reset voltage provided by R1 into the source of T0; thereafter, EM provides a high voltage signal, TE is turned on, and the first light-emitting control voltage, the second light-emitting control voltage, the third light-emitting control voltage, the fourth light-emitting control voltage, the fifth light-emitting control voltage, the sixth light-emitting control voltage, the seventh light-emitting control voltage or the eighth light-emitting control voltage is connected to the gate of T4 to control T4 to be turned on or off. When T4 is turned on, T0 drives M1 to emit light.

[0586] As shown in FIG22 , based on at least one embodiment of the pixel circuit shown in FIG18 , the amplitude control subcircuit may include a data writing subcircuit and an energy storage subcircuit;

[0587] The data writing subcircuit includes a first data writing transistor T1 and a second data writing transistor T2; the energy storage subcircuit includes a storage capacitor C1; the driving subcircuit includes a driving transistor T0; the first on-off control circuit includes a first on-off control transistor T4; the light emitting element is a micro light emitting diode M1;

[0588] The source of TE is electrically connected to the gate of T4;

[0589] The first end of C1 is electrically connected to the gate of T0, and the second end of C2 is electrically connected to the first common electrode terminal VM1;

[0590] The gate of T1 is electrically connected to the first scan line GT1, the drain of T1 is electrically connected to the data line DA, the source of T1 is electrically connected to the gate of T0; the drain of T0 is electrically connected to the high voltage terminal VDD;

[0591] The gate of T2 is electrically connected to the second scan line GT2, the source of T2 is electrically connected to the data line DA, and the drain of T2 is electrically connected to the gate of T0;

[0592] The source of T0 is electrically connected to the drain of T4 , the source of T4 is electrically connected to the anode of M1 , and the cathode of M1 is electrically connected to the low voltage terminal VSS.

[0593] In at least one embodiment shown in FIG. 22 , T1 is an n-type transistor and T2 is a p-type transistor, so as to expand the voltage range of the display data voltage provided by the data line DA that can be written into the gate of T0 .

[0594] In at least one embodiment shown in FIG. 22 , T0 and T4 are n-type transistors.

[0595] When at least one embodiment of the pixel circuit of the present disclosure as shown in Figure 22 is working, first GT1 provides a high voltage signal or GT2 provides a low voltage signal, and T1 or T2 is turned on to write the display data voltage provided by DA into the gate of T0; thereafter, EM provides a high voltage signal, TE is turned on, and the first light-emitting control voltage, the second light-emitting control voltage, the third light-emitting control voltage, the fourth light-emitting control voltage, the fifth light-emitting control voltage, the sixth light-emitting control voltage, the seventh light-emitting control voltage or the eighth light-emitting control voltage is connected to the gate of T4 to control T4 to be turned on or off. When T4 is turned on, T0 drives M1 to emit light.

[0596] The display device described in the embodiment of the present disclosure includes a display panel; the display area of ​​the display panel has a plurality of sub-pixels, and the above-mentioned pixel circuit is disposed in each sub-pixel.

[0597] Optionally, the display panel includes a silicon substrate; the pixel circuit is disposed on the silicon substrate. In this case, the transistor included in the pixel circuit may be a CMOS (Complementary Metal Oxide Semiconductor) transistor.

[0598] In at least one embodiment of the present disclosure, the substrate included in the display panel may be a semiconductor substrate, such as a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate of silicon germanium, an SOI (Silicon On Insulator) substrate, etc. The substrate may also include an organic resin material such as epoxy resin, triazine, silicone resin or polyimide. In some example embodiments, the substrate may be an FR4 type printed circuit board (PCB), or may be a flexible PCB that is easily deformed. In some example embodiments, the substrate may include a ceramic material such as silicon nitride, AlN (aluminum nitride) or Al2O3 (aluminum oxide), or a metal or metal compound, or any one of a metal core printed circuit board (MCPCB) and a metal copper clad laminate (MCCL).

[0599] In at least one embodiment of the present disclosure, the display device may be a silicon-based display device, the display panel in the display device includes a silicon substrate, the pixel circuit in the display panel may be a silicon-based field-effect transistor, and the silicon substrate may include silicon elements, such as polycrystalline silicon or single crystal silicon.

[0600] In some embodiments, a silicon-based field-effect transistor (FET), also known as a silicon-based transistor, comprises a silicon substrate, a thin-film microbridge, and at least one thin-film transistor. The silicon substrate comprises at least one microcavity, each of which allows the thin-film microbridge located above the microcavity to be suspended in the air. The thin-film microbridge is disposed above the silicon substrate, and the thin-film transistor is disposed above the center region of each thin-film microbridge. Silicon-based transistors have the following advantages over glass-based thin-film transistors:

[0601] 1. The size of silicon-based transistors is tens to hundreds of nanometers, while the size of glass-based thin-film transistors is several microns to tens of microns. Silicon-based transistors are small in size.

[0602] 2. The on-time of silicon-based transistors is tens of picoseconds, while the on-time of glass-based thin-film transistors is between tens and hundreds of nanoseconds. The on-time of silicon-based transistors is faster.

[0603] 3. The stability of silicon-based transistors is higher than that of transistors prepared on glass substrates, and the pixel driving circuit composed of glass-based transistors does not require compensation for threshold voltage.

[0604] The display device provided in the embodiments of the present disclosure may be any product or component with a display function, such as a watch, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0605] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit comprising a light-emitting circuit, a light-emitting control circuit, a first control circuit, and a switch control circuit; The light-emitting control circuit is electrically connected to the light-emitting control terminal, the control voltage input terminal and the light-emitting circuit respectively, and is used to control the connection between the control voltage input terminal and the light-emitting circuit under the control of the light-emitting control signal provided by the light-emitting control terminal; The light emitting circuit is used to emit light according to the control voltage provided by the control voltage input terminal; The first control circuit is electrically connected to at least two data voltage terminals, at least two scan terminals, and N switch control terminals, respectively, and is configured to control the switch control signals provided to the switch control terminals according to the data voltages provided by the data voltage terminals under the control of the scan signals provided by the scan terminals; N is an integer greater than 1; The switch control circuit includes N switch control terminals, N light emitting control voltage terminals and N switch control sub-circuits; n is a positive integer less than or equal to N; The nth switch control subcircuit is electrically connected to the nth switch control terminal, the nth light-emitting control voltage terminal and the control voltage input terminal respectively, and is used to control the connection between the nth light-emitting control voltage terminal and the control voltage input terminal under the control of the nth switch control signal provided by the nth switch control terminal.

2. The pixel circuit according to claim 1, wherein: The light-emitting control voltage provided by the light-emitting control voltage terminal is a DC voltage, and the light-emitting control voltages provided by the N light-emitting control voltage terminals are different from each other.

3. The pixel circuit according to claim 1, wherein: The light-emitting control voltage provided by the light-emitting control voltage terminal is a square wave voltage signal, and the duty cycles of the light-emitting control voltages provided by the N light-emitting control voltage terminals are different from each other.

4. The pixel circuit according to claim 1, wherein: N is equal to 2 a , a is a positive integer.

5. The pixel circuit according to claim 1, wherein: The first control circuit includes a first data writing circuit, a second data writing circuit and a first control sub-circuit; The first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the first data access terminal respectively, and is used to write the first data voltage provided by the first data voltage terminal into the first data access terminal under the control of the first scanning signal provided by the first scanning terminal; The second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the second data access terminal respectively, and is used to write the second data voltage provided by the second data voltage terminal into the second data access terminal under the control of the second scanning signal provided by the second scanning terminal; The first control subcircuit is electrically connected to the first data access terminal, the second data access terminal and N switch control terminals, respectively, and is used to control the provision of corresponding switch control signals to the N switch control terminals according to the potential of the first data access terminal and the potential of the second data access terminal.

6. The pixel circuit according to claim 5, wherein: The first control subcircuit includes a first latch, a second latch, a third latch, a fourth latch, a first control switch and a second control switch; N is equal to 4; The input end of the first latch is electrically connected to the first data access end, and the output end of the first latch is electrically connected to the control end of the first control switch. The first latch is used to latch the voltage signal input by the first data access end and output a first output voltage. The first output voltage is in opposite phase to the voltage signal input by the first data access end. The input end of the second latch is electrically connected to the second data access end, and the output end of the second latch is electrically connected to the control end of the second control switch. The second latch is used to latch the voltage signal input by the second data access end and output a second output voltage. The second output voltage is inversely proportional to the voltage signal input by the second data access end. The input end of the third latch is electrically connected to the first end of the first control switch, and the output end of the third latch is electrically connected to the first switch control end. The third latch is used to latch the voltage signal input to the input end and output a third output voltage. The third output voltage is inversely proportional to the voltage signal input to the input end of the third latch. The input end of the fourth latch is electrically connected to the first end of the second control switch, and the output end of the fourth latch is electrically connected to the third switch control end. The fourth latch is used to latch the voltage signal input to the input end and output a fourth output voltage. The fourth output voltage is inversely proportional to the voltage signal input to the input end of the fourth latch. The control end of the first control switch is electrically connected to the output end of the first latch, and the second end of the first control switch is electrically connected to the output end of the second latch, and the first control switch is used to control the connection or disconnection between the first end of the first control switch and the second end of the first control switch under the control of the potential of the control end; The control end of the second control switch is electrically connected to the input end of the first latch, and the second end of the second control switch is electrically connected to the input end of the second latch. The second control switch is used to control the connection or disconnection between the first end of the second control switch and the second end of the second control switch under the control of the potential of the control end; The first switch control terminal is electrically connected to the output terminal of the third latch, and the second switch control terminal is electrically connected to the input terminal of the third latch; The third switch control terminal is electrically connected to the output terminal of the fourth latch, and the fourth switch control terminal is electrically connected to the input terminal of the fourth latch.

7. The pixel circuit according to claim 6, wherein: The first latch includes a first inverter and a second inverter; An input terminal of the first inverter is electrically connected to an input terminal of the first latch, and an output terminal of the first inverter is electrically connected to an output terminal of the first latch; The input end of the second inverter is electrically connected to the output end of the first inverter, and the output end of the second inverter is electrically connected to the input end of the first inverter; The second latch includes a third inverter and a fourth inverter; The input end of the third inverter is electrically connected to the input end of the second latch, and the output end of the third inverter is electrically connected to the output end of the second latch; The input end of the fourth inverter is electrically connected to the output end of the third inverter, and the output end of the fourth inverter is electrically connected to the input end of the third inverter; The third latch includes a fifth inverter and a sixth inverter; The input end of the fifth inverter is electrically connected to the input end of the third latch, and the output end of the fifth inverter is electrically connected to the output end of the third latch; The input end of the sixth inverter is electrically connected to the output end of the fifth inverter, and the output end of the sixth inverter is electrically connected to the input end of the fifth inverter; The fourth latch includes a seventh inverter and an eighth inverter; The input end of the seventh inverter is electrically connected to the input end of the fourth latch, and the output end of the seventh inverter is electrically connected to the output end of the fourth latch; The input end of the eighth inverter is electrically connected to the output end of the seventh inverter, and the output end of the eighth inverter is electrically connected to the input end of the seventh inverter.

8. The pixel circuit according to claim 6, wherein: The first control switch is a first control transistor, and the second control switch is a second control transistor; The control electrode of the first control transistor is electrically connected to the output terminal of the first latch, the first electrode of the first control transistor is electrically connected to the input terminal of the third latch, and the second electrode of the first control transistor is electrically connected to the output terminal of the second latch; The control electrode of the second control transistor is electrically connected to the input end of the first latch, the first electrode of the second control transistor is electrically connected to the input end of the fourth latch, and the second electrode of the second control transistor is electrically connected to the input end of the second latch.

9. The pixel circuit according to claim 5, wherein: The first data writing circuit includes a first writing transistor, and the second data writing circuit includes a second writing transistor; The control electrode of the first write transistor is electrically connected to the first scan terminal, the first electrode of the first write transistor is electrically connected to the first data voltage terminal, and the second electrode of the first write transistor is electrically connected to the first data access terminal; The control electrode of the second write transistor is electrically connected to the second scan end, the first electrode of the second write transistor is electrically connected to the second data voltage end, and the second electrode of the second write transistor is electrically connected to the second data access end.

10. The pixel circuit according to claim 1, wherein: The first control circuit includes a first data writing circuit, a second data writing circuit, a third data writing circuit, a fourth data writing circuit and a second control sub-circuit; The first data writing circuit is electrically connected to the first scanning terminal, the first data voltage terminal and the first data access terminal respectively, and is used to write the first data voltage provided by the first data voltage terminal into the first data access terminal under the control of the first scanning signal provided by the first scanning terminal; The second data writing circuit is electrically connected to the second scanning terminal, the second data voltage terminal and the second data access terminal respectively, and is used to write the second data voltage provided by the second data voltage terminal into the second data access terminal under the control of the second scanning signal provided by the second scanning terminal; The third data writing circuit is electrically connected to the third scanning terminal, the third data voltage terminal and the third data access terminal respectively, and is used to write the third data voltage provided by the third data voltage terminal into the third data access terminal under the control of the third scanning signal provided by the third scanning terminal; The fourth data writing circuit is electrically connected to the fourth scanning terminal, the fourth data voltage terminal and the fourth data access terminal respectively, and is used to write the fourth data voltage provided by the fourth data voltage terminal into the fourth data access terminal under the control of the fourth scanning signal provided by the fourth scanning terminal; The second control subcircuit is electrically connected to the first data access terminal, the second data access terminal, the third data access terminal, the fourth data access terminal, and N switch control terminals, respectively, and is configured to control the provision of corresponding switch control signals to the N switch control terminals, respectively, based on the potential of the first data access terminal, the potential of the second data access terminal, the potential of the third data access terminal, and the potential of the fourth data access terminal.

11. The pixel circuit according to claim 10, wherein: The second control subcircuit includes a first latch, a second latch, a third latch, a fourth latch, a fifth latch, a sixth latch, a seventh latch, an eighth latch, a ninth latch, a tenth latch, a first control switch, a second control switch, a third control switch, a fourth control switch, a fifth control switch, and a sixth control switch; N is equal to 8; The input end of the first latch is electrically connected to the first data access end, and the output end of the first latch is electrically connected to the control end of the first control switch. The first latch is used to latch the voltage signal input by the first data access end and output a first output voltage. The first output voltage is in opposite phase to the voltage signal input by the first data access end. The input end of the second latch is electrically connected to the second data access end, and the output end of the second latch is electrically connected to the control end of the second control switch. The second latch is used to latch the voltage signal input by the second data access end and output a second output voltage. The second output voltage is inversely proportional to the voltage signal input by the second data access end. The input end of the third latch is electrically connected to the first end of the first control switch, and the output end of the third latch is electrically connected to the control end of the third control switch. The third latch is used to latch the voltage signal input to the input end and output a third output voltage, and the third output voltage is inversely proportional to the voltage signal input to the input end of the third latch; The input end of the fourth latch is electrically connected to the first end of the second control switch, and the output end of the fourth latch is electrically connected to the control end of the fifth control switch. The fourth latch is used to latch the voltage signal input to the input end and output a fourth output voltage, and the fourth output voltage is inversely proportional to the voltage signal input to the input end of the fourth latch. The input end of the fifth latch is electrically connected to the first end of the third control switch, and the output end of the fifth latch is electrically connected to the second switch control end. The fifth latch is used to latch the voltage signal input to the input end and output a fifth output voltage. The fifth output voltage is inversely proportional to the voltage signal input to the input end of the fifth latch. The input end of the sixth latch is electrically connected to the third data access end, and the output end of the sixth latch is electrically connected to the second end of the third control switch. The sixth latch is used to latch the voltage signal input to the input end and output a sixth output voltage, and the sixth output voltage is inversely proportional to the voltage signal input to the input end of the sixth latch. The input end of the seventh latch is electrically connected to the first end of the fourth control switch, and the output end of the seventh latch is electrically connected to the fourth switch control end. The seventh latch is used to latch the voltage signal input to the input end and output a seventh output voltage. The seventh output voltage is inversely proportional to the voltage signal input to the input end of the seventh latch. The input end of the eighth latch is electrically connected to the first end of the fifth control switch, and the output end of the eighth latch is electrically connected to the sixth switch control end. The eighth latch is used to latch the voltage signal input to the input end and output an eighth output voltage. The eighth output voltage is inversely proportional to the voltage signal input to the input end of the eighth latch. The input end of the ninth latch is electrically connected to the fourth data access end, and the output end of the ninth latch is electrically connected to the second end of the fifth control switch. The ninth latch is used to latch the voltage signal input to the input end and output a ninth output voltage, and the ninth output voltage is inversely proportional to the voltage signal input to the input end of the ninth latch. The input terminal of the tenth latch is electrically connected to the first terminal of the sixth control switch, and the output terminal of the tenth latch is electrically connected to the eighth switch control terminal. The tenth latch is used to latch the voltage signal input to the input terminal and output a tenth output voltage, and the tenth output voltage is inversely proportional to the voltage signal input to the input terminal of the tenth latch. The control end of the first control switch is electrically connected to the output end of the first latch, and the second end of the first control switch is electrically connected to the output end of the second latch, and the first control switch is used to control the connection or disconnection between the first end of the first control switch and the second end of the first control switch under the control of the potential of the control end; The control end of the second control switch is electrically connected to the input end of the first latch, and the second end of the second control switch is electrically connected to the input end of the second latch. The second control switch is used to control the connection or disconnection between the first end of the second control switch and the second end of the second control switch under the control of the potential of the control end; The control end of the third control switch is electrically connected to the output end of the third latch, and the third control switch is used to control the connection or disconnection between the input end of the fifth latch and the output end of the sixth latch under the control of the potential of the control end; The control end of the fourth control switch is electrically connected to the input end of the third latch, and the fourth control switch is used to control the connection or disconnection between the input end of the seventh latch and the input end of the sixth latch under the control of the potential of the control end; The control end of the fifth control switch is electrically connected to the output end of the fourth latch, and the fifth control switch is used to control the input end of the eighth latch to be electrically connected to the output end of the ninth latch under the control of the potential of the control end; The control end of the sixth control switch is electrically connected to the input end of the fourth latch, and the sixth control switch is used to control the connection between the input end of the tenth latch and the input end of the ninth latch under the control of the potential of the control end; The first switch control terminal is electrically connected to the input terminal of the fifth latch, and the seventh switch control terminal is electrically connected to the input terminal of the tenth latch.

12. The pixel circuit according to claim 11, wherein: The first latch includes a first inverter and a second inverter; An input terminal of the first inverter is electrically connected to an input terminal of the first latch, and an output terminal of the first inverter is electrically connected to an output terminal of the first latch; The input end of the second inverter is electrically connected to the output end of the first inverter, and the output end of the second inverter is electrically connected to the input end of the first inverter; The second latch includes a third inverter and a fourth inverter; The input end of the third inverter is electrically connected to the input end of the second latch, and the output end of the third inverter is electrically connected to the output end of the second latch; The input end of the fourth inverter is electrically connected to the output end of the third inverter, and the output end of the fourth inverter is electrically connected to the input end of the third inverter; The third latch includes a fifth inverter and a sixth inverter; The input end of the fifth inverter is electrically connected to the input end of the third latch, and the output end of the fifth inverter is electrically connected to the output end of the third latch; The input end of the sixth inverter is electrically connected to the output end of the fifth inverter, and the output end of the sixth inverter is electrically connected to the input end of the fifth inverter; The fourth latch includes a seventh inverter and an eighth inverter; The input end of the seventh inverter is electrically connected to the input end of the fourth latch, and the output end of the seventh inverter is electrically connected to the output end of the fourth latch; The input end of the eighth inverter is electrically connected to the output end of the seventh inverter, and the output end of the eighth inverter is electrically connected to the input end of the seventh inverter; The fifth latch includes a ninth inverter and a tenth inverter; The input end of the ninth inverter is electrically connected to the input end of the fifth latch, and the output end of the ninth inverter is electrically connected to the output end of the fifth latch; The input end of the tenth inverter is electrically connected to the output end of the ninth inverter, and the output end of the tenth inverter is electrically connected to the input end of the ninth inverter; The sixth latch includes an eleventh inverter and a twelfth inverter; The input end of the eleventh inverter is electrically connected to the input end of the sixth latch, and the output end of the eleventh inverter is electrically connected to the output end of the sixth latch; The input end of the twelfth inverter is electrically connected to the output end of the eleventh inverter, and the output end of the twelfth inverter is electrically connected to the input end of the eleventh inverter; The seventh latch includes a thirteenth inverter and a fourteenth inverter; The input end of the thirteenth inverter is electrically connected to the input end of the seventh latch, and the output end of the thirteenth inverter is electrically connected to the output end of the seventh latch; The input end of the fourteenth inverter is electrically connected to the output end of the thirteenth inverter, and the output end of the fourteenth inverter is electrically connected to the input end of the thirteenth inverter; The eighth latch includes a fifteenth inverter and a sixteenth inverter; The input end of the fifteenth inverter is electrically connected to the input end of the eighth latch, and the output end of the fifteenth inverter is electrically connected to the output end of the eighth latch; The input end of the sixteenth inverter is electrically connected to the output end of the fifteenth inverter, and the output end of the sixteenth inverter is electrically connected to the input end of the fifteenth inverter; The ninth latch includes a seventeenth inverter and an eighteenth inverter; The input end of the seventeenth inverter is electrically connected to the input end of the ninth latch, and the output end of the seventeenth inverter is electrically connected to the output end of the ninth latch; The input end of the eighteenth inverter is electrically connected to the output end of the seventeenth inverter, and the output end of the eighteenth inverter is electrically connected to the input end of the seventeenth inverter; The tenth latch includes a nineteenth inverter and a twentieth inverter; The input end of the nineteenth inverter is electrically connected to the input end of the tenth latch, and the output end of the nineteenth inverter is electrically connected to the output end of the tenth latch; The input terminal of the 20th inverter is electrically connected to the output terminal of the 19th inverter, and the output terminal of the 20th inverter is electrically connected to the input terminal of the 19th inverter.

13. The pixel circuit according to claim 11, wherein: The first control switch is a first control transistor, the second control switch is a second control transistor; the third control switch is a third control transistor, and the fourth control switch is a fourth control transistor; The fifth control switch is a fifth control transistor, and the sixth control switch is a sixth control transistor; The control electrode of the first control transistor is electrically connected to the output terminal of the first latch, the first electrode of the first control transistor is electrically connected to the input terminal of the third latch, and the second electrode of the first control transistor is electrically connected to the output terminal of the second latch; The control electrode of the second control transistor is electrically connected to the input terminal of the first latch, the first electrode of the second control transistor is electrically connected to the input terminal of the fourth latch, and the second electrode of the second control transistor is electrically connected to the input terminal of the second latch; The control electrode of the third control transistor is electrically connected to the output terminal of the third latch, the first electrode of the third control transistor is electrically connected to the input terminal of the fifth latch, and the second electrode of the third control transistor is electrically connected to the output terminal of the sixth latch; The control electrode of the fourth control transistor is electrically connected to the input terminal of the third latch, the first electrode of the fourth control transistor is electrically connected to the input terminal of the seventh latch, and the second electrode of the fourth control transistor is electrically connected to the input terminal of the sixth latch; The control electrode of the fifth control transistor is electrically connected to the output terminal of the fourth latch, the first electrode of the fifth control transistor is electrically connected to the input terminal of the eighth latch, and the second electrode of the fifth control transistor is electrically connected to the output terminal of the ninth latch; The control electrode of the sixth control transistor is electrically connected to the input end of the fourth latch, the first electrode of the sixth control transistor is electrically connected to the input end of the tenth latch, and the second electrode of the sixth control transistor is electrically connected to the input end of the ninth latch.

14. The pixel circuit according to claim 10, wherein: The first data write circuit includes a first write transistor, the second data write circuit includes a second write transistor, the third data write circuit includes a third write transistor, and the fourth data write circuit includes a fourth write transistor; The control electrode of the first write transistor is electrically connected to the first scan terminal, the first electrode of the first write transistor is electrically connected to the first data voltage terminal, and the second electrode of the first write transistor is electrically connected to the first data access terminal; The control electrode of the second write transistor is electrically connected to the second scan terminal, the first electrode of the second write transistor is electrically connected to the second data voltage terminal, and the second electrode of the second write transistor is electrically connected to the second data access terminal; The control electrode of the third write transistor is electrically connected to the third scan terminal, the first electrode of the third write transistor is electrically connected to the third data voltage terminal, and the second electrode of the third write transistor is electrically connected to the third data access terminal; The control electrode of the fourth write transistor is electrically connected to the fourth scan end, the first electrode of the fourth write transistor is electrically connected to the fourth data voltage end, and the second electrode of the fourth write transistor is electrically connected to the fourth data access end.

15. The pixel circuit according to any one of claims 1 to 14, wherein: The light emitting circuit includes a light emitting element; The light emitting control circuit is electrically connected to the first electrode of the light emitting element, and is used to control the connection between the control voltage input terminal and the first electrode of the light emitting element under the control of the light emitting control signal; The second electrode of the light emitting element is electrically connected to the first voltage end.

16. The pixel circuit according to any one of claims 1 to 14, wherein: The light-emitting circuit includes an amplitude control subcircuit, a driving subcircuit, a first on-off control subcircuit and a light-emitting element; the first terminal of the driving subcircuit is electrically connected to the second voltage terminal; The amplitude control subcircuit is used to control the driving current generated by the driving subcircuit according to the display data voltage; The light emitting control circuit is used to control the connection between the control voltage input terminal and the control terminal of the first on-off control subcircuit under the control of the light emitting control signal; The control end of the first on-off control subcircuit is electrically connected to the light-emitting control circuit, the first end of the first on-off control subcircuit is electrically connected to the second end of the driving subcircuit, and the second end of the first on-off control subcircuit is electrically connected to the light-emitting element; the first on-off control subcircuit is used to control the connection between the driving subcircuit and the light-emitting element under the control of the potential of its control end.

17. The pixel circuit according to claim 16, wherein: The amplitude control subcircuit includes a data writing subcircuit, an energy storage subcircuit and a reset subcircuit; The data writing sub-circuit is electrically connected to the first scan line, the data line and the control terminal of the driving sub-circuit respectively, and is used to write the data voltage provided by the data line into the control terminal of the driving sub-circuit under the control of the first scan signal provided by the first scan line; The reset sub-circuit is electrically connected to the first scan line, the reset voltage terminal and the second terminal of the driving sub-circuit respectively, and is used to control the reset voltage provided by the reset voltage terminal to be written into the second terminal of the driving sub-circuit under the control of the first scan signal; The energy storage subcircuit is electrically connected to the control terminal of the driving subcircuit and the second terminal of the driving subcircuit respectively, and is used for storing electrical energy; The driving sub-circuit is used to generate a driving current under the control of the potential of its control terminal.

18. The pixel circuit according to claim 16, wherein: The amplitude control subcircuit includes a data writing subcircuit and an energy storage subcircuit; The data writing sub-circuit is electrically connected to the scan line, the data line and the control terminal of the driving sub-circuit respectively, and the data writing sub-circuit is used to write the voltage of the data provided by the data line into the control terminal of the driving sub-circuit under the control of the scan signal provided by the scan line; The energy storage subcircuit is electrically connected to the control terminal and the first common electrode terminal of the driving subcircuit respectively, and is used for storing electric energy; The driving sub-circuit is used to generate a driving current under the control of the potential of its control terminal.

19. The pixel circuit according to claim 18, wherein: The scan lines include a second scan line and a third scan line; The data writing sub-circuit includes a first data writing transistor and a second data writing transistor; The control electrode of the first data writing transistor is electrically connected to the second scan line, the first electrode of the first data writing transistor is electrically connected to the data line, and the second electrode of the first data writing transistor is electrically connected to the control terminal of the driving sub-circuit; The control electrode of the second data writing transistor is electrically connected to the third scan line, the first electrode of the second data writing transistor is electrically connected to the data line, and the second electrode of the second data writing transistor is electrically connected to the control terminal of the driving sub-circuit; The first data writing transistor is an n-type transistor, and the second data writing transistor is a p-type transistor.

20. The pixel circuit according to any one of claims 1 to 14, wherein: The nth switch control subcircuit includes an nth switch control transistor; The control electrode of the nth switch control transistor is electrically connected to the nth switch control terminal, the first electrode of the nth switch control transistor is electrically connected to the nth light emitting control voltage terminal, and the second electrode of the nth switch control transistor is electrically connected to the control voltage input terminal.

21. The pixel circuit according to any one of claims 1 to 14, wherein: The light emitting control circuit includes a light emitting control transistor; The control electrode of the light emitting control transistor is electrically connected to the light emitting control terminal, the first electrode of the light emitting control transistor is electrically connected to the control voltage input terminal, and the second electrode of the light emitting control transistor is electrically connected to the light emitting circuit.

22. The pixel circuit according to any one of claims 1 to 14, wherein: The light-emitting element included in the light-emitting circuit is a micro light-emitting diode or a sub-millimeter light-emitting diode; the first electrode of the light-emitting element is an anode, and the second electrode of the light-emitting element is a cathode.

23. A display device comprising a display panel; The display area of ​​the display panel has a plurality of sub-pixels, and each sub-pixel is provided with a pixel circuit according to any one of claims 1 to 22.

24. The display device according to claim 23, wherein: The display panel includes a silicon substrate; The pixel circuit is arranged on the silicon substrate.

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