Memory system, operating method thereof, memory controller, and storage medium

Abstract

The embodiment of the invention discloses a memory system and an operation method thereof, a memory controller and a storage medium, and the memory system comprises a memory device which comprises a plurality of word lines; the plurality of storage units coupled with the same word line form at least one physical page; the memory controller is configured to obtain a first parameter of a first physical page in the plurality of physical pages in the process of executing the data inspection operation; the first parameter is a parameter used for generating a target reference voltage in a preset model, and the target reference voltage is used as a reading voltage when a reading operation is executed on the physical page; the plurality of physical pages comprise a first physical page and a second physical page, the first physical page is a target physical page of data inspection operation, and the second physical page is the other physical pages except the first physical page; generating a first parameter of the second physical page according to the first parameter of the first physical page in combination with a position relationship between the second physical page and the first physical page; and storing the first parameters of the first physical page and the second physical page.

Description

Memory system and operating method thereof, memory controller and storage medium TECHNICAL FIELD

[0001] The present application relates to, but is not limited to, a memory system and operating method thereof, a memory controller and a storage medium. BACKGROUND

[0002] With the development of technology, the market size of the integrated circuit industry is becoming larger and larger, and the process and technology of non-volatile memory devices in the entire integrated circuit industry have developed by leaps and bounds in recent years. Among them, the application of NAND type memory is particularly widespread. The NAND type memory realizes the function of data storage by capturing and storing electric charges in the gate dielectric layer of the storage unit it contains. However, as the use time increases, the electric charges stored in the storage unit will change with the increase of the use time, repeated read operations, cross temperature, etc., and thus will affect the correctness of reading the data stored in the storage unit.

[0003] SUMMARY

[0004] In a first aspect, an embodiment of the present application provides a memory system, comprising: a memory device comprising a plurality of word lines; each word line is coupled to a plurality of storage units, and the plurality of storage units coupled to the same word line form at least one physical page; a memory controller coupled to the memory device and configured to: in the process of performing a data patrol operation, obtain a first parameter of a first physical page in a plurality of physical pages; the first parameter is a parameter in a preset model used to generate a target reference voltage, and the target reference voltage is used as a read voltage for the physical page when performing a read operation; the plurality of physical pages include the first physical page and a second physical page, the first physical page is a target physical page of the data patrol operation in the plurality of physical pages, and the second physical page is the remaining physical page in the plurality of physical pages except the first physical page; generate the first parameter of the second physical page according to the first parameter of the first physical page and the positional relationship between the second physical page and the first physical page; save the first parameter of the first physical page and the first parameter of the second physical page.

[0005] In a second aspect, an embodiment of the present application provides a memory controller coupled with at least one memory device, the memory device including a plurality of word lines; each word line is coupled with a plurality of memory cells, and the plurality of memory cells coupled with the same word line form at least one physical page; the memory controller includes an interface, a cache, and a control unit; wherein the control unit is configured to: obtain a first parameter of a first physical page in the plurality of physical pages according to data fed back by the memory device; the first parameter is a parameter in a preset model used to generate a target reference voltage, and the target reference voltage is used as a read voltage when the physical page performs a read operation; the plurality of physical pages include the first physical page and a second physical page, the first physical page is a target physical page of the data patrol operation in the plurality of physical pages, and the second physical page is a remaining physical page other than the first physical page in the plurality of physical pages; generate the first parameter of the second physical page according to the first parameter of the first physical page and in combination with a positional relationship between the second physical page and the first physical page; and save the first parameter of the first physical page and the first parameter of the second physical page in the cache.

[0006] In a third aspect, an embodiment of the present application provides an operation method of a memory system, the operation method including: obtaining a first parameter of a first physical page in a plurality of physical pages in a process of performing a data patrol operation; the first parameter is a parameter in a preset model used to generate a target reference voltage, and the target reference voltage is used as a read voltage when the physical page performs a read operation; the memory system includes at least one memory device, and the memory device includes a plurality of word lines; each word line is coupled with a plurality of memory cells, and the plurality of memory cells coupled with the same word line form at least one physical page; the plurality of physical pages include the first physical page and a second physical page, the first physical page is at least one physical page performing the data patrol operation, and the second physical page is a remaining physical page other than the first physical page in the plurality of physical pages; generating the first parameter of the second physical page according to the first parameter of the first physical page and in combination with a positional relationship between the second physical page and the first physical page; and saving the first parameter of the first physical page and the first parameter of the second physical page.

[0007] In a fourth aspect, an embodiment of the present application provides a storage medium, and the storage medium stores executable instructions, and when the executable instructions are executed, the steps of the operation method of any one of the third aspect can be implemented. BRIEF DESCRIPTION OF DRAWINGS

[0008] In the drawings, like reference numerals refer to same or similar functionalities throughout the several views of the drawings. The drawings are not necessarily to scale. It is to be understood that the drawings merely depict some embodiments in accordance with the disclosure and should not be considered to be limiting of the scope of the disclosure.

[0009] FIG. 1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0010] FIG. 2A is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0011] FIG. 2B is a schematic diagram of an exemplary solid state drive having a memory system according to an embodiment of the present disclosure;

[0012] FIG. 3 is a schematic diagram of an exemplary memory including a peripheral circuit according to an embodiment of the present disclosure;

[0013] FIG. 4 is a schematic diagram of a cross-section of an array of memory cells including NAND type memory strings according to an embodiment of the present disclosure;

[0014] FIG. 5 is a schematic diagram of an exemplary memory device including an array of memory cells and a peripheral circuit according to an embodiment of the present disclosure;

[0015] FIG. 6 is a schematic diagram of an implementation flow of a method of operation performed by a peripheral circuit of a memory device according to an embodiment of the present disclosure;

[0016] FIG. 7A is a schematic diagram of a threshold voltage distribution corresponding to a pair of memory cells including 2 storage bits according to an embodiment of the present disclosure;

[0017] FIG. 7B is a schematic diagram of a threshold voltage distribution corresponding to a pair of memory cells including 3 storage bits according to an embodiment of the present disclosure;

[0018] FIG. 7C is a schematic diagram of a threshold voltage distribution corresponding to a pair of memory cells including 4 storage bits according to an embodiment of the present disclosure;

[0019] FIG. 8 is a schematic diagram of a threshold voltage distribution of a memory cell when a first result is obtained according to an embodiment of the present disclosure;

[0020] FIG. 9 is a schematic diagram of a first parameter of different physical pages as shown in FIG. 7B at a fourth level read voltage L4 according to an embodiment of the present disclosure;

[0021] FIG. 10 is a schematic diagram of a first parameter of different physical pages as shown in FIG. 7B at a seventh level read voltage L7 according to an embodiment of the present disclosure;

[0022] FIG. 11 is a schematic diagram of a preset model according to an embodiment of the present disclosure;

[0023] FIG. 12 is a diagram illustrating a determination of a first preset interval according to an embodiment of the present application;

[0024] FIG. 13 is a diagram illustrating a first method of obtaining a reference read voltage according to an embodiment of the present application;

[0025] FIG. 14 is a diagram illustrating a second method of obtaining a reference read voltage according to an embodiment of the present application;

[0026] FIG. 15 is a diagram illustrating a third method of obtaining a reference read voltage according to an embodiment of the present application;

[0027] FIG. 16 is a diagram illustrating a fourth method of obtaining a reference read voltage according to an embodiment of the present application;

[0028] FIG. 17 is a diagram illustrating a result of confirming a target reference voltage of a second level read voltage L2 according to an embodiment of the present application;

[0029] FIG. 18 is a diagram illustrating a result of confirming a target reference voltage of a fourth level read voltage L4 according to an embodiment of the present application;

[0030] FIG. 19 is a flow chart illustrating a method of operating a memory system according to an embodiment of the present application;

[0031] FIG. 20 is a diagram illustrating an exemplary configuration of a memory system according to an embodiment of the present application;

[0032] FIG. 21 is a block diagram illustrating a memory system according to an embodiment of the present application;

[0033] FIG. 22 is a timing diagram illustrating an exemplary operation of starting a single level read mode according to an embodiment of the present application;

[0034] FIG. 23 is a timing diagram illustrating an exemplary operation of performing a data patrol according to an embodiment of the present application;

[0035] FIG. 24 is a flow chart illustrating a method of operating a memory system according to an embodiment of the present application;

[0036] FIG. 25 is a diagram illustrating an exemplary configuration of a storage medium according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] Exemplary embodiments of the present application will be described more fully hereinafter with reference to the accompanying drawings; however, they are not intended to limit the present application to particular embodiments. Rather, the present application includes all solutions falling within the scope of the present application. The present application can be variously embodied and should not be construed as being limited to only the embodiments set forth herein. Rather, the embodiments are provided so that the present application can be more thoroughly understood and so that the scope of the present application can be completely conveyed to those skilled in the art.

[0038] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon

[0039] Furthermore, the drawings are not necessarily drawn to scale. Like reference numerals in different drawings denote like or similar elements. For the sake of clarity, not all steps, functions or aspects of the implementations are explained in detail. The description is merely exemplary of the principles of the present application. Furthermore, each of the examples given is exemplary and explanatory only. The application is not limited to these examples.

[0040] The flow diagrams shown in the drawings are merely examples and do not necessarily include all steps. For example, some steps can be split into multiple steps, some steps can be combined or partially combined, and the order of the steps can be changed as necessary.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] The memory device in the embodiments of the present application includes, but is not limited to, a three-dimensional NAND type memory. For the convenience of understanding, the three-dimensional NAND type memory is taken as an example for description.

[0043] FIG. 1 illustrates a block diagram of an exemplary system 100 having a memory device, in accordance with some aspects of the present application. The system 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a Virtual Reality (VR) device, an Argument Reality (AR) device, or any other suitable electronic device having a storage. As shown in FIG. 1, the system 100 can include a host 108 and a memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 can be a processor (e.g., a Central Processing Unit (CPU)) or a System of Chip (SoC) (e.g., an Application Processor (AP)) of an electronic device. The host 108 can be configured to send or receive data to or from the memory device 104.

[0044] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104, and communicate with the host 108. In some embodiments, the memory controller 106 is designed for operation in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0045] In some embodiments, the memory controller 106 is designed for operation in a high duty cycle environment, such as a Solid State Disk (SSD) or an embedded Muti Media Card (eMMC) used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., and enterprise storage arrays.

[0046] The memory controller 106 can be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions with respect to data stored in or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translations, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes with respect to data read from or written to the memory device 104.

[0047] The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., the host 108) according to a particular communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, etc.

[0048] The memory controller 106 and the one or more memory devices 104 can be integrated into various types of memory devices, such as included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0049] In one example as shown in FIG. 2A, the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 with a host (e.g., the host 108 in FIG. 1).

[0050] In another example as shown in FIG. 2B, the memory controller 106 and the plurality of memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 with a host (e.g., the host 108 in FIG. 1). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202. FIG. 3 shows a schematic circuit diagram of an exemplary memory device 300 including a peripheral circuit, in accordance with some aspects of the present application. The memory device 300 can be an example of the memory device 104 in FIG. 1. The memory device 300 can include a memory cell array 301 and a peripheral circuit 302 coupled to the memory cell array 301. By way of example, the memory cell array 301 is a three-dimensional NAND type memory cell array, in which the memory cells 306 are NAND type memory cells provided in the form of an array of memory strings 308, each of which extends vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 can hold a continuous analog value, e.g., a voltage or a charge, which depends on the number of electrons captured within a region of the memory cell 306. Each memory cell 306 can be a floating gate type memory cell including a floating gate transistor, or a charge trap type memory cell including a charge trapping transistor.

[0051] In some embodiments, each storage unit 306 is a single-level cell (SLC) that has two possible storage states and thus can store one bit of data. For example, a first storage state "0" can correspond to a first voltage range, and a second storage state "1" can correspond to a second voltage range. In some embodiments, each storage unit 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take on one of three possible programmed levels from an erased state by writing one of three possible nominal storage values to the cell, a fourth nominal storage value can be used for the erased state.

[0052] It is noted that the storage states referred to herein are also referred to as storage states of the storage units of the present disclosure. Different storage units have different numbers of storage states. For example, a SLC type storage unit has two storage states (i.e., two memory states), which include one programmed state and one erased state. For another example, a MLC type storage unit has four storage states, which include one erased state and three programmed states. For yet another example, a TLC type storage unit has eight storage states, which include one erased state and seven programmed states. In some embodiments, a QLC type storage unit has sixteen storage states, which include one erased state and fifteen programmed states.

[0053] As shown in FIG. 3, each memory string 308 can include a bottom select transistor (BSG) 310 (also referred to as a source side select transistor) at its source end and a top select transistor (TSG) 312 (also referred to as a drain side select transistor) at its drain end. The BSG 310 and TSG 312 can be configured to activate a selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled through the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a respective bit line (BL) 316 from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than a threshold voltage of the transistor having the TSG 312) or a deselect voltage (e.g., 0 V) to the respective TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than a threshold voltage of the transistor having the BSG 310) or a deselect voltage (e.g., 0 V) to the respective BSG 310 via one or more BSG lines 315.

[0054] As shown in FIG. 3, the memory strings 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic unit of data for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased at the same time. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and unselected memory blocks 304 in the same face as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be appreciated that in some examples, erase operations can be performed at a half memory block level, at a quarter memory block level, or at a level having any suitable number of memory blocks or any suitable fraction of a memory block. The memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each memory block can be coupled to multiple word lines, with the multiple memory cells coupled by each word line forming one or more physical pages, where the number of physical pages is related to the number of storage bits contained by the memory cells, with, for example, multiple SLCs coupled by each word line forming one physical page, multiple MLCs coupled by each word line forming two physical pages, and multiple TLCs coupled by each word line forming three physical pages. In some specific embodiments, as shown in FIG. 3, the multiple memory cells (one bit of storage) coupled by each word line form one physical page 320. Referring to FIG. 3, each of the plurality of memory cells 306 is coupled to a respective word line 318, and each memory string 308 is coupled to a respective bit line 316 through a respective select transistor (e.g., select transistor (TSG) 312).

[0055] FIG. 4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including a memory string 308 in the example of a NAND, in accordance with some aspects of the present application. As shown in FIG. 4, the NAND memory cell array 301 can include a stack structure 410 including a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically penetrating the gate layers 411 and the insulating layers 412, wherein the channel structure and each gate layer form a memory cell, and the channel structure and the plurality of gate layers in the stack structure 410 form a memory string 308. The gate layers 411 and the insulating layers 412 can be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412.

[0056] The constituent material of the gate layers 411 can include an electrically conductive material. The electrically conductive material includes, but is not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each gate layer 411 includes a metal layer, e.g., a tungsten layer. In some implementations, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 can include a control gate that surrounds a memory cell. The gate layers 411 at the top of the layer stack 410 can laterally extend as upper select gate lines, the gate layers 411 at the bottom of the layer stack 410 can laterally extend as lower select gate lines, and the gate layers 411 that laterally extend between the upper select gate lines and the lower select gate lines can as word line layers.

[0057] In some embodiments, the layer stack 410 can be disposed on a substrate 401. The substrate 401 can include silicon (e.g., single crystalline silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0058] In some embodiments, the memory string 308 includes a channel structure that extends vertically through the layer stack 410. In some implementations, the channel structure includes a channel hole that is filled with a semiconductor material(s) (e.g., as a semiconductor channel) and a dielectric material(s) (e.g., as a memory film). In some implementations, the semiconductor channel includes silicon, e.g., polysilicon. In some implementations, the memory film is a composite dielectric layer that includes a tunneling layer, a storage layer (also referred to as a “charge trapping / storage layer”), and a blocking layer. The channel structure can have a cylindrical shape (e.g., a column shape). According to some implementations, the semiconductor channel, the tunneling layer, the storage layer, and the blocking layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer can include silicon nitride, silicon oxynitride, or any combination thereof. The blocking layer can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film can include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0059] Referring back to FIG. 3, the peripheral circuitry 302 can be coupled to the memory cell array 301 through the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating the operation of the memory cell array 301 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell 306 via the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, FIG. 5 illustrates some exemplary peripheral circuitry including a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, registers 514, an interface 516, and a data bus 518. It should be appreciated that additional peripheral circuitry not shown in FIG. 5 can also be included in some examples.

[0060] The page buffer / sense amplifier 504 can be configured to read data from and program (write) data to the memory cell array 301 in accordance with control signals from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed to the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verify operation to ensure that data has been correctly programmed into the memory cells 306 coupled to a selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306 and amplify a small voltage swing to an identifiable logic level in a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying bit line voltages generated from the voltage generator 510.

[0061] Row decoders / word line drivers 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of memory cell array 301 and to select / deselect word lines 318 of memory blocks 304. Row decoders / word line drivers 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, row decoders / word line drivers 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, row decoders / word line drivers 508 are configured to perform program operations on memory cells 306 coupled to selected word line(s) 318. Voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltages, program voltages, pass voltages, channel boost voltages, verify voltages, etc.), bit line voltages, and source line voltages to be supplied to memory cell array 301.

[0062] Control logic 512 can be coupled to and configured to control the operation of each of the other portions of the peripheral circuitry described above. Registers 514 can be coupled to control logic 512 and include status registers, command registers, and address registers for storing status information, command operation codes (OP codes), and command addresses used to control the operation of each of the peripheral circuitry. Interface 516 can be coupled to control logic 512 and act as a control buffer to buffer and relay control commands received from a host (not shown) to control logic 512 and to buffer and relay status information received from control logic 512 to the host. Interface 516 can also be coupled to column decoders / bit line drivers 506 via data bus 518 and act as a data I / O interface and data buffer to buffer and relay data to and from memory cell array 301.

[0063] The basic principle of a three-dimensional NAND-type memory is that a certain amount of charge is injected into a memory cell by a carrier (electron or hole) crossing a charge barrier to complete the data writing process, and then the stored data can be read according to the threshold voltage when the memory cell is turned on. Therefore, in order to read the correct data, a high-efficiency error correction algorithm with strong error correction capability is usually introduced during data reading.

[0064] However, as the use time increases, the charge stored in the memory cell will change with the increase of the use time, repeated read operations, cross temperature, etc., thereby affecting the correctness of data reading. When the threshold voltage shifts significantly upwards or downwards, the possibility of reading error will be very large when the original read voltage is used to read the data of the memory cell, and when the read error exceeds the error correction capability, it will also cause the data reading of the memory cell to fail.

[0065] In some embodiments, a data scrub operation is widely used in consumer-grade SSDs and enterprise-grade SSDs to maintain the integrity and reliability of stored data through periodic checks and error correction mechanisms. Among them, consumer-grade SSDs are mainly used in consumer products such as personal computers and mobile devices, and are required to have high speed, stability, thinness, etc. Enterprise-grade SSDs are mainly used in high-load scenarios such as data centers and servers, and are required to have high reliability, high performance, large capacity, etc. For example, data centers store a large amount of enterprise data, and servers usually need to process a large amount of real-time data, so there is a very high requirement for the integrity and security of the data. Data scrubbing is an important means to ensure the integrity and reliability of enterprise-grade SSD data, especially in server and data center scenarios, by periodically detecting and checking data, discovering and correcting potential errors, and ensuring the high availability and security of the storage system.

[0066] Next, the process of the data scrub operation is exemplarily described.

[0067] In some embodiments, during the execution of the data scrub operation on a storage block, when the fail bit count (FBC) of the data of the storage unit of the acquired physical page is less than or equal to a first preset threshold, it indicates that the integrity and reliability of the data of the storage unit in the storage block are not affected, and the data scrub operation can be continued on other storage blocks.

[0068] In some embodiments, during the execution of the data scrub operation, when the fail bit count of the data of the storage unit of the acquired physical page exceeds the first preset threshold, the data of the storage unit corresponding to the physical page needs to be corrected and then moved (also known as error correction rewriting), which is equivalent to a refresh operation on the data.

[0069] In some embodiments, during the execution of the data scrub operation, when the fail bit count of the data of the storage unit of the acquired physical page exceeds the first preset threshold, a read retry operation can be triggered to successfully read the correct data through multiple attempts. The read retry operation can usually be performed by querying the retry table provided by the manufacturer. The essence of the read retry operation is an error correction mechanism. The retry table can provide a reference voltage for reading data. By querying the retry table to try to read the voltage deviating from the normal threshold voltage, each storage unit is read again and the error correction algorithm is used for error correction, trying to correctly read the data. If the read error data is corrected, the query of the retry table is stopped. If the read error data cannot be corrected, the retry table is queried until the entire retry table is traversed.

[0070] The above-mentioned re-reading operation mode will increase the number of trial and error and consume more time because the re-reading table needs to be queried piece by piece. In addition, the re-reading table provided by the manufacturer is only a reference value in some specific environment, and the real use scenario is changing, so the re-reading table provided by the manufacturer cannot cover many scenarios, and the data in the re-reading table may not be corrected even if it is traversed, which will waste a lot of processing time. In summary, the re-reading operation mode through repeated polling of the re-reading table consumes a long time and affects the response time of subsequent commands, thereby affecting the performance of the device.

[0071] In other embodiments, during the execution of the data patrol operation, when the failure bit count of the data of the storage unit of the acquired physical page exceeds a second preset threshold, a garbage collection (GC) operation is triggered, that is, the storage block where the corresponding physical page is located is marked as a bad block, and the valid data in the storage block where the corresponding physical page is located is copied to a new storage block, and then the bad block is erased to release the storage space. It can be understood that when the failure bit count of the data of the storage unit of the acquired physical page exceeds the second preset threshold, it indicates that the failure bit count of the data of the storage unit exceeds the maximum error correction capability of the system or the invalid data in the storage block where the corresponding physical page is located reaches the erasure standard.

[0072] Here, the first preset threshold is less than the second preset threshold, wherein the first preset threshold can be understood as the error correction warning value of the data of the storage unit to ensure the integrity and reliability of the data to prevent further expansion of errors or data loss, and can ensure that the re-reading operation or error correction rewriting is performed when the error of the data has not caused serious impact. The second preset threshold can be understood as the upper limit of the correctable range of the data of the storage unit.

[0073] Although the data patrol operation is an important means to maintain the integrity and reliability of the stored data, the re-reading operation triggered in the data patrol operation will affect the efficiency of the data patrol, consume additional system resources and time, in addition, the error correction rewriting operation or garbage collection operation triggered in the data patrol operation will increase the write amplification (WA) effect and affect the system performance.

[0074] Based on one or more of the above problems, in a first aspect, the embodiments of the present application provide a memory system.

[0075] As shown in FIG. 6, the memory system includes a memory device including a plurality of word lines; each word line is coupled to a plurality of storage units, and the plurality of storage units coupled to the same word line form at least one physical page;

[0076] a memory controller coupled to the memory device and configured to perform the following steps:

[0077] Step S10: In the process of performing the data patrol operation, a first parameter of a first physical page in the plurality of physical pages is obtained; the first parameter is a parameter in a preset model used for generating a target reference voltage, the target reference voltage is used as a read voltage for the physical page when performing a read operation; the plurality of physical pages include the first physical page and a second physical page, the first physical page is a target physical page of the data patrol operation in the plurality of physical pages, and the second physical page is a remaining physical page in the plurality of physical pages except the first physical page;

[0078] Step S20: According to the first parameter of the first physical page, the first parameter of the second physical page is generated in combination with a positional relationship between the second physical page and the first physical page.

[0079] Step S30: The first parameter of the first physical page and the first parameter of the second physical page are saved.

[0080] Here, the structure of the memory device is referred to the aforementioned FIG. 3, which will not be repeated here.

[0081] In some embodiments, the memory device includes a memory cell array including a plurality of memory blocks, each memory block including a plurality of physical pages; the first physical page and the second physical page are located in the same memory block.

[0082] It should be noted that, in order to balance resources and time, reduce resource consumption and improve the efficiency of the data patrol operation, the data patrol operation performed during the power-on of the memory system does not need to traverse all the physical pages in a memory block, in other words, the data patrol operation can be performed in a way of sampling data patrol, for example, when performing the data patrol operation on a memory block, the read results of all the physical pages coupled to at least one word line in the memory block are obtained, wherein the first physical page in the memory block is the target physical page of the data patrol operation in the plurality of physical pages, and the second physical page is the remaining physical page in the plurality of physical pages except the first physical page.

[0083] For example, a plurality of memory cells (one bit of storage) coupled to each word line shown in FIG. 3 form a physical page 320. As shown in FIG. 3, each memory block 304 can be coupled to z word lines, where z is a positive integer. In some embodiments, when performing a data patrol operation on a memory block 304, the read results of all physical pages coupled to a word line in the memory block 304 are obtained, i.e., the read results of one physical page are obtained. For example, the read results of the physical page 320 coupled to the xth word line WLx shown in FIG. 3 are obtained. It can be understood that the xth word line WLx is the target word line of the data patrol operation, and the physical page 320 coupled to the xth word line WLx is the target physical page of the data patrol operation, i.e., the first physical page. The x-1 physical pages coupled to the 1st to (x-1)th word lines (WL1, WL2, WL3, WL4 to WLx-1) are the second physical pages.

[0084] It can be understood that when a plurality of SLCs coupled to each word line form a physical page, the read results of all physical pages coupled to a word line in the memory block obtained in the data patrol operation are the read results of one physical page coupled to the word line. When a plurality of MLCs coupled to each word line form two physical pages, the read results of all physical pages coupled to a word line in the memory block obtained in the data patrol operation are the read results of two physical pages coupled to the word line. When a plurality of TLCs coupled to each word line form three physical pages, the read results of all physical pages coupled to a word line in the memory block obtained in the data patrol operation are the read results of three physical pages coupled to the word line. In summary, all physical pages coupled to the target word line of the data patrol operation are the first physical pages.

[0085] FIG. 3 is only an example and is not intended to limit the number of word lines, physical pages, and memory cells, or the specific structure of the memory device in the present application.

[0086] In some embodiments, the period of the data patrol operation generally depends on the specific application scenario and requirements. Generally, the period of the data patrol can be determined according to factors such as data importance and sensitivity, system usage frequency and load, etc. For example, for important or sensitive data, more frequent patrols may be required to ensure data integrity and reliability. High-load systems may require more frequent patrols to cope with data changes and system load.

[0087] Here, during power-up of the memory system, the periodically performed data patrol operation includes data patrol operations on different memory blocks. In the embodiments of the present application, the process of performing a data patrol operation on one of the plurality of memory blocks is taken as an example for illustration.

[0088] In some embodiments, the preset model used to generate the target reference voltage is related to the characteristics of the memory device, and the preset model can be fitted by a large number of experimental results before the memory device is shipped and saved in the memory device.

[0089] Exemplarily, the preset model is encoded into a code, and the code is saved into the firmware or software of the memory device.

[0090] In some embodiments, a large amount of data is collected through a large number of experiments before the memory device is shipped, and can be analyzed after preprocessing by removing outliers, sorting, denoising, etc. The preset model is fitted using statistical methods, machine learning or other modeling techniques, wherein the parameters of the preset model include the first parameter.

[0091] In some embodiments, the preset model is a quadratic function model, and the first parameter is the curvature of the curve of the quadratic function model. The specific way of obtaining the target reference voltage according to the preset model and the first parameter will be further described in the following.

[0092] In some embodiments, the preset model includes a quadratic function model, which includes the following function relationship:

[0093] y = a(x + b) 2 +c

[0094] Wherein, y is the first result, x is the reference read voltage, b is used to represent the prediction parameter, a is the first parameter, and c is the second parameter.

[0095] Exemplarily, using data-driven methods such as machine learning or deep learning, a large number of reference read voltages and corresponding first results are collected, a preset model is established to represent the relationship between the reference read voltage and the first result, and the related parameters (such as the first parameter and the second parameter) of the preset model are obtained.

[0096] The meaning of the first result and the specific way of obtaining the first result are introduced below.

[0097] Here, the first result represents the number of bits that flip in the two read results of the physical page to be executed read operation at the first read voltage and the second read voltage.

[0098] Here, the first read voltage and the second read voltage are both generic concepts, and a difference between the first read voltage and the second read voltage is less than a preset voltage. In some embodiments, the second read voltage is greater than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of 5 mV to 20 mV. For example, the difference between the first read voltage and the second read voltage can be 5 mV, 10 mV, 15 mV, or 20 mV. In other embodiments, the second read voltage is less than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of -5 mV to -20 mV. For example, the difference between the first read voltage and the second read voltage can be -5 mV, -10 mV, -15 mV, or -20 mV.

[0099] In some embodiments, the memory device is configured to: read the stored data of the physical page at the first read voltage to obtain a second result; read the stored data of the physical page at the second read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count a number of bits in the fourth result representing a flip of the third result compared to the second result to obtain the first result.

[0100] In some embodiments, the memory device includes: a first latch, a second latch, and a third latch. The first latch is configured to store the second result. The second latch is configured to store the third result. The third latch is configured to store the fourth result.

[0101] Here, the first read voltage and the second read voltage are associated in sequence, that is, the second read voltage is obtained by a third adjustment based on the first read voltage. Based on this, a difference between the first read voltage and the second read voltage is a third step. In some embodiments, the third step is set to a range of 5 mV to 20 mV. For example, the third step can be 5 mV, 10 mV, 15 mV, or 20 mV. The preset voltage is related to the third step, and can be a voltage slightly greater than the third step. In some embodiments, the preset voltage is set to a range of 6 mV to 21 mV. For example, the preset voltage can be 6 mV, 11 mV, 16 mV, or 21 mV. In other embodiments, the preset voltage is set to a range of -6 mV to -21 mV. For example, the preset voltage can be -6 mV, -10 mV, -16 mV, or -21 mV.

[0102] It is to be noted that the first read voltage and the second read voltage are generic concepts, the target read voltage and the read voltage obtained after the first adjustment and the second adjustment of the target read voltage can be referred to as the first read voltage, and the read voltage obtained after the third adjustment of the first read voltage can be referred to as the second read voltage. That is, the first read voltage is a generic concept, which can be understood as the target read voltage or the target adjusted read voltage (the voltage obtained after the target read voltage is adjusted by a target step, wherein the range of the target step can be set to 20mV to 40mV, and exemplarily, the first step of the first adjustment can be 20mV, 30mV, 40mV, and the range of the target step can also be set to 50mV to 150mV, and exemplarily, the second step of the second adjustment can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV or 150mV).

[0103] In some embodiments, the memory controller is configured to generate the first parameter of the second physical page according to the first parameter of the first physical page, the positional relationship between the second physical page and the first physical page, and a mapping function. The mapping function represents the relationship between the first parameters of the plurality of physical pages.

[0104] It can be understood that when the preset model and the first parameter are fitted by a large number of experimental results before the memory device is shipped, the first parameters of the physical pages coupled to different word lines can be recorded, and the recorded first parameters of the physical pages coupled to different word lines can be analyzed and counted to establish the relationship between the first parameters of the physical pages coupled to different word lines. Exemplarily, the positional relationship between the physical pages coupled to different word lines and the relationship between the first parameters of the physical pages coupled to different word lines can be established according to the collected first parameters of the physical pages coupled to different word lines, and presented in the form of a mapping function.

[0105] In some embodiments, the storage unit has P storage bits, and the P storage bits correspond to 2 P -1 level read voltage; wherein P is an integer greater than or equal to 1; the mapping function includes 2 P -1 first mapping functions corresponding to the 2 P -1 level read voltage, respectively.

[0106] In some embodiments, the P storage bits correspond to P pages, respectively, and the P-bit storage unit reads its P-bit storage data by 2 P -1 level read voltage. It can be understood that the physical pages coupled to the same word line can have different first parameters under different level read voltages, and therefore the first parameters of the physical pages coupled to different word lines can have different relationships under different level read voltages, which are presented in the form of a plurality of first mapping functions, wherein 2P -1 first mapping function can be the same or different.

[0107] For example, when the number of storage bits is 1, the mapping function includes 1 first mapping function, corresponding to the relationship of the first parameter of the physical page coupled to different word lines at the 1st level of read voltage; when the number of storage bits is 2, the mapping function includes 3 first mapping functions, respectively corresponding to the relationship of the first parameter of the physical page coupled to different word lines at the 3rd level of read voltage; when the number of storage bits is 3, the mapping function includes 7 first mapping functions, respectively corresponding to the relationship of the first parameter of the physical page coupled to different word lines at the 7th level of read voltage; when the number of storage bits is 4, the mapping function includes 15 first mapping functions, respectively corresponding to the relationship of the first parameter of the physical page coupled to different word lines at the 15th level of read voltage.

[0108] For example, when the number of storage bits of the storage unit includes two bits, the corresponding storage states include the 0th state to the 4th state, as shown in FIG. 7A, the 4 states are the 0th state (also referred to as the erase state) E, the 1st state (also referred to as the 1st storage state) P1, the 2nd state (also referred to as the 2nd storage state) P2, and the 3rd state (also referred to as the 3rd storage state) P3, and the binary data corresponding to the 4 states are 11, 10, 00, and 01, respectively. Accordingly, the memory device includes two pages, namely, the lower page (LP) and the upper page (UP).

[0109] For example, the two-bit storage unit reads the storage data of the four states of the two bits through three levels of read voltage (the first level of read voltage L1, the second level of read voltage L2, and the third level of read voltage L3 shown in FIG. 7A).

[0110] For example, one page corresponds to multiple levels of read voltage, and the other page corresponds to one level of read voltage. As shown in FIG. 7A, the binary data corresponding to the lower page is 1001, and the first level of read voltage L1 and the third level of read voltage L3 are required to read the lower page. The binary data corresponding to the upper page is 1100, and the second level of read voltage L2 is required to read the upper page.

[0111] For example, when the number of storage bits of the storage unit includes three bits, the corresponding storage states include the 0th state to the 7th state, as shown in FIG. 7B, the 8 states are the 0th state (also referred to as the erase state) E, the 1st state (also referred to as the 1st storage state) P1, the 2nd state (also referred to as the 2nd storage state) P2,..., the 7th state (also referred to as the 7th storage state) P7, and the binary data corresponding to the 8 states are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. Accordingly, the memory device includes three pages, namely, the lower page, the middle page (MP), and the upper page.

[0112] For example, the storage unit shown in FIG. 7B, a three-bit storage unit reads its three-bit eight-state storage data through seven levels of read voltages (the first level read voltage L1, the second level read voltage L2, the third level read voltage L3, the fourth level read voltage L4, the fifth level read voltage L5, the sixth level read voltage L6, and the seventh level read voltage L7 shown in FIG. 7B).

[0113] For example, each page corresponds to multiple levels of read voltages, as shown in FIG. 7B, the binary data corresponding to the lower page is 10000111, respectively, and the lower page requires the first level read voltage L1 and the fifth level read voltage L5 to be read. The binary data corresponding to the middle page is 11001100, respectively, and the middle page requires the second level read voltage L2, the fourth level read voltage L4, and the sixth level read voltage L6 to be read. The binary data corresponding to the upper page is 11100001, respectively, and the upper page requires the third level read voltage L3 and the seventh level read voltage L7 to be read.

[0114] For example, when the storage bit number of the storage unit includes four bits, the corresponding storage state includes the 0th state to the 15th state, as shown in FIG. 7C, the 16 states are the 0th state (also known as the erase state) E, the 1st state (also known as the 1st storage state) P1, the 2nd state (also known as the 2nd storage state) P2, …, the 15th state (also known as the 15th storage state) P15, respectively. The binary data corresponding to the 16 states is 1111, 0111, 0110, …, 1110, respectively. Accordingly, the memory device includes four pages, namely the lower page, the middle page, the upper page, and the extra page (XP). Here, the four storage bits corresponding to the 16 states are stored in the lower page, the middle page, the upper page, and the extra page, respectively.

[0115] For example, the storage unit shown in FIG. 7C, a four-bit storage unit reads its four-bit sixteen-state storage data through 15 levels of read voltages (the first level read voltage L1, the second level read voltage L2, the third level read voltage L3, the fourth level read voltage L4, the fifth level read voltage L5, the sixth level read voltage L6, the seventh level read voltage L7, the eighth level read voltage L8, the ninth level read voltage L9, the tenth level read voltage L10, the eleventh level read voltage L11, the twelfth level read voltage L12, the thirteenth level read voltage L13, the fourteenth level read voltage L14, and the fifteenth level read voltage L15 shown in FIG. 7C).

[0116] Exemplarily, each page corresponds to multiple levels of read voltages, as shown in FIG. 7C, the binary data corresponding to the lower page is 1100000011111100 respectively, and reading the lower page requires the second level of read voltage L2, the eighth level of read voltage L8 and the fourteenth level of read voltage L14. The binary data corresponding to the middle page is 1110000110000111 respectively, and reading the middle page requires the third level of read voltage L3, the seventh level of read voltage L7, the ninth level of read voltage L9 and the thirteenth level of read voltage L13. The binary data corresponding to the upper page is 1111100000110001 respectively, and reading the upper page requires the fifth level of read voltage L5, the tenth level of read voltage L10, the twelfth level of read voltage L12 and the fifteenth level of read voltage L15. The binary data corresponding to the extra page is 1000110000011111 respectively, and reading the extra page requires the first level of read voltage L1, the fourth level of read voltage L4, the sixth level of read voltage L6 and the eleventh level of read voltage L11.

[0117] In some embodiments, the first result corresponding to a specific voltage (e.g., the first read voltage V0 shown in FIG. 8) can be understood as follows: the specific voltage is adjusted by a third adjustment, i.e., the specific voltage and the specific voltage after the third adjustment (e.g., the second read voltage V1 shown in FIG. 8) have a first voltage difference AV1, and the number of bits that flip in the two read results of the physical page at the specific voltage and the specific voltage after the third adjustment can be used as the first result corresponding to the specific voltage.

[0118] In some embodiments, before obtaining the first result corresponding to the target read voltage of the physical page, the read mode of the memory device is set to a single level read mode (SLR); the single level read mode includes reading at least one bit of storage data stored in the storage unit by a first level read voltage.

[0119] In some specific embodiments, the memory device is configured to enter the single level read mode in response to a mode setting command, and obtain the first result corresponding to the target read voltage of the physical page in the single level read mode.

[0120] In some specific embodiments, the storage data of the physical page is read at the first read voltage to obtain a second result; the second result is stored in a first latch of the memory device. Exemplarily, as shown in FIG. 8, the storage data of the physical page is read at the first read voltage V0 to obtain a second result. Specifically, the storage unit with a threshold voltage less than the target read voltage V0 is marked as bit 1, and the storage unit with a threshold voltage greater than the target read voltage V0 is marked as bit 0 to obtain the second result, and the second result is stored in the first latch of the memory device.

[0121] Next, the first read voltage is adjusted for a third time to obtain a second read voltage, and the storage data of the physical page is read at the second read voltage to obtain a third result; the third result is stored in a second latch of the memory device. For example, as shown in FIG. 8, the first read voltage V0 is adjusted for a third time, and the storage data of the physical page is read at the second read voltage V1 obtained after the adjustment to obtain a third result. Specifically, the storage cells with threshold voltages less than the second read voltage V1 are marked as bit 1, and the storage cells with threshold voltages greater than the second read voltage V1 are marked as bit 0 to obtain the third result, and the third result is stored in a second latch of the memory device.

[0122] Next, the second result and the third result are subjected to a logical operation to obtain a fourth result; the fourth result is stored in a third latch of the memory device. For example, as shown in FIG. 8, the second result and the third result are subjected to an exclusive-OR operation to obtain a fourth result; the fourth result is stored in a third latch of the memory device.

[0123] It should be noted that the exclusive-OR operation is one of the basic logical operations. In binary, if two binary numbers at the same position are the same, the result is “0”, and if two binary numbers at the same position are different, the result is “1” (i.e., the same is 0, and the different is 1).

[0124] Next, the number of bits in the fourth result representing the flipping of the third result compared with the second result is counted to obtain the first result. For example, as shown in FIG. 8, the part of the fourth result with bit 1 represents the number of storage cells with threshold voltages different between the first read voltage V0 and the second read voltage V1, in other words, the part of the fourth result with bit 1 represents the number of bits that flip in the two read results of the physical page at the first read voltage V0 and the second read voltage V1, and the number is denoted as the first result Y1 corresponding to the first read voltage V0.

[0125] In some embodiments, the plurality of word lines includes Q word line groups (WL Groups), and the first mapping function includes Q second mapping functions corresponding to the Q word line groups respectively; the relationship between the first parameters of the physical pages coupled to the word lines in the same word line group conforms to the corresponding second mapping function; wherein Q is an integer greater than or equal to 1; the memory controller is configured to: when obtaining the first parameter of the first physical page, obtain the first parameter of the physical page coupled to at least one word line in each word line group of the Q word line groups.

[0126] As shown in FIG. 9, the position or number of a physical page in a storage block is taken as an abscissa, and the first parameter corresponding to the physical page is taken as an ordinate, and the abscissa and the ordinate form a point. Exemplarily, the plurality of word lines include six word line groups (G1, G2, G3, G4, G5, and G6), which can also be referred to as physical page groups, and the first mapping function of the first parameters of the physical pages coupled to different word lines under the fourth level read voltage L4 includes six second mapping functions corresponding to the six word line groups respectively; the relationship between the first parameters of the physical pages coupled to different word lines in a same word line group conforms to the corresponding second mapping function. Exemplarily, in the scenario shown in FIG. 9, for a memory system including three-bit storage units, the mapping function of the relationship between the first parameters of the physical pages coupled to different word lines includes seven first mapping functions, and at least one first mapping function includes six second mapping functions, where the seven first mapping functions can be the same or different.

[0127] It can be understood that, before the memory device is shipped, the preset model and the first parameters are fitted according to a large number of experimental results, and the relationship between the first parameters of the physical pages coupled to different word lines under the same level read voltage can be described by the first mapping function, where the first mapping function can include a plurality of second mapping functions, that is, the first mapping function can be a mapping function set composed of a plurality of second mapping functions. Each second mapping function is used to describe the relationship between the first parameters of the physical pages at different positions in a same storage block. Therefore, the plurality of word lines can be grouped according to actual experimental results, so as to more accurately describe the relationship between the first parameters of the physical pages coupled to different word lines by the second mapping function.

[0128] In this way, it is beneficial to manage the relationship between the first parameters of a larger number of physical pages, so as to better utilize the relationship between the first parameters of the physical pages to further optimize the performance of the memory system.

[0129] As shown in FIG. 10, the relationship between the first parameters of all the physical pages in a same storage block can be described by one second mapping function, that is, the first mapping function of the first parameters of the physical pages coupled to different word lines under the seventh level read voltage L7 includes one second mapping function corresponding to one word line group.

[0130] It should be noted that the number of the first mapping functions and the second mapping functions provided in the embodiments of the present application is only an example, and the actual number of the first mapping functions and the second mapping functions is related to the characteristics of the memory device, and should not excessively limit the protection scope of the present application.

[0131] In some embodiments, the memory controller is configured to: when acquiring the first parameter of the first physical page, acquire the first parameter of at least one word-coupled physical page in each of the Q word line groups. This ensures that each word line group has a representative first parameter of a physical page for acquiring the first parameters of the remaining physical pages in the same word line group, allowing for specific adjustments and optimizations for different word line groups based on a specific second mapping function, thereby improving the overall performance and stability of the memory system.

[0132] The first parameter is a key parameter in the preset model used to generate the target reference voltage. By pre-establishing the relationship between the first parameters of physical pages coupled to different word lines, as well as a table of the first parameter values ​​corresponding to each physical page, during the data inspection operation, based on the first parameters of some physical pages (the first physical page), the positional relationship between physical pages coupled to different word lines (the second physical page and the first physical page), and combined with the mapping function, the first parameters of the remaining physical pages (the second physical page) can be dynamically generated, and the first parameters of the first physical page and the first parameters of the second physical page can be saved. This can improve the efficiency of data inspection and protect the integrity and reliability of the data.

[0133] In some embodiments, the memory controller is configured to: during a read operation following a data inspection operation, obtain a target reference voltage for at least one of the second physical pages based on a first parameter stored in the second physical page; and perform a read operation on at least one of the second physical pages according to the obtained target reference voltage.

[0134] In some implementations, dynamically updating the first parameter of the second physical page during the read operation after the data inspection operation is performed is beneficial for obtaining the target reference voltage based on the latest first parameter during subsequent read operations, thereby making the read operation more accurate and reducing the probability of decoding failure.

[0135] In some embodiments, the parameter table updated for the Nth time includes the first parameters of the first physical page and the first parameters of the second physical page saved for the Nth time; the memory controller is configured to: obtain the read result of the first physical page during the data inspection operation; if the decoding fails according to the read result, update the first parameters of the first physical page based on the first parameters of the first physical page saved in the parameter table updated for the Nth time, and generate the first parameters of the second physical page according to the updated first parameters of the first physical page; save the updated first parameters of the first physical page and the generated first parameters of the second physical page for the N+1th time as the parameter table updated for the N+1th time; N is a positive integer.

[0136] In some embodiments, an initial mapping table of first parameter relationships between physical pages coupled to different word lines is established before the memory device leaves the factory. During the initial data inspection operation, the read result of the first physical page is obtained. If the decoding fails based on the read result, the first parameter of the first physical page is updated based on the first parameter of the first physical page stored in the parameter table of the first update (i.e., the initial mapping table), and the first parameter of the second physical page is generated based on the updated first parameter of the first physical page. The updated first parameter of the first physical page and the generated first parameter of the second physical page are saved a second time as the parameter table of the second update.

[0137] It should be noted that the condition for determining decoding failure of the read result here is that the failure bit count of the read result is less than or equal to the third preset threshold, where the third preset threshold can be less than or equal to the first preset threshold. Understandably, during the data inspection operation, when the failure bit count of the acquired read result is lower than or equal to the error correction warning value of the storage unit, the parameter table is updated to obtain the target reference voltage to improve the accuracy of the read data, preventing further expansion of errors or data loss. This ensures dynamic adjustment (update) of the parameter table before data errors cause serious impact, avoiding triggering reread or error correction rewrite operations.

[0138] In some embodiments, the memory controller is configured to: load a relation table representing the mapping function and the parameter table updated for the Nth time from the memory device in response to power-on of the memory system; and save the parameter table updated for the N+1th time in the memory device in response to power-off of the memory system.

[0139] In some implementations, in response to power-on of the memory system, the latest mapping function relationship table and parameter table are loaded to ensure that the memory system uses the latest first parameter value at startup. In response to power-off of the memory system, the latest parameter table is saved to ensure that the memory system can continue to use the latest first parameter at the next startup.

[0140] It should be noted that during the power-on period of the memory system, the data inspection process for other memory blocks in the periodically performed data inspection operation can be referred to the relevant description in the above embodiments, and will not be repeated here.

[0141] The process of obtaining the target reference voltage based on the preset model and its first parameter will be described in detail below.

[0142] In some embodiments, the memory controller is configured to: acquire M first results corresponding to the physical page under M reference read voltages; the first results include the number of bits that flipped in two read results of the physical page under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; based on the M first results and the M reference read voltages, combined with the quadratic function model and the first parameter in the Nth updated mapping table, acquire a predicted reference voltage; the quadratic function model represents the relationship between the first results and the reference read voltages; all M first results are within a first preset interval; based on the predicted reference voltage, determine a target reference voltage and the first parameter in the N+1th updated parameter table.

[0143] It should be noted that the predicted reference voltage here can be directly used as the target reference voltage to perform the read operation on the data to be read, or it can be obtained after further processing. The specific method for obtaining the predicted reference voltage will be described in more detail later.

[0144] In some embodiments, the preset model is a quadratic function model, and the first preset interval represents the range between a first threshold and a second threshold of the curve containing the quadratic function model; the first threshold is greater than the second threshold.

[0145] In some embodiments, the memory controller is configured to: obtain a first result corresponding to the physical page at a target read voltage; and, based on the fact that the first result corresponding to the physical page at the target read voltage is within a first preset interval, use the target read voltage as a reference read voltage and use the first result within the first preset interval as the first result corresponding to the reference read voltage.

[0146] In some embodiments, the memory controller is configured to: obtain prediction parameters of the quadratic function model based on the M first results and the M reference read voltages, in conjunction with the quadratic function model; the prediction parameters are the reference read voltages corresponding to the minimum of the first results on the curve where the quadratic function model is located; obtain the prediction reference voltage based on the prediction parameters; and determine the target reference voltage and the first parameter in the parameter table updated for the N+1th time based on the prediction reference voltage.

[0147] In some specific embodiments, the functional relationship in the fitted preset model includes relevant parameters. When obtaining the predicted reference voltage, the values ​​of the relevant parameters can be obtained based on M first results, M reference reading voltages, and the functional relationship. Furthermore, the reference reading voltage corresponding to the minimum value of the first result on the curve containing the preset model can be obtained, and this reference reading voltage is used as the predicted reference voltage. In some embodiments, the preset model includes a quadratic function model, which includes the following functional relationship:

[0148] y = a(x + b) 2 +c

[0149] Where y is the first result, x is the reference reading voltage, b is used to characterize the prediction parameters, a is the first parameter, and c is the second parameter.

[0150] As shown in Figure 11, based on the functional relationships included in the above quadratic function model, it can be seen that the extreme value of the curve containing this quadratic function model is located at the position where the axis of symmetry is x = -b, that is, at the position where the derivative of the curve containing this quadratic function model is 0. For example, when the first parameter is greater than 0, the y value (first result) corresponding to x = -b is the minimum value of the curve containing this quadratic function model, and the coordinates of this extreme point (point A in Figure 10) are (-b, c).

[0151] In some implementations, the prediction parameter is the opposite of b, meaning the prediction parameter represents the x-coordinate of the curve containing the minimum value of the quadratic function model.

[0152] As shown in Figure 11, the axis of symmetry of the curve containing the quadratic function model (at x = -b) is offset from the y-axis (at x = 0) by -b. That is, the distance between the axis of symmetry of the curve containing the quadratic function model and the y-axis is the absolute value of b, |b|.

[0153] Here, x = 0 can be understood as the position of the default reading voltage. In this application, the term "the first result corresponding to the default reading voltage" can be simply referred to as "the default first result". The coordinates corresponding to the default first result (point B in Figure 11) are (0, ab). 2 +c). The default read voltage can be the read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage corresponding to the moment of writing, at which point the corresponding offset value is 0. It can be understood that when the target read voltage has an offset of -b compared to the default read voltage (x=0), the first result corresponding to that target read voltage is the minimum value. It can be understood that using the target read voltage corresponding to the minimum value of the first result (equivalent to the prediction parameter here) as the prediction reference voltage, and determining the target reference voltage based on the prediction reference voltage, results in a low error rate and high reliability in the read results.

[0154] It should be noted that the target read voltage (equivalent to the prediction parameter) corresponding to the minimum value of the first result is used as the prediction reference voltage, i.e., -b is used as the prediction reference voltage. This represents the offset of the prediction reference voltage from the default read voltage by -b, not that the prediction reference voltage is negative. When -b is greater than 0, it means that the prediction reference voltage is offset to the right by |b| compared to the default read voltage; when -b is less than 0, it means that the prediction reference voltage is offset to the right by |b| compared to the default read voltage. In other words, the relationship between the actual voltage of the prediction reference voltage (denoted as Vpre) and the actual voltage of the default read voltage (denoted as Vdefault) is as follows:

[0155] Vpre = Vdefault + (-b)

[0156] Similarly, after determining the target reference voltage based on the predicted reference voltage, using the target reference voltage to perform a read operation on a physical page means using the actual voltage of the target reference voltage to perform the read operation on the physical page. It should be noted that when there is only one set of predicted parameters, it is directly used as the predicted reference voltage. However, when there are multiple sets of predicted parameters, the predicted reference voltage needs to be determined based on all sets of predicted parameters.

[0157] In some embodiments, as shown in FIG11, the first preset interval represents the range between the first threshold and the second threshold of the curve where the quadratic function model is located; the first threshold (Th1) is greater than the second threshold (Th2).

[0158] Figure 12 is a schematic diagram of determining a first preset interval according to an embodiment of this application. In some embodiments, the multiple solid dots shown in Figure 12 represent a large amount of data (multiple target read voltages and multiple first results corresponding to the multiple target read voltages) collected through numerous experiments before the memory device leaves the factory. When fitting a preset model based on the data shown in Figure 12, the selection of data directly affects the accuracy of the fitted preset model. For example, when the first result of the selected data is too high (e.g., the solid dots in the dashed box region A1 or dashed box region A2 shown in Figure 12), the fitted preset model will not match the distribution curve of the actual threshold voltage. Specifically, the preset model fitted by selecting the solid dots in the dashed box region A1 or dashed box region A2 is a quadratic function model with the opening facing downwards, which does not match the distribution curve of the actual threshold voltage (a quadratic function model with the opening facing upwards). When the first result of the selected data is too low (e.g., the solid dots in the dashed box region A3 shown in Figure 12), the error of the fitted preset model is too large, causing the position of the target reference voltage obtained according to the preset model to deviate too much from the actual read voltage.

[0159] In some implementations, the first preset interval ranges from 50 to 200.

[0160] It should be noted that the range of the first preset interval provided in the embodiments of this application is only an example. The range of the first preset interval is related to the characteristics of the memory device and should not excessively limit the scope of protection of this application.

[0161] In some embodiments, the memory controller is configured to: acquire a first result corresponding to the physical page at a target read voltage; and, based on the fact that the first result corresponding to the physical page at the target read voltage is within a first preset interval, use the target read voltage as a reference read voltage; and, based on the fact that the first result corresponding to the physical page at the target read voltage is outside the first preset interval, acquire at least one new target read voltage, acquire the first result corresponding to the at least one new target read voltage, until the first result corresponding to the latest target read voltage is within the first preset interval.

[0162] Here, the first and second parameters can be obtained when fitting a preset model and stored in a memory device.

[0163] For example, the preset model includes a quadratic function model, and the quadratic function model includes the following functional relationship (1):

[0164] y = a(x + b) 2 +c

[0165] The first and second parameters in a functional relationship can be optimized using, but are not limited to, least squares, gradient descent, Bayesian optimization, Newton's method, and quasi-Newton methods, and the optimal first and second parameters can be stored in a memory device. Least squares is a parameter estimation method that estimates parameters by minimizing the sum of squared residuals between the actual collected data and the predicted values ​​of the quadratic function model. Gradient descent uses the parameters of the quadratic function model as the optimization objective, using gradient descent to find the parameter values ​​that minimize the fitting error of the quadratic function model. It calculates the gradient of the loss function with respect to the first and second parameters, and then updates the values ​​of the first and second parameters in the opposite direction of the gradient until convergence is achieved.

[0166] In some embodiments, as shown in FIG13, the memory controller is configured to: acquire a first result corresponding to the physical page at the target read voltage, i.e., acquire point C (x) shown in FIG13. c ,y c ); The first result (y) corresponding to point C c If the target voltage (x) at point C is within the first preset range, then the target voltage (x) at point C will be read. c This serves as a reference reading voltage.

[0167] It should be noted that Figure 13 uses point C as an example with the default first result, and should not unduly limit the scope of protection of this application. Furthermore, point C is the point corresponding to the first result obtained under the default reading voltage according to the method of obtaining the first result in the foregoing embodiments. Therefore, point C is an actual value, which may or may not be located on the curve of the quadratic function model.

[0168] In some embodiments, as shown in FIG14, the memory controller is configured to: based on point C (x c ,y c The first result (y) corresponding to ) c If the target voltage is outside the first preset range, at least one new target reading voltage is acquired, and the first result corresponding to the at least one new target reading voltage is acquired, until the first result corresponding to the latest target reading voltage is within the first preset range.

[0169] It is understandable that the target reading voltage can only be used as a reference reading voltage to obtain the predicted reference voltage when the first result corresponding to the target reading voltage falls within a first preset range. This enhances the accuracy and reliability of obtaining the predicted reference voltage based on multiple reference reading voltages and multiple first results.

[0170] In some embodiments, at least two of the M reference read voltages are located on opposite sides of the axis of symmetry of the curve containing the quadratic function model; the memory controller is configured to: when acquiring the reference read voltage, acquire the reference read voltage located on a first side of the axis of symmetry of the curve containing the quadratic function model; and determine the reference read voltage located on a second side of the axis of symmetry based on the reference read voltage located on the first side.

[0171] In some implementations, the first and second parameters can be obtained when fitting a preset model and stored in a memory device. Based on the coordinates of point C in Figure 13 or Figure 14, the functional relationship of the quadratic function model, and the first and second parameters, an initial value of b can be obtained. Based on this initial value of b, the axis of symmetry x = -b of the curve containing the quadratic function model can be obtained.

[0172] It should be noted that the first side refers to one side of the axis of symmetry of the curve containing the quadratic function model (as shown in Figures 13 and 14 at x = -b), and the second side refers to the other side of the axis of symmetry of the curve containing the quadratic function model. When the first side is to the right of the axis of symmetry, the second side is to the left of the axis of symmetry. When the first side is to the left of the axis of symmetry, the second side is to the right of the axis of symmetry.

[0173] For example, the target read voltage (x) corresponding to point C in Figure 13c ) is the reference reading voltage on the first side of the axis of symmetry of the curve containing the quadratic function model.

[0174] The following will detail the process of obtaining the reference reading voltage on the first side of the curve containing the quadratic function model and the reference reading voltage on the second side of the curve containing the quadratic function model.

[0175] In some implementations, the method of re-acquiring at least one new target read voltage based on the fact that the first result corresponding to the physical page at the target read voltage is outside a first preset range includes, but is not limited to, using the read voltage obtained by adjusting the target read voltage by a target step size as the new target read voltage. For example, as shown in FIG14, the target read voltage (x) is... c The reading voltage (x) obtained after adjustment with the target step size d Using this as the new target read voltage, obtain the first result (y) corresponding to the physical page under the new target read voltage. e That is, to obtain point E (x) as shown in Figure 14. d ,y e At this point, point E is an actual value, and the first result (y) corresponding to point E is... e When the voltage is within the first preset range, the new target reading voltage (x) corresponding to point E will be... d This serves as a reference reading voltage. The target step size can be set from 20mV to 40mV. For example, the first adjustment step size can be 20mV, 30mV, or 40mV. The target step size can also be set from 50mV to 150mV. For example, the second adjustment step size can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV, or 150mV.

[0176] In some implementations, the memory controller is configured to: based on the target read voltage, the first result corresponding to the target read voltage, the target read voltage, the target first result, and a third mapping function, obtain a fitted read voltage on a first side corresponding to the target first result, since the first result corresponding to the physical page at the target read voltage is outside a first preset interval; the third mapping function is obtained based on a quadratic function model, a first parameter, and a second parameter; the target first result is within a second preset interval, and the first preset interval is within the range of the second preset interval.

[0177] For example, as shown in Figure 14, the memory controller is configured to: based on point C (x c ,y c The first result (y) corresponding to ) c ) is outside the first preset range, based on the target reading voltage (x) c), the first result (y) corresponding to the target reading voltage c ), target first result (y) d ) and the third mapping function, to obtain the first result (y) relative to the target. d The corresponding fitted reading voltage (x) on the first side d That is, based on the coordinates of point C and the first result of the target (y d ) and the third mapping function, to obtain point D (x d ,y d The third mapping function includes the following relation (2):

[0178] Where x1 and y1 represent the x and y coordinates of the acquired actual point, respectively, y2 represents the target first result, which is an arbitrary value within the second preset interval, and x2 represents the fitted reading voltage. The third mapping function aims to obtain the fitted reading voltage (e.g., x2 as shown in Figure 14) based on a value within the second preset interval and the acquired actual point (e.g., point C). d The first preset interval is located within the range of the second preset interval. Optionally, the range of the second preset interval is 30 to 220.

[0179] Set the coordinates of point C and the first result of the target (y) d By substituting the first and second parameters into the relational expression (2) of the first mapping function, point D (x) can be obtained. d ,y d ).

[0180] It should be noted that Figure 14 and the third mapping function are explained with the first side as the axis of symmetry and point C located on the first side.

[0181] At this time, point D (x d ,y d Let D be a fitted point, and let x be the x-coordinate of point D. d That is, the fitted read voltage on the first side. The memory controller is configured to: use this fitted read voltage as the new target read voltage, and obtain the fitted read voltage (x) of the physical page on the first side using the method of obtaining the first result in the aforementioned embodiment. d The first result (y) under ) e That is, to obtain point E (x) d ,y e Point E is the actual point; based on the fitting data on the first side, the first result corresponding to the voltage (the ordinate y of point E) is read. e If the voltage is within the first preset range, the fitted reading voltage (x) on the first side will be within the first preset range. d This serves as a reference reading voltage for the first side.

[0182] In some embodiments, the fitted reading voltage on the first side (the x-coordinate corresponding to point D) is used to... d As the new target read voltage, the fitted read voltage (x) of the physical page on the first side is obtained using the method of obtaining the first result in the aforementioned embodiment. d The first result (y) under ) f That is, to obtain point F (x) d ,y f The memory controller is also configured to: read the first result (the y-coordinate of point F) corresponding to the fitted read voltage on the first side. f If the value is outside the first preset interval, based on the previous fitted reading voltage on the first side, the first result corresponding to the previous fitted reading voltage on the first side, the target first result, and the third mapping function, the next fitted reading voltage on the first side corresponding to the target first result is obtained, until the first result corresponding to the latest fitted reading voltage on the first side falls within the first preset interval. The latest fitted reading voltage on the first side is then used as a reference reading voltage on the first side. It can be understood that this is based on the previous known actual point F (x...). d ,y f The first result of the objective (one randomly selected from the second preset interval and y) d Different values) and the third mapping function (relationship (2)) to obtain the next fitted reading voltage on the first side corresponding to the target first result, until the first result corresponding to the latest fitted reading voltage on the first side is within the first preset range, and the latest fitted reading voltage on the first side is used as a reference reading voltage on the first side.

[0183] In some embodiments, the memory controller is configured to: adjust the value of a first parameter and adjust a third mapping function accordingly, based on the number of times the first result corresponding to the latest fitted read voltage on the first side is outside the first preset interval being greater than or equal to a preset number; and obtain the next adjusted fitted read voltage on the first side corresponding to the target first result based on the previous fitted read voltage on the first side, the first result corresponding to the previous fitted read voltage on the first side, the target first result, and the adjusted third mapping function, until the first result corresponding to the latest adjusted fitted read voltage on the first side is within the first preset interval.

[0184] Here, the preset number of attempts represents the upper limit of the number of trials and errors using the preset model. If, after the preset number of attempts, the first result corresponding to the fitted reading voltage of the first side obtained using the preset model is outside the first preset range, it means that the selected preset model may not meet the actual needs and more in-depth parameter adjustments are required. The preset number of attempts can be adjusted according to the actual situation. In some embodiments, the preset number of attempts is 3-7 times. For example, the preset number of attempts can be 3, 5, or 7 times.

[0185] In some implementations, when the number of times the first result corresponding to the fitted reading voltage of the first side obtained by the method in the foregoing embodiments is outside the first preset interval is greater than or equal to a preset number, it indicates that multiple actual points have been obtained. Based on the multiple actual points obtained, combined with the functional relationship (1) of the quadratic function model and the second parameter (constant), the value of the adjusted first parameter can be obtained. It is understood that in actual use, adjusting the first parameter of the quadratic function model in combination with actual points can improve the accuracy and reliability of the quadratic function model, and make the adjusted first parameter infinitely close to the first parameter corresponding to the actual reading voltage distribution curve. In this way, it can better reflect the actual situation and can be flexibly applied to changes in actual use scenarios, thereby improving the practicality of the quadratic function model.

[0186] For example, the preset number of times is 3. The number of times the first result corresponding to the fitting reading voltage of the first side obtained by the method in the above embodiment is outside the first preset interval is equal to 3. That is, at least 3 actual points are obtained at this time. The coordinates of the 3 actual points are recorded as (x3,y3) and (x4,y4), and (x5,y5) respectively. Based on any 2 actual points among the 3 actual points obtained, such as (x3,y3) and (x4,y4), combined with the functional relationship (1) of the quadratic function model, the calculation formula (1) of b can be obtained as follows:

[0187] Based on the calculation formula (1) for b, and according to the functional relationship of the quadratic function model and the fact that the second parameter is constant, the calculation formula (2) for the first parameter can be obtained as follows:

[0188] It can be understood that the first parameter obtained here can be used as the first parameter in the parameter table of the N+1th update.

[0189] For example, based on the three actual points already obtained, and combined with the functional relationship (1) of the quadratic function model, the calculation formula (3) for b can be obtained as follows:

[0190] Based on the calculation formula (3) for b, and according to the functional relationship (1) of the quadratic function model and the fact that the second parameter is a constant, the calculation formula (4) for the first parameter can be obtained as follows:

[0191] Thus, the value of the adjusted first parameter is obtained, and the value of the adjusted first parameter is substituted into the functional relationship (2) of the third mapping function to adjust the third mapping function accordingly.

[0192] In some embodiments, the memory controller is configured to: obtain a fitted read voltage on the second side corresponding to the target first result based on a reference read voltage on the first side, a first result corresponding to the reference read voltage on the first side, a target first result, and a fourth mapping function; the fourth mapping function is obtained based on a quadratic function model, a first parameter / adjusted first parameter, and a second parameter; obtain the first result corresponding to the physical page at the fitted read voltage on the second side; and, based on the fact that the first result corresponding to the fitted read voltage on the second side is within a preset range, use the fitted read voltage on the second side as a reference read voltage on the second side.

[0193] For example, as shown in Figure 15, the memory controller is configured to: based on a reference read voltage on the first side (the x-coordinate corresponding to point G) g The first result corresponding to a reference reading voltage on the first side (the y-coordinate of point G). g ), target first result (y) h And the fourth mapping function, to obtain the first result (y) relative to the target. h The corresponding fitted reading voltage (x) on the second side h That is, based on the coordinates of point G, obtain the first result (y) relative to the target. h The corresponding fitted reading voltage (x) on the second side h Specifically, based on the coordinates of point G and the first result of the target (y... h And the fourth mapping function, to obtain point H(x) h ,y h The fourth mapping function includes the following relation (3):

[0194] Where x1 and y1 represent the x and y coordinates of the acquired actual point, respectively, y2 represents the target first result, which is an arbitrary value within the second preset interval, and x2 represents the fitted reading voltage. The fourth mapping function aims to obtain the fitted reading voltage (e.g., x2 as shown in Figure 15) based on a value within the second preset interval combined with the acquired actual point (e.g., point G). h ).

[0195] Set the coordinates of point G and the first result of the target (y) h By substituting the first parameter / adjusted first parameter and second parameter into the relational expression (3) of the fourth mapping function, point H (x) can be obtained. h ,y h ).

[0196] At this time, point H (x h ,y h H is a fitted point, and the x-coordinate of the point H is... h This refers to the fitted read voltage on the second side. The memory controller is configured to use this fitted read voltage as the new target read voltage, and to obtain the fitted read voltage (x) of the physical page on the second side using the same method as obtaining the first result in the aforementioned embodiment. h The first result (y) under ) i That is, to obtain point I (x) h ,y i Point I is the actual point; based on the fitted data on the second side, the first result corresponding to the voltage (the ordinate y of point I) is read. i If the voltage is within the first preset range, the fitted reading voltage (x) on the second side will be within the range of the second preset range. h This serves as a reference reading voltage for the second side.

[0197] In some embodiments, the memory controller is configured to: based on the first result corresponding to the fitted read voltage on the second side being outside a preset interval, and based on the previous fitted read voltage on the second side, the first result corresponding to the previous fitted read voltage on the second side, the target first result, and a fifth mapping function, obtain the next fitted read voltage on the second side corresponding to the target first result, until the first result corresponding to the latest fitted read voltage on the second side is within a first preset interval, and use the latest fitted read voltage on the second side as a reference read voltage on the second side; the fifth mapping function is obtained based on a quadratic function model, the first parameter / adjusted first parameter, and the second parameter.

[0198] In some embodiments, as shown in Figures 15 and 16, the fitted reading voltage on the second side (the abscissa x corresponding to point H) is... h As the new target read voltage, the fitted read voltage (x) of the physical page on the second side is obtained using the method of obtaining the first result in the aforementioned embodiment. h The first result (y) under ) j That is, to obtain point J (x) h ,y j The peripheral circuitry is also configured to: read the first result (the ordinate y of point J) corresponding to the fitted voltage on the second side. j() is outside the first preset interval, based on the previous fitted reading voltage (x-coordinate of point J) on the second side. h The first result corresponding to the previous fitted reading voltage on the second side (the ordinate of point J, y) j ), target first result (y) k And the fifth mapping function, to obtain the first result (y) relative to the target. k The next fitted read voltage (x) corresponding to the second side k That is, to obtain point K (x) as shown in Figure 16. k ,y k ), until the latest fitted read voltage (x) on the second side k The first result (y) under ) l The value is within the first preset interval, i.e., point L (x) as shown in Figure 16. k ,y l The corresponding ordinate is within the first preset interval, and the latest fitted reading voltage (x) on the second side is used. k The fifth mapping function is obtained based on a quadratic function model, the first parameter / adjusted first parameter, and the second parameter. The fifth mapping function includes the following relationship (4):

[0199] Where x1 and y1 represent the x and y coordinates of the acquired actual point, respectively, y2 represents the target first result, which is an arbitrary value within the second preset interval, and x2 represents the fitted reading voltage. The third mapping function aims to obtain the fitted reading voltage (e.g., x2 as shown in Figure 16) based on a value within the second preset interval and the acquired actual point (e.g., point J). k ).

[0200] Set the coordinates of point J and the first result of the target (y) k By substituting the first parameter / adjusted first parameter and second parameter into the relational expression (4) of the fifth mapping function, the K point (x) can be obtained. k ,y k ).

[0201] At this time, point K (x) k ,y k K is a fitted point, and the x-coordinate of point K is... k This refers to the fitted read voltage on the second side. The memory controller is configured to use this fitted read voltage as the new target read voltage, and to obtain the fitted read voltage (x) of the physical page on the second side using the same method as obtaining the first result in the aforementioned embodiment. k The first result (y) under ) l That is, to obtain point L (x k ,yl ), where point L is the actual point; based on the latest fitted data on the second side, read the first result corresponding to the voltage (the ordinate y of point L). l If the voltage is within the first preset range, the latest fitted reading voltage (x) on the second side will be used. k This serves as a reference reading voltage for the second side.

[0202] It should be noted that in the embodiments of this application, points A, B, D, H, and K are all fitted points, located on the curve of the quadratic function model. Points C, E, F, G, I, J, and L are all actual points, which may or may not be located on the curve of the quadratic function model.

[0203] In this embodiment of the application, the method of obtaining the reference reading voltage of the first side / second side in the aforementioned embodiment can be used to obtain M reference reading voltages and the corresponding first results under the M reference readings, and the prediction parameters can be obtained based on the M reference reading voltages and the M first results.

[0204] In some embodiments, the first parameter is a variable and the second parameter is a constant; the memory controller is configured to: obtain prediction parameters based on the M first results and the M reference read voltages, combined with a quadratic function model; and use the prediction parameters as prediction reference voltages.

[0205] For example, based on M first results, M reference reading voltages, a quadratic function model, and second parameters, N sets of prediction parameters are obtained, where N equals

[0206] Here, the second parameter can be obtained when fitting the preset model and stored in the memory device.

[0207] In some implementations, M equals 2, then N equals 1. Substituting the coordinates corresponding to the two reference reading voltages and the two first results into the calculation formula (1) of b, b can be calculated, and a set of prediction parameters can be obtained. These prediction parameters are then used as the prediction reference voltage.

[0208] In some implementations, M is greater than 2, and N is equal to Based on M reference read voltages and M first results, we can obtain Two reference read voltages and their corresponding two first results are combined in a way that is based on By combining the various combinations with the calculation formula (1) for b, we can obtain... Group prediction parameters. Determine. Outliers in group prediction parameters; based on The median and standard deviation of the group prediction parameters are used to identify outliers or to... The maximum and minimum values ​​in the group prediction parameters are both considered outliers. The median or average of the remaining prediction parameters after removing outliers is used as the prediction reference voltage.

[0209] In this way, by identifying and removing outliers from multiple sets of prediction parameters, the accuracy and reliability of the remaining prediction parameters when used to determine the predicted reference voltage are ensured.

[0210] In some embodiments, the first parameter and the second parameter are both variables; the memory controller is configured to: obtain prediction parameters based on M first results and M reference read voltages, combined with a quadratic function model; use the prediction parameters as the target read voltage to obtain the first result corresponding to the physical page under the target read voltage of the prediction parameters; obtain new prediction parameters based on the M first results, M reference read voltages, prediction parameters, and the first result corresponding to the target read voltage of the prediction parameters, combined with a quadratic function model; and use the new prediction parameters as the prediction reference voltage.

[0211] In some implementations, the second parameter is a variable, but an initial value can be obtained when fitting a preset model and stored in a memory device.

[0212] For example, based on M first results, M reference reading voltages, a quadratic function model, and the initial value of the second parameter, combined with the calculation formula (1) for b, N sets of prediction parameters are obtained, where N equals

[0213] In some implementations, M equals 2, then N equals 1. Substituting the coordinates of the two reference reading voltages and the two first results into the calculation formula (1) of b, b can be calculated, and a set of prediction parameters can be obtained. The prediction parameters are used as the target reading voltage to obtain the first result of the physical page under the target reading voltage of the prediction parameters, that is, another actual point is obtained at this time. Next, the coordinates of the three actual points (the two reference reading voltages and their corresponding two first results, the prediction parameters and the first result under the target reading voltage of the prediction parameters) are substituted into the calculation formula (3) of b to calculate b, and a new set of prediction parameters can be obtained. The new prediction parameters are used as the prediction reference voltage.

[0214] Thus, by using the predicted parameters and the first result corresponding to the read voltage to obtain new predicted parameters, the accuracy of the obtained predicted reference voltage can be improved.

[0215] In some implementations, the M reference reading voltages are located on the same side of the axis of symmetry of the curve containing the quadratic function model. For example, all M reference reading voltages are located on the first side of the axis of symmetry of the curve containing the quadratic function model, or all M reference reading voltages are located on the second side of the axis of symmetry of the curve containing the quadratic function model.

[0216] In some implementations, at least two of the M reference read voltages lie on either side of the axis of symmetry of the curve containing the quadratic function model. Points located on either side of the axis of symmetry of the curve containing the quadratic function model are more representative, covering a wider data range, and can improve the accuracy and reliability of determining prediction parameters based on the reference read voltages to further obtain the predicted reference voltage.

[0217] The process of obtaining the target reference voltage of the physical page using the aforementioned preset model and its first parameter is applicable to both the first and second physical pages.

[0218] For example, as shown in Figure 17, the offset value corresponding to the default read voltage is 0. The difference between the target read voltage and the default read voltage is used as the horizontal axis, and the first result corresponding to the target read voltage is used as the vertical axis. These two axes will form a point. The point corresponding to the target reference voltage is the point where the target reference voltage is used as the horizontal axis. The hollow point in Figure 17 is the actual point formed by the target read voltage and its corresponding first result corresponding to the second-level read voltage L2 as shown in Figure 7B. The solid point in Figure 17 is the point on the curve where the preset model (e.g., a quadratic function model) corresponding to the second-level read voltage L2 is located, as shown in Figure 7B. Referring to Figure 17, it can be seen that the actual target reference voltage (Vvalley) almost coincides with the lowest point on the curve where the preset model is located, indicating that the method of determining the target reference voltage through the preset model in this application embodiment has high accuracy.

[0219] For example, as shown in Figure 18, the offset value corresponding to the default read voltage is 0. The difference between the target read voltage and the default read voltage is used as the horizontal axis, and the first result corresponding to the target read voltage is used as the vertical axis. These two axes will form a point. The point corresponding to the target reference voltage is the point where the target reference voltage is used as the horizontal axis. The hollow point in Figure 18 is the actual point formed by the target read voltage and its corresponding first result corresponding to the fourth-level read voltage L4 as shown in Figure 7B. The solid point in Figure 18 is the point on the curve where the preset model (e.g., a quadratic function model) corresponding to the fourth-level read voltage L4 is located, as shown in Figure 7B. Referring to Figure 18, it can be seen that the actual target reference voltage (Vvalley) almost coincides with the lowest point on the curve where the preset model is located.

[0220] Firstly, the memory system provided in this application samplees data from a first physical page within a storage block through a data inspection operation. It then obtains the first parameters of the first physical page, generates the first parameters of a second physical page, and saves both the first and second physical page parameters. By dynamically adjusting the first parameters based on the read results of the data inspection operation and further obtaining the target reference voltage of the physical page, the accuracy of data reading is improved. Simultaneously, it reduces reread operations, error correction and rewrite operations, and garbage collection operations in the data inspection operation, thereby reducing write amplification and significantly improving data inspection efficiency.

[0221] Figure 19 is a flowchart of the operation method of the memory system provided in an embodiment of this application. The detailed process of performing the data inspection operation will be described in detail below with reference to Figure 19.

[0222] In step S101, a mapping function relationship table and a parameter table are established between the first parameters of physical pages with different word lines. It can be considered that an initial mapping table and an initial parameter table of the relationship between the first parameters of physical pages with different word lines are established before the first data inspection operation is performed.

[0223] After the memory system is powered on, step S102 is executed. A mapping function table representing the relationship between the first parameters of physical pages with different word lines and a parameter table updated for the Nth time are loaded from the memory device. Taking N equals 1 as an example, after the memory system is powered on, an initial mapping table representing the relationship between the first parameters of physical pages with different word lines and a parameter table updated for the first time (initial parameter table) are loaded from the memory device.

[0224] In step S103, a data inspection operation is performed. The data inspection operation performed during the power-on of the memory system does not need to traverse all physical pages in a memory block. In other words, a sampling data inspection method can be used to perform the data inspection operation. For example, when performing a data inspection operation on a memory block, the read result of at least one physical page in the memory block is obtained. The first physical page in the memory block is the target physical page of the data inspection operation among multiple physical pages, and the second physical page is the remaining physical pages among the multiple physical pages excluding the first physical page.

[0225] Next, step S104 is executed to determine whether the decoding of the read result obtained from the data inspection operation was successful.

[0226] It should be noted that the condition for determining decoding failure of the read result here is that the failure bit count of the read result is less than or equal to the third preset threshold, where the third preset threshold can be less than or equal to the first preset threshold. Understandably, during the data inspection operation, when the failure bit count of the acquired read result is lower than or equal to the error correction warning value of the storage unit, the parameter table is updated to obtain the target reference voltage to improve the accuracy of the read data, preventing further expansion of errors or data loss. This ensures dynamic adjustment of the parameter table before data errors cause serious impact, avoiding triggering reread or error correction rewrite operations.

[0227] If the judgment result of step S104 is yes, then step S105 is executed to end the data inspection operation on the current storage block. It can be understood that a yes judgment result in step S104 indicates that the read result obtained by the data inspection operation was successfully decoded, meaning that no anomalies were found in the data inspection operation of the current storage block, and the data inspection operation on the current storage block can be ended.

[0228] If the judgment result of step S104 is negative, proceed to step S106 to update the first parameter of the first physical page according to the parameter table updated for the Nth time. Specifically, if the decoding fails due to the read result, update the first parameter of the first physical page based on the first parameter of the first physical page stored in the parameter table updated for the Nth time.

[0229] Next, step S107 is executed, whereby the first parameters of the second physical page are generated based on the updated first parameters of the first physical page. Specifically, the relevant descriptions of obtaining the target reference voltage of the physical page and updating the first parameters based on the preset model and its first parameters in the foregoing embodiments can be referred to, and will not be repeated here.

[0230] Next, step S108 is executed, where the first parameter of the updated first physical page and the first parameter of the generated second physical page are saved for the N+1th time as the parameter table for the N+1th update; N is a positive integer.

[0231] Execute step S105 to end the data inspection operation on the current storage block.

[0232] It should be noted that the periodically performed data inspection operation during the power-on of the memory system includes data inspection operations on different memory blocks. Figure 19 illustrates the process of performing a data inspection operation on one of multiple memory blocks as an example. After step S105, data inspection operations can continue to be performed on the remaining memory blocks.

[0233] It should be noted that after step S105 in this embodiment, the data migration operation or garbage collection operation can be avoided. This is because the failure to decode the first physical page obtained by the data inspection operation does not mean that the data itself is unrecoverable. It can be understood that the reading conditions used are inappropriate. By dynamically updating the first parameter and obtaining the target reference voltage of the physical page according to the preset model and the first parameter in the aforementioned embodiment, the subsequent reading operation or data inspection operation can be performed. That is, optimizing the reading voltage can successfully read the data, thus avoiding unnecessary rereading operations, data migration operations and garbage collection operations.

[0234] Here, the read result of the first physical page obtained in the data inspection operation still uses the failure bit reaching a certain threshold (the third preset threshold) as the trigger condition. However, when the decoding of the read result of the first physical page obtained in the data inspection operation fails, a reread operation or data relocation operation is not immediately performed. Instead, the first parameter of each physical page is dynamically updated to generate the target reference voltage in subsequent read operations or data inspection operations. That is, the threshold voltage offset of each physical page in the memory block is obtained. Therefore, the read condition can be changed without performing a reread operation or data relocation operation to improve the success rate and accuracy of data reading. In this way, the data inspection operation can be made faster and more efficient, which not only optimizes the performance of the memory system, but also extends the service life of the memory system.

[0235] In some embodiments, the third preset threshold is set to be less than or equal to the first preset threshold, so that timely processing can be carried out before the data is completely unrecoverable or severely damaged.

[0236] In some embodiments, as shown in Figures 20 and 21, the memory system 102 includes: one or more memory devices 104; and a memory controller 106 coupled to and controlling the memory devices 104.

[0237] As shown in Figure 20, in some specific embodiments, the memory system 102 is coupled to the host, responds to the host's instructions, and performs various feedback operations. The memory system 102 may include a memory controller 106 and a memory device 104. The memory controller 106 is used to control the memory device 104 to perform read, write, erase, and other operations. The memory controller 106 and the memory device 104 may also be coupled in any suitable manner.

[0238] The memory controller 106 may include a host interface (I / F) 1061, a memory interface (I / F) 1062, a control unit 1063, a read-only memory (ROM) 1069, a random access memory (RAM) 1070, an error correction module 1064, a garbage collection module 1065, a wear leveling module 1066, a data buffer 1067, and a bus 1060. The host interface 1061 is the connection interface between the host 108 and the memory controller 106, allowing the host and the memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 is the connection interface between the memory controller 106 and the memory device 104, and is used to implement data transfer between the memory controller 106 and the memory device 104. The control unit 1063 is used to control the memory controller 106 as a whole. The specific steps performed by the memory controller mentioned above are mainly executed and completed by the control unit 1063. In some specific embodiments, the control unit 1063 is, for example, a central processing unit (CPU) or a microprocessor (MCU). The ROM 1069 typically contains the firmware or firmware program code of the memory controller 106. This code is used to initialize and operate the various components of the memory controller. The RAM 1070 is typically used to cache data. The error correction module 1064 may further include an encoding unit and a decoding unit; the encoding unit is used to encode the data to be stored to obtain check data, and the decoding unit is used to decode the check data to detect and correct possible erroneous data during data transmission.

[0239] Garbage collection module 1065 is used to read out valid data from some storage blocks, rewrite it, and then mark these storage blocks to obtain new spare storage blocks after the storage space of the memory device reaches a certain threshold. The general implementation of garbage collection can be divided into three steps: selecting source storage blocks with less valid data; finding valid data from the source storage blocks; and writing the valid data to the target storage block. At this point, all data in the source storage block becomes invalid data, and the source storage block is marked as a new spare storage block. Wear leveling module 1066 is used to maintain a balanced wear (erase count) of each storage block in the memory system through data statistics and algorithms. The general implementation of wear leveling can be divided into two steps: selecting source storage blocks containing cold data; reading valid data from the source storage blocks and writing it to storage blocks with relatively high erase counts. At this point, the valid data in the source storage blocks becomes invalid data and is marked. Data buffer 1067 is used to cache data.

[0240] Secondly, embodiments of this application provide a memory controller coupled to at least one memory device, the memory device including multiple word lines; each word line coupled to multiple memory cells, and the multiple memory cells coupled to the same word line form at least one physical page; the memory controller includes: an interface, a cache, and a control unit; wherein, the control unit is configured to: obtain a first parameter of a first physical page among the multiple physical pages according to data fed back by the memory device; the first parameter is a parameter in a preset model for generating a target reference voltage, the target reference voltage being used as a read voltage for performing a read operation on the physical page; the multiple physical pages include the first physical page and a second physical page, the first physical page being the target physical page for the data inspection operation among the multiple physical pages, and the second physical page being the remaining physical pages among the multiple physical pages excluding the first physical page; generate a first parameter of the second physical page according to the first parameter of the first physical page and in combination with the positional relationship between the second physical page and the first physical page; and save the first parameter of the first physical page and the first parameter of the second physical page through the cache.

[0241] The specific steps executed by the memory controller are mainly performed and completed by the control unit 1063 in Figure 20. The interface of the memory controller can be understood by referring to the memory interface 1062 in Figure 20, and the cache of the memory controller can be understood by referring to the RAM 1070 in Figure 20.

[0242] In some embodiments, the control unit is configured to send a data inspection start command to the memory device via the interface before obtaining the first parameter of at least one of the plurality of physical pages based on the data fed back by the memory device.

[0243] For example, as shown in FIG21, the control unit of the memory controller 106 sends a data inspection start command to the memory device 104 before obtaining the first parameter of at least one physical page among a plurality of physical pages based on the data fed back by the memory device 104.

[0244] In some embodiments, the control unit is configured to: generate the first parameters of the second physical page based on the first parameters of the first physical page, the positional relationship between the second physical page and the first physical page, and in conjunction with a mapping function; the mapping function characterizes the relationship between the first parameters of the plurality of physical pages.

[0245] In some embodiments, the storage unit has P bits, where P storage bits correspond to 2^32 bits. P -1 level read voltage; where P is an integer greater than or equal to 1; the mapping function includes the 2 P The reading voltages for level -1 correspond to 2P -1 first mapping function.

[0246] In some embodiments, the plurality of word lines includes Q word line groups, and the first mapping function includes Q second mapping functions corresponding to the Q word line groups respectively; the relationship between the first parameters of the physical pages coupled to each word line in the same word line group conforms to the corresponding second mapping function; wherein, Q is an integer greater than or equal to 1; the control unit is configured to: when obtaining the first parameters of the first physical page, obtain the first parameters of the physical pages coupled to at least one word line in each of the Q word line groups.

[0247] In some embodiments, the control unit is configured to: during a read operation following a data inspection operation, obtain a target reference voltage for at least one of the second physical pages based on a plurality of first parameters of the second physical page stored in the cache; and perform a read operation on at least one of the second physical pages according to the obtained target reference voltage.

[0248] In some embodiments, the parameter table updated for the Nth time includes the first parameters of the first physical page and the first parameters of the second physical page saved for the Nth time; the control unit is configured to: obtain read results of multiple first physical pages from the memory device through the interface; if decoding fails according to the read results, update the first parameters of the first physical page based on the first parameters of the first physical page saved in the mapping table updated for the Nth time, and generate the first parameters of the second physical page according to the updated first parameters of the first physical page; perform the N+1th saving of the updated first parameters of the first physical page and the generated first parameters of the second physical page as the parameter table updated for the N+1th time; N is a positive integer.

[0249] In some embodiments, the control unit is configured to: load the relation table characterizing the mapping function and the parameter table updated for the Nth time from the memory device in response to power-on of the memory controller; and save the parameter table updated for the N+1th time in the memory device in response to power-off of the memory controller.

[0250] In some embodiments, the preset model is a quadratic function model, and the first parameter is the curvature of the curve containing the quadratic function model.

[0251] In some embodiments, the control unit is configured to: acquire M first results corresponding to the physical page under M reference read voltages; the first results include the number of bits that flipped in two read results of the physical page under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; based on the M first results and the M reference read voltages, combined with the quadratic function model and the first parameter in the Nth updated mapping table, acquire a predicted reference voltage; the quadratic function model represents the relationship between the first results and the reference read voltages; all M first results are within a first preset interval; based on the predicted reference voltage, determine the target reference voltage and the first parameter in the N+1th updated parameters.

[0252] Secondly, the memory controller provided in this application samplees data from the first physical page within the memory block through a data inspection operation. By obtaining the first parameters of the first physical page, it generates the first parameters of the second physical page and saves the first parameters of both the first and second physical pages. By dynamically adjusting the first parameters based on the read results of the data inspection operation and further obtaining the target reference voltage of the physical page, the accuracy of data reading is improved. Simultaneously, it reduces reread operations, error correction and rewrite operations, and garbage collection operations in the data inspection operation, thereby reducing write amplification and significantly improving data inspection efficiency.

[0253] Thirdly, this application provides an operation method for a memory system, the operation method comprising:

[0254] During the data inspection operation, a first parameter of the first physical page among multiple physical pages is obtained; the first parameter is a parameter in a preset model used to generate the target reference voltage, and the target reference voltage is used as the read voltage when the physical page is read; the memory system includes at least one memory device, and the memory device includes multiple word lines; each word line is coupled to multiple memory cells, and the multiple memory cells coupled to the same word line form at least one physical page; the multiple physical pages include the first physical page and the second physical page, the first physical page is at least one physical page for performing the data inspection operation, and the second physical page is the remaining physical pages among the multiple physical pages other than the first physical page;

[0255] Based on the first parameter of the first physical page, and combined with the positional relationship between the second physical page and the first physical page, the first parameter of the second physical page is generated;

[0256] Save the first parameter of the first physical page and the first parameter of the second physical page.

[0257] In some embodiments, the operation method of the memory system includes: generating the first parameters of the second physical page based on the first parameters of the first physical page, the positional relationship between the second physical page and the first physical page, and combining a mapping function; the mapping function characterizes the relationship between the first parameters of the plurality of physical pages.

[0258] In some embodiments, the storage unit has P bits, where P storage bits correspond to 2^32 bits. P -1 level read voltage; where P is an integer greater than or equal to 1; the mapping function includes the 2 P The reading voltages for level -1 correspond to 2 P -1 first mapping function.

[0259] In some embodiments, the plurality of word lines includes Q word line groups, and the first mapping function includes Q second mapping functions corresponding to the Q word line groups respectively; the relationship between the first parameters of the physical pages coupled to each word line in the same word line group conforms to the corresponding second mapping function; wherein, Q is an integer greater than or equal to 1; the operation method of the memory system includes: when obtaining the first parameters of the first physical page, obtaining the first parameters of at least one physical page coupled to at least one word line in each of the P word line groups.

[0260] In some embodiments, the method of operating the memory system includes: during a read operation following a data inspection operation, obtaining a target reference voltage of at least one of the second physical pages based on a first parameter of the saved second physical pages; and performing a read operation on at least one of the second physical pages according to the obtained target reference voltage of at least one of the second physical pages.

[0261] In some embodiments, the parameter table updated for the Nth time includes the first parameters of the first physical page and the first parameters of the second physical page saved for the Nth time; the operation method of the memory system includes: during the data inspection operation, obtaining the read result of the first physical page; if the decoding fails according to the read result, updating the first parameters of the first physical page based on the first parameters of the first physical page saved in the parameter table updated for the Nth time, and generating the first parameters of the second physical page according to the updated first parameters of the first physical page; performing the N+1th saving of the updated first parameters of the first physical page and the generated first parameters of the second physical page as the parameter table updated for the N+1th time; N is a positive integer.

[0262] In some embodiments, the method of operating the memory system includes: loading a relation table characterizing the mapping function and the parameter table updated for the Nth time from the memory device in response to power-on of the memory system; and saving the parameter table updated for the (N+1)th time in the memory device in response to power-off of the memory system.

[0263] In some embodiments, the preset model is a quadratic function model, and the first parameter is the curvature of the curve containing the quadratic function model.

[0264] In some embodiments, the operation method of the memory system includes: obtaining M first results corresponding to the physical page under M reference read voltages; the first results include the number of bits that are flipped in two read results under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; obtaining a predicted reference voltage based on the M first results and the M reference read voltages, combined with the quadratic function model and the first parameter in the Nth updated mapping table; the quadratic function model represents the relationship between the first results and the reference read voltages; all M first results are within a first preset interval; and determining a target reference voltage and the first parameter in the N+1th updated parameter table based on the predicted reference voltage.

[0265] In some embodiments, the first preset interval represents the range between a first threshold and a second threshold of the curve containing the quadratic function model; the first threshold is greater than the second threshold.

[0266] In some embodiments, the method of operating the memory system includes: obtaining a first result corresponding to the physical page under a target read voltage; and, based on the fact that the first result corresponding to the physical page under the target read voltage is within a first preset interval, using the target read voltage as a reference read voltage, and using the first result within the first preset interval as the first result corresponding to the reference read voltage.

[0267] In some embodiments, the operation method of the memory system includes: obtaining prediction parameters of the quadratic function model based on the M first results and the M reference read voltages, combined with the quadratic function model; the prediction parameters are the reference read voltages corresponding to the minimum of the first results on the curve where the quadratic function model is located; obtaining the prediction reference voltage based on the prediction parameters; and determining the target reference voltage and the first parameter in the parameter table updated for the N+1th time based on the prediction reference voltage.

[0268] In some embodiments, the method of operating the memory system includes: acquiring a first result corresponding to the physical page at a target read voltage; and using the target read voltage as a reference read voltage based on the fact that the first result corresponding to the physical page at the target read voltage is within a first preset interval; and acquiring at least one new target read voltage based on the fact that the first result corresponding to the physical page at the target read voltage is outside the first preset interval, and acquiring the first result corresponding to the at least one new target read voltage, until the first result corresponding to the latest target read voltage is within the first preset interval.

[0269] In some embodiments, at least two of the M reference read voltages are located on opposite sides of the axis of symmetry of the curve containing the quadratic function model; the operation method of the memory system includes: when acquiring the reference read voltage, acquiring the reference read voltage on a first side of the axis of symmetry of the curve containing the quadratic function model; and determining the reference read voltage on a second side of the axis of symmetry based on the reference read voltage on the first side.

[0270] This application embodiment also provides an operation method for a memory controller, wherein the memory controller is coupled to at least one memory device, the memory device including multiple word lines; each word line is coupled to multiple memory cells, and the multiple memory cells coupled to the same word line form at least one physical page; the operation method includes: sending a data inspection start command to the memory device through the interface of the memory controller; obtaining a first parameter of a first physical page among the multiple physical pages according to the data fed back by the memory device; the first parameter is a parameter in a preset model for generating a target reference voltage, the target reference voltage being used as the read voltage when performing a read operation on the physical page; generating a first parameter of a second physical page based on the first parameter of the first physical page and the positional relationship between the second physical page and the first physical page; and storing the first parameter of the first physical page and the first parameter of the second physical page through the cache of the memory controller.

[0271] Figure 22 is a timing diagram of an exemplary single-level read mode operation provided in this application. DQx can represent a data bus signal, and Cycle Type can further represent the type of data bus signal.

[0272] As shown in Figure 22, the setting function command may include, for example, a subcommand (e.g., EFh). Exemplarily, the memory device initiates a single-level read mode upon receiving a subcommand EFh. In single-level read mode, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received subcommands 00h and 30h. During the read time, the data DATA (e.g., Dn) corresponding to the page at the received address can be cached in the page buffer first, and then the data DATA can be read on demand. It should be noted that in the above embodiment, when performing a reread operation, the memory device and the memory controller need to frequently transmit (Din / Dout) the data (e.g., Dn) corresponding to a physical page, which takes a long time.

[0273] Figure 23 is a timing diagram of a data inspection operation provided in an embodiment of this application. As shown in Figure 23, the read command may include, for example, two subcommands (e.g., 00h and 30h). Exemplarily, the memory device transmits the address ADDR (e.g., two column addresses C1-C2 and three row addresses R1-R3) of the data to be read between the received subcommands 00h and 30h. After the memory device receives subcommand 30h, during the read time, the data DATA (e.g., Dn) corresponding to the page at the received address can be cached in the page buffer first, and then the data DATA can be read on demand.

[0274] In an exemplary embodiment, the memory device 104 transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. After receiving sub-command 30h, the memory device 104 receives sub-commands EFh and xxh of the data inspection start instruction. Under the instruction of the data inspection start instruction, the memory device 104 acquires the read results of a portion of the physical pages and feeds back the data to the memory controller. It should be noted that the feedback data may be the failure bit count of the read results of the portion of the physical pages acquired by the data inspection operation. The memory controller obtains a first parameter of a first physical page from a plurality of physical pages based on feedback data received from the memory device. The first parameter is a parameter in a preset model used to generate a target reference voltage, which is used as the read voltage when performing a read operation on the physical page. The plurality of physical pages includes a first physical page and a second physical page. The first physical page is at least one physical page that performs a data inspection operation, and the second physical page is the remaining physical pages from the plurality of physical pages excluding the first physical page. Based on the first parameter of the first physical page and the positional relationship between the second physical page and the first physical page, the first parameter of the second physical page is generated. The first parameter of the first physical page and the first parameter of the second physical page are saved.

[0275] It should be noted that the data inspection start command provided in the embodiments of this application is only an example and should not excessively limit the scope of protection of this application.

[0276] In some embodiments, as shown in FIG24, the process of performing data inspection operation is verified by the operation method of the memory system provided in the embodiments of this application.

[0277] In step S201, a mapping function relationship table and a parameter table are established between the first parameters of physical pages coupled to different word lines. Next, step S202 is executed.

[0278] In step S202, a full disk fill operation is performed, that is, data is written to the SSD to be tested. Next, step S203 is executed.

[0279] In step S203, a temperature adjustment process is performed. For example, to accelerate the reduction in the data retention capability of the SSD under test, the SSD is heated, for instance, by using a temperature adjustment device to raise the temperature of the SSD to a preset temperature threshold. Here, the preset temperature threshold is lower than the upper limit of the SSD's specified retention temperature.

[0280] Next, step S204 is executed, and the SSD under test is powered on. When the SSD under test is powered on, a mapping function relationship table representing the relationship between the first parameters of physical pages with different word lines and a parameter table updated for the Nth time are loaded from the memory device. Taking N equals 1 as an example, after the SSD under test is powered on, an initial mapping table representing the relationship between the first parameters of physical pages with different word lines and a parameter table updated for the first time (initial parameter table) are loaded from the memory device.

[0281] Next, step S205 is executed to perform a data inspection operation on the first physical page. It should be noted that the data inspection operation does not need to traverse all physical pages in a storage block; that is, a sampling data inspection method can be used. For example, when performing a data inspection operation on a storage block, the read results of at least one physical page in the storage block are obtained. Here, the first physical page in the storage block is the target physical page for the data inspection operation among multiple physical pages, and the second physical page is the remaining physical pages among the multiple physical pages excluding the first physical page.

[0282] Next, step S206 is executed to determine whether the decoding of the read result obtained from the data inspection operation was successful.

[0283] If the judgment result of step S206 is yes, then step S207 is executed to end the operation.

[0284] If the judgment result of step S206 is negative, proceed to step S208 to perform a read operation on the second physical page. It should be noted that before executing step S208, if the decoding fails based on the read result, the first parameters of the first physical page are updated based on the first parameters of the first physical page stored in the parameter table updated for the Nth time. Further, the first parameters of the second physical page are generated based on the updated first parameters of the first physical page. The updated first parameters of the first physical page and the generated first parameters of the second physical page are saved for the N+1th time as the parameter table updated for the N+1th time. Specifically, refer to the description of obtaining the target reference voltage of the physical page and updating the first parameters based on the preset model and its first parameters in the foregoing embodiments; these details will not be repeated here.

[0285] Here, in this embodiment of the application, a temperature-changing operation is performed on the SSD under test before powering on to accelerate the weakening of its data retention capability. Therefore, during the temperature-changing operation, by controlling the duration for which the SSD under test is kept at a preset temperature threshold, the threshold voltage of the storage cell in the SSD under test can be shifted. This verifies whether the judgment result of step S206 is negative. The operation method provided in this embodiment of the application can update the first parameter of the first physical page and the first parameter of the second physical page, and further obtain the target reference voltage of the second physical page based on the updated first parameter, so as to improve the accuracy of performing read operations on the second physical page that has not undergone data inspection.

[0286] It is understood that in this embodiment of the application, in step S208, the target reference voltage obtained according to the updated first parameter of the second physical page is used to perform a read operation on the second physical page, and the obtained read result is successfully decoded.

[0287] Next, proceed to step S207 to end the operation.

[0288] This application also provides a storage medium storing executable instructions, which, when executed, can implement the steps of the operation method described in the above embodiments of this application.

[0289] In some specific embodiments, the storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it may be a device that includes one or any combination of the above-mentioned memory devices.

[0290] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0291] As an example, executable instructions may, but do not necessarily, correspond to files in a file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0292] As an example, executable instructions can be deployed to execute on a single electronic device, or on multiple electronic devices located in one location, or on multiple electronic devices distributed across multiple locations and interconnected via a communication network.

[0293] In some specific embodiments, referring to FIG25, FIG25 is a schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application; wherein, the storage medium includes a first storage medium corresponding to the memory controller 106 and a second storage medium corresponding to the memory system 102; when the executable instructions are executed by the memory controller, the first storage medium can be used to implement the steps of the operation method of the memory controller in the above embodiments of the present application; when the executable instructions are executed by the memory system, the second storage medium can be used to implement the steps of the operation method of the memory system in the above embodiments of the present application.

[0294] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0295] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made under the inventive concept of this application using the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application.

Claims

1. A memory system, comprising: a memory device including a plurality of word lines; each word line is coupled with a plurality of memory cells, and the plurality of memory cells coupled with the same word line forms at least one physical page; a memory controller coupled with the memory device and configured to: obtain a first parameter of a first physical page in a plurality of the physical pages during execution of a data patrol operation; the first parameter is a parameter in a preset model used to generate a target reference voltage, the target reference voltage is used as a read voltage for the physical page when performing a read operation; the plurality of physical pages include the first physical page and a second physical page, the first physical page is a target physical page of the data patrol operation in the plurality of physical pages, and the second physical page is a remaining physical page in the plurality of physical pages except the first physical page; generate a first parameter of the second physical page according to the first parameter of the first physical page and the positional relationship between the second physical page and the first physical page; save the first parameter of the first physical page and the first parameter of the second physical page.

2. The memory system of claim 1, wherein, the memory controller is configured to: generate the first parameter of the second physical page according to the first parameter of the first physical page, the positional relationship between the second physical page and the first physical page, and a mapping function; the mapping function represents the relationship between the first parameters of the plurality of physical pages.

3. The memory system of claim 2, wherein, The storage unit has P storage bits, and P storage bits correspond to 2 P a read voltage of level 1; wherein P is an integer greater than or equal to 1; the mapping function includes 2 P P first mapping functions corresponding to the 2 P P first mapping functions corresponding to the 2 4. The memory system of claim 3, wherein, the plurality of word lines include Q word line groups, and the first mapping function includes Q second mapping functions corresponding to the Q word line groups respectively; the relationship between the first parameters of the physical pages coupled with each word line in the same word line group conforms to the corresponding second mapping function; wherein Q is an integer greater than or equal to 1; the memory controller is configured to: obtain the first parameter of the physical page coupled with at least one word line in each word line group in the Q word line groups when obtaining the first parameter of the first physical page.

5. The memory system of claim 1, wherein, the memory controller is configured to: obtain a target reference voltage of at least one of the second physical pages based on the saved first parameter of the second physical page during execution of a read operation after the data patrol operation; perform a read operation on at least one of the second physical pages according to the obtained target reference voltage of at least one of the second physical pages.

6. The memory system of claim 1, wherein, the Nth updated parameter table includes the Nth saved first parameter of the first physical page and the first parameter of the second physical page; the memory controller is configured to: obtain a read result of the first physical page during execution of a data patrol operation; update the first parameter of the first physical page based on the saved first parameter of the first physical page in the Nth updated parameter table according to decoding failure of the read result, and generate the first parameter of the second physical page according to the updated first parameter of the first physical page; perform an N+1th saving of the updated first parameter of the first physical page and the generated first parameter of the second physical page as an N+1th updated parameter table; N is a positive integer.

7. The memory system of claim 6, wherein, the memory controller is configured to: in response to the memory system being powered on, loading a relation table representing a mapping function and the Nth updated parameter table from the memory device; in response to the memory system being powered off, saving the N+1th updated parameter table in the memory device.

8. The memory system of claim 6, wherein, The preset model is a quadratic function model, and the first parameter is the curvature of the curve of the quadratic function model.

9. The memory system of claim 8, wherein, The memory controller is configured to: obtain M first results corresponding to the physical page under M reference read voltages; the first result includes the number of bits representing the flipping of the read results of the physical page under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; obtain a predicted reference voltage according to the M first results and the M reference read voltages, in combination with the quadratic function model and the first parameter in the Nth updated mapping table; The quadratic function model represents the relationship between the first result and the reference read voltage. The M first results are all within a first preset interval. Based on the predicted reference voltage, determine the target reference voltage and the first parameter in the N+1th updated parameter table.

10. The memory system of claim 9, wherein, The first preset interval represents the range between the first threshold and the second threshold of the curve of the quadratic function model; the first threshold is greater than the second threshold.

11. The memory system of claim 9, wherein, The memory controller is configured to: obtain a first result corresponding to the physical page under a target read voltage; and According to the first result corresponding to the physical page under the target read voltage being within the first preset interval, the target read voltage is taken as one of the reference read voltages, and the first result within the first preset interval is taken as the first result corresponding to the reference read voltage.

12. The memory system of claim 9, wherein, The memory controller is configured to: obtain a predicted parameter of the quadratic function model according to the M first results and the M reference read voltages, in combination with the quadratic function model; the predicted parameter is the reference read voltage corresponding to the minimum first result on the curve of the quadratic function model; obtain the predicted reference voltage according to the predicted parameter; Based on the predicted reference voltage, determine the target reference voltage and the first parameter in the N+1th updated parameter table.

13. The memory system of claim 10, wherein, The memory controller is configured to: obtain a first result corresponding to the physical page under a target read voltage; and According to the first result corresponding to the physical page under the target read voltage being within the first preset interval, the target read voltage is taken as one of the reference read voltages; According to the first result corresponding to the physical page under the target read voltage being outside the first preset interval, at least one new target read voltage is re-obtained, and a first result corresponding to the at least one new target read voltage is obtained until the first result corresponding to the latest target read voltage is within the first preset interval.

14. The memory system of claim 13, wherein, At least two reference read voltages in the M reference read voltages are on both sides of the axis of symmetry of the curve of the quadratic function model. The memory controller is configured to: In the acquiring the reference read voltage, a reference read voltage on a first side of a symmetry axis of a curve of the quadratic function model is acquired; and According to the reference read voltage on the first side, a reference read voltage on a second side of the symmetry axis is determined.

15. The memory system of claim 1, wherein, The memory device includes a plurality of memory blocks, and each memory block includes a plurality of physical pages; the first physical page and the second physical page are located in the same memory block.

16. The memory system of claim 9, wherein, The memory device is configured to: read the stored data of the physical page at the first read voltage to obtain a second result; read the stored data of the physical page at the second read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; count the number of bits in the fourth result representing the flipping of the third result compared with the second result to obtain the first result.

17. The memory system of claim 16, wherein, The memory device includes a first latch, a second latch, and a third latch; The first latch is configured to store the second result; The second latch is configured to store the third result; The third latch is configured to store the fourth result.

18. A memory controller coupled with at least one memory device, the memory device comprising a plurality of word lines; Each word line is coupled to a plurality of memory cells, and the plurality of memory cells coupled to the same word line form at least one physical page; The memory controller includes an interface, a cache, and a control unit; wherein The control unit is configured to: acquire a first parameter of a first physical page in the plurality of physical pages according to the data fed back by the memory device; the first parameter is a parameter in a preset model used to generate a target reference voltage, and the target reference voltage is used as a read voltage for the physical page when performing a read operation; the plurality of physical pages include the first physical page and a second physical page, the first physical page is a target physical page of a data patrol operation in the plurality of physical pages, and the second physical page is a remaining physical page in the plurality of physical pages except the first physical page; generate a first parameter of the second physical page according to the first parameter of the first physical page and the positional relationship between the second physical page and the first physical page; save the first parameter of the first physical page and the first parameter of the second physical page in the cache.

19. The memory controller of claim 18, wherein, The control unit is configured to: send a data patrol start instruction to the memory device through the interface before acquiring the first parameter of at least one physical page in the plurality of physical pages according to the data fed back by the memory device.

20. The memory controller of claim 18, wherein, The control unit is configured to: generate the first parameter of the second physical page according to the first parameter of the first physical page, the positional relationship between the second physical page and the first physical page, and a mapping function; the mapping function represents the relationship between the first parameters of the plurality of physical pages.

21. The memory controller of claim 20, wherein, The storage unit has P storage bits, and P storage bits correspond to 2 P a read voltage of level 1; wherein P is an integer greater than or equal to 1. The mapping function includes 2 P -1 level read voltage corresponding to 2 P -1 first mapping The plurality of word lines include Q word line groups, and the first mapping function includes Q second mapping functions corresponding to the Q word line groups respectively; the relationship between the first parameters of the physical pages coupled to the word lines in the same word line group conforms to the corresponding second mapping function; wherein Q is an integer greater than or equal to 1.

22. The memory controller of claim 21, wherein, The plurality of word lines include Q word line groups, and the first mapping function includes Q second mapping functions corresponding to the Q word line groups respectively; the relationship between the first parameters of the physical pages coupled to the word lines in the same word line group conforms to the corresponding second mapping function; wherein Q is an integer greater than or equal to 1. The control unit is configured to: In acquiring the first parameters of the first physical pages, acquire the first parameters of physical pages coupled to at least one word line in each of the Q word line groups.

23. The memory controller of claim 18, wherein, The control unit is configured to: In a read operation after performing a data patrol operation, acquire a target reference voltage of at least one of the second physical pages based on the plurality of first parameters of the second physical pages saved by the cache; Perform a read operation on at least one of the second physical pages according to the acquired target reference voltage of at least one of the second physical pages.

24. The memory controller of claim 18, wherein, The Nth updated parameter table includes the first parameters of the first physical pages and the first parameters of the second physical pages saved in the Nth time; The control unit is configured to: Obtain read results of the plurality of first physical pages from the memory device through the interface; According to the read result decoding failure, update the first parameters of the first physical pages based on the first parameters of the first physical pages saved in the Nth updated mapping table, and generate the first parameters of the second physical pages according to the updated first parameters of the first physical pages; Perform the N+1th saving of the updated first parameters of the first physical pages and the generated first parameters of the second physical pages as the N+1th updated parameter table; N is a positive integer.

25. The memory controller of claim 24, wherein, The control unit is configured to: In response to the power-on of the memory controller, load the relationship table representing the mapping function and the Nth updated parameter table from the memory device; In response to the power-off of the memory controller, save the N+1th updated parameter table in the memory device.

26. The memory controller of claim 24, wherein, The preset model is a quadratic function model, and the first parameter is the curvature of the curve of the quadratic function model.

27. The memory controller of claim 26, wherein, The control unit is configured to: Obtain M first results corresponding to the physical page under M reference read voltages; the first result includes the number of bits representing the flipping of the read results of the physical page under the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; M is an integer greater than or equal to 2; According to the M first results and the M reference read voltages, the first parameters in the Nth updated mapping table and the quadratic function model, obtain a predicted reference voltage; The quadratic function model represents the relationship between the first result and the reference read voltage; The M first results are all within a first preset interval; Based on the predicted reference voltage, determine the target reference voltage and the first parameters in the N+1th updated parameter table.

28. An operating method of a memory system, the operating method comprising: In the process of performing a data patrol operation, acquiring a first parameter of a first physical page in a plurality of physical pages; The first parameter is a parameter in a preset model used to generate a target reference voltage, and the target reference voltage is used as a read voltage when performing a read operation on the physical page; The memory system includes at least one memory device, and the memory device includes a plurality of word lines; Each word line is coupled to a plurality of memory cells, and the plurality of memory cells coupled to the same word line form at least one physical page; The plurality of physical pages include the first physical page and a second physical page, the first physical page is at least one physical page for performing the data patrol operation, and the second physical page is the remaining physical page except the first physical page in the plurality of physical pages; According to the first parameter of the first physical page, in combination with the positional relationship between the second physical page and the first physical page, the first parameter of the second physical page is generated; The first parameter of the first physical page and the first parameter of the second physical page are saved.

29. A storage medium, the storage medium storing executable instructions, when the executable instructions are executed, the steps of the operation method of claim 28 can be implemented.

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