Memory system and operating method thereof, computer readable storage medium

Abstract

Embodiments of the present disclosure provide a memory system and an operating method thereof, and a computer readable storage medium, the memory system comprising a memory device and a memory controller coupled with the memory device; the memory controller is configured to: trigger assertion when an exception occurs in a running process of firmware of the memory system; set a flag of aborting a hardware sequence command when the hardware sequence command is not completed for release within a preset time after the firmware exception; in response to the flag of aborting the hardware sequence command, abort the hardware sequence command so that the hardware sequence command is completed for release.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, a memory system and its operation method, and a computer-readable storage medium. Background Technology

[0002] With the rapid development of data storage technology, more and more data storage systems are appearing in electronic devices used by people, such as solid-state drives (SSDs). Due to their characteristics of fast read and write speeds, shock resistance, low power consumption, no noise, low heat generation, and light weight, SSDs have been widely used in military, automotive, industrial, medical, and aerospace fields.

[0003] However, there are still many problems to be solved in the memory systems of related technologies. Summary of the Invention

[0004] According to a first aspect of the present disclosure, a memory system is provided, the memory system including a memory device and a memory controller coupled to the memory device; the memory controller is configured to:

[0005] An assertion is triggered when an error occurs in the firmware of the memory system during operation;

[0006] If a firmware error occurs and the hardware sequence command is not released within a preset time, a flag is set to abort the hardware sequence command.

[0007] In response to the flag indicating that the hardware sequence command should be aborted, the hardware sequence command is aborted, thereby releasing the hardware sequence command.

[0008] In some implementations, the memory controller is configured to:

[0009] When the hardware sequence command is released within the preset time, no flag is set to terminate the hardware sequence command.

[0010] In some implementations, the preset time is greater than 2 seconds.

[0011] In some implementations, the memory controller is configured to:

[0012] After the hardware sequence command is released, a command is sent to save the abnormal situation information to the memory device.

[0013] In some implementations, the memory controller is configured to:

[0014] Before sending the command to save the abnormal scene information to the memory device, send the command to store the abnormal scene information to the cache of the memory controller;

[0015] After the hardware sequence command completes its release, a command is sent to save the abnormal situation information stored in the cache of the memory controller to the memory device.

[0016] In some implementations, the memory controller is configured to:

[0017] Before sending the command to save the abnormal situation information to the memory device, a command to reset the memory device is sent.

[0018] In some implementations, the memory controller is configured to:

[0019] After an assertion is triggered, if it is determined that the exception is not caused by the execution of an error correction code operation, the assertion processing mode is determined.

[0020] In some implementations, the memory controller is configured to:

[0021] After an assertion is triggered, when it is determined that the exception is caused by the execution of an error correction code operation, and the location of the memory device that caused the exception is the first time that an exception caused by the execution of an error correction code operation has occurred, the assertion processing mode is determined to be triggered.

[0022] In some implementations, the memory controller is configured to:

[0023] Obtain the anomaly scene information, which was stored in the memory device prior to the occurrence of the anomaly, regarding the location of the memory device corresponding to the occurrence of the anomaly;

[0024] Based on the anomaly scene information of the location of the memory device that caused the anomaly, which was stored in the memory device before the anomaly occurred, it is determined whether the location of the memory device that caused the anomaly is the first time that an anomaly caused by performing an error correction code operation has occurred.

[0025] In some implementations, the memory controller is configured to:

[0026] After determining that the assertion handling mode has been triggered, a command to terminate the running program is sent.

[0027] According to a second aspect of the present disclosure, another memory system is provided, the memory system including a memory device and a memory controller coupled to the memory device; the memory controller is configured to:

[0028] An assertion is triggered when an error occurs in the firmware of the memory system during operation;

[0029] When the exception is caused by performing an error correction code operation, and the location of the memory device that caused the exception is not the first time that an exception caused by performing an error correction code operation has occurred, it is determined that the assertion processing mode will not be triggered.

[0030] In some implementations, the memory controller is configured to:

[0031] Obtain the anomaly scene information, which was stored in the memory device prior to the occurrence of the anomaly, regarding the location of the memory device corresponding to the occurrence of the anomaly;

[0032] Based on the anomaly scene information of the location of the memory device that caused the anomaly, which was stored in the memory device before the anomaly occurred, it is determined whether the location of the memory device that caused the anomaly is not the first time an anomaly caused by performing an error correction code operation has occurred.

[0033] In some implementations, the memory controller is configured to:

[0034] After determining that the assertion processing mode will not be triggered, a command is sent to save the event log information to the memory device.

[0035] In some implementations, the memory controller is configured to:

[0036] When the exception is not caused by the execution of error correction code operation, or when the exception is caused by the execution of error correction code operation, and the location of the memory device that caused the exception to occur is the first time that an exception caused by the execution of error correction code operation has occurred, the assertion processing mode is determined to be triggered.

[0037] In some implementations, the memory controller is configured to:

[0038] After determining that the assertion handling mode has been triggered, a command to terminate the running program is sent.

[0039] According to a third aspect of the present disclosure, a method for operating a memory system is provided, the method comprising:

[0040] An assertion is triggered when an error occurs in the firmware of the memory system during operation;

[0041] If a firmware error occurs and the hardware sequence command is not released within a preset time, a flag is set to abort the hardware sequence command.

[0042] In response to the flag indicating that the hardware sequence command should be aborted, the hardware sequence command is aborted, thereby releasing the hardware sequence command.

[0043] In some embodiments, the method further includes:

[0044] When the hardware sequence command is released within the preset time, no flag is set to terminate the hardware sequence command.

[0045] In some implementations, the preset time is greater than 2 seconds.

[0046] In some embodiments, the method further includes:

[0047] After the hardware sequence command is released, a command is sent to save the abnormal situation information to the memory device.

[0048] In some embodiments, the method further includes:

[0049] Before sending the command to save the abnormal scene information to the memory device, send the command to store the abnormal scene information to the cache of the memory controller;

[0050] After the hardware sequence command completes its release, a command is sent to save the abnormal situation information stored in the cache of the memory controller to the memory device.

[0051] In some embodiments, the method further includes:

[0052] Before sending the command to save the abnormal situation information to the memory device, a command to reset the memory device is sent.

[0053] In some embodiments, the method further includes:

[0054] After an assertion is triggered, if it is determined that the exception is not caused by the execution of an error correction code operation, the assertion processing mode is determined.

[0055] In some embodiments, the method further includes:

[0056] After an assertion is triggered, when it is determined that the exception is caused by the execution of an error correction code operation, and the location of the memory device that caused the exception is the first time that an exception caused by the execution of an error correction code operation has occurred, the assertion processing mode is determined to be triggered.

[0057] In some embodiments, the method further includes:

[0058] Obtain the anomaly scene information, which was stored in the memory device prior to the occurrence of the anomaly, regarding the location of the memory device corresponding to the occurrence of the anomaly;

[0059] Based on the anomaly scene information of the location of the memory device that caused the anomaly, which was stored in the memory device before the anomaly occurred, it is determined whether the location of the memory device that caused the anomaly is the first time that an anomaly caused by performing an error correction code operation has occurred.

[0060] In some embodiments, the method further includes:

[0061] After determining that the assertion handling mode has been triggered, a command to terminate the running program is sent.

[0062] According to a fourth aspect of the present disclosure, another method of operating a memory system is provided, the method comprising:

[0063] An assertion is triggered when an error occurs in the firmware of the memory system during operation;

[0064] When the exception is caused by performing an error correction code operation, and the location of the memory device that caused the exception is not the first time that an exception caused by performing an error correction code operation has occurred, it is determined that the assertion processing mode will not be triggered.

[0065] In some embodiments, the method further includes:

[0066] Obtain the anomaly scene information, which was stored in the memory device prior to the occurrence of the anomaly, regarding the location of the memory device corresponding to the occurrence of the anomaly;

[0067] Based on the anomaly scene information of the location of the memory device that caused the anomaly, which was stored in the memory device before the anomaly occurred, it is determined whether the location of the memory device that caused the anomaly is not the first time an anomaly caused by performing an error correction code operation has occurred.

[0068] In some embodiments, the method further includes:

[0069] After determining that the assertion processing mode will not be triggered, a command is sent to save the event log information to the memory device.

[0070] In some embodiments, the method further includes:

[0071] When the exception is not caused by the execution of error correction code operation, or when the exception is caused by the execution of error correction code operation, and the location of the memory device that caused the exception to occur is the first time that an exception caused by the execution of error correction code operation has occurred, the assertion processing mode is determined to be triggered.

[0072] In some embodiments, the method further includes:

[0073] After determining that the assertion handling mode has been triggered, a command to terminate the running program is sent.

[0074] According to a fifth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, performs an operation method as described in any of some embodiments. Attached Figure Description

[0075] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0076] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0077] Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0078] Figure 3a This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure;

[0079] Figure 3b This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure;

[0080] Figure 4 This is a schematic cross-sectional view of a memory array including memory strings according to an embodiment of the present disclosure;

[0081] Figure 5 This is a schematic diagram of an exemplary memory including a memory array and peripheral circuitry according to an embodiment of the present disclosure;

[0082] Figure 6 This is a schematic diagram illustrating the implementation flow of an operation method for a memory system according to an embodiment of the present disclosure;

[0083] Figure 7 This is a schematic flowchart illustrating the framework of an operation method for a memory system according to an embodiment of the present disclosure;

[0084] Figure 8 This is a schematic diagram illustrating the implementation flow of an operation method for a memory system according to another embodiment of the present disclosure;

[0085] Figure 9 This is a schematic flowchart illustrating the operation method of a memory system according to another embodiment of the present disclosure. Detailed Implementation

[0086] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0087] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0088] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0089] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0090] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0091] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0092] In order to gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0093] Figure 1 A block diagram of an exemplary system 100 having memory according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit) of an electronic device or a system-on-a-chip (e.g., an application processor). The host 108 may be configured to send data to or receive data from the memory device 104.

[0094] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as secure digital cards, compact flash memory cards, universal serial bus flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0095] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable function, such as formatting the memory device 104. The memory controller 106 can communicate with an external device (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with an external device via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), Peripheral Component Interconnect High Speed ​​(PCHIHS), Advanced Technology Attached Protocol (ATIP), Serial Advanced Technology Attached Protocol (STP), Parallel Advanced Technology Attached Protocol (PATP), Minicomputer Small Interface Protocol (MSIP), Enhanced Small Disk Interface (MSDI), Integrated Drive Electronic Devices Protocol (IDEMP), firmware protocols, etc.

[0096] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an embedded multimedia card package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a compact flash memory card, a smart media card, a memory stick, a multimedia card, a secure digital card, UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include components for connecting the SSD 206 to a host computer (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0097] Figure 3a An exemplary schematic diagram of a three-dimensional NAND flash memory array is provided, such as... Figure 3a As shown, the memory array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered rows of memory cells parallel to the gate isolation structure. Every four rows of memory cells are separated by a gate isolation structure and an up-select gate isolation structure. Each row of memory cells includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory array into multiple memory blocks. Multiple second gate isolation structures can divide the memory blocks into multiple finger memory regions. An up-select gate isolation structure located in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory chips. Figure 3a The storage block shown contains 6 memory chips. In practical applications, the number of memory chips in a storage block is not limited to this. A memory cell in a memory chip coupled to a word line can be called a memory page (English expression: Page), and here a memory page is a physical page.

[0098] It should be noted that, Figure 3a The number of cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0099] Figure 3bA schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND-type memory array, where memory cells 306 are NAND memory cells, provided in the form of an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0100] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0101] like Figure 3bAs shown, each memory string 308 may include a bottom-selected transistor (BST) 310 at its source end and a top-selected transistor (TST) 312 at its drain end. BST 310 and TST 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TST 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TST312) or a deselection voltage (e.g., 0V) to the corresponding TST312 via one or more TSL (Top selected line) 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BST310) or a deselection voltage (e.g., 0V) to the corresponding BST310 via one or more BSL (Bottom Selected line) 315.

[0102] like Figure 3bAs shown, memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) biased and coupled to the source line 314 of the selected memory block and unselected memory blocks on the same plane as the selected memory block can be used. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a memory page 320 of memory cell 306. The size of a memory page 320, in bits, can be related to the number of memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding memory page 320, as well as gate lines coupling the control gates. (This is in conjunction with the preceding...) Figure 3a A memory page 320 contains multiple memory cells 306, which are separated by an upselect gate isolation structure and a gate isolation structure. The multiple memory cells between the upselect gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to the gate isolation structure and the upselect gate isolation structure. The memory cells in the memory chip sharing the same word line form a programmable (read / write) page.

[0103] Figure 4 A schematic cross-sectional view of an exemplary memory array 301 including a memory string 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of memory cells included in the memory array 301 is mainly related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0104] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0105] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0106] In some embodiments, the memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0107] Return to reference Figure 3bPeripheral circuitry 302 can be coupled to memory array 301 via bit line 316, word line 318, source line 314, BSL 315, and TSL 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSL 315, and TSL 313, and sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0108] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0109] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory array 301 and to select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSL 315 and TSL 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0110] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0111] Operations on the memory system (such as writing data, reading data, erasing data, etc.) can be performed by running firmware stored in the memory system.

[0112] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0113] Firmware errors (bugs) inevitably occur during firmware operation. Traditionally, this is handled by directly triggering assertions, which in turn trigger the assertion handling mode, terminating program execution and saving the error context. However, with the increasing demands on 3D NAND flash memory, ensuring successful saving of error context information after firmware failures and improving user testing efficiency have become pressing issues.

[0114] To address one or more of the aforementioned problems, embodiments of this disclosure provide a method for operating a memory system, such as... Figure 6 As shown, the method includes:

[0115] Step S1001: When an error occurs in the firmware of the memory system during operation, an assertion is triggered;

[0116] Step S1002: If the hardware sequence command fails to be released within a preset time after the firmware malfunctions, a flag is set to terminate the hardware sequence command.

[0117] Step S1003: In response to the flag indicating that the hardware sequence command is aborted, the hardware sequence command is aborted, thereby releasing the hardware sequence command.

[0118] The following will combine Figure 6 as well as Figure 7 The operation methods of the memory system are described in detail.

[0119] Here, firmware is a program written into an erasable programmable read-only memory or electrically erasable programmable read-only memory. It refers to the device "driver" stored inside the memory system. Through firmware, the operating system can perform specific actions according to the standard device driver. Firmware is the software that performs the most basic and lowest-level work of a system.

[0120] In some specific examples, the firmware is stored in read-only memory or a memory device within the memory controller of the memory system.

[0121] Firmware inevitably encounters exceptions during operation. These exceptions trigger assertions and, under certain conditions, further trigger assertion handling mode, thereby saving the exception context information. This exception context information can include the PC pointer, stack usage information, register coredump information, etc. By saving this exception context information, the fault context is preserved, providing data support for subsequent system recovery.

[0122] When a firmware error occurs, it may be executing or about to execute hardware sequence commands. Hardware sequence commands can be understood as commands that specify the execution order of read, write, and erase commands. When an error occurs during firmware operation, the current task needs to be cleared and the hardware sequence commands released in order to save the error context information. However, if the hardware sequence commands cannot be released, the firmware will get stuck in an infinite loop (while), causing the saving of the error context information to fail.

[0123] Regarding how the hardware sequence command should specifically complete the release, this disclosure proposes different implementation methods based on different situations.

[0124] In some embodiments, in the triggered assertion processing mode, if a hardware sequence command fails to be released within a preset time after a firmware exception, a flag is set to abort the hardware sequence command.

[0125] It is understandable that abnormal situation information can only be saved after the hardware sequence command is released. If the hardware sequence command is not released within a preset time, it means that the firmware is stuck in the while loop and cannot be released automatically. In this embodiment of the present disclosure, a flag for terminating the hardware sequence command is set, and the hardware sequence command is forcibly released in response to the flag in the subsequent process. This can avoid the problem of failure to save abnormal situation information due to the inability of the hardware sequence command to be released automatically.

[0126] In some embodiments, the method further includes:

[0127] When the hardware sequence command is released within the preset time, no flag is set to terminate the hardware sequence command.

[0128] Understandably, hardware sequence commands can also be released automatically. The time required for hardware sequence commands to complete automatic release is generally short. When a hardware sequence command completes release within a preset time, it means that the firmware is not stuck in the while loop and the hardware sequence command has completed automatic release. Therefore, it is not necessary to set an additional flag to stop the hardware sequence command to force its release.

[0129] In some embodiments, the preset time is greater than 2 seconds.

[0130] It should be noted that the preset time range given in the above embodiments is merely an exemplary demonstration. It is not intended to limit the range of preset times in the embodiments of this disclosure. In practical applications, the preset time range can be set according to the normal automatic release time of the hardware sequence command.

[0131] In some specific examples, such as Figure 7As shown, it can be checked whether a flag for terminating the hardware sequence command is set. If the flag for terminating the hardware sequence command is set, the hardware sequence command is directly and forcibly terminated, so that the hardware sequence command is forcibly released.

[0132] In some embodiments, the method further includes:

[0133] After the hardware sequence command is released, a command is sent to save the abnormal situation information to the memory device.

[0134] In some embodiments, the method further includes:

[0135] Before sending the command to save the abnormal scene information to the memory device, send the command to store the abnormal scene information to the cache of the memory controller;

[0136] After the hardware sequence command completes its release, a command is sent to save the abnormal situation information stored in the cache of the memory controller to the memory device.

[0137] Here, when an exception occurs during firmware operation, an assertion will be triggered. After the assertion is triggered, the exception context information will first be cached in the cache of the memory controller. After the hardware sequence command is released, the exception context information stored in the memory controller will be transferred to a specific storage block in the memory device.

[0138] In some embodiments, such as Figure 7 As shown, the method further includes:

[0139] Before sending the command to save the abnormal situation information to the memory device, a command to reset the memory device is sent.

[0140] It is understandable that when sending the command to save the abnormal situation information to the memory device, the memory device may still be executing other commands, which may prevent the command to save the abnormal situation information from being executed. Therefore, before sending the command to save the abnormal situation information to the memory device, the memory device needs to be reset so that the abnormal situation information can be saved.

[0141] An error during firmware operation will trigger an assertion. The assertion can further judge the abnormal situation of the firmware and determine whether the abnormal situation meets certain set conditions. If the set conditions are not met, the assertion processing mode will not be triggered, the program will continue to run, and the problem information will not be saved. The assertion processing mode will be triggered only when the set conditions are met. In the assertion processing mode, the program will be terminated and the abnormal situation information will be saved.

[0142] In some embodiments, the method further includes:

[0143] After an assertion is triggered, if it is determined that the exception is not caused by the execution of an error correction code operation, the assertion processing mode is determined.

[0144] In some embodiments, the method further includes:

[0145] After an assertion is triggered, when it is determined that the exception is caused by the execution of an error correction code operation, and the location of the memory device that caused the exception is the first time that an exception caused by the execution of an error correction code operation has occurred, the assertion processing mode is determined to be triggered.

[0146] It is understandable that firmware runtime exceptions can occur in various ways. When certain special exceptions, such as those caused by error correction code operations (including 0x43C and 0xA107), occur, and the memory location corresponding to the exception has previously experienced such an exception, the firmware cannot guarantee that such an exception will not occur. Therefore, it is unnecessary to save the exception context information every time. Garbage collection and host read operations can respectively cause 0x43C and 0xA107 exceptions.

[0147] In some embodiments, the method further includes:

[0148] Obtain the anomaly scene information, which was stored in the memory device prior to the occurrence of the anomaly, regarding the location of the memory device corresponding to the occurrence of the anomaly;

[0149] Based on the anomaly scene information of the location of the memory device that caused the anomaly, which was stored in the memory device before the anomaly occurred, it is determined whether the location of the memory device that caused the anomaly is the first time that an anomaly caused by performing an error correction code operation has occurred.

[0150] Understandably, after the current exception occurs, the exception context information of the exception that occurred before the corresponding memory device location that caused the exception can be read from the memory device. It can be determined whether the current exception has occurred before at the corresponding memory device location, thereby determining whether this exception is the first time it has occurred at that location, and then determining whether to trigger the assertion processing mode.

[0151] In some embodiments, the method further includes:

[0152] After determining that the assertion handling mode has been triggered, a command to terminate the running program is sent.

[0153] In this embodiment of the disclosure, after triggering the assertion, the abnormal situation is further judged. When it is determined that the abnormality is not caused by the execution of error correction code operation, or when it is determined that the abnormality is caused by the execution of error correction code operation, and the location of the memory device that caused the abnormality occurs for the first time due to the execution of error correction code operation, the assertion processing mode is triggered. This can avoid triggering the assertion processing mode when the abnormality caused by the execution of error correction code operation occurs repeatedly at the same location, thereby avoiding unnecessary termination of the running program and unnecessary saving of abnormal situation information, thereby improving the user's testing efficiency.

[0154] This disclosure provides an operation method for a memory system, the method comprising: triggering an assertion when an error occurs in the firmware of the memory system during operation; setting a flag to abort the hardware sequence command if the hardware sequence command is not released within a preset time after the firmware error; and aborting the hardware sequence command in response to the flag, thereby causing the hardware sequence command to be released. In this disclosure, when an error occurs in the firmware during operation, the release status of the hardware sequence command is judged. If the hardware sequence command is not released within a preset time, it indicates that the firmware is stuck in an infinite loop and cannot release automatically. By setting a flag to abort the hardware sequence command, the hardware sequence command is forcibly aborted, thereby forcibly releasing the hardware sequence command, which can avoid the problem of failure to save abnormal situation information due to the inability to release the hardware sequence command.

[0155] This disclosure provides another method for operating a memory system, such as... Figure 8 As shown, the method includes:

[0156] Step S2001: When an error occurs in the firmware of the memory system during operation, an assertion is triggered;

[0157] Step S2002: When the exception is caused by the execution of error correction code operation, and the location of the memory device that caused the exception is not the first time that an exception caused by the execution of error correction code operation has occurred, determine that the assertion processing mode is not triggered.

[0158] In some specific examples, exceptions occurring during firmware runtime include various scenarios. When certain special exceptions, such as those caused by error-correction code operations (including 0x43C and 0xA107), are detected by the memory system, the corresponding memory location causing the exception will generally be marked as a Medium Error. The program will continue running, but this exception at that location may still trigger assertion handling, causing the test to terminate midway. Furthermore, since the memory location corresponding to the exception has previously experienced this exception, the firmware cannot guarantee that such an exception will not occur. Therefore, it is unnecessary to save the exception context information every time. The 0x43C and 0xA107 exceptions can be caused during garbage collection and host read operations, respectively.

[0159] It is understandable that if the assertion processing mode is triggered, the program will be terminated and the exception context information will be saved, which will take some time, resulting in low user testing efficiency. In this embodiment of the present disclosure, after the assertion is triggered, the exception situation is further judged. When the exception is caused by the execution of error correction code operation, and the memory device corresponding to the occurrence of the exception is not the first time that the exception caused by the execution of error correction code operation has occurred, the assertion processing mode is not triggered. This can avoid unnecessary termination of the program and unnecessary saving of exception context information when the exception caused by the execution of error correction code operation occurs repeatedly in the same location, thereby improving user testing efficiency.

[0160] The following will combine Figure 8 as well as Figure 9 The operation methods of the memory system are described in detail.

[0161] In some embodiments, the method further includes:

[0162] Obtain the anomaly scene information, which was stored in the memory device prior to the occurrence of the anomaly, regarding the location of the memory device corresponding to the occurrence of the anomaly;

[0163] Based on the anomaly scene information of the location of the memory device that caused the anomaly, which was stored in the memory device before the anomaly occurred, it is determined whether the location of the memory device that caused the anomaly is not the first time an anomaly caused by performing an error correction code operation has occurred.

[0164] Understandably, after the current exception occurs, the exception scene information of the previous exception that occurred at the location of the memory device that caused the exception can be read from the memory device. This allows us to determine whether the current exception has occurred at the corresponding location of the memory device before, and thus determine whether the assertion processing mode should be triggered.

[0165] In some embodiments, the method further includes:

[0166] After determining that the assertion processing mode will not be triggered, a command is sent to save the event log information to the memory device.

[0167] Here, the event log information simply records the exception, such as the time when the exception occurred and the location of the corresponding memory device.

[0168] In some embodiments, the method further includes:

[0169] When the exception is not caused by the execution of error correction code operation, or when the exception is caused by the execution of error correction code operation, and the location of the memory device that caused the exception to occur is the first time that an exception caused by the execution of error correction code operation has occurred, the assertion processing mode is determined to be triggered.

[0170] In some embodiments, the method further includes:

[0171] After determining that the assertion handling mode has been triggered, a command to terminate the running program is sent.

[0172] Understandably, the firmware provided to users generally does not trigger assertions. If an assertion is triggered, it indicates a serious problem, and the program will not continue to run in a loop. However, the 0x43C and 0xA107 exceptions are special, caused by an uncorrectable UECC error generated on the memory device. Even after handling the exception problem later, the firmware cannot guarantee that such exceptions will not recur. Therefore, it is unnecessary to repeatedly record the exception context information for such exceptions, nor is it necessary to terminate the program. Since terminating the program and saving the exception context information both consume a lot of time, this would result in low testing efficiency.

[0173] This disclosure provides an operation method for a memory system, comprising: triggering an assertion when an exception occurs in the firmware of the memory system during operation; and determining that an assertion processing mode is not triggered when the exception is caused by executing error correction code operations and the location of the memory device that caused the exception is not the first time an exception caused by executing error correction code operations has occurred. In this disclosure, when an exception occurs during firmware operation, the exception situation is further judged. When the exception is caused by executing error correction code operations and the location of the memory device that caused the exception is not the first time an exception caused by executing error correction code operations has occurred, the assertion processing mode is not triggered. This avoids unnecessary program termination and unnecessary saving of exception context information, thereby improving testing efficiency and saving storage capacity for exception context information.

[0174] Based on the above-described operation method of the memory system, this disclosure also provides a memory system, the memory system including a memory device and a memory controller coupled to the memory device; the memory controller is configured to:

[0175] An assertion is triggered when an error occurs in the firmware of the memory system during operation;

[0176] If a firmware error occurs and the hardware sequence command is not released within a preset time, a flag is set to abort the hardware sequence command.

[0177] In response to the flag indicating that the hardware sequence command should be aborted, the hardware sequence command is aborted, thereby releasing the hardware sequence command.

[0178] In some embodiments, the memory controller is configured to:

[0179] When the hardware sequence command is released within the preset time, no flag is set to terminate the hardware sequence command.

[0180] In some embodiments, the preset time is greater than 2 seconds.

[0181] In some embodiments, the memory controller is configured to:

[0182] After the hardware sequence command is released, a command is sent to save the abnormal situation information to the memory device.

[0183] In some embodiments, the memory controller is configured to:

[0184] Before sending the command to save the abnormal scene information to the memory device, send the command to store the abnormal scene information to the cache of the memory controller;

[0185] After the hardware sequence command completes its release, a command is sent to save the abnormal situation information stored in the cache of the memory controller to the memory device.

[0186] In some embodiments, the memory controller is configured to:

[0187] Before sending the command to save the abnormal situation information to the memory device, a command to reset the memory device is sent.

[0188] In some embodiments, the memory controller is configured to:

[0189] After an assertion is triggered, if it is determined that the exception is not caused by the execution of an error correction code operation, the assertion processing mode is determined.

[0190] In some embodiments, the memory controller is configured to:

[0191] After an assertion is triggered, when it is determined that the exception is caused by the execution of an error correction code operation, and the location of the memory device that caused the exception is the first time that an exception caused by the execution of an error correction code operation has occurred, the assertion processing mode is determined to be triggered.

[0192] In some embodiments, the memory controller is configured to:

[0193] Obtain the anomaly scene information, which was stored in the memory device prior to the occurrence of the anomaly, regarding the location of the memory device corresponding to the occurrence of the anomaly;

[0194] Based on the anomaly scene information of the location of the memory device that caused the anomaly, which was stored in the memory device before the anomaly occurred, it is determined whether the location of the memory device that caused the anomaly is the first time that an anomaly caused by performing an error correction code operation has occurred.

[0195] In some embodiments, the memory controller is configured to:

[0196] After determining that the assertion handling mode has been triggered, a command to terminate the running program is sent.

[0197] In some embodiments, the memory system includes a memory card or a solid-state drive.

[0198] Based on the above-described operation method of the memory system, this disclosure also provides another memory system, the memory system including a memory device and a memory controller coupled to the memory device; the memory controller is configured to:

[0199] An assertion is triggered when an error occurs in the firmware of the memory system during operation;

[0200] When the exception is caused by performing an error correction code operation, and the location of the memory device that caused the exception is not the first time that an exception caused by performing an error correction code operation has occurred, it is determined that the assertion processing mode will not be triggered.

[0201] In some embodiments, the memory controller is configured to:

[0202] Obtain the anomaly scene information, which was stored in the memory device prior to the occurrence of the anomaly, regarding the location of the memory device corresponding to the occurrence of the anomaly;

[0203] Based on the anomaly scene information of the location of the memory device that caused the anomaly, which was stored in the memory device before the anomaly occurred, it is determined whether the location of the memory device that caused the anomaly is not the first time an anomaly caused by performing an error correction code operation has occurred.

[0204] In some embodiments, the memory controller is configured to:

[0205] After determining that the assertion processing mode will not be triggered, a command is sent to save the event log information to the memory device.

[0206] In some embodiments, the memory controller is configured to:

[0207] When the exception is not caused by the execution of error correction code operation, or when the exception is caused by the execution of error correction code operation, and the location of the memory device that caused the exception to occur is the first time that an exception caused by the execution of error correction code operation has occurred, the assertion processing mode is determined to be triggered.

[0208] In some embodiments, the memory controller is configured to:

[0209] After determining that the assertion handling mode has been triggered, a command to terminate the running program is sent.

[0210] Here, the specific structure and composition of the memory system can be referred to the aforementioned section. Figure 1 , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4 , Figure 5 A detailed introduction is provided below. For the sake of brevity, it will not be elaborated upon here.

[0211] Based on the above-described memory system operation method, this disclosure also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the operation method described in any of the above embodiments.

[0212] Here, implementing all or part of the processes in the methods of the above embodiments can be accomplished by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the methods described above. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive, etc.; the storage medium can also include combinations of the above types of memory.

[0213] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0214] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0215] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory system, characterized in that, The memory system includes a memory device and a memory controller coupled to the memory device; the memory controller is configured to: An assertion is triggered when an error occurs in the firmware of the memory system during operation; If a firmware error occurs and the hardware sequence command is not released within a preset time, a flag is set to abort the hardware sequence command. The hardware sequence command includes commands that specify the execution order of each command in the read, write, and erase commands; In response to the flag indicating that the hardware sequence command should be aborted, the hardware sequence command is aborted, thereby releasing the hardware sequence command.

2. The memory system according to claim 1, characterized in that, The memory controller is configured to: When the hardware sequence command is released within the preset time, no flag is set to terminate the hardware sequence command.

3. The memory system according to claim 1 or 2, characterized in that, The preset time is greater than 2 seconds.

4. The memory system according to claim 1 or 2, characterized in that, The memory controller is configured to: After the hardware sequence command is released, a command is sent to save the abnormal situation information to the memory device.

5. The memory system according to claim 4, characterized in that, The memory controller is configured to: Before sending the command to save the abnormal scene information to the memory device, send the command to store the abnormal scene information to the cache of the memory controller; After the hardware sequence command completes its release, a command is sent to save the abnormal situation information stored in the cache of the memory controller to the memory device.

6. The memory system according to claim 4, characterized in that, The memory controller is configured to: Before sending the command to save the abnormal situation information to the memory device, a command to reset the memory device is sent.

7. The memory system according to claim 1 or 2, characterized in that, The memory controller is configured to: After an assertion is triggered, if it is determined that the exception is not caused by the execution of an error correction code operation, the assertion processing mode is determined.

8. The memory system according to claim 1 or 2, characterized in that, The memory controller is configured to: After an assertion is triggered, when it is determined that the exception is caused by the execution of an error correction code operation, and the location of the memory device that caused the exception is the first time that an exception caused by the execution of an error correction code operation has occurred, the assertion processing mode is determined to be triggered.

9. The memory system according to claim 8, characterized in that, The memory controller is configured to: Obtain the anomaly scene information, which was stored in the memory device prior to the occurrence of the anomaly, regarding the location of the memory device corresponding to the occurrence of the anomaly; Based on the anomaly scene information of the location of the memory device that caused the anomaly, which was stored in the memory device before the anomaly occurred, it is determined whether the location of the memory device that caused the anomaly is the first time that an anomaly caused by performing an error correction code operation has occurred.

10. The memory system according to claim 7, characterized in that, The memory controller is configured to: After determining that the assertion handling mode has been triggered, a command to terminate the running program is sent.

11. A memory system, characterized in that, The memory system includes a memory device and a memory controller coupled to the memory device; the memory controller is configured to: An assertion is triggered when an error occurs in the firmware of the memory system during operation; When the exception is caused by performing an error correction code operation, and the location of the memory device that caused the exception is not the first time that an exception caused by performing an error correction code operation has occurred, it is determined that the assertion processing mode will not be triggered.

12. The memory system according to claim 11, characterized in that, The memory controller is configured to: Obtain the anomaly scene information, which was stored in the memory device prior to the occurrence of the anomaly, regarding the location of the memory device corresponding to the occurrence of the anomaly; Based on the anomaly scene information of the location of the memory device that caused the anomaly, which was stored in the memory device before the anomaly occurred, it is determined whether the location of the memory device that caused the anomaly is not the first time an anomaly caused by performing an error correction code operation has occurred.

13. The memory system according to claim 11, characterized in that, The memory controller is configured to: After determining that the assertion processing mode will not be triggered, a command is sent to save the event log information to the memory device.

14. The memory system according to claim 11, characterized in that, The memory controller is configured to: When the exception is not caused by the execution of error correction code operation, or when the exception is caused by the execution of error correction code operation, and the location of the memory device that caused the exception to occur is the first time that an exception caused by the execution of error correction code operation has occurred, the assertion processing mode is determined to be triggered.

15. The memory system according to claim 14, characterized in that, The memory controller is configured to: After determining that the assertion handling mode has been triggered, a command to terminate the running program is sent.

16. A method for operating a memory system, characterized in that, The method includes: An assertion is triggered when an error occurs in the firmware of the memory system during operation; If a firmware error occurs and the hardware sequence command is not released within a preset time, a flag is set to abort the hardware sequence command; the hardware sequence command includes commands that specify the execution order of each command among the read, write, and erase commands; In response to the flag indicating that the hardware sequence command should be aborted, the hardware sequence command is aborted, thereby releasing the hardware sequence command.

17. The operating method according to claim 16, characterized in that, The method further includes: When the hardware sequence command is released within the preset time, no flag is set to terminate the hardware sequence command.

18. The operating method according to claim 16 or 17, characterized in that, The preset time is greater than 2 seconds.

19. The operating method according to claim 16 or 17, characterized in that, The method further includes: After the hardware sequence command is released, a command is sent to save the abnormal situation information to the memory device.

20. The operating method according to claim 19, characterized in that, The method further includes: Before sending the command to save the abnormal scene information to the memory device, send the command to store the abnormal scene information to the cache of the memory controller; After the hardware sequence command completes its release, a command is sent to save the abnormal situation information stored in the cache of the memory controller to the memory device.

21. The operating method according to claim 19, characterized in that, The method further includes: Before sending the command to save the abnormal situation information to the memory device, a command to reset the memory device is sent.

22. The operating method according to claim 16 or 17, characterized in that, The method further includes: After an assertion is triggered, if it is determined that the exception is not caused by the execution of an error correction code operation, the assertion processing mode is determined.

23. The operating method according to claim 16 or 17, characterized in that, The method further includes: After an assertion is triggered, when it is determined that the exception is caused by the execution of an error correction code operation, and the location of the memory device that caused the exception is the first time that an exception caused by the execution of an error correction code operation has occurred, the assertion processing mode is determined to be triggered.

24. The operating method according to claim 23, characterized in that, The method further includes: Obtain the anomaly scene information, which was stored in the memory device prior to the occurrence of the anomaly, regarding the location of the memory device corresponding to the occurrence of the anomaly; Based on the anomaly scene information of the location of the memory device that caused the anomaly, which was stored in the memory device before the anomaly occurred, it is determined whether the location of the memory device that caused the anomaly is the first time that an anomaly caused by performing an error correction code operation has occurred.

25. The operating method according to claim 22, characterized in that, The method further includes: After determining that the assertion handling mode has been triggered, a command to terminate the running program is sent.

26. A method for operating a memory system, characterized in that, The method includes: An assertion is triggered when an error occurs in the firmware of the memory system during operation; When the exception is caused by performing an error correction code operation, and the location of the memory device that caused the exception is not the first time that an exception caused by performing an error correction code operation has occurred, it is determined that the assertion processing mode will not be triggered.

27. The operating method according to claim 26, characterized in that, The method further includes: Obtain the anomaly scene information, which was stored in the memory device prior to the occurrence of the anomaly, regarding the location of the memory device corresponding to the occurrence of the anomaly; Based on the anomaly scene information of the location of the memory device that caused the anomaly, which was stored in the memory device before the anomaly occurred, it is determined whether the location of the memory device that caused the anomaly is not the first time an anomaly caused by performing an error correction code operation has occurred.

28. The operating method according to claim 26, characterized in that, The method further includes: After determining that the assertion processing mode will not be triggered, a command is sent to save the event log information to the memory device.

29. The operating method according to claim 26, characterized in that, The method further includes: When the exception is not caused by the execution of error correction code operation, or when the exception is caused by the execution of error correction code operation, and the location of the memory device that caused the exception to occur is the first time that an exception caused by the execution of error correction code operation has occurred, the assertion processing mode is determined to be triggered.

30. The operating method according to claim 29, characterized in that, The method further includes: After determining that the assertion handling mode has been triggered, a command to terminate the running program is sent.

31. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, performs the operating method as described in any one of claims 16 to 30.

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