Memory controller and data processing method

Abstract

The present invention relates to a memory controller and a data processing method. The memory controller includes an error correction code engine, a buffer memory, and a microprocessor. The microprocessor performs a repeated read operation on a memory device in response to a first decoding result of intended data to obtain a plurality of read results of a data chunk containing the intended data, wherein the data chunk includes a plurality of bits. The microprocessor further performs a data reconstruction and correction procedure based on the read results of the data chunk. In the data reconstruction operation, the microprocessor determines a bit value corresponding to a bit of the data chunk based on the read results of the data chunk to generate a reconstructed data chunk. In the error correction operation, the microprocessor provides the reconstructed data chunk to the error correction code engine to obtain a second decoding result of the intended data.

Description

Technical Field

[0001] This invention relates to a data processing method and a corresponding memory controller that can effectively improve the error correction performance of a memory device. Background Technology

[0002] With the evolution of encoding technology, many error correction codes (or error correction codes) have been developed for use in error correction code engines for memory devices, and the error correction capabilities of these codes vary. Generally speaking, the stronger the error correction capability of an error correction code engine, the more expensive it is, because it is usually developed using more complex error correction codes with stronger error correction capabilities. However, due to cost considerations, error correction codes with relatively weaker error correction capabilities are still widely used.

[0003] For example, for slower storage devices (such as Universal Serial Bus (USB) flash drives), BCH (an abbreviation of Bose, Chaudhuri, and Hocquenghem) codes are still widely chosen as error correction codes due to their advantages of simple design, low cost, and small size. However, BCH codes have limited correction capabilities. With the same amount of data, BCH codes can typically correct fewer errors than other higher-order error correction codes.

[0004] In order to enhance error correction performance in products that use error correction codes with relatively weak error correction capabilities, this invention proposes a data processing method and a corresponding memory controller to improve the error correction performance of memory devices. Summary of the Invention

[0005] One object of the present invention is to improve the error correction performance of memory devices.

[0006] According to one embodiment of the present invention, a memory controller coupled to a memory device for controlling access operations of the memory device includes an error correction code engine, a buffer memory, and a microprocessor. The error correction code engine encodes data to be written to the memory device and decodes data read from the memory device. The buffer memory provides data buffering. After the error correction code engine completes decoding and outputs a first decoding result of the predetermined data, the microprocessor, in response to the first decoding result indicating error correction failure, performs repeated read operations on the memory device to obtain multiple read results of data blocks containing the predetermined data in the memory device. The data blocks include multiple bits, and the read results are obtained and stored in the buffer memory in a state where the error correction code engine has not performed decoding. The microprocessor further executes a data reconstruction and correction procedure based on the reading result of the data block. The data reconstruction and correction procedure includes a data reconstruction operation and an error correction operation. In the data reconstruction operation, the microprocessor determines the bit value corresponding to the bit of the data block based on the reading result of the data block to generate a reconstructed data block. In the error correction operation, the microprocessor provides the reconstructed data block to the error correction code engine to obtain a second decoding result of the given data.

[0007] According to another embodiment of the present invention, a data processing method, executed by a memory controller coupled to a memory device, includes: after an error correction code engine completes decoding processing and outputs a first decoding result of predetermined data, in response to the first decoding result of the predetermined data indicating error correction failure, performing a repeated read operation on the memory device to obtain multiple read results of a data block containing predetermined data in the memory device, wherein the data block includes multiple bits, and the read results are obtained in a state without decoding processing by the error correction code engine and stored in a buffer memory of the memory controller; and performing a data reconstruction and correction procedure based on the read results of the data block to obtain a second decoding result of the predetermined data. The step of performing the data reconstruction and correction procedure based on the read results of the data block further includes: determining a bit value corresponding to a bit of the data block based on the read results of the data block to generate a reconstructed data block; and providing the reconstructed data block to the error correction code engine of the memory controller to obtain the second decoding result of the predetermined data. Attached Figure Description

[0008] Figure 1 This shows a block diagram example of a data storage device according to an embodiment of the present invention.

[0009] Figure 2 This diagram shows an example flowchart of a data processing method according to an embodiment of the present invention.

[0010] Figure 3 This illustrates a data processing flow example according to an embodiment of the present invention.

[0011] Figure 4 This displays an example of a table showing the bit value statistics of each bit read manually according to an embodiment of the present invention.

[0012] [Symbol Explanation]

[0013] 100: Data storage device

[0014] 110: Memory controller

[0015] 112: Microprocessor

[0016] 112C: Program Code

[0017] 112M: Read-Only Memory

[0018] 114: Memory Interface

[0019] 116: Buffer memory

[0020] 118: Host Interface

[0021] 120: Memory device

[0022] 130: Main unit

[0023] 140: Error correction code engine

[0024] 400: Statistical Table Detailed Implementation

[0025] Numerous specific details are described below to provide a thorough understanding of embodiments of the invention. However, those skilled in the art will appreciate how the invention can be practiced in the absence of one or more specific details or in reliance on other methods, elements, or materials. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring the main concepts of the invention.

[0026] Throughout this specification, references to "an embodiment" or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one of the various embodiments of the invention. Therefore, the phrases "in an embodiment of the invention," "according to an embodiment of the invention," "in an example," or "according to an example" appearing in various places throughout this specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples.

[0027] Furthermore, to make the objectives, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below in detail with reference to the accompanying drawings. The purpose is to illustrate the spirit of the present invention and not to limit the scope of protection of the present invention. It should be understood that the following embodiments can be implemented by software, hardware, firmware, or any combination thereof.

[0028] Figure 1 This diagram illustrates a block diagram example of a data storage device according to an embodiment of the present invention. The data storage device 100 may include a memory device 120 and a memory controller 110. The memory controller 110 is used to access the memory device 120 and control its operation. The memory device 120 may be a non-volatile (NV) memory device (e.g., a flash memory) and may include one or more memory elements (e.g., one or more flash memory dies, one or more flash memory chips, or other similar elements).

[0029] Data storage device 100 may be coupled to a host device 130. Host device 130 may include at least a processor, a power supply circuit, and at least one random access memory (RAM), such as at least one dynamic random access memory (DRAM), at least one static random access memory (SRAM), etc. (not shown above). Figure 1 The processor and random access memory (RAM) can be interconnected via a bus and coupled to a power supply circuit to obtain power. The processor controls the operation of the host device 130. The power supply circuit can supply power to the processor, RAM, and data storage device 100, for example, by outputting one or more drive voltages to the data storage device 100. The data storage device 100 can obtain the drive voltage from the host device 130 as its power source and provide storage space for the host device 130.

[0030] According to one embodiment of the present invention, the host device 130 may issue instructions to the data storage device 100, such as read instructions or write instructions, to access the data stored in the memory device 120, or the host device 130 may issue instructions to the data storage device 100 to further control and manage the data storage device 100.

[0031] According to one embodiment of the present invention, the memory controller 110 may include a microprocessor 112, a read-only memory (ROM) 112M, a memory interface 114, a buffer memory 116, and a host interface 118. The ROM 112M is used to store program code 112C. The microprocessor 112 is used to execute program code 112C to control access to the memory device 120. Program code 112C may include one or more program modules, such as bootloader program code. When the data storage device 100 receives power from the host device 130, the microprocessor 112 may execute an initialization program of the data storage device 100 by executing program code 112C. In the initialization program, the microprocessor 112 may load a set of in-system programming (ISP) code (not shown) from the memory device 120. Figure 1 The microprocessor 112 can execute this set of in-system programming code, enabling the data storage device 100 to possess various functions. According to one embodiment of the invention, this set of in-system programming code may include, but is not limited to: one or more program modules related to memory access (e.g., read, write, and erase), such as a read operation module, a lookup table module, a wear leveling module, a read refresh module, a read reclaim module, a garbage collection module, a sudden power off recovery (SPOR) module, and an uncorrectable error correction code (UECC) module, which are respectively provided to perform corresponding read, lookup table, wear leveling, read refresh, read reclaim, garbage collection, sudden power off recovery, and error handling of detected UECC errors.

[0032] Memory interface 114 includes an error correction code engine 140. The error correction code engine 140 may internally include a data buffer (not shown) for temporarily storing data to assist the engine in performing encoding and decoding operations. During the write process of writing data to memory device 120, the error correction code engine 140 encodes the data to be written to memory device 120, for example, by performing error correction code (ECC) encoding to generate additional parity bits. During the read process of reading data from memory device 120, the error correction code engine 140 decodes the data read from memory device 120 to detect erroneous bits in the data, and, if correctable (e.g., the number of erroneous bits in the data does not exceed the upper limit of the number of erroneous bits that the error correction code engine 140 can correct), corrects the bit values ​​of the erroneous bits.

[0033] In a typical configuration, memory device 120 includes multiple memory elements, such as multiple flash memory dies or multiple flash memory chips, and each memory element may contain multiple memory blocks. Memory controller 110 performs data erasure operations on memory device 120 on a block-by-block basis. Additionally, a memory block may record (contain) a specific number of data pages, such as physical data pages, wherein memory controller 110 performs data write operations on memory device 120 on a page-by-page basis.

[0034] In practice, the memory controller 110 can use its internal components to perform various control operations, such as using the memory interface 114 to control the access operations of the memory device 120 (especially the access operations to at least one memory block or at least one data page), using the buffer memory 116 to perform the necessary buffering operations, and using the host interface 118 to communicate with the host device 130.

[0035] In one embodiment, the memory controller 110 communicates with the host device 130 via the host interface 118 and using a standard communication protocol. For example, the aforementioned standard communication protocol includes (but is not limited to): Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, CF interface standard, MMC interface standard, eMMC interface standard, UFS interface standard, Advanced Technology Attachment (ATA) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, Parallel Advanced Technology Attachment (PATA) standard, etc.

[0036] In one embodiment, the buffer memory 116 used to provide data buffering is implemented as random access memory. For example, the buffer memory 116 may be static random access memory, but the invention is not limited thereto. In other embodiments, the buffer memory 116 may be dynamic random access memory.

[0037] In one embodiment, the data storage device 100 may be a portable storage device (e.g., a memory card conforming to SD / MMC, CF, MS, XD standards, a USB flash drive, etc.), and the host device 130 may be an electronic device that can be connected to the data storage device, such as a mobile phone, a laptop, a desktop computer, etc. In another embodiment, the data storage device 100 may be a solid-state drive or an embedded storage device conforming to UFS or eMMC specifications, and may be disposed in an electronic device, such as a mobile phone, a laptop, or a desktop computer, in which case the host device 130 may be a processor of the electronic device.

[0038] As described above, in order to enhance the error correction performance of the data storage device 100, the present invention proposes a data processing method and a corresponding memory controller, which attempts to successfully decode the data by recombining the original content of the read data and performing the error correction operation again.

[0039] Figure 2 This diagram illustrates an example flowchart of a data processing method according to an embodiment of the present invention. The data processing method proposed in this invention can be executed by a memory controller 110 and may include the following steps:

[0040] Step S202: In response to a first decoding result of predetermined data, a repeated read operation is performed on the memory device 120 to obtain multiple read results of a data chunk containing the predetermined data in the memory device 120. In one embodiment of the present invention, the repeated read operation may be triggered when the first decoding result is a result indicating that error correction has failed.

[0041] Step S204: Execute a data reconstruction and correction procedure based on multiple read results of the data block to obtain a second decoding result of the predetermined data. According to an embodiment of the present invention, the data reconstruction and correction procedure may include a data reconstruction operation and an error correction operation. In the data reconstruction operation, the memory controller 110 may determine the bit value corresponding to each bit in the data block based on multiple read results of the data block to generate a reconstructed data block. In the error correction operation, the memory controller 110 may provide the reconstructed data block to the error correction code engine 140, so that the error correction code engine 140 decodes the reconstructed data block to obtain a second decoding result of the predetermined data.

[0042] In embodiments of the present invention, the second decoding result may indicate successful error correction or failure. When the second decoding result indicates successful error correction, it means that all erroneous bits in the given data can be detected and corrected back to the correct bit values. That is, the correct content of the given data can be restored by the error correction code engine 140. Conversely, when the second decoding result indicates failure, it means that the number of erroneous bits in the given data still exceeds the upper limit of the number of erroneous bits that the error correction code engine 140 can correct, therefore the error correction code engine 140 cannot successfully perform error correction on the currently reconstructed data block.

[0043] In an embodiment of the present invention, if the second decoding result indicates successful error correction, the memory controller 110 may terminate the current data processing flow. If the second decoding result indicates unsuccessful error correction, the memory controller 110 may further execute the following steps:

[0044] Step S206: Based on the multiple read results of the data block, re-execute the data reconstruction and correction procedure to obtain a third decoding result of the given data. Since step S206 is not mandatory, it is omitted here. Figure 2 The middle part is indicated by a dashed line.

[0045] According to an embodiment of the present invention, when re-executing the data reconstruction and correction procedure, the memory controller 110 may modify the bit value corresponding to at least one bit of the reconstructed data block according to one or more flip logics to regenerate the reconstructed data block, and provide the regenerated reconstructed data block to the error correction code engine 140, so that the error correction code engine 140 decodes the regenerated reconstructed data block to obtain the third decoding result of the predetermined data.

[0046] Similarly, in embodiments of the present invention, if the third decoding result indicates successful error correction, the memory controller 110 may terminate the current data processing flow. If the third decoding result indicates unsuccessful error correction, the memory controller 110 may execute step S206 again to obtain the fourth decoding result of the predetermined data, and so on.

[0047] Generally, when the memory controller 110 executes a read operation on the memory device 120 in response to a read instruction received from the host device 130 requesting to read predetermined data, the memory controller 110 accesses the memory device 120 through the memory interface 114 to read the predetermined data, and the error correction code engine 140 performs decoding processing on the read data. The decoding operation of the error correction code engine 140 includes detecting erroneous bits in the predetermined data and attempting to correct the erroneous bits to repair errors that occurred when the predetermined data was stored in the memory device 120. If the number of erroneous bits in the predetermined data does not exceed the upper limit of the number of erroneous bits that the error correction code engine 140 can correct, the error correction code engine 140 can successfully repair the erroneous bits in the predetermined data and restore the correct content of the predetermined data. If the number of erroneous bits in the given data exceeds the upper limit of the number of erroneous bits that the error correction code engine 140 can correct, it means that an error that cannot be corrected by the error correction code (ECC Uncorrectable Error) has occurred. The error correction code engine 140 cannot determine the correct content of the given data, so it will set the decoding result to indicate that the error correction has failed.

[0048] In the existing design, when an error correction failure occurs, the memory controller 110 directly reports an error correction failure (ECC Failure) to the host device 130 and provides the read data to the host device 130. Since the memory controller 110 cannot detect which bits in the data are erroneous, and therefore cannot repair the erroneous bits in the data, the memory controller 110 can only provide the read result containing many unknown erroneous bits to the host device 130.

[0049] To address the aforementioned problems, and particularly to enhance error correction performance in products employing error correction codes with relatively weak error correction capabilities, this invention proposes the aforementioned data processing method and corresponding memory controller. This method attempts to successfully decode the data by recombining the original read data and performing the error correction operation again. The following paragraphs will provide a more detailed explanation.

[0050] Figure 3 This illustrates an example of a data processing flow according to an embodiment of the present invention. In this embodiment, the data processing flow applying the aforementioned data processing method may begin in an error correction failure (ECC Failure) state, but unlike existing designs, this error correction failure is not reported to the host device 130 at this time. Assuming the host device 130 issues a read instruction to read a given piece of data of size kilobytes (KB), the memory controller 110 will access the memory device 120 in response to the received read instruction to attempt to read the given data. When an error correction failure occurs on the read data (step S302), the microprocessor 112 of the memory controller 110 will manually perform a repeated read operation, performing multiple read operations on a data block containing the given data (step S304).

[0051] In embodiments of the present invention, a data block may include multiple bits, and the content of the data block may include predetermined data and corresponding parity information, wherein the parity information is information generated by the error correction code engine 140 when writing the predetermined data into the memory device 120, which helps to correct errors subsequently. Therefore, the data block read by the microprocessor 112 in step S304 may include multiple data bits of the predetermined data and one or more bits (parity bits) corresponding to the parity information. For example, in step S304, the microprocessor 112 may read the predetermined data and the corresponding parity information N times to obtain N read results, where N is a positive integer greater than 1.

[0052] In embodiments of the present invention, the manual read operation refers to the microprocessor 112 skipping the error correction operation of the error correction code engine 140 when reading the memory device 120. Therefore, the data obtained by the microprocessor 112 is the most original read result (raw data) of the given data and parity information. That is, the read result that has not been decoded by the error correction code engine 140 or has not been corrected by the error correction code engine 140.

[0053] Generally, when the memory controller 110 activates the card, it writes the error correction code-related settings into the system data block of the memory device 120. This system data block stores the data required for the operation of the memory controller 110. During the initialization process of the data storage device 100, the memory controller 110 can configure a corresponding control module based on the contents of the system data block. For example, this module might be a flash memory control module generated by the microprocessor 112 through executing software or firmware code to control the memory device 120. For instance, the microprocessor 112 can set the length of the parity bits for the flash memory control module based on the contents of the system data block.

[0054] Assuming that in a previous write operation that wrote 1KB (one thousand bytes) of predetermined data to memory device 120, the error correction engine 140 generated an additional 120B (120 bytes) of parity information (or parity bits), this 120B of parity information will be written to memory device 120 along with the 1KB of predetermined data.

[0055] When performing a non-manual read operation (i.e., a general read operation), such as when the aforementioned memory controller 110 reads predetermined data in response to a read instruction from the host device 130, the microprocessor 112 issues a read instruction to the memory device 120 through the flash memory control module. The read instruction specifies the starting address of the read operation and sets the read length to (1KB + 120B) to read the predetermined data and its corresponding parity information simultaneously. In response to this read instruction, the memory device 120 sends the read data back to the error correction engine 140. The read data is temporarily stored in the data buffer inside the error correction engine 140, and the error correction engine 140 performs a decoding operation on the data. After decoding is completed, regardless of whether the decoding result is successful or unsuccessful, the error correction code engine 140 will discard the 120B parity information and only transmit the 1KB of predetermined data (which will be the corrected predetermined data if there are erroneous bits and they can be corrected) to the buffer memory 116 of the memory controller 110, and then the memory controller 110 will transmit it back to the host device 130.

[0056] During manual read operations, the microprocessor 112 also issues a read command to the memory device 120 through the flash memory control module. The read command specifies the starting address of the read operation and sets the read length to (1KB + 120B) to read the predetermined data and its corresponding parity information. However, at this time, the microprocessor 112 disables the decoding function of the error correction engine 140, or disables it. In response to this read command, the memory device 120 sends the read data back to the error correction engine 140, and the (1KB + 120B) read data temporarily stored in the data buffer inside the error correction engine 140 is directly transferred to the buffer memory 116 of the memory controller 110. Therefore, compared to performing a normal read operation, the error correction engine 140 only transmits the predetermined data to be read to the buffer memory 116. When performing a manual read operation, the error correction engine 140 transmits the predetermined data to be read and its corresponding parity information to the buffer memory 116 together.

[0057] According to one embodiment of the present invention, the error correction code engine 140 can be disabled during repeated read operations. For example, the error correction code engine 140 can be enabled by default, and the microprocessor 112 can temporarily disable the error correction code engine 140 by setting a corresponding register during the period when repeated read operations need to be performed (i.e., the period when multiple manual read operations need to be performed). According to another embodiment of the present invention, the microprocessor 112 can also temporarily disable the error correction code engine 140 during the period when repeated read operations need to be performed by other setting methods, or temporarily disable the decoding function of the error correction code engine 140 during the period when repeated read operations need to be performed.

[0058] According to an embodiment of the present invention, in step S304, the microprocessor 112 manually performs N repeated reading operations on the data block containing predetermined data and its corresponding parity information, so that each bit of the data block has corresponding N reading results, and stores the N reading results of each bit in the buffer memory 116.

[0059] According to an embodiment of the present invention, after obtaining N read results for each bit, the microprocessor 112 can perform a data reconstruction operation (step S306) using the read results to reconstruct the content of the given data and its corresponding parity information. In step S306, the microprocessor 112 can further analyze the content of the read results for each bit, for example, to accumulate how many times the bit value of each bit of the data block was determined to be 1 and how many times its bit value was determined to be 0 in N reads, so as to obtain the corresponding statistical results.

[0060] Figure 4This displays an example of a statistical table showing the bit values ​​of manually read bits according to an embodiment of the present invention. In the statistical table 400, each bit is separated by a different bit index value. For example, the bit index values ​​shown in the table are 0 to 9151, where bits 0 to 8191 are the content of a given data (in this example, the given data size is 8KB), and bits 8192 to 9151 are the odd and even bits corresponding to this given data.

[0061] According to one embodiment of the present invention, in a data reconstruction operation, the microprocessor 112 can select a majority value as the bit value corresponding to each bit based on the N read results corresponding to each bit. Taking the statistical table 400 as an example, since the read results of bit value 0 are the majority among the 10 read results of bits 0, 1, and 3, the microprocessor 112 can set the bit values ​​of bits 0, 1, and 3 to 0 during reconstruction. Similarly, since the read results of bit value 1 are the majority among the 10 read results of bits 2, the microprocessor 112 can set the bit value of bit 2 to 1 during reconstruction. The remaining bits can be deduced in the same way. The microprocessor 112 can determine the bit value corresponding to each bit in the data block according to this rule to generate a reconstructed data block. It should be noted that the present invention is not limited to data reconstruction by selecting a majority value. For example, in other embodiments of the present invention, the minority value of the N reading results can also be set to the bit value corresponding to a portion of the bits.

[0062] Next, the microprocessor 112 can provide a reconstructed data block to the error correction code engine 140, and the error correction code engine 140 performs error correction decoding operations on the reconstructed data block (step S308). In one embodiment of the present invention, the error correction code engine 140 can be restored to an enabled state during periods when it is not performing repeated read operations, or the microprocessor 112 can restore the decoding function of the error correction code engine 140.

[0063] The microprocessor 112 can determine whether the decoding result of step S308 is still an error correction failure (step S310). If not, it means the error correction is successful, and the microprocessor 112 can write the data recovered by the error correction code engine 140 back to the memory device 120 (step S312) to save the correct content of the predetermined data. According to an embodiment of the present invention, the microprocessor 112 can write the recovered data back to the memory device 120 through a data update operation. For example, the microprocessor 112 can regard the data recovered by the error correction code engine 140 as the updated data of the logical address corresponding to the predetermined data, and store it in the memory device 120. When the host device 130 wants to access the data content of this logical address next time, it can read the correct content.

[0064] As described above, after decoding is complete, the error correction engine 140 transmits the predetermined data (either the corrected predetermined data or the aforementioned recovered data if there are erroneous bits that can be corrected) to the buffer memory 116 of the memory controller 110. Therefore, the microprocessor 112 can write the data in the buffer memory 116 back to the memory device 120.

[0065] If the decoding result of step S308 still indicates error correction failure, the microprocessor 112 can further determine whether there are other alternative data reconstruction operations to choose from (step S314). In embodiments of the present invention, the data reconstruction operation performed in step S204 or the first entry into step S306 can be a preset data reconstruction operation, while the data processing method proposed in the present invention can design one or more alternative data reconstruction operations to provide for when the data reconstruction and correction procedure needs to be re-executed (e.g., such as...). Figure 3 As shown, it is used when the determination in step S310 is "yes".

[0066] If the microprocessor 112 determines that there are no other alternative data reconstruction operations to choose from, it reports the error correction failure and data recovery failure to the host device 130 (step S316) (the data recovery failure is marked in the figure to distinguish it from step S302), and provides the read predetermined data content to the host device 130. If the microprocessor 112 determines that there are other alternative data reconstruction operations to choose from, the process flow can return to step S306 (or, in some embodiments, it can return to step S304).

[0067] In the embodiments of the present invention, since only the relevant parts of the data reconstruction operation differ when the data reconstruction and correction procedures are re-executed, while the error correction operation is the same, the relevant parts of the data reconstruction operation will be described below.

[0068] According to an embodiment of the present invention, when re-executing the data reconstruction and correction procedure, the microprocessor 112 may modify the bit value corresponding to at least one bit in the data block according to one or more flip logic based on the reading result of the previously obtained data block and the previously reconstructed data block, so as to regenerate the reconstructed data block. The flip logic is a logical condition for selecting bits whose bit values ​​can be flipped (for example, flipping the originally set bit value 0 to 1, or flipping the originally set bit value 1 to 0).

[0069] According to one embodiment of the present invention, the flip logic may be a logic condition in which the probability of the read bit value being determined as 0 is similar to that of the read bit value being determined as 1, or the difference between the number of times the read bit value is determined as 0 and the number of times the read bit value is determined as 1 is less than a threshold value.

[0070] For example, the microprocessor 112 may select one or more bits in N reads whose difference between the number of times the bit value was determined to be 1 and the number of times the bit value was determined to be 0 (i.e., the difference of count values ​​in the statistics table 400) is less than a threshold value, and modify the bit value corresponding to at least one of these bits to regenerate the reconstructed data block.

[0071] Taking statistical table 400 as an example, assuming the threshold is set to 3 during the first re-execution of the data reconstruction and correction procedure, the microprocessor 112 can select at least the 3rd bit whose bit value can be flipped (because the difference in the count value of the 3rd bit (6-4=2) is less than 3). Since the bit value of the 3rd bit was set to 0 during the previous execution of the data reconstruction and correction procedure, the microprocessor 112 can modify the bit value of the 3rd bit to 1 during the first re-execution of the data reconstruction and correction procedure. The microprocessor 112 can follow this logic to select bits whose bit values ​​can be flipped and modify their bit values ​​to regenerate the reconstructed data blocks.

[0072] According to another embodiment of the invention, the toggle logic may also be set according to the properties of the memory device 120. For example, the toggle logic may be a logic condition regarding whether each bit is stored in an error-prone storage location in the memory device 120. The microprocessor 112 may select one or more bits stored in error-prone storage locations in the memory device 120 and modify the bit value corresponding to at least one of them to regenerate a reconstructed data block.

[0073] According to another embodiment of the present invention, the alternative data reconstruction operation can also be designed to reread the data block and reconstruct the data block. For example, the microprocessor 112 can return to step S304 with the previously set reading voltage and manually perform the aforementioned repeated reading operation on the given data again, and then perform the data reconstruction operation in step S306 according to the newly obtained reading result, thereby also having the opportunity to achieve the result of modifying the bit value corresponding to at least one bit in the data block.

[0074] According to another embodiment of the present invention, an alternative data reconstruction operation can also be designed to read the data block again after adjusting the read voltage and then reconstruct the data block. For example, the microprocessor 112 can analyze the voltage currently programmed to the memory device 120 through the corresponding firmware to obtain a programmed voltage distribution map, and determine a better read voltage based on this voltage distribution map. Then, the newly determined read voltage can be used to return to step S304 to manually perform the aforementioned repeated read operation on the given data again, and then the data reconstruction operation is performed in step S306 based on the newly obtained read result, thereby potentially achieving the result of modifying the bit value corresponding to at least one bit in the data block.

[0075] In embodiments of the present invention, multiple read results are obtained by repeatedly reading data and corresponding parity information, and the read results with a higher probability of correctness are extracted to reconstruct the data. This helps to improve the data repair success rate of the error correction code engine 140. Assume that the error correction code engine 140 can correct a maximum of 60 erroneous bits, and in a certain read, 70 bits of the data block containing the given data are erroneous, resulting in error correction failure. In this case, by applying the data processing method proposed in this invention, if the bit values ​​corresponding to 10 bits are reconstructed (or flipped) to the correct values ​​during data reconstruction or additional bit value flipping operations, the decoding result of the given data will no longer be an error correction failure. Therefore, by applying the data processing method proposed in this invention, the probability of correcting erroneous data can be significantly increased, thereby effectively improving the error correction performance of the memory device. In particular, for memory devices equipped with error correction code engines that have relatively weak error correction capabilities, not only can the error correction performance of the memory device be greatly improved, but the cost of the memory device can also be reduced as a result.

[0076] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. A memory controller coupled to a memory device for controlling access operations of the memory device, comprising: An error correction code engine is used to encode data to be written to the memory device and to decode data read from the memory device; A buffer memory used to provide data buffering; as well as A microprocessor, after the error correction code engine completes decoding and outputs a first decoding result of predetermined data, in response to the first decoding result indicating error correction failure, performs a repeated read operation on the memory device to obtain multiple read results of a data block containing the predetermined data in the memory device, wherein the data block includes multiple bits, and the multiple read results are obtained and stored in the buffer memory without the error correction code engine decoding process. The microprocessor further executes a data reconstruction and correction procedure based on the multiple read results of the data block. The data reconstruction and correction procedure includes a data reconstruction operation and an error correction operation. In the data reconstruction operation, the microprocessor determines the bit value corresponding to the multiple bits of the data block based on the multiple read results of the data block to generate a reconstructed data block. In the error correction operation, the microprocessor provides the reconstructed data block to the error correction code engine to obtain a second decoding result of the given data.

2. The memory controller as claimed in claim 1, characterized in that, The first decoding result of the given data is a result indicating that the error correction has failed.

3. The memory controller as described in claim 1, characterized in that, The content of this data block includes the given data and the parity information corresponding to the given data.

4. The memory controller as claimed in claim 1, characterized in that, The multiple read results of the data block are the original read results obtained from the memory device and not decoded by the error correction code engine at the time of acquisition, for subsequent use in the data reconstruction operation.

5. The memory controller as claimed in claim 1, characterized in that, The error correction engine is disabled during the repeated read operation so that the multiple read results retain the original read state of each data bit in the data block for subsequent use in the data reconstruction operation.

6. The memory controller as claimed in claim 1, characterized in that, In this data reconstruction operation, the microprocessor selects one of the multiple read results corresponding to each bit as the bit value corresponding to that bit.

7. The memory controller as claimed in claim 1, characterized in that, After completing the repeated read operation and the data reconstruction operation, when the second decoding result of the given data is a result indicating error correction failure, the microprocessor re-executes the data reconstruction and correction procedure. When the microprocessor re-executes the data reconstruction and correction procedure, the microprocessor modifies the bit value corresponding to at least one bit of the reconstructed data block according to the multiple read results of the data block to regenerate the reconstructed data block, and provides the reconstructed data block to the error correction code engine to obtain a third decoding result of the given data.

8. A data processing method, executed by a memory controller coupled to a memory device, comprising: After an error correction code engine completes the decoding process and outputs a first decoding result of a given data, in response to the first decoding result of the given data indicating that the error correction has failed, a repeated read operation is performed on the memory device to obtain multiple read results of a data block containing the given data in the memory device, wherein the data block includes multiple bits, and the multiple read results are obtained in a state without the decoding process of the error correction code engine and are stored in a buffer memory of the memory controller; as well as Based on the multiple read results of the data block, a data reconstruction and correction procedure is performed to obtain a second decoding result of the given data. The steps for performing the data reconstruction and correction procedure based on the multiple read results of the data block also include: Based on the multiple read results of the data block, determine the bit value corresponding to the multiple bits of the data block to generate a reconstructed data block; as well as The reconstructed data block is provided to the error correction engine of the memory controller to obtain the second decoding result of the given data.

9. The data processing method as described in claim 8, characterized in that, The first decoding result of the given data is a result indicating that the error correction has failed.

10. The data processing method as described in claim 8, characterized in that, The content of this data block includes the given data and the parity information corresponding to the given data.

11. The data processing method as described in claim 8, characterized in that, The multiple read results of the data block are the original read results obtained from the memory device and not decoded by the error correction code engine at the time of acquisition, for subsequent use in the data reconstruction operation.

12. The data processing method as described in claim 8, characterized in that, Also includes: The error correction engine is disabled during the repeated read operation so that the multiple read results retain the original read state of each data bit in the data block for subsequent use in the data reconstruction operation.

13. The data processing method as described in claim 8, characterized in that, The step of determining the bit value corresponding to the multiple bits of the data block based on the multiple read results of the data block further includes: Based on the multiple read results corresponding to each bit, select one of the values ​​as the bit value corresponding to that bit.

14. The data processing method as described in claim 8, characterized in that, After completing the repeated reading operation and the data reconstruction operation, when the second decoding result of the given data indicates that error correction has failed, the data processing method further includes: The data reconstruction and correction procedure is re-executed to obtain a third decoding result of the given data. The steps involved in re-executing the data reconstruction and correction procedure also include: Based on the multiple read results of the data block, modify the bit value corresponding to at least one bit of the reconstructed data block to regenerate the reconstructed data block; and The regenerated data block is provided to the error correction engine to obtain the third decoding result of the given data.

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