Read operations enabling pattern analysis in NAND components

Abstract

In one embodiment, a method includes applying a first reference drive voltage to word lines of a memory cell to generate a respective first resulting voltage level from each respective cell of the word lines; and storing, in the memory, a first respective logical value indicated by the respective first resulting voltage level of each memory cell. The method also includes applying a second reference drive voltage to word lines of the memory cells to generate a respective second result voltage level from each respective cell in the word lines while detecting a pattern of logic values stored in the memory in parallel. The memory is modified based on a second respective logic value indicated by a respective second resulting voltage level, and at least one of the first reference driving voltage and the second reference driving voltage is modified based on the detected mode data.

Description

TECHNICAL FIELD

[0001] The present disclosure aims to detect patterns in data output by applying read reference voltages to word lines of memory cells, and in particular, to detect patterns in intermediate data output by a word line after each reference voltage is applied when multiple reference voltages are used in a single bit read operation. BACKGROUND

[0002] In some memory devices, memory cells are capable of storing more than one bit per cell. For example, triple level cell (TLC) memory can store a total of three bits, where a total of eight different possible voltage levels represent each combination of bits. To determine the stored bit values, one or more reference drive voltages can be used. For example, in TLC memory, reading the most significant bit (MSB) can only require one reference drive voltage, but reading the central significant bit (CSB) can require three different reference drive voltages.

[0003] However, as memory cells experience more read / write operations, the stored voltage corresponding to a particular bit combination can shift, and using one or more reference drive voltages to determine the stored bit values can result in an erroneous read. In some approaches, in response to detecting an erroneous read (e.g., by a cyclic redundancy check (CRC) on the output bit values), multiple read retry voltages can be substituted for the reference drive voltages, or an automatic reference count (ARC) process can be used to modify the reference voltages. However, both of these processes require processing time, which can delay read / write operations (e.g., from the memory device to a host device). SUMMARY

[0004] According to some embodiments of the present disclosure, the methods and systems provided herein are used to dynamically select reference drive voltages based on sensed patterns in the output of a word line of a memory cell prior to reading a single bit (e.g., during the application of a first and second reference voltage among 3 voltages required to read the CSB of a 3-bit cell). In some embodiments, a sensed pattern based on a first reference drive voltage can be detected when a second reference drive voltage is input during a read process. In some embodiments, a second sensed pattern based on the first and second reference drive voltages can be detected when a third reference drive voltage is input during a read process. In some embodiments, there can be any number of reference drive voltages between two and seven, where each sensed pattern corresponds to a respective applied drive voltage.

[0005] It should be noted that "first" and "second" reference drive voltages as described herein are intended to describe the order in which such voltages are applied, and are not limited to only the first and second actual reference voltages applied to a word line of a memory cell to read one of the bit locations. For example, in a memory cell storing three bits, the "first" reference drive voltage can refer to either the first or second actual reference voltage, and the "second" reference drive voltage can refer to either the second or third actual reference voltage, respectively.

[0006] In another example in which reading bits in a memory cell (e.g., storing at least two bits) requires, for example, seven reference drive voltages, the first reference drive voltage can refer to any one of the first through sixth actual reference voltages, and the second reference drive voltage can refer to any one of the second through seventh actual reference voltages. More generally, for any cell storing at least two bits, for a read operation (e.g., for one of the stored bits) requiring n+1 reference drive voltages, the "first" reference drive voltage can refer to any one of the first through n actual reference drive voltages, and the "second" reference drive voltage refers to an actual reference drive voltage that is subsequently applied after the "first" reference drive voltage, as shown in the following table: "first" reference drive voltage "second" reference drive voltage first actual reference voltage second actual reference voltage second actual reference voltage third actual reference voltage … … nth actual reference voltage n+1th actual reference voltage

[0007] In some embodiments, a method of allowing data to be read from a memory includes applying a first reference drive voltage to a word line of a memory cell to produce a respective first resulting voltage level from each respective cell in the word line. For each respective first resulting voltage level output by each cell in the word line, a first respective logic value indicated by the respective first resulting voltage level is stored in the memory (e.g., a respective latch coupled to each respective memory cell). The method also includes applying a second reference drive voltage to the word line of the memory cell to produce a respective second resulting voltage level from each respective cell in the word line while also detecting a pattern of logic values stored in the memory. For each respective second resulting voltage level output by each cell in the word line, the memory is modified based on a second respective logic value indicated by the respective second resulting voltage level. At least one of the first and second reference drive voltages is modified based on the detected pattern data. In some embodiments utilizing more than two reference drive voltages, the method also includes applying each additional reference voltage to the word line of the memory cell to produce a respective additional resulting voltage level from each cell in the word line to be stored in the memory. The method also includes detecting a pattern of logic values in the memory as each additional reference is being applied, where the pattern of respective logic values in the memory is detected before the new additional resulting voltage level is stored in the memory.

[0008] According to some embodiments of the present disclosure, a system includes a memory, a word line of memory cells configured to store data, and a control circuit. The control circuit is configured to apply a first reference drive voltage to the word line of memory cells to produce a respective first resulting voltage level from each respective cell in the word line. For each respective first resulting voltage level output by each cell in the word line, the control circuit stores in the memory a first respective logic value indicated by the respective first resulting voltage level. The control circuit then applies a second reference voltage to the word line of memory cells to produce a respective second resulting voltage level from each respective cell in the word line while also detecting a pattern of logic values stored in the memory. For each respective second resulting voltage level output by each cell in the word line, the control circuit then modifies the memory based on a second respective logic value indicated by the respective second resulting voltage level. Based on the detected pattern data, the control circuit is also configured to modify at least one of the first reference drive voltage and the second reference drive voltage. For example, the modification of the at least one reference drive voltage can occur when an erroneous read operation occurs (e.g., where the erroneous read can be detected by a cyclic redundancy check (CRC) or other suitable process). In some pattern detection applications without intermediate reference drive voltages, when an erroneous read occurs, a read retry process is performed to recalibrate the reference drive voltages. However, with only a final read operation output, all reference drive voltages are retried until a combination of reference voltages successfully returns a correct bit (e.g., the read retry process can repeat multiple times), and each retry is an additional read operation. As more retries occur, the latency time for the read operation that was initially requested increases. Thus, by obtaining intermediate data outputs from each respective reference drive voltage, rather than only a final read operation output, the process of recalibrating the reference drive voltages (e.g., when an erroneous read occurs) is simplified and requires fewer retries, thereby reducing the overhead latency time of the read operation. BRIEF DESCRIPTION OF DRAWINGS

[0009] The present disclosure is described in detail according to one or more various embodiments, with reference to the accompanying drawings. The drawings are provided for purposes of illustration only and merely depict typical or example embodiments. These drawings are provided to facilitate an understanding of the concepts disclosed herein and should not be considered to narrow the scope of the disclosure in any way. It should be readily appreciated that the drawings are not necessarily drawn to scale of the objects that they represent.

[0010] Figure 1 A block diagram of a system including a host communicatively coupled to a memory device is shown in accordance with some embodiments of the present disclosure; Figure 2A block diagram illustrating word lines of memory cells coupled to respective series of latches according to some embodiments of the present disclosure is shown; Figure 3A An illustrative timeline of a central significant bit read process and a corresponding mode detection process for word lines of memory cells according to some embodiments of the present disclosure is depicted; Figure 3B An illustrative timeline of a sensing process of a second reference voltage as described in Figure 3A Figures 4A-4B A central significant bit (CSB) read process for a triple level cell (TLC) flash memory cell without a mode detection process according to some embodiments of the present disclosure is depicted; Figure 5 A CSB read process for a TLC flash memory cell with a mode detection process according to some embodiments of the present disclosure is depicted; Figures 6A-6B An illustrative flowchart of a read process with a mode detection process occurring during program suspend according to some embodiments of the present disclosure is shown; Figure 7 An illustrative flowchart of steps for dynamically modifying one or more read reference drive voltages based on detected mode data according to some embodiments of the present disclosure is shown; and Figure 8 A flowchart of steps of modifying at least one of a first drive voltage or a second drive voltage according to embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0011] In memory devices including word lines of memory cells, multiple reference drive voltages can be used to determine stored bit values in the memory cells. However, as the memory cells undergo more read / write operations, the stored voltages corresponding to particular bit combinations can shift, and using one or more reference drive voltages to determine the stored bit values can result in stuck or erroneous reads.

[0012] ​According to some embodiments of the present disclosure, the methods and systems provided herein are used to dynamically select a reference drive voltage based on a detected mode of each reference drive voltage applied to a word line of a memory cell. The methods and systems provided herein can be used to dynamically select or detect a mode of more than two reference drive voltages. In some embodiments, when a second reference drive voltage is input during a read process, a mode based on a first reference drive voltage can be detected. In some embodiments utilizing at least a third reference drive voltage, when a third reference drive voltage is input during a read process, a second sensing mode based on the first and second reference drive voltages can be detected. In some embodiments utilizing more than three reference drive voltages, the process can be reiterate until each respective reference drive voltage has been input during a read process. The present disclosure is directed to reducing the overhead latency during a read operation when an erroneous read occurs.

[0013] Figure 1 A block diagram of a system 100 including a host device 102 communicatively coupled with a memory device 108 is shown in accordance with some embodiments of the present disclosure. The host device 102 can be, for example, a computer (e.g., with an on-board memory device 108) or any other suitable computing device that utilizes read and / or write operations from memory. As shown, the host device 102 is coupled to the memory device 108. In some embodiments, the memory device 108 can be internal to the host 102, or the memory device 108 can be external to the host 102. In some embodiments, the devices can be coupled through the use of one or more buses of Non-Volatile Memory Express (NVMe) over Peripheral Component Interconnect Express (PCIe). However, it should be understood that any other suitable protocol or combination of protocols can be used. For example, such protocols can include Serial Attached Small Computer System Interface (SAS), Serial Advanced Technology Attachment (SATA), any other suitable protocol, or any combination thereof.

[0014] The host device 102 includes control circuitry 104, memory 105, and input / output (I / O) circuitry 106, although it will be understood that the host device 102 can have other components included in other suitable embodiments. For example, the control circuitry 104 can be included in a controller, where the controller can include one or more central processing units (CPUs), or other configurable controllers such as one or more programmable logic arrays (PLAs), one or more field programmable gate arrays (FPGAs), one or more complex programmable logic devices (CPLDs), any other suitable controller circuitry, or any combination thereof. The memory 105 can include random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, any other suitable memory, or combinations thereof. In some embodiments, the I / O circuitry 106 can include a PCIe adapter to communicatively couple the host device 102 and the memory device 108 (e.g., over one or more buses) (e.g., using the NVMe over PCIe protocol). In some embodiments, the host device 102 can store information (e.g., from a user using the host device 102, an external server, an operating system, other suitable applications, or combinations thereof) in the memory device 108 through the I / O circuitry 106.

[0015] The memory device 108 includes a controller 110 and word lines of memory cells 115, where each cell 1161-116 n is coupled to a respective series of latches 1181-118 n Although only one word line is shown for ease of reference, in some embodiments, the memory device 108 can include multiple word lines. In some embodiments, the word lines of memory cells 115 can include 18,000 cells (e.g., where n is equal to 18,000 and the word lines of memory cells 115 include cells 1161-116 18000 20000 cells, or any other suitable number of cells. The controller 110 includes control circuitry 111, where the control circuitry 111 is configured to read data from and write data to the word lines of memory cells 115 by, for example, providing one or more reference drive voltages to the word lines of memory cells 115. In some embodiments, the read and write operations in the memory device 108 occur when respective commands are received from the host device 102 (e.g., via the I / O circuitry 106). In some embodiments, the cells 1161-116 nThis can be a three-level cell (TLC) flash memory cell. In some embodiments, a TLC flash memory cell can store voltages corresponding to combinations of three bits (e.g., the most significant bit, the middle significant bit, and the least significant bit). In some embodiments, the flash memory cell can include any number from two bits to seven bits and can store several different voltages corresponding to the total number of combinations of the stored bit number. In an ideal TLC flash memory, eight different combinations of three bits can be represented by eight discrete voltage levels stored in the TLC flash memory. However, those skilled in the art will understand that when a read / write operation is performed on the TLC flash memory, the discrete voltage corresponding to each combination of the three stored bits may change or shift over time.

[0016] Units 1161-116 n It can be used with the corresponding latches 1181-118 n Coupling. In some embodiments, each latch 1181-118 n This may include sense amplifier data latches (SDL), transfer data latches (TDL), countable data latches (CDL), or combinations thereof. Latch 1181-118 n It can store the contents contained in the corresponding units 1161-116 n Information (e.g., bit data) in the memory. In some embodiments, reading data from the word line of memory cell 115 may include reading latches 1181-118 in a latch read operation. n The data in the memory. For example, latch reading can be performed by control circuitry 111 on memory device 105.

[0017] In some embodiments, reading data from the word lines of memory cell 115 includes configuration control circuitry 111 to configure each memory cell 1161-116 n One or more reference drive voltages are applied. Multiple bits are stored in each memory cell 1161-116. n In some applications, multiple drive voltages and bit-by-bit logic operations may be used to determine the value of a specific bit. For example, the method provided in this paper (e.g., as shown in Figure 3-) Figure 5 The example described herein is for reading the central significant bit (CSB) in a TLC flash memory cell. However, those skilled in the art will appreciate that similar operations can occur in suitable embodiments, which include storing more or fewer than three bits in each memory cell, determining the values ​​of different bits (e.g., the most significant bit or the least significant bit, other bits stored in each memory cell, or combinations thereof).

[0018] As previously noted, the first and second reference drive voltages as described herein are relative and are not limited to only the first and second actual reference voltages specifically applied to the word line of the memory cell. For example, in a memory cell storing seven bits, the first and second reference drive voltages as described herein can refer to the second and third actual reference voltages, respectively, the third and fourth actual reference voltages, respectively, the sixth and seventh actual reference voltages, respectively, or any nth and nth+1 actual reference voltages, respectively. In some embodiments including multiple iterations or pairs of reference drive voltages, the relative first and second reference drive voltages described herein can refer to different actual reference voltages at each iteration or pairing. For example, in a memory cell storing seven bits, the methods described herein utilizing the first and second reference drive voltages can first be applied to the first and second actual reference voltages, respectively, and then to the second and third actual reference voltages, respectively, any suitable nth and nth+1 actual reference voltages, respectively, or combinations thereof. Similarly, the third reference drive voltage as described herein is also relative and can refer to an nth+2 actual reference voltage if the first reference drive voltage refers to an nth actual reference voltage. For example, if the first reference drive voltage refers to a fifth actual reference voltage, the third reference drive voltage refers to a seventh actual reference voltage. Thus, while the following can be described in the context of a CSB read of a word line of a TLC flash memory cell, it will be understood that, particularly when the present disclosure is applied to a memory cell storing more than three bits, the first, second, and third reference drive voltages can refer to any nth, nth+1, and nth+2 actual reference drive voltages, respectively.

[0019] Figure 2 A block diagram of a word line of a memory cell 115 coupled to a respective series of latches 1181-118 n is shown in accordance with some embodiments of the present disclosure. As shown, each latch in the series of latches 1181-118 n may include a respective sense-amplifier data latch (SDL) 1201-120 n , a respective transfer data latch (TDL) 1221-122 n , and a respective countable data latch (CDL) 1241-124 n . It will be understood that other combinations of latches can be suitable in other embodiments, and each latch 1181-118 n may include additional latches.

[0020] Sense amplifier data latch 1201 can be configured to receive bit data as a voltage from cell 1161 and amplify the received voltage. In some embodiments, cell 1161 can include any number of bits from two to seven. For example, cell 1161 can be TLC flash memory and thus include three different data bits. When reading data from cell 1161, each bit can be read by utilizing one or more reference drive voltages. Using the previous example where cell 1161 is TLC flash memory, reading the center significant bit (CSB) can utilize three reference drive voltages (e.g., where the three reference drive voltages can be referred to herein as a first reference drive voltage R2, a second reference drive voltage R4, and a third reference drive voltage R6), where each applied reference drive voltage outputs one bit (e.g., 0 or 1) to SDL 1201, where 0 corresponds to a first output voltage and 1 corresponds to a second output voltage having a value that is separated and discrete from the first output voltage. However, because the first output voltage and the second output voltage can have a small value difference, SDL 1201 can amplify the output such that there is a larger value difference that separates the first output voltage and the second output voltage (e.g., to prevent a read error).

[0021] The output bit value (e.g., represented by the amplified voltage level) is then sent to a transfer data latch (TDL) 1221, which can act as temporary storage that holds the output bit value. In some embodiments, TDL 1221 can hold the output bit value until a latch read occurs. As described in Figure 1 the latch read can be performed by, for example, control circuit 111, and the latch read can include reading the data in TDL 1221. In some embodiments, the bit value previously stored in TDL 1221 can be compared to a new bit value received from SDL 1201. For example, the comparison can occur when multiple reference drive voltages are used for a bit read (e.g., reading the CSB). Figure 4B An illustrative example of the comparison process is described in

[0022] According to some embodiments of the present disclosure, latch 1181 can further include a countable data latch (CDL) 1241. CDL 1241 can receive the bit value stored in TDL 1221. In some embodiments, the latch read (e.g., performed by control circuit 111, as described in Figure 1The latch read can read data stored in the TDL 1221, instead of the data stored in the CDL 1241. In some embodiments, the latch read can read data stored in the TDL 1221, and the data stored in the CDL 1241 can instead be read as part of a different mode detection process performed by the control circuit 111.

[0023] Although only the latch 1181 including the SDL 1201, the TDL 1221, and the CDL 1241 is described, it will be understood that respective latches corresponding to other memory cells 1162-116 n The mode detection process can count the total number of logical 1 bits, the total number of logical 0 bits, or a combination thereof, across all CDLs in the word line of memory cells 115. Further, according to some embodiments of the present disclosure, the mode detection process can occur concurrently with a read process (e.g., which utilizes a plurality of reference drive voltages), a comparison process (at the TDL), or a combination thereof.

[0024] In the absence of the application of the mode detection process, a read operation performed by the memory device 105 (e.g., requested by the host device 102) can return the requested bits from each cell of the word line of memory cells, but not the intermediate data (e.g., the output produced by each applied reference drive voltage, the output produced by the logical bit-by-bit operation, or a combination thereof). However, as described above, the mode detection process can be applied to determine whether the memory device 105 is operating in the first mode or the second mode. Figure 1As explained in the Background, when read / write operations are performed on TLC flash memory, the discrete voltages corresponding to each combination of three stored bits can change or drift over time. If the reference drive voltage is not changed accordingly, false readings can occur. When a false read is detected (e.g., by a cyclic redundancy check (CRC) on the output bit values) and a subsequent retry procedure is applied to select a different reference drive voltage, the memory device 105 can have little or no information about which reference drive voltage was incorrect or which intermediate step returned an incorrect result. Thus, based on previous trends and patterns observed in the drift of stored voltage levels over time, a controller on the memory device (e.g., the controller 110) retries with a predetermined set of reference drive voltage levels, which has low accuracy and can result in a large number of performed retries (e.g., corresponding to a large overhead latency time in the requested read operation). By performing pattern analysis and / or bit counting on the output for each reference drive voltage, it can be easier to infer which reference drive voltage and / or step in the read operation caused the false read, resulting in higher accuracy in the read retry procedure (e.g., requiring fewer retries, which results in less latency time). Furthermore, as described below, the pattern analysis procedure occurs back-to-back with the read operation, resulting in little or no additional overhead latency time for the pattern analysis procedure itself (although more processing power and / or additional latches (e.g., CDLs) are required for each memory cell).

[0025] Figure 3A An illustrative timeline of a central effective bit read procedure 300 and corresponding pattern detection procedure for a word line of memory cells is depicted in accordance with some embodiments of the present disclosure. Figure 3A An illustrative timeline of a central effective bit read procedure 300 and corresponding pattern detection procedure for a word line of memory cells is depicted in accordance with some embodiments of the present disclosure. Figure 1 An illustrative timeline of a central effective bit read procedure 300 and corresponding pattern detection procedure for a word line of memory cells is depicted in accordance with some embodiments of the present disclosure. Figure 2 Examples of the methods and systems explained in the Background can be modified, moved, removed, or added to in some embodiments for different bit reads (e.g., MSB, LSB, other suitable bits, or combinations thereof) and / or different types of memory cells (e.g., each cell storing a different number of bits). Figure 3A Examples of the methods and systems explained in the Background can be modified, moved, removed, or added to in some embodiments for different bit reads (e.g., MSB, LSB, other suitable bits, or combinations thereof) and / or different types of memory cells (e.g., each cell storing a different number of bits). Figure 3A Examples of the methods and systems explained in the Background can be modified, moved, removed, or added to in some embodiments for different bit reads (e.g., MSB, LSB, other suitable bits, or combinations thereof) and / or different types of memory cells (e.g., each cell storing a different number of bits).

[0026] At time tO, a read command 302 is received and processed, where the read command 302 can be provided by a host (e.g., host device 102) external to the memory device. In some embodiments, the read command 302 can be processed and then executed by the control circuit 111, an external controller, or a combination thereof. At time tl, a first reference drive voltage R2 is applied to the word line of the memory cells in an R2 sensing process 304, and the output bits from each memory cell can be sent to, for example, a respective SDL as described in Figure 2 TLC flash memory cell can store eight discrete voltage levels, where each voltage level corresponds to a different combination of three binary bits, and three reference drive voltages are needed to read the value of the CSB. When a reference drive voltage is applied, if the voltage level stored in the TLC flash memory is higher than the applied reference drive voltage, a voltage corresponding to a logical 0 is returned (e.g., output to the SDL), and if the voltage level stored in the TLC flash memory is lower than the applied reference drive voltage, a voltage corresponding to a logical 1 is returned. In some embodiments, if any output voltage is detected, a logical value of zero can be determined, and if no output voltage is detected, a logical 1 can be determined. In some embodiments, if any output voltage is detected, a logical value of 1 can be determined, and if no output voltage is detected, a logical 0 can be determined. The returned voltage is amplified at the SDL (e.g., to more clearly distinguish between logical 0 and logical 1) and sent to the TDL and CDL.

[0027] At time t2, the output bits from each cell of the R2 sensing process 304 are complete, and a second reference drive voltage R4 is applied to the word line of the memory cells in an R4 sensing process 306. Similar to the R2 sensing process 304, in response to the applied second reference drive voltage R4, the output bits from each memory cell can be sent to a respective SDL for amplification. Once the data is amplified at the SDL, additional operations can be needed in order to correctly read and return the bit values stored in the memory (e.g., CSB). In some embodiments, the additional operations can be a bit-by-bit logical operation at each TDL, where each bit-by-bit logical operation includes negating the incoming bit value (e.g., output in response to the applied second reference drive voltage R4) and then performing an OR operation on the negated incoming bit value and the bit value currently stored in the TDL (e.g., output from the applied first reference drive voltage R2). The logical operation process will be further explained in Figure 4B

[0028] ​As the R4 sense process 306 is occurring at time t2, a mode detection process (R2 bit count process 308) is also occurring. As previously described, the mode detection process is illustrated as a bit count process, but can be any suitable process that detects a pattern of values stored in the CDL of a word line of a memory cell. In some embodiments, the R2 bit count process 308 can include counting the number of logical ones in the data stored in the TDL (e.g., by sending the data stored in the TDL to the CDL for counting, as the TDL can be undergoing other storage operations from the R4 sense process 306). However, it will be understood that the R2 bit count process 308 can include additional processes or can be replaced by different processes to determine the pattern of data stored in the TDL. For example, the R2 bit count process 308 can include a count of logical zeros in the data stored in the TDL, a ratio of total logical ones to logical zeros in the TDL, or a combination thereof. In some embodiments, the time required to perform the R2 bit count process 308 is lower than the time required to perform the R4 sense process 306 (e.g., less than a time value equal to t3 minus t2), such that the R2 bit read process 308 occurs without any overhead processing time added to the execution of the read process 300.

[0029] At time t3, the output bits from the R4 sense process 306 for each cell are complete, and a third reference drive voltage R6 is applied to the word line of the memory cell in a R6 sense process 310. The R6 sense process 310 is the same as the R4 sense process 306, but with the third reference drive voltage applied, and in some embodiments, with a different logical bit-by-bit operation occurring at each TDL as compared to the logical bit-by-bit operation performed in the R4 sense process 308. In some embodiments, each bit-by-bit logical operation in the R6 sense process 310 includes an AND operation of the incoming bit value (e.g., an output in response to the applied third reference drive voltage) and the bit value currently stored in the TDL. The logical operation process will be further explained in Figure 4B . The stored value in each TDL is then replaced by the resulting bit value of the logical bit-by-bit operation of each TDL.

[0030] While the R6 sense process 310 is occurring, the R2+R4 bit count process 312 is also occurring. The process in the R2+R4 bit count process 312 is the same as described in the R2 bit count process 308, but as a result of the R4 sense process 306, the bits stored in the CDL are counted. In some embodiments, the time required to perform the R2+R4 bit count process 312 is lower than the time required to perform the R6 sense process 310 (e.g., a time value less than t4 minus t3), such that the R2+R4 bit count process 312 occurs without any overhead processing time being added to the execution of the read process 300.

[0031] At t4, the data output process 314 completes execution of the read command in 302. During the data output process 314, the data saved in memory (e.g., TDL) containing the output bit values of the R6 sense process 310 is read by the control circuit 111. It will be understood that the bit values read in the data output process 314 represent the actual values of the CSB stored in the memory cells.

[0032] While the data output process 314 is occurring, the R2+R4+R6 bit count process 316 is also occurring. The process in the R2+R4+R6 bit count process 316 is the same as described in the R2+R4 bit count process 312, but as a result of the R6 sense process 310, the bits stored in the CDL are counted. In some embodiments, the time required to perform the R2+R4+R6 bit count process 316 is lower than the time required to perform the data output process 314, such that the R2+R4+R6 bit count process 316 occurs without any overhead processing time being added to the execution of the read process 300.

[0033] Figure 3B An illustrative timeline 350 of a sense process of a second reference drive voltage as described in Figure 3A FIG. 3B, in accordance with some embodiments of the present disclosure. As shown, the sense process of the second reference drive voltage is the R4 sense process 306, which begins at time t2 (e.g., corresponding to the time at which the R4 sense process 306 begins in the read process 300 of FIG. 3A). The R4 sense process 306 is performed in the same manner as described in FIG. 3A, and the R4 sense process 306 is completed at time t3. Figure 3AR4 sensing process 306 begins at step 352 with the application of a second reference drive voltage. In some embodiments, the application of the reference drive voltage to the word line occurs within two microseconds. Immediately thereafter, at time t2a, a bit line pre-charge process occurs at step 354 in which the applied voltage to the word line of the memory cell has time to travel through each respective memory cell. In some embodiments, the bit line pre-charge process occurs within 6 microseconds. Immediately thereafter, at time t2b, sensing occurs at step 356. If a voltage is sensed (e.g., the applied reference drive voltage is higher than the voltage of the memory cell), a logic 1 is output, and if no voltage is sensed at step 356 (e.g., the applied reference drive voltage is lower than the voltage of the memory cell), a logic 0 is output.

[0034] At time t2c, sensing at step 356 is complete, and a 0.5 microsecond break interval occurs at step 358. The sensed bit value can be transferred to the SDL, where it will be amplified, and then sent to the TDL to be read or stored in memory, and / or to the CDL to be counted. In some embodiments, steps 356 and 358 can occur in combination within 1.5 microseconds.

[0035] While steps 352, 354, 356, and 358 of the R4 sensing process 306 are occurring, the R2 bit count process 308 is also occurring, as described in Figure 3A . As shown, in some embodiments, the R2 bit count process 308 can begin slightly later after t2, so long as the R2 bit count process 308 is complete before time t3.

[0036] Figures 4A-4B A CSB read process 400 for TLC flash memory cells is depicted, in accordance with some embodiments of the present disclosure, for a modeless detection process. Similar to FIG. 3, Figures 4A-4B , a CSB read process 400 is described in the context of the application of a respective CSB to a word line for reading a TLC flash memory cell (e.g., each memory cell having 3 bits stored). Figure 1 , and Figure 2 . Although the methods and systems described in Figures 4A-4B are described in the context of specific structures, components, and processes of the present disclosure, it will be understood that, in some embodiments, one or more of the processes described in Figures 4A-4B may be modified, moved, removed, or added for different bit reads (e.g., MSB, LSB, other suitable bits, or combinations thereof) and / or different types of memory cells (e.g., each cell storing a different number of bits).

[0037] Figure 4AA drive voltage applied to a TLC flash memory cell storing a voltage corresponding to a three-bit combination is shown. The TLC flash memory cell has eight discrete voltage levels 402a-402h, where each discrete voltage level corresponds to a different combination of three bits stored in the TLC memory cell. For example, voltage 402a can correspond to binary value 111, voltage 402b can correspond to binary value 110, and voltage 402h can correspond to binary value 000. To determine the CSB in the CSB read process 400, three reference drive voltages can be needed (e.g., including a first reference drive voltage 404a, a second reference drive voltage 402b, and a third reference drive voltage 404c). The first reference drive voltage 404a can be at a voltage level between the voltage levels representing 110 and 101 (e.g., 402b and 402c, respectively). The second reference drive voltage 404b can be at a voltage level between the voltage levels representing 100 and 011 (e.g., 402d, 402e), and the third reference drive voltage 404c can be at a voltage level between the voltage levels representing 010 and 001 (e.g., 402f, 402g).

[0038] It will be appreciated that a non-ideal TLC flash memory cell does not store an exact voltage level for a bit combination (e.g., if a binary value 110 is stored, removed, and then stored again in a TLC flash memory, the two stored voltages will not necessarily be exactly equal). Because a TLC flash memory cell has a small total voltage, precision of the stored voltage level can be difficult. Accordingly, the voltage levels 402a-402h are shown in FIG. 4 as probability distributions, where a distribution function value at a particular voltage level represents a probability that the corresponding bit combination is stored in a memory cell having the particular voltage level. As shown, the distributions for each combination of three binary bits are each centered at the ideal discrete voltage level corresponding to the respective combination (e.g., the highest probability).

[0039] However, as previously described, over time performing read / write operations in a non-ideal TLC flash memory cell, the stored voltage level for one or more combinations can shift. For example, if the stored voltage level 402b increases over time, then an increase in the number of erroneous reads can occur if the first reference drive voltage 404a does not change (e.g., the CSB read process 400 can more frequently read a 1 bit as a 0 bit in error, especially for the 110 binary value in this example).

[0040] Figure 4B An illustrative graph 450 of bit values output at each step of the CSB read process 400 is depicted in accordance with some embodiments of the present disclosure. In some embodiments, Figure 4BThe output bit values described in Figure 3A The output bit values of the logical bitwise operations described in are illustrated in FIG. 4B. Column 452 illustrates the eight possible combinations of three particular binary bits. As previously described, each combination is represented as a discrete voltage level in a TLC flash memory cell. For each combination listed in column 452, the corresponding value in column 454 illustrates the resulting bit value after applying a first reference drive voltage R2 (e.g., 404a) to the TLC flash memory cell. If the TLC flash memory cell is storing a voltage level below the first reference drive voltage, a logical 1 is returned, and if the TLC flash memory cell is storing a voltage level above the first reference drive voltage, a logical 0 is returned. It will be understood that the output of column 454 is the output value of the R2 sensing process (e.g., which is sent to the SDL), stored in memory (e.g., TDL), and counted in the CDL (e.g., in the R2 bit count process).

[0041] For each combination listed in column 452, the corresponding value in column 456 illustrates the resulting bit value after applying a second reference drive voltage R4 (e.g., 404b) to the TLC flash memory cell. If the TLC flash memory cell is storing a voltage level below the second reference drive voltage, a logical 1 is returned, and if the TLC flash memory cell is storing a voltage level above the second reference drive voltage, a logical 0 is returned.

[0042] The results in column 456 are then inverted, and a logical OR operation is performed between the inverted values from column 456 and the corresponding bit values from column 454 (e.g., which are stored in the TDL) to obtain the resulting bit values illustrated in column 458. It will be understood that the output of column 458 is the output value of the R4 sensing process (e.g., which is sent to the SDL), stored in memory (e.g., TDL), and counted in the CDL (e.g., in the R2+R4 bit count process).

[0043] For each combination listed in column 452, the corresponding value in column 460 illustrates the resulting bit value after applying a second reference drive voltage R6 (e.g., 404c) to the TLC flash memory cell. If the TLC flash memory cell is storing a voltage level below the third reference drive voltage, a logical 1 is returned, and if the TLC flash memory cell is storing a voltage level above the third reference drive voltage, a logical 0 is returned.

[0044] A logical AND operation is performed between the result value from column 460 and the corresponding bit value from column 458 (e.g., which is stored in TDL) to obtain the result bit value shown in column 462. It will be understood that the output of column 462 is the output value of the R6 sensing process (e.g., which is sent to SDL), stored in memory (e.g., TDL), and counted in CDL (e.g., during the R2+R4+R6 bit counting process). As shown, the result bit value shown in column 462 corresponds precisely to the CSB value of the corresponding bit combination in column 452.

[0045] Figure 5 A CSB read process 500 for a TLC flash memory cell with a pattern detection procedure is depicted according to some embodiments of the present disclosure. Similar to Figure 3, Figure 5 This describes an application for reading the corresponding CSB of a word line in a TLC flash memory cell (e.g., each memory cell has 3 bits stored). Figure 1 and Figure 2 Examples of the methods and systems explained herein, and in some embodiments, modifications, moves, removals, or additions may be made for different bit reads (e.g., MSB, LSB, other suitable bits, or combinations thereof) and / or different types of memory cells (e.g., each cell stores a different number of bits). Figure 5 One or more of the processes described in the text.

[0046] and Figure 4A resemblance, Figure 5 It includes eight discrete voltage levels 402a-402h, which correspond to the probability distribution of voltages stored in TLC flash memory cells for specific combinations of three binary bits. Figure 5 It also includes three reference drive voltages 404a-404c (e.g., R2, R4 and R6 respectively).

[0047] As the results of executing the R2 sensing process, the R4 sensing process, and the R6 sensing process, the first result 554, the second result 556, and the third result 562 are returned, respectively. The first result 554 corresponds to… Figure 4B The result value in column 454, the second result 558 corresponds to the result value in column 458, and the third result 562 corresponds to the result value in column 462. In a CSB read procedure without pattern detection (e.g., CSB read procedure 400), (e.g., in...) Figure 3AThe third result 562 is output in the latch read only, where the third result 562 is the CSB value. However, in the CSB read process 500 utilizing the pattern detection process, the pattern detection process is performed on the intermediate results 554 and 558. As shown, the pattern detection process is a bit count of logical ones in the word line of the memory cell. In some embodiments, the pattern detection process can be a bit count of logical ones, a bit count of logical zeros, a ratio of logical ones to logical zeros, other suitable pattern detection processes, or a combination thereof. In some embodiments, as Figure 2 As described in the CSB read process 500, the bit count can be performed utilizing a series of CDLs for each of the cells in the word line of the memory cell, where the bit value in the corresponding TDL (e.g., memory) is transferred to the CDL for bit count when the bit value in the TDL is overwritten or read (e.g., when the next step in the CSB read process is being performed).

[0048] When an error read operation occurs (e.g., and is detected by, for example, a CRC process), the memory device can determine which reference drive voltage can need to be adjusted based on the detected pattern. For example, if the R2 sense process is expected to return approximately 50% logical ones and 50% logical zeros (e.g., a random distribution), and the pattern analysis determines that only 25% of the output bits from the R2 sense process are logical ones (e.g., the stored voltage in the memory cell is lower than the R2 voltage), the R2 voltage can be determined to be incorrect and be shifted upward by a predetermined amount. In some embodiments, the predetermined amount can be a fixed value. In some embodiments, the predetermined amount can be variable based on the returned results of the sense process. In future reads, this new R2 voltage will be used in place of the previous R2 voltage until another erroneous read occurs and the reference drive voltage can need to be shifted again.

[0049] Figures 6A-6B Illustrative flowcharts 600 and 650 of a read process with a pattern detection process occurring during program suspend are shown, respectively, in accordance with some embodiments of the present disclosure. Figures 6A-6B The processes described in the CSB read process for a word line of a TLC flash memory cell. For example, the word line of the memory cell can correspond to Figure 1 The word line of the memory cell 115 in FIG. 1 A has memory cells 1161-116 n and corresponding coupled latches 1181-118 n In addition, in some embodiments, the latches 1181-118 nEach latch in the system may include a corresponding SDL (e.g., SDL 120), TDL (e.g., TDL 122), and CDL (e.g., CDL 124). For example, when internal garbage collection is stopped or memory devices are utilized (e.g., Figure 1 When other suitable operations are performed on the memory (e.g., TDL or CDL) of the memory device 105 in the host device 102, a program suspension may occur when a read operation is requested (e.g., from the host device 102). In some embodiments, when a program suspension occurs, the data corresponding to the suspended program in the latch cannot be read and must remain in the latch memory (e.g., to prevent loss). Therefore, in order to perform, for example, a CSB read of a word line of a memory cell (e.g., such that the memory cell includes at least a TLC flash memory cell), the suspended data may move around the latch while sensing and pattern detection processes occur.

[0050] like Figure 2 As described herein, latches (e.g., latches 1181, 1182, ..., 118) n This can include SDL, TDL, and CDL. In illustrative flowcharts 600 and 650, SDL 602 can represent all SDLs in the word lines of a memory cell (e.g., SDL 1201, 1202, ..., 120...). n TDL 604 can represent all TDLs in the word line of the memory cell, and CDL 606 can represent all CDLs in the word line of the memory cell. CDL 606 can currently hold suspended program data, and the read process shown by flowcharts 600 and 650 can begin at step 612, in which the suspended program data is transferred to the TDL (e.g., temporary memory).

[0051] In step 614, the R2 sensing process is executed (e.g., R2 sensing process 304 as described in FIG3), and the output bit value is sent to the corresponding SDL in SDL 602. Figure 2 As described above, at SDL 602, the received voltage (e.g., corresponding to the output bit value) is amplified, resulting in a larger voltage difference between logic 1 and logic 0 (e.g., making it easier to distinguish between logic 1 and logic 0). Then, in step 616, the amplified R2 sensing data is sent to CDL. It will be understood that in some embodiments, the amplified sensing data can be sent to TDL 604 during normal reads (e.g., without program suspension). However, because TDL 604 is currently storing suspended program data, TDL 604 may not have space in memory to store the R2 sensing data.

[0052] In step 618, the execution of the R4 sensing process begins (e.g., as...).Figure 3A The R4 sense data is then transmitted to the CDL 606 in step 622. It will be understood that if no overhead time resulted from the additional bit count process in step 620, the execution of step 620 can be completed prior to the R4 sense data being transmitted to the CDL in step 622.

[0053] Once the R4 sense data is transmitted to the CDL 606 in step 622, the R4 sense data can be compared to the corresponding R2 sense data in a bit-wise logical operation. In some embodiments, the logical bit-wise operation can be a negation of the R4 sense data (i.e., ~SDL) and then an "or" operation with the corresponding R2 sense data currently in the CDL 606 (i.e., (~SDL) | CDL).

[0054] In step 626, the execution of the R6 sense process is initiated (e.g., as described in step 310 of FIG. 3). Figure 3A The R6 sense data is then transmitted to the CDL 606 in step 630. It will be understood that if no overhead time resulted from the additional bit count process in step 628, the execution of step 628 can be completed prior to the R6 sense data being transmitted to the CDL in step 630.

[0055] Once the R6 sense data is transmitted to the CDL 606 in step 632, the R6 sense data can be compared to the corresponding sense data currently in the CDL 606 (e.g., (~R4) | R2) using a bit-wise logical operation. In some embodiments, the bit-wise logical operation can be an "and" operation between the R6 sense data (e.g., from the SDL 602) and the data currently in the CDL 606 (e.g., where the bit-wise logical operation can be represented as R6 || ((~R4) | R2) or SDL & CDL).

[0056] At step 634, a pattern detection process can be performed on the result data from step 632 in CDL 606. In some embodiments, the pattern detection process can be a bit count of logic 1s. When the execution of step 634 is performed, the suspended program data can be transferred to SDL 602. It will be understood that the output data (e.g., the requested data) of the read process is represented by the result of step 632, and in order to read out the data (e.g., from data output process 314 in Figure 3A , the data from step 632 is needed in TDL 604. Thus, the suspended program data is moved to SDL 602 to free up memory space in TDL 604 (e.g., where the suspended program data cannot be immediately moved to CDL 606 because CDL 606 is storing data from step 632). The data from step 632 in CDL 606 is then transferred to TDL 604, where the requested read process output data is responded to. Then, at step 640, the suspended program data is finally returned to CDL 606.

[0057] Figure 7 An illustrative flowchart 700 of steps for dynamically modifying one or more read reference drive voltages based on detected pattern data is shown in accordance with some embodiments of the present disclosure. Although the steps of flowchart 700 are described as being performed by control circuit 111 in Figure 1 , the steps of flowchart 700 can also be performed, for example, by an external controller (e.g., coupled to memory device 105), an additional controller on the memory device, other suitable controller and / or processor, or a combination thereof. Although the steps of Figure 7 are described in the context of specific structures, components, and processes of the present disclosure, and although a particular order and flow of steps are depicted in Figure 7 , it will be understood that, in some embodiments, one or more of the steps can be modified, moved, removed, or added, and the order of the steps depicted in Figure 7 may be modified.

[0058] As previously noted, the first and second reference drive voltages as described herein are relative and are not limited to only the first and second actual reference voltages specifically applied to the word line of the memory cell. For example, in a memory cell storing seven bits, the first and second reference drive voltages as described herein can refer to the second and third actual reference voltages, respectively, the third and fourth actual reference voltages, respectively, the sixth and seventh actual reference voltages, respectively, or any nth and n+1 actual reference voltages, respectively. In some embodiments including multiple iterations or pairs of reference drive voltages, the relative first and second reference drive voltages described herein can refer to different actual reference voltages at each iteration or pairing. For example, in a memory cell storing seven bits, the methods described herein utilizing the first and second reference drive voltages can first be applied to the first and second actual reference voltages, respectively, and then to the second and third actual reference voltages, respectively, any suitable nth and n+1 actual reference voltages, respectively, or combinations thereof. Similarly, the third reference drive voltage as described herein is also relative and can refer to an n+2 actual reference voltage if the first reference drive voltage refers to an n actual reference voltage. For example, if the first reference drive voltage refers to the fifth actual reference voltage, the third reference drive voltage refers to the seventh actual reference voltage. Thus, while the following can be described in the context of a CSB read of the word line of a TLC flash memory cell, it will be understood that, particularly when the present disclosure is applied to a memory cell storing more than three bits, the first, second, and third reference drive voltages can refer to any nth, n+1, and n+2 actual reference drive voltages, respectively.

[0059] The process begins at step 702, where control circuitry (e.g., control circuitry 111 of Figure 1 applies a first reference drive voltage to each memory cell in a word line of memory cells. In some embodiments, the first reference drive voltage can be R2 (e.g., as described in step 304 of FIG. 3), and the word line of memory cells can be word line 115 in Figure 1 Each memory cell (e.g., cells 1161, 1162,..., 116 n ) generates a respective first resulting voltage level in response to the applied first reference drive voltage. The process can then continue to step 704.

[0060] At step 704, the control circuitry (e.g., control circuitry 111 of Figure 1The control circuit 111 stores in memory a first corresponding logic value indicated by each corresponding first result voltage level. In some embodiments, each first result voltage level may be one of two discrete possible voltage levels (e.g., the first result voltage level corresponds to a binary bit). For example, if the first result voltage level is equal to a first possible voltage level, the corresponding logic value may be logic 1. If the first result voltage level is equal to a second possible voltage level, the corresponding logic value may be logic 0. In some embodiments, the possible voltage level may be equal to zero. In some embodiments, each unit may be attached to one or more latches (e.g., latches 1181-118). n Each latch may contain a memory (e.g., TDL) to store the output binary bit value from the applied first reference drive voltage. Processing can then proceed to step 706.

[0061] In step 706, the control circuit (e.g., Figure 1 The control circuit 111 applies a second reference drive voltage to each memory cell in the word lines of the memory cell. In some embodiments, the second reference drive voltage may be R4 (e.g., as described in step 306 of FIG3). Each memory cell (e.g., cells 1161-116) n The second result voltage level is generated in response to the applied second reference driving voltage. The process can then proceed to step 708.

[0062] In step 708, the control circuit (e.g., Figure 1 The control circuit 111 detects a pattern of logic values ​​stored in the memory. As shown, step 708 can be performed in parallel with elements of step 706. However, it will be understood that in some embodiments, step 708 can be performed after step 706 (e.g., sequentially). In some embodiments, the detected pattern is provided by the control circuit to a coupled external controller, and the external controller can perform additional steps related to the detected pattern. In some embodiments, the pattern can be a bit count of the total number of logic 1s stored in the memory (e.g., TDL in the word line of the memory cell). In some embodiments, the pattern can be a bit count of logic 0s, the ratio of total logic 1s to total logic 0s, other suitable patterns, or combinations thereof. In some embodiments, pattern detection can occur simultaneously with a second reference drive voltage being applied to the word line of the memory cell and a corresponding second result voltage level being generated. The process can then continue to step 710.

[0063] In step 710, the control circuit (e.g., Figure 1The control circuit 111 can modify the memory based on the corresponding second logic value indicated by each corresponding second result voltage level. Similar to step 704, in some embodiments, each second voltage level may correspond to a binary bit (e.g., logic 0 or logic 1, depending on the corresponding voltage level). In some embodiments, each corresponding second logic value can be compared with a corresponding first logic value (e.g., which is stored in memory) by bit-by-bit logic operations. For example, each corresponding second logic value can be inverted, and the corresponding inverted second logic value can be compared with an OR operation of the corresponding first logic value. Thus, the resulting bit value can be stored in memory in place of the corresponding first logic value. Processing can then continue to step 712.

[0064] In step 712, the control circuit (e.g., Figure 1 The control circuit 111, or an external controller (as previously described), modifies at least one of the first reference drive voltage and the second reference drive voltage based on the detected pattern data. In some embodiments, the first reference drive voltage can be modified directly based on the detected pattern data. In some embodiments, the detected pattern data may be a total count of logic 1 bits, and the number of logic 1 results based on the expected distribution can indicate whether and how the first reference drive voltage should be modified. For example, if the expected distribution is 50% logic 1 and 50% logic 0 (e.g., the binary bit values ​​are random), then if the detected pattern is, for example, 80% logic 1 (e.g., the storage voltage level of the memory cell is lower than the first reference drive voltage) and 20% logic 0 (e.g., the storage voltage level of the memory cell is higher than the first reference drive voltage), the first reference drive voltage can be modified to decrease by a predetermined amount. In some embodiments, the predetermined amount may be a fixed value. In some embodiments, the predetermined amount may be variable based on the return result of the sensing process. In some embodiments, the modification of the second drive voltage may be based on the current modification value stored in memory (e.g., based on the first and second result voltage levels).

[0065] It will be understood that in some embodiments utilizing more than two reference voltages, the process can be repeated. Figure 7 The steps are as follows. Because the first and second reference driving voltages are relative, iteration can be performed separately for any nth and (n+1)th actual reference voltages. Figure 7 The steps. For example, in Figure 7 In the second iteration of the steps, the first reference driving voltage may refer to the second actual reference voltage, and the second reference driving voltage may refer to the third actual reference voltage. In some embodiments, the steps can be repeated iteratively. Figure 7 The steps continue until all actual reference voltages have been modified.

[0066] Figure 8 A flowchart 800 illustrating steps of modifying at least one of the first drive voltage or the second drive voltage according to embodiments of the present disclosure is shown. Although the steps of the flowchart 800 are described as being performed by the control circuit 111 in the memory device 105, the steps of the flowchart 800 can also be performed, for example, by an external controller (e.g., coupled to the memory device 105), an additional controller on the memory device, other suitable controller and / or processor, or a combination thereof. Although the steps of the flowchart 800 are described in the context of the particular structures, components, and processes of the present disclosure, the steps of the flowchart 800 can be performed by other suitable structures, components, and processes in other suitable contexts. Figure 1 Figure 8 Although a particular order and flow of steps are depicted in Figure 8 , it will be understood that, in some embodiments, one or more of the steps can be modified, moved, removed, or added, and the order of the steps depicted in Figure 8 may be modified. For example, it will be understood that not all of the steps of Figure 8 may be performed each time a mode analysis occurs, and in some embodiments, the steps of Figure 8 may be performed only when a read error occurs (e.g., and is detected by, for example, a CRC process).

[0067] ​As previously described, the first and second reference drive voltages as described herein are relative and are not limited to only the first and second actual reference voltages specifically applied to the word line of the memory cell. For example, in a memory cell storing seven bits, the first and second reference drive voltages as described herein can refer to the second and third actual reference voltages, respectively, the third and fourth actual reference voltages, respectively, the sixth and seventh actual reference voltages, respectively, or any nth and nth+1 actual reference voltages, respectively. In some embodiments including multiple iterations or pairs of reference drive voltages, the relative first and second reference drive voltages described herein can refer to different actual reference voltages at each iteration or pairing. For example, in a memory cell storing seven bits, the methods described herein utilizing the first and second reference drive voltages can first be applied to the first and second actual reference voltages, respectively, and then to the second and third actual reference voltages, respectively, any suitable nth and nth+1 actual reference voltages, respectively, or combinations thereof. Similarly, the third reference drive voltage as described herein is also relative and can refer to an nth+2 actual reference voltage if the first reference drive voltage refers to an nth actual reference voltage. For example, if the first reference drive voltage refers to a fifth actual reference voltage, the third reference drive voltage refers to a seventh actual reference voltage. Thus, while the following can be described in the context of a CSB read of a word line of a TLC flash memory cell, it will be understood that, particularly when the present disclosure is applied to a memory cell storing more than three bits, the first, second, and third reference drive voltages can refer to any nth, nth+1, and nth+2 actual reference drive voltages, respectively.

[0068] At step 802, control circuitry (e.g., control circuitry 111 of Figure 1 At step 802, control circuitry (e.g., control circuitry 111 of Figure 7 In some embodiments, the detected pattern can be a bit count of logic ones (e.g., across the word line of the memory cell), a bit count of logic zeros, a ratio of logic ones to logic zeros, other suitable patterns, or combinations thereof. For example, in the described embodiments, it will be understood that the detected pattern is a bit count of logic ones. Processing can then continue to step 804.

[0069] At step 804, the control circuit (e.g., control circuit 111, or in some embodiments, an external controller) determines whether the number of logic ones in the detected pattern is above a first particular number. In some embodiments, the first particular number can be based on the total number of memory cells in the word line, an expected distribution of logic ones and logic zeros, or a combination thereof. As an illustrative example, for a word line of 18000 memory cells and an expected distribution of 50% logic ones, the first particular number can be set to about 10000 (e.g., slightly more than 50% to account for variations without overcorrecting the reference drive voltage). If the number of logic ones is above the first particular number (e.g., step 804 is "yes"), then processing can continue to step 806. If the number of logic ones is not above the first particular number (e.g., step 804 is "no"), then processing can continue to step 808.

[0070] At step 806, the control circuit (e.g., control circuit 111) of the memory device decreases the first reference drive voltage. In some embodiments, the decrease can be based on how high the bit count of logic ones is compared to the first particular number. For example, the higher the bit count of logic ones (i.e., the further the bit count of logic ones is from the first particular number), the further the first reference drive voltage is from the optimal first reference drive voltage. Thus, if the first particular number for a word line of 18000 memory cells is, for example, 10000 logic ones, and the bit count results in 15000 logic ones, then the first reference drive voltage can decrease by a greater amount compared to a bit count result of, for example, 11000 logic ones. Processing can then continue to step 812. Figure 1 At step 808, the control circuit (e.g., control circuit 111, or in some embodiments, an external controller) determines whether the number of logic ones in the detected pattern is below a second particular number. In some embodiments, the second particular number can be based on the total number of memory cells in the word line, an expected distribution of logic ones and logic zeros, or a combination thereof. As an illustrative example, for a word line of 18000 memory cells and an expected distribution of 50% logic ones, the second particular number can be set to about 8000 (e.g., slightly less than 50% to account for variations without overcorrecting the reference drive voltage). If the number of logic ones is less than the second particular number (e.g., step 808 is "yes"), then processing can continue to step 810. If the number of logic ones is not less than the second particular number (e.g., step 808 is "no"), then processing can continue to step 812.

[0071] At step 810, the control circuit (e.g., control circuit 111) of the memory device increases the first reference drive voltage. In some embodiments, the increase can be based on how low the bit count of logic ones is compared to the second particular number. For example, the lower the bit count of logic ones (i.e., the further the bit count of logic ones is from the second particular number), the further the first reference drive voltage is from the optimal first reference drive voltage. Thus, if the second particular number for a word line of 18000 memory cells is, for example, 8000 logic ones, and the bit count results in 7000 logic ones, then the first reference drive voltage can increase by a greater amount compared to a bit count result of, for example, 9000 logic ones. Processing can then continue to step 812.

[0072] Figure 1 ​The control circuit 111) increases the first reference drive voltage. In some embodiments, this increase may be based on how low the number of logic 1 bits is compared to a second specific number. For example, the lower the number of logic 1 bits (i.e., the further the number of logic 1 bits is compared to the second specific number), the further the first reference drive voltage is from the optimal first reference drive voltage. Therefore, if the second specific number of word lines for 18,000 memory cells is, for example, 8,000 logic 1s, and the bit count results in 3,000 logic 1s, then the first reference drive voltage may increase more significantly compared to a bit count result of, for example, 6,000 logic 1s. The process can then proceed to step 812.

[0073] In step 812, the control circuit (e.g., Figure 1 The control circuit 111) determines a second mode of the logic value based on the value stored in the memory. In some embodiments, step 812 may occur if the word line of the memory cell is a word line of a TLC flash memory cell (or has more than three levels, such as a quad-level cell (QLC)), and if the read process utilizes more than one reference drive voltage (e.g., CSB read). It will be understood that when steps 804 through 810 are performed, a second reference drive voltage is applied to the word line of the memory cell, and the value stored in the memory is a new value based on the output bit value of the applied second reference drive voltage (e.g., a bit-by-bit logic operation between the corresponding bit value output by the second reference drive voltage and the corresponding bit value output by the first reference drive voltage). In some embodiments, the second mode of the logic value may be a bit count of logic 1 (e.g., counting the bits of the new value stored in the memory), a bit count of logic 0, a ratio of logic 1 to logic 0, other suitable modes, or combinations thereof. Processing may then proceed to step 814.

[0074] In step 814, the control circuit (e.g., control circuit 111, or in some embodiments, an external controller) determines whether logic 1 in the second detection mode is higher than a first specific number. In some embodiments, the first specific number may be the first specific number determined in step 804. If the number of logic 1 is higher than the first specific number (e.g., step 814 is "yes"), the process may continue to step 816. If the number of logic 1 is not higher than the first specific number (e.g., step 814 is "no"), the process may continue to step 818.

[0075] In step 816, the control circuit (e.g., Figure 1the second reference drive voltage. In some embodiments, the decrease can be based on how high the bit count of logic ones is compared to the first particular number. For example, the higher the bit count of logic ones (i.e., the further the bit count of logic ones is from the first particular number), the further the second reference drive voltage is from the optimal second reference drive voltage. Thus, if the first particular number of 18,000 memory cells of the word line is, for example, 10,000 logic ones, and the bit count results in 15,000 logic ones, the second reference drive voltage can decrease more than if the bit count results in, for example, 11,000 logic ones. Processing can then continue to step 822.

[0076] At step 818, the control circuit (e.g., control circuit 111, or in some embodiments, an external controller) determines whether the logic ones in the detected pattern are below a second particular number. In some embodiments, the second particular number can be the second particular number determined in step 808. If the number of logic ones is less than the second particular number (e.g., step 818 is "Yes"), processing can continue to step 820. If the number of logic ones is not below the second particular number (e.g., step 818 is "No"), processing can continue to step 822.

[0077] At step 820, the control circuit (e.g., control circuit 111, or in some embodiments, an external controller) increases the second reference drive voltage. In some embodiments, the increase can be based on how low the bit count of logic ones is compared to the second particular number. For example, the lower the bit count of logic ones (i.e., the further the bit count of logic ones is from the second particular number), the further the second reference drive voltage is from the optimal second reference drive voltage. Thus, if the second particular number of 18,000 memory cells of the word line is, for example, 8,000 logic ones, and the bit count results in 3,000 logic ones, the second reference drive voltage can increase more than if the bit count results in, for example, 6,000 logic ones. Processing can then continue to step 822. Figure 1 At step 822, the control circuit (e.g., control circuit 111, or in some embodiments, an external controller) determines whether the bit count of logic ones is below a third particular number. In some embodiments, the third particular number can be the third particular number determined in step 812. If the number of logic ones is less than the third particular number (e.g., step 822 is "Yes"), processing can continue to step 824. If the number of logic ones is not below the third particular number (e.g., step 822 is "No"), processing can continue to step 826.

[0078] Figure 1 ​to the memory cell's word line. In some embodiments, the application of the modified reference drive voltage occurs in a future read operation (e.g., where the process can loop back to 802 when the next output bit value from the word line is counted). In some embodiments with more than two reference drive voltages (e.g., CSB reads), additional steps can be included in flowchart 800 to determine whether an additional reference drive voltage should be increased, decreased, or not changed, and the modified additional reference drive voltage applied in future reads.

[0079] It will be understood that in some embodiments with more than two reference voltages, the steps of Figure 8 may be repeated. Because the first reference drive voltage and the second reference drive voltage are relative, the steps of Figure 8 may be iterated for any nth actual reference voltage and nth+1 actual reference voltage, respectively. For example, in a second iteration of the steps of Figure 8 , the first reference drive voltage can refer to the second actual reference voltage, and the second reference drive voltage can refer to the third actual reference voltage. In some embodiments, the steps of Figure 8 may be iteratively repeated until all actual reference voltages have been modified.

[0080] The foregoing merely illustrates the principles of the disclosure and various modifications can be made by those skilled in the art without departing from the scope of the disclosure. The above-described embodiments are presented for purposes of illustration and are not intended to limit the scope of the disclosure, which is defined in the following claims. The disclosure can take many forms other than those explicitly described herein. Accordingly, it is not intended that the scope of the claims be limited to the foregoing illustrative structures merely because the latter were presented as examples.

[0081] While some portions of the disclosure can refer to examples, any such reference is only to provide a clear conception of the disclosure, and does not constitute an acknowledgement or admission that any such reference is in fact prior art.

Claims

1. A method for allowing data to be read from a memory, the method comprising: A first reference drive voltage is applied to the word line of the memory cell to generate a corresponding first result voltage level from each corresponding cell in the word line; For each corresponding first result voltage level output by each cell in the word line, a first corresponding logic value indicated by the corresponding first result voltage level is stored in memory; A second reference drive voltage is applied to the word line of the memory cell to generate a corresponding second result voltage level from each corresponding cell in the word line; Detect patterns in logical values ​​stored in memory; For each corresponding second result voltage level output by each cell in the word line, the memory is modified based on the second corresponding logic value indicated by the corresponding second result voltage level. and Modify at least one of the first reference drive voltage and the second reference drive voltage based on the detected pattern data.

2. The method of claim 1, wherein the mode of detecting the logic value occurs in parallel with the word line of applying the second reference drive voltage to the memory cell.

3. The method according to claim 1, wherein the method further comprises: In future read operations, the modified first reference drive voltage and second reference drive voltage will be applied to the word line of the memory cell.

4. The method of claim 1, wherein the mode for detecting the logical value includes: While applying a second reference drive voltage to the word line of the memory cell and before modifying the memory based on the second logic value, the pattern of the logic value is detected.

5. The method of claim 1, wherein detecting the pattern of logical values ​​stored in the memory comprises calculating the number of logical 1s stored in the memory.

6. The method of claim 5, wherein modifying at least one of the first reference drive voltage and the second reference drive voltage based on detected pattern data includes reducing the first drive voltage in response to determining that the number of logic 1s in a pattern of logic values ​​is higher than a first specific number.

7. The method of claim 5, wherein modifying at least one of the first reference drive voltage and the second reference drive voltage based on detected pattern data includes increasing the first drive voltage in response to determining that the number of logic 1s in a pattern of logic values ​​is less than a second specific number.

8. The method of claim 1, wherein detecting the pattern of logical values ​​stored in the memory comprises calculating the number of logical 0s stored in the memory.

9. The method of claim 1, wherein detecting the pattern of logical values ​​stored in the memory comprises calculating the ratio of logical 1s to logical 0s stored in the memory.

10. The method of claim 1, wherein the memory comprises a latch array, and wherein each latch in the latch array stores a logic value.

11. The method of claim 1, wherein the pattern of the logical value is a first pattern, the method further comprising: The second mode is based on the detection of logical values ​​based on the second logical value stored in memory.

12. The method according to claim 11, wherein the method further comprises: A third reference drive voltage is applied to the word line of the memory cell to generate a corresponding third result voltage level from each corresponding cell in the word line; Detect the second pattern of logical values ​​stored in the modified memory; For each corresponding third result voltage level output by each cell in the word line, the memory is modified based on the third corresponding logic value indicated by the corresponding third result voltage level; and Based on the detected first mode data or the detected second mode data, modify at least one of the first reference drive voltage, the second reference drive voltage, or the third drive voltage.

13. The method of claim 1, wherein the memory cell comprises a multi-level flash memory cell, the multi-level flash memory cell comprising at least two reference bits and at most seven reference bits, the method further comprising: At least one bit of each memory cell is read using more than one reference drive voltage.

14. The method of claim 12, wherein the memory cell comprises a three-level cell (TLC) flash memory cell, the method further comprising: Read the corresponding central significant bit (CSB) of each memory cell.

15. The method of claim 12, wherein: The memory modification based on the second corresponding logic value includes the result of a first bitwise logic operation stored between each stored first logic value and each corresponding second logic value, and The memory modified based on the third corresponding logic value includes the result of a second bitwise logic operation between each third logic value and each corresponding logic value stored in the memory modified based on the second corresponding logic value.

16. The method of claim 15, wherein: The first bitwise logical operation between each stored first logical value and each corresponding second logical value includes inverting the corresponding second logical value, and then performing an OR operation between the inverted second logical value and the corresponding stored first logical value; and The second bitwise logical operation between each third logical value and each corresponding logical value stored in memory modified based on the second corresponding logical value includes performing an AND operation between the corresponding third logical value and the corresponding logical value stored in the modified memory.

17. The method of claim 12, wherein: The first pattern for detecting logical values ​​stored in memory includes calculating the number of logical 1s stored in memory before modifying the memory based on a second corresponding logical value; and The second mode for detecting logical values ​​stored in memory includes calculating the number of logical 1s stored in memory after modifying the memory based on a second corresponding logical value and before modifying the memory based on a third corresponding logical value.

18. The method of claim 12, further comprising: (a) A fourth reference drive voltage is applied to the word line of the memory cell to generate a fourth corresponding resulting voltage level from each corresponding cell in the word line; (b) Detect the third mode of the logical value stored in the modified memory; (c) For each corresponding fourth result voltage level output by each cell in the word line, modify the memory based on the fourth corresponding logic value indicated by the corresponding fourth result voltage level; For any additional reference drive voltage, repeat steps (a)-(c); and Modify at least one of the reference drive voltages based on at least one of the detected mode data.

19. A system comprising: Memory; Word lines of memory cells configured to store data; The control circuit is configured as follows: A first reference drive voltage is applied to the word line of the memory cell to generate a corresponding first result voltage level from each corresponding cell in the word line. For each corresponding first result voltage level output by each cell in the word line, a first corresponding logic value indicated by the corresponding first result voltage level is stored in memory. A second reference drive voltage is applied to the word line of the memory cell to generate a corresponding second resulting voltage level from each corresponding cell in the word line. Detect patterns in logical values ​​stored in memory. For each corresponding second result voltage level output by each cell in the word line, the memory is modified based on the second corresponding logic value indicated by the corresponding second result voltage level, and Modify at least one of the first reference drive voltage and the second reference drive voltage based on the detected pattern data.

20. The system of claim 19, wherein the control circuit is further configured to: In future read operations, the modified first reference drive voltage and second reference drive voltage will be applied to the word line of the memory cell.

21. The system of claim 19, wherein the control circuit is configured to detect a pattern of logical values ​​stored in the memory by calculating the number of logical 1s stored in the memory.

22. The system of claim 19, wherein the memory comprises a latch array, and wherein each latch in the latch array is configured to store a logical value.

23. The system of claim 19, wherein the logic 1 mode is a first mode, and wherein the control circuit is further configured to: A third reference drive voltage is applied to the word line of the memory cell to generate a corresponding third result voltage level from each corresponding cell in the word line; A second pattern for detecting logical values ​​based on a second logical value stored in modified memory; For each corresponding third result voltage level output by each cell in the word line, the memory is modified based on the third corresponding logic value indicated by the corresponding third result voltage level; and Based on the detected first mode data or the detected second mode data, modify at least one of the first reference drive voltage, the second reference drive voltage, or the third drive voltage.

24. The system of claim 19, wherein the memory unit comprises a multi-level flash memory unit, the multi-level flash memory unit comprising at least two reference bits and at most seven reference bits, and wherein the control circuitry is further configured to: At least one bit of each memory cell is read using more than one reference drive voltage.

25. The system of claim 23, wherein the control circuit is configured to: The memory is modified based on the second corresponding logical value, using the result of a first bit-by-bit logical operation between each stored first logical value and each corresponding second logical value. The memory is modified based on the third corresponding logic value by means of the result of a second bitwise logic operation between each third logic value and each corresponding logic value stored in the memory modified based on the second corresponding logic value.

26. The system of claim 23, wherein the control circuit is further configured to: (a) A fourth reference drive voltage is applied to the word line of the memory cell to generate a fourth corresponding resulting voltage level from each corresponding cell in the word line; (b) Detect the third mode of the logical value stored in the modified memory; (c) For each corresponding fourth result voltage level output by each cell in the word line, modify the memory based on the fourth corresponding logic value indicated by the corresponding fourth result voltage level; For any additional reference drive voltage, repeat steps (a)-(c); and Modify at least one of the reference drive voltages based on at least one of the detected mode data.

27. A non-transitory computer-readable medium having non-transitory computer-readable instructions thereon, the non-transitory computer-readable instructions causing the circuit, when executed by the circuit, to: A first reference drive voltage is applied to the word line of the memory cell to generate a corresponding first result voltage level from each corresponding cell in the word line; For each corresponding first result voltage level output by each cell in the word line, a first corresponding logic value indicated by the corresponding first result voltage level is stored in memory; A second reference drive voltage is applied to the word line of the memory cell to generate a corresponding second result voltage level from each corresponding cell in the word line; Detect patterns in logical values ​​stored in memory; For each corresponding second result voltage level output by each cell in the word line, the memory is modified based on the second corresponding logic value indicated by the corresponding second result voltage level. and Modify at least one of the first reference drive voltage and the second reference drive voltage based on the detected pattern data.

Images