Testing communication receiver using periodic signals

Abstract

A system (100) includes a test transmitter (102) including a pseudorandom bit sequence (PRBS) generator and a signal generation circuit. The PRBS generator is configured to generate a PRBS. The signal generation circuit is configured to generate a test signal comprising a repetition of a truncated portion of the PRBS such that a period of the repetition is shorter than a period of the PRBS.

Description

[0001] Cross-references to related applications This application claims the benefit of U.S. Provisional Patent Application 63 / 581,005, filed September 7, 2023, the disclosure of which is incorporated herein by reference.

[0002] Invention Field This invention relates generally to communication systems, and more particularly to the testing of communication receivers. Background of the Invention Digital communication systems, especially digital communication receivers, present significant testing challenges. Some background on testing digital communication systems can be found in “A survey of communication protocol testing” (Lai, R., Journal of Systems and Software, 62(1), 21–46 (2002)), which includes a literature review on communication protocol testing, focusing on five areas: test sequence generation methods, test coverage, failure models and prediction, test tools, and experience reporting.

[0004] Other communication system testing backgrounds can be found in "BER Testing of Communication Interfaces" (Yongquan Fan, & Zilic, Z. IEEE Transactions on Instrumentation and Measurement, 57(5) (2008)). The authors propose a general bit error rate (BER) testing scheme to characterize the quality of communication interfaces. This paper proposes a scheme for BER testing of Field Programmable Gate Arrays (FPGAs) for both design and evaluation phases, consisting of a Bit Error Rate Tester (BERT) core and a novel Additive White Gaussian Noise (AWGN) generator core; the authors also propose a pipelined structure utilizing the central limit theorem, which can achieve a speedup of four times or more. Invention Overview Embodiments of the present invention described herein provide a system including a test transmitter comprising a pseudo-random bit sequence (PRBS) generator and a signal generation circuit. The PRBS generator is configured to generate a PRBS. The signal generation circuit is configured to generate a test signal comprising repetition of a truncated portion of the PRBS, such that the period of repetition is shorter than the period of the PRBS.

[0006] In some embodiments, when generating a test signal, the signal generation circuit is configured to generate a sequence of groups, the sequence of groups including (i) repetition of a truncated portion of the PRBS used as a payload, and (ii) additional symbols.

[0007] In some embodiments, the system further includes a receiver circuit and a test circuit. The receiver circuit is configured to receive and decode a test signal. The test circuit is configured to generate a reference signal that is identical to a truncated portion of the PRBS, and to evaluate the performance of the receiver circuit by comparing the reference signal with the test signal decoded by the receiver circuit.

[0008] In an example embodiment, the test circuitry in the receiver is configured to generate a repeating reference signal that includes a truncated portion of the PRBS. In another embodiment, the test signal generated by the transmitter includes additional symbols interleaved between repetitions of the truncated portions of the PRBS, and the test circuitry in the receiver is configured to omit the additional symbols from comparisons with the reference signal.

[0009] Furthermore, according to embodiments of the present invention, a test transmitter is also provided, comprising an encoder and a test sequence generation circuit. The encoder is configured to encode an input data sequence using a non-terminating forward error correction (FEC) code. The test sequence generation circuit is configured to generate a periodic FEC cyclic test sequence having a preset period length, which, when repeatedly encoded by the encoder, forms a valid non-terminating encoded data stream based on the FEC code.

[0010] In some embodiments, each cycle of the FEC cyclic test sequence begins in the same state of the encoder. In some embodiments, the test sequence generation circuit is configured to insert cyclic redundancy check (CRC) codes within the FEC cyclic test sequence.

[0011] According to embodiments of the present invention, a method for generating a test signal is also provided, comprising generating a pseudo-random bit sequence (PRBS). A test signal is generated, the test signal comprising repetition of a truncated portion of the PRBS, such that the period of repetition is shorter than the period of the PRBS.

[0012] Furthermore, according to embodiments of the present invention, a method for generating test signals is also provided, comprising: operating an encoder that encodes an input data sequence using a non-terminating forward error correction (FEC) code; generating a periodic FEC cyclic test sequence having a preset period length; and forming a valid non-terminating encoded data stream based on the FEC code when the sequence is repeatedly encoded by the encoder.

[0013] The invention will be more fully understood from the following detailed description of embodiments thereof, taken in conjunction with the accompanying drawings, in which: Brief description of the attached diagram Figure 1 This is a block diagram schematically illustrating a test system according to an embodiment of the present invention; Figure 2 This is a block diagram schematically illustrating an OIF 800ZR test transmitter configured in Mode A according to an embodiment of the present invention; Figure 3 This is a block diagram schematically illustrating an OIF 400ZR test transmitter configured in Mode B according to an embodiment of the present invention; Figure 4 This is a flowchart illustrating a method for creating an effective periodic test sequence according to an embodiment of the present invention; Figure 5A This is a flowchart illustrating, according to an embodiment of the present invention, a method for testing a communication receiver under test (RUT) in a first test mode; and Figure 5B This is a flowchart illustrating, according to an embodiment of the present invention, a method for testing a communication RUT in a second test mode. Detailed Implementation

[0014] Overview Modern high-speed digital communication systems are often complex and present testing challenges. We will describe these systems primarily with reference to optical (via fiber optic) communication systems; however, the invention is by no means limited to optical communication systems and can be applied to other suitable communication systems, such as those employing electrical, optical, and electromagnetic signal transmission.

[0015] Over the past few years, many proprietary systems and standards for fiber optic communication have emerged. Examples include the Optical Interconnect Forum (OIF) standards 400ZR / 800ZR, openZR+, and OpenROADM.

[0016] For example, the 400ZR standard specifies that, using QAM16 modulation at a rate of 60 to 68 Gbaud, the transmission distance without amplification can reach 80 kilometers, and with amplification, the transmission distance can reach 120 kilometers. Regarding forward error correction (FEC), the 400ZR standard supports the Cascaded FEC (CFEC) method, which combines inner and outer FEC codes to enhance performance compared to standard FEC codes.

[0017] When using QAM16 modulation, the 800ZR is similar but faster.

[0018] To test and calibrate communication equipment, different parts of the modem need to be tested with various signals. On the receiver (Rx) side, tests can be performed using test signals from a compatible transmitter or from dedicated test equipment.

[0019] Using test equipment for testing and calibration is preferred because the transmitted signal is of high quality and defects and errors can be inserted for testing purposes.

[0020] The disadvantage of using test equipment is that the transmission length is usually limited, so periodic signals should be used, and some communication standards may not cover such signals adequately.

[0021] The embodiments of the invention disclosed herein provide apparatus and methods for testing a communication receiver (referred to as a receiver under test, or RUT) using instances of multiple relatively short-period test signals. In one embodiment, the test transmitter is configured to operate in one of two modes: a first mode (mode A) and a second mode (mode B).

[0022] In the embodiments disclosed below, mode A is used to test the demodulator section of the RUT using a truncated pseudo-random bit sequence (PRBS) that is input to the modulator section of the test transmitter. The RUT is modified to compare the output of the RUT demodulator with the truncated PRBS sequence and output a mismatch (if any).

[0023] In another embodiment disclosed below, Mode B is used to test the complete RUT using an FEC cyclic test sequence, which also generates a cyclic sequence at the output of the transmitter. The test sequence is input to a test transmitter, which outputs a cyclic signal with a period length of an integer number of superframes. The test results can be checked by calculating the CRC error of the RUT. In some Mode B embodiments, the RUT includes a Multi-Block Alignment Signal (MBAS) circuit that is modified according to the length of the test sequence period.

[0024] Finally, in the embodiments disclosed below, a method for generating FEC cyclic input sequences is disclosed.

[0025] System Description Forward error correction (FEC) using Bose, Chaudhuri, and Hocquenghem (BCH) codewords generates output symbols based on the input signal and the internal state of the FEC circuitry. Some communication standards (e.g., 400ZR, 800ZR) use an infinite sequence of interleaved BCH codewords, resulting in unterminated codes, meaning there is no point in time where the encoding ends (as opposed to BCH codes, Hamming codes, and other block codes). In the following description, we will use the term FEC to refer to unterminated FEC (such as OFEC or CFEC).

[0026] In the embodiments disclosed below, we use a test apparatus that includes a modified communication transmitter to test a communication receiver (hereinafter referred to as the receiver under test, or RUT). We focus on two test scenarios—the demodulator test scenario (hereinafter referred to as Mode A) and the complete receiver test scenario (hereinafter referred to as Mode B).

[0027] Figure 1 This is a block diagram schematically illustrating a test system 100 according to an embodiment of the present invention. The test system 100 includes a test transmitter 102, a medium 104 (e.g., an optical fiber cable), and a receiver under test (RUT) 106.

[0028] We arbitrarily divide the transmission link of the test transmitter 102 into two main circuits—encoder 108 and modulator 110. Encoder 108 includes some or all of the following circuits ( Figure 1 (Not shown): Cyclic Redundancy Code (CRC) circuitry, padding circuitry, scrambler, forward error correction (FEC) encoder, and interleaver. Modulator 110 includes a mapper and circuitry to add synchronization bits and pilot bits to the transmitted signal.

[0029] Similarly, we divide the receive link into a demodulator 112 and a decoder 114. The demodulator 112 includes circuitry for synchronizing the input data based on synchronization bits and pilot bits, as well as a demapper. The decoder 114 includes some or all of the following circuitry: an FEC decoder, a descrambler, a deinterleaving unit, a padding remover, and a CRC checker. It should be noted that in some embodiments, not all of the above functions are included; furthermore, in embodiments, other functions may be added to the link, such as testing error correction code (ECC) insertion in the transmitter and error correction circuitry in the RUT.

[0030] according to Figure 1In the example embodiment shown, the test transmitter 120 includes a configuration switch 116 that sets the test mode to either mode A or mode B. Mode A primarily tests the demodulation functionality of the RUT, while mode B tests the full functionality of the RUT. In mode A, the Tx encoder 108 is not used; instead, a Tx pseudo-random binary sequence (PRBS) generator 118 transmits periodically truncated PRBS sequences to the Tx modulator 110. The truncated PRBS generator 118 generates PRBS starting from a given seed; in some embodiments, the seed can be changed between tests, for example, the seed can be preloaded by the processor (not shown) of the test transmitter. PRBS lengths are relatively large (e.g., a 31-bit PRBS31 is 2,147,483,647 bits long) and may be impractical to use as a test signal; therefore, the truncated PRBS generator 118 transmits repetitions of truncated PRBS. In some embodiments, the truncated PRBS length is an integer number of superframes (as defined in 400ZR / 800ZR and other standards).

[0031] according to Figure 1 In the example embodiment shown, for Mode A testing, RUT 106 includes a comparator 120 that compares the sequence received by demodulator 112 with a periodically truncated PRBS sequence generated by Rx-truncated PRBS generator 122. In some embodiments, Rx-truncated PRBS generator 122 is identical to Tx-truncated PRBS generator 118, starting from the same seed and generating the same sequence (a Tx-Rx truncated PRBS synchronization technique that can be used in embodiments will be described below). Therefore, when in Mode A, the test result can be observed at the output of comparator 120 (in some embodiments, RUT 106 may also include an error counter to count errors detected by the comparator).

[0032] In the embodiments, various truncated PRBS synchronization techniques can be used: 1. In some embodiments, when the length of the truncated PRBS is a single superframe, the Rx truncated PRBS generator can be restarted (to a preset seed value) in response to a synchronization signal detected by the demodulator 112.

[0033] 2. In other embodiments, when the length of the truncated PRBS is one or more superframes, the Rx PRBS generator can detect the last state of the truncated PRBS period and, in response, restart to a preset seed value.

[0034] 3. In yet another embodiment, when the truncated PRBS length is one or more superframes, the RUT includes a superframe counter that is reset at the start of the test (e.g., in response to a global RUT reset signal), increments in response to a synchronization signal detected by the demodulator 112, and is reset when a preset number of superframes have been received.

[0035] 4. Finally, in some other embodiments, the test transmitter transmits an out-of-band truncated PRBS restart signal, and the Rx-truncated PRBS generator resets in response to receiving the restart instruction.

[0036] The following will refer to Figure 2 A detailed description of the OIF 800ZR test transmitter set to mode A.

[0037] When test system 100 is set to mode B test, switch 116 routes the output of Tx encoder 108 to Tx modulator 110, thus PRBS generator 118 is not used. Forward error correction (FEC) cyclic sequence generator 124 transmits periodic test sequences to Tx encoder 108, which encodes the sequences (including functions such as adding CRC, scrambling, FEC encoding, interleaving, etc.) and transmits the encoded signals to Tx modulator 110.

[0038] The periodic test sequence generated by the FEC loop sequence generator 124 is repetitive, with a cycle time of an integer number of superframes. Furthermore, the periodic test sequence is established such that the resulting Tx encoder output will also be periodic. This requirement can be challenging because the FEC encoder output of the Tx test transmitter is generated based on the input and the internal FEC encoder state, which changes in response to the input. In this embodiment, the FEC loop sequence is configured such that when input is given to the FEC circuitry, the internal FEC encoder state will also be cyclical, with the same cycle time.

[0039] The following will refer to Figure 3 The description details the OIF 400ZR test transmitter set to Mode A. See below for further information. Figure 4 Describe an example technique for generating such FEC cyclic sequences.

[0040] When in mode B, the test results can be obtained by observing the CRC error count output by the Rx decoder 114.

[0041] In some embodiments, the test transmitter 102 further includes an error insertion circuit 126 to test the fault resilience and fault recovery of the RUT 104. The error insertion circuit can be configured to insert errors into various test transmitter circuits under software control. In some embodiments, the error insertion circuit is also configured to insert errors into a medium, for example, by controlling a variable optical attenuator coupled to an optical fiber.

[0042] Therefore, according to Figure 1 As shown and in the example embodiments described above, the test transmitter can test the RUT in two modes—modulator-demodulator test (mode A), in which a periodically truncated PRBS signal is used to test modulation and demodulation, and complete test (mode B), in which a periodic input designed to generate periodic outputs is used to test the complete communication path.

[0043] The configuration of test system 100 is cited by way of example. Other configurations may be used in alternative embodiments. For example, in some embodiments, the test transmitter is configured to test the RUT only in mode A, and therefore, some circuitry of the test transmitter circuitry may not be used. In other embodiments, testing is performed only in mode B. In one embodiment, the test system is configured to use a single test transmitter to test multiple receivers (in some cases, a fiber optic splitter may be required).

[0044] In this embodiment, the communication system is not necessarily optical—a variety of suitable communication systems, whether wired and wireless, electrical, electromagnetic, or optical, may be used.

[0045] Figure 2 This is a block diagram schematically illustrating an OIF 800ZR test transmitter 200 configured in Mode A according to an embodiment of the present invention. According to the OIF specification, the transmitter includes: 1. CRC circuit 202, which receives the input sequence and adds a 32-bit CRC code to the input bit group; 2. The scrambling / filling circuit 204 receives the output of the CRC circuit, adds a fixed value of fill bits, and then scrambles the data; 3. FEC encoder 206, which adds forward error correction code to the input of the fill / scramble circuit 204 output and generates unterminated FEC code; 4. Interleaver 208, which interleaves the unterminated FEC code output by FEC encoder 206; 5. Mapping circuit 210, which maps the output of interleaver 208 to symbols; and 6. Synchronization / pilot circuit 212, which adds synchronization signal, pilot signal and other auxiliary signals to the output of mapping circuit 210.

[0046] For Mode A testing, the connection between interleaver 208 and mapping circuit 210 is broken (e.g., by...). Figure 1 The configuration switch 116 is set to mode A, and the truncated PRBS generator circuit emits periodically truncated PRBSs to the input of the mapping circuit. As explained above, the period length of the truncated PRBSs is an integer number of superframes. Appropriate circuitry is added to the RUT to check for errors in the periodically truncated PRBS sequence.

[0047] Figure 3 This is a block diagram schematically illustrating an OIF 400ZR test transmitter 300 in Mode B configuration according to an embodiment of the present invention. According to the OIF specification, the transmitter includes: 1. CRC circuit 302, which receives the input sequence and adds a 32-bit CRC code to the input bit group; 2. Error decorrelator interleaver (EDI) circuit 304, which modifies the output of CRC circuit 302 to reduce the possible correlation of errors.

[0048] 3. Multi-Block Alignment Signal (MBAS) circuit 306, which counts superframes (the contents of the MBAS 306 are input to the EDI circuit 304). 4. FEC encoder 308, which receives the output of EDI circuit 304, adds forward error correction bits, and generates unterminated FEC output code; 5. Status register 310, which temporarily stores the status of FEC encoder 308; 6. Error Decorrelator Deinterleaver (EDD) / Hamming circuit 312, which receives the unterminated FEC code from FEC encoder 308 and performs inverse decorrelation on the parity bits.

[0049] 7. Mapper / interleaver circuit 314, which receives the output of EDD / Hamming circuit 314, maps data into symbols and interleaves the symbols; and 8. Synchronization / pilot circuit 316, which adds synchronization signal and pilot signal according to subframe, and adds other auxiliary signals to the output of mapper / interleaver circuit 314.

[0050] For the Mode B test, the FEC cyclic sequence generator 318, connected to the input of the CRC circuit 302, generates the input sequence for the test transmitter. Furthermore, the MBAS circuit is modified to wrap around the superframe count to zero when the number of superframes in the test cycle is reached.

[0051] As mentioned above, the periodic input sequence is FEC cyclic, such that the state of state 310 is the same at the beginning of all cycles.

[0052] Generate FEC cycle mode This is also a periodic test signal for valid FEC codewords, which cannot be generated by retransmitting any periodic sequence (including integer numbers of superframes) because a single BCH codeword would not be a valid codeword in the gap between two repeating sequences. In this embodiment, a sequence is constructed such that all BCH codewords will be valid when repeated. The technique for constructing such an "FEC cycle" sequence is outlined below.

[0053] First, we note that the state of a BCH encoder can be described by a finite number of bits, representing the synodal or partial parity check of a BCH codeword that has not yet been fully encoded. Let us denote the size of the state as . .

[0054] The code is a linear code, therefore the encoder is a binary linear system. For a fixed number of input bits, Given (e.g., the length of the sequence), we can find matrices A, B, C, and D such that: in: It is the encoder's state at the beginning of the encoded segment.

[0055] This is the encoder's state at the end of the encoded segment.

[0056] This is the encoder's input data.

[0057] It is the output of the encoder.

[0058] Periodic conditions can be achieved by adding additional conditions: These equations can be solved to find and Multiple solutions are possible. We will prefer the solution with higher entropy (a trivial solution with 0 entropy may not be very useful). Note that in the embodiments, more than one solution may be used to achieve a wider range of test diversity.

[0059] In typical communication standards, input data is modified before FEC encoding; for example, a CRC code is added to the data, and sometimes the data is scrambled. The effect of these modifications is typically (e.g., in the ZR 800) a linear operation on the output plus a fixed value: In this new set of equations, the size of the input has been changed from Become Furthermore, factors E and F have been added. By solving these overdetermined equations, we can find the source that will generate a periodic, effective signal. The status and input.

[0060] Whether a solution to the equation exists depends on the properties of matrices A, B, and E. The equation can be modified by changing its period to one or more superframes. A solution to the equation (if one exists) can be found using common mathematical techniques: This can be represented in matrix form: if A solution exists in the subspace spanned by the column vectors of X.

[0061] Figure 4 Flowchart 400 schematically illustrates a method for creating a valid FEC cycle test sequence according to an embodiment of the invention. This flowchart is typically executed offline by a suitable computer software program (hereinafter referred to as "SW") using a simulation model of the transmitter, and the created test sequence is loaded into test transmitter 102. Figure 1 ) FEC cyclic sequence generator 124.

[0062] For the sake of simplicity, we will refer to the sequence of input data bits as D, the FEC state as S, the state and input data as S / D, and the single set bit word (applicable to both FEC state and input data) as SSB.

[0063] The flowchart begins with a reset S / D operation 402, where SW sets the state and input data to zero. Next, at the apply encoder operation 404, SW starts the transmitter simulation from a zero-state and zero-input data to generate a vector E (as defined above). SW stores the vector E, which will be used in further operations.

[0064] The switch now enters the reset S / D and bit pointer operation 406, where the switch sets the status and input data to zero and sets the bit pointer variable pointing to the encoder status bit to zero. Next, at the generate SSB status operation 408, the switch generates the encoder status, where the bit pointed to by the bit pointer is binary 1 and all other bits are binary 0.

[0065] In the encoder operation 410, the SW runs a transmitter simulation to encode the all-zero input data sequence using the initial input states set in operation 408. The SW saves the post-simulation state of each initial state in memory and proceeds to the XOR matrix column operation 412, in which each encoded result A_i is XORed with matrix E (derived in operation 404) to obtain A_i+E.

[0066] Now, in the last bit pointer check operation 414, the SW checks whether the bit pointer points to the last state bit (e.g., for an 8-bit state, the SW checks whether the bit pointer is equal to binary 10000000). If the bit pointer has not yet reached the last state bit, the SW enters the bit pointer increment operation 416, incrementing the bit pointer to point to the next state bit, and then re-enters operation 408 to generate the next SSB state.

[0067] In operation 414, if the bit pointer points to the last status bit, the SW will enter the reset S / D and bit pointer operation 418, where the SW sets the status and input bits to zero and sets the bit pointer variable pointing to the input data bit to zero. Next, in the generate SSB input operation 420, the SW generates the input data sequence, where the input data bit pointed to by the bit pointer is binary 1 and all other bits are binary 0.

[0068] In the encoder operation 422, the SW runs a transmitter simulation, starting from an all-zero state, and encodes the SSB input sequence using the input data set in operation 420. The SW saves the post-simulation state of each SSB input data in memory and proceeds to the XOR matrix column operation 424, in which the encoded result B_i is XORed with matrix E (derived in operation 404) to obtain Bi+E.

[0069] Now, in the last bit pointer check operation 426, SW checks if the bit pointer points to the last sequence of bits. If the bit pointer has not yet reached the last sequence of bits, SW enters the bit pointer increment operation 428, incrementing the bit pointer to point to the next data bit, and then re-enters operation 420 to generate the next data SSB.

[0070] If, in operation 426, the bit pointer points to the last bit of the input data sequence, then SW will enter operation 430 to find matrix A, where SW performs an XOR operation between the post-simulation state saved in operation 410 and matrix E to find matrix A. Similarly, in the subsequent operation 432 to find matrix B, SW performs an XOR operation between the post-simulation state saved in operation 422 and matrix E to find matrix B.

[0071] Now, in the solution search operation 434, SW searches for a solution to the non-homogeneous overdetermined linear system of equations s = As + Binp + E, which has multiple solutions. The solution can be found using, for example, Gaussian elimination or other methods known in the art.

[0072] SW can optionally enter the lookup output operation 436, in which the test transmitter is simulated with the calculated input and the generated output is stored. In an embodiment, the stored output can be used in a simplified test transmitter that includes only the PHY.

[0073] The method described above creates periodic test signals for communication standards such as OIF ZR800, OpenZR+, and OpenroadM. The created test signals will have valid CRC and FEC codewords, allowing for direct BER measurement by monitoring CRC errors. The relatively long period length will not affect BER measurement because spikes appear at multiples of the sequence period.

[0074] For the OIF ZR400 standard, there is an additional synchronization signal (MBAS) that increments by 1 for each superframe and wraps back to zero at 128. Therefore, sequences shorter than 128 superframes will be invalid. In one embodiment, the RUT is modified to support an MBAS wraparound value less than 128; in another embodiment, the wraparound value is one superframe; in still other embodiments, the value can be any other integer number of superframes, and in yet another embodiment, the MBAS signal wraparound value is programmable.

[0075] The example references... Figure 4 The methods shown and described above for finding the FEC cyclic input sequence are illustrated. Other methods may be used in alternative embodiments. For example, in some embodiments, the tester performs operations 418 to 428 prior to operations 406 to 416. In some embodiments, some operations may run simultaneously, for example, on a multi-core processor.

[0076] Figure 5A Flowchart 500 schematically illustrates a method for testing a communication RUT in a first test mode according to an embodiment of the invention. This flowchart is executed by test hardware and software (referred to as a test instrument). The RUT being tested will be referred to as the receiver under test (RUT).

[0077] The flowchart begins with a periodic PRBS generation operation 502, where the tester generates a periodic test sequence by truncating the PRBS sequence into an integer number of superframes. Next, at a transmit sequence to modulator operation 504, the tester transmits the periodic test sequence to the modulator section of a communication transmitter compatible with the receiver under test, bypassing the transmitter's encoder section. In some embodiments, the transmitter's encoder section includes CRC generation, padding, scrambling, FEC encoding, and interleaving, and may include mapping and the addition of synchronization symbols and pilot symbols.

[0078] Next, at transmitter output operation 506, the tester transmits the transmitter's output to the RUT via a suitable medium (e.g., optical fiber). In an embodiment, for testing purposes, the tester may inject errors into various stages of the transmitter and / or the medium.

[0079] Finally, in comparison output operation 508, the tester compares the output of the demodulator section of the RUT with the periodically truncated PRBS sequence of operation 502. In this embodiment, this comparison is performed by circuitry added to the RUT.

[0080] Figure 5B Flowchart 550 schematically illustrates a method for testing a communication receiver in a second test mode according to an embodiment of the invention. This flowchart is executed by test hardware and software (referred to as a test instrument). The receiver under test is referred to as the receiver under test (RUT).

[0081] The flowchart begins with the optional modification of the MBAS operation 552, in which the tester modifies the RUT's Multi-Block Alignment Signal (MBAS) circuitry to reset it according to the size of the test sequence (as referenced above). Figure 4 This operation is optional and is required in communication systems that include MBAS (e.g., 400ZR).

[0082] Next, in the FEC cyclic sequence generation operation 554, the tester generates a cyclic test sequence with a period length of an integer number of superframes, thereby causing the transmitter's FEC encoder to operate cyclically, and thus causing the transmitter's cyclic output (as already referred above). Figure 4 A method for finding FEC cycle test sequences is described.

[0083] Now, in the transmit sequence to tester operation 556, the tester transmits a periodic test sequence to the communication transmitter, which in turn generates a cyclic transmission signal in response. Now, in the transmit transmitter output operation 558, the tester transmits the transmitter's output to the RUT via a suitable medium (e.g., optical fiber). In this embodiment, for testing purposes, the tester may inject errors into various stages of the transmitter and / or the medium.

[0084] Finally, at operation 560, the tester observes the CRC errors output by the RUT to evaluate the operation of the RUT.

[0085] Extended to non-periodic test sequences In some embodiments, the techniques described above can be used for non-periodic testing. For example, in the 800ZR specification, the equations disclosed above can be used to transmit data, ensuring that the encoder's state is known at the end of a superframe. This eliminates the initial synchronization phase of the decoder, during which the initial state is unknown and the input stream cannot be decoded until enough bits have been received. In one embodiment, the initial transmission can use some data bits to ensure that the final or initial state is zero.

[0086] The above references Figures 1 to 5B The described apparatus and methods (including all their units and subunits) are exemplary configurations and methods shown purely for clarity of concept. Any other suitable methods and configurations may be used in alternative embodiments. For example, in an embodiment, a combination of mode A and mode B testing may be used.

[0087] In various embodiments, the test transmitter 102 and receiver 106 (including their sub-units) may be implemented using suitable hardware, such as one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) or a combination of ASICs and FPGAs.

[0088] Therefore, it should be understood that the above embodiments are cited by way of example, and the invention is not limited to what has been specifically shown and described above. Rather, the scope of the invention includes combinations and sub-combinations of the various features described above, as well as variations and modifications of the invention that would be conceived by one of skill in the art upon reading the above description and that are not disclosed in the prior art. Documents incorporated herein by reference are considered part of this application, and the definitions in this specification should be considered only, unless any terms are defined in these incorporated documents in a manner that conflicts to some extent with the definitions expressly or implicitly made in this specification.

Claims

1. A system comprising: Test transmitter, including: - A pseudo-random bit sequence (PRBS) generator, configured to generate PRBS; and - A signal generation circuit is configured to generate a test signal comprising a repetition of a truncated portion of the PRBS, such that the period of the repetition is shorter than the period of the PRBS.

2. The system according to claim 1, wherein, When generating the test signal, the signal generation circuit is configured to generate a sequence of groups, the sequence of groups including (i) a repetition of a truncated portion of the PRBS used as a payload, and (ii) additional symbols.

3. The system according to claim 1 or 2, further comprising: The receiver circuit is configured to receive and decode the test signal; and The test circuit is configured to generate a reference signal that is identical to a truncated portion of the PRBS, and to evaluate the performance of the receiver circuit by comparing the reference signal with the test signal decoded by the receiver circuit.

4. The system according to claim 3, wherein, The test circuit in the receiver is configured to generate a repeating reference signal that includes a truncated portion of the PRBS.

5. The system according to claim 3, wherein: The test signal generated by the transmitter includes additional symbols interleaved between repetitions of the truncated portion of the PRBS; and The test circuit in the receiver is configured to omit the additional symbols from the comparison with the reference signal.

6. A test transmitter, comprising: The encoder is configured to encode the input data sequence using unterminated forward error correction (FEC) codes; and A test sequence generation circuit is configured to generate a periodic FEC cyclic test sequence with a preset period length. When the periodic FEC cyclic test sequence is repeatedly encoded by the encoder, a valid non-terminating encoded data stream is formed based on the FEC code.

7. The test transmitter according to claim 6, wherein, Each cycle of the FEC cyclic test sequence begins in the same state of the encoder.

8. The test transmitter according to claim 6 or 7, wherein, The test sequence generation circuit is configured to insert cyclic redundancy check (CRC) codes into the FEC cyclic test sequence.

9. A method for generating a test signal, comprising: Generate pseudo-random bit sequence PRBS; and A test signal is generated, the test signal comprising a repetition of a truncated portion of the PRBS, such that the period of the repetition is shorter than the period of the PRBS.

10. The method according to claim 9, wherein, Generating the test signal includes generating a sequence of groups, the sequence of groups including: (i) a repetition of a truncated portion of the PRBS used as a payload, and (ii) additional symbols.

11. The method according to claim 9 or 10, further comprising: In the receiver being tested: Receive and decode the test signal; A reference signal is generated, which is the same as the repetition of the truncated portion of the PRBS; and The performance of the receiver circuit is evaluated by comparing the reference signal with the test signal decoded by the receiver.

12. The method according to claim 11, wherein, Generating the reference signal includes generating a repetition of the truncated portion of the PRBS.

13. The method according to claim 11, wherein: The test signal includes additional symbols interwoven between the repetitions of the truncated portion of the PRBS; and The comparison with the reference signal includes omitting the additional symbols from the comparison with the reference signal.

14. A method for generating a test signal, comprising: Operate the encoder, which encodes the input data sequence using non-terminating forward error correction (FEC) codes; and A periodic FEC cyclic test sequence with a preset period length is generated. When the periodic FEC cyclic test sequence is repeatedly encoded by the encoder, a valid non-terminating encoded data stream is formed according to the FEC code.

15. The method according to claim 14, wherein, Each cycle of the FEC cyclic test sequence begins in the same state of the encoder.

16. The method according to claim 14 or 15, wherein, Generating the FEC cyclic test sequence includes inserting a cyclic redundancy check (CRC) code into the FEC cyclic test sequence.

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