Package substrates employing film substrates and external pre-impregnated (PPG) substrates to support high density bumps and wire bond connections, and related hybrid integrated circuit (IC) packages and methods of manufacture

Abstract

Hybrid package substrates that employ a film metallization layer with an external pre-impregnated (PPG) region to support high density bumps and wire bond connections of dies of corresponding bumps and wire bond connections in an IC package, as well as related hybrid integrated circuit (IC) packages and methods of manufacture are disclosed. The package substrate includes film metallization layers of softer flexible material that may be more easily patterned to support the formation of high density, reduced pitch metal interconnects to support finer bump pitch connections with a bottom first die in a die region of the package substrate. The package substrate also includes one or more PPG regions, the PPG metallization layer being adjacent to the die region of the package substrate, which enhances the film metallization layers and also supports the formation of wire bond pads to achieve a wire bond connection with an upper second die in the hybrid IC package.

Description

[0001] Priority Application

[0002] This application claims priority to U.S. Patent Application Serial No. 18 / 458,242, filed August 30, 2023, and entitled “PACKAGE SUBSTRATE EMPLOYING FILM SUBSTRATE AND AN OUTER PRE-IMPREGNATED (PPG) SUBSTRATE(S) TO SUPPORT HIGH DENSITY BUMP AND WIRE BOND CONNECTIONS, AND RELATED HYBRID INTEGRATED CIRCUIT (IC) PACKAGES AND FABRICATION METHODS,” which is incorporated by reference herein in its entirety. BACKGROUND

[0003] I. TECHNICAL FIELD

[0004] The field of the disclosure relates to integrated circuit (IC) packages, and more specifically to hybrid IC packages including stacked dies and electrically coupling respective lower and upper dies to a package substrate using bump and wire bond connections.

[0005] II. BACKGROUND

[0006] Integrated circuits (ICs) are the cornerstone of electronic devices. ICs are packaged in IC packages, also referred to as “semiconductor packages” or “chip packages.” An IC package includes one or more semiconductor dies that are the ICs, mounted on a package substrate and electrically coupled to the package substrate to provide physical support and electrical interface for the dies. The package substrate includes one or more metallization layers that include electrical traces (e.g., metal lines) with vertical interconnect vias (through-holes) that couple the electrical traces together between adjacent metallization layers to provide electrical interface between the dies. The dies are electrically connected to exposed metal interconnects in a top or outer layer of the package substrate to electrically couple the semiconductor dies to the electrical traces of the package substrate. The package substrate includes an outer metallization layer coupled to external metal interconnects (e.g., solder bumps) to provide an external interface between the dies in the IC package for mounting the IC package on a circuit board to connect the dies with other circuitry.

[0007] Some IC packages are referred to as“hybrid” IC packages, which include multiple dies for different purposes or applications. For example, a hybrid IC package can include a modem die as part of front-end circuitry to support a communication interface. The hybrid IC package can also include one or more memory dies that provide memory to support data storage and access by the modem die, such as for buffering and outgoing data to be modulated and / or demodulated data. Thus, in these hybrid IC packages, multiple dies are typically stacked on top of each other in a vertical direction in the IC package. The bottom-most die, which is directly adjacent to the package substrate of the IC package, is electrically coupled to metal interconnects in the upper metallization layer of the package substrate by die interconnects. For example, the die interconnects can include solder bumps or higher density ball grid array (BGA) interconnects (e.g., flip chip BGA (FCBGA)) as part of the die that couple to the metal interconnects in the package substrate to physically and electrically connect the bottom die to the package substrate. Other stacked dies, which are not directly adjacent to the package substrate of the IC package, can be electrically coupled to the upper metallization layer of the package substrate by wire bonds. Die-to-die (D2D) electrical connections can be made between the stacked dies through electrical connections formed in the metallization layer of the package substrate.

[0008] Importantly, the package substrate is manufactured to provide sufficient strength and stability to limit or avoid warping of the IC package in the hybrid IC package due to the increased height of the IC package due to the stacked dies. SUMMARY

[0009] Aspects disclosed herein include a package substrate that employs a film substrate and an external pre-impregnated (PPG) substrate to support high-density bump and wire bond connections of dies in an IC package. Related hybrid integrated circuit (IC) packages and methods of manufacture are also disclosed. The package substrate includes a film substrate having one or more film metallization layers each having a film insulating layer of a relatively soft flexible material that does not include a relatively hard reinforcing material such as a PPG material. As a result, the film insulating layer can be more easily patterned to support formation of high-density, reduced-pitch metal interconnects to support finer pitch bumping of higher-density dies. In this manner, the film metallization layers of the film substrate can support higher-density bumping connections with a first bottom die (e.g., flip-chip) having high-density bump connections (e.g., flip-chip ball grid array (FCBGA)). The softer material film insulating layer also supports compression bonding with the first bottom die. For example, the film metallization layers can be formed as an anisotropic conductive film (ABF) layer of a relatively soft polyimide material. The first bottom die can be coupled to first metal interconnects exposed from the external film metallization layers of the film substrate in a first die region of the package substrate to couple the first bottom die to the package substrate as part of a hybrid IC package. However, forming wire bond pads on the relatively soft material external film metallization layers of the film substrate to support wire bond connections with a second upper die of the package substrate in the hybrid IC package can not be feasible. This is due to material properties of the flexible, soft material used to form the film insulating layers in the film substrate can not support wire bonding techniques such as heat, pressure, and / or ultrasonic energy.

[0010] In this regard, in example aspects, to also support wire bond pads on the package substrate to support wire bond connections to a second upper die in the hybrid IC package, the package substrate also includes one or more PPG substrates in a second region of the film substrate that is outside of and laterally adjacent to the first die region of the package substrate. PPG substrates are substrates that include a reinforcing material, such as woven fiberglass or other fibers, that are impregnated in a resin matrix, such as epoxy, to provide a more robust, stronger, and less flexible substrate. The combination of resin and fibers can be partially cured or "pre-impregnated" prior to use in the manufacturing process. The PPG substrates include one or more PPG metallization layers coupled (e.g., formed) adjacent to the outer film metallization layers of the film substrate, where each PPG metallization layer includes a PPG insulating layer and a metal layer with metal interconnects. The PPG metallization layers not only reinforce the film metallization layers of the film substrate to increase strength and stability to reduce or minimize warpage, but also support the formation of wire bond pads in the second region adjacent to the first die region that can better withstand wire bonding techniques. In this regard, the wire bond pads can be formed as part of or in contact with the metal interconnects exposed from the outer PPG metallization layers in the PPG substrates to support wire bond connections between the second upper die of the hybrid IC package and its package substrate. The metal interconnects of the outer PPG metallization layers are coupled to the metal interconnects of the film metallization layers in the film substrate to facilitate electrical coupling of the second upper die to the film substrate of the package substrate. In this way, the package substrate is a hybrid substrate in that it includes a film substrate of softer material film metallization layers to support finer pitch metal interconnects for finer pitch bumps to connect to the first bottom die in the first die region, but also includes PPG substrates of PPG metallization layers in a second region outside of the die region to provide strength and stability to the film substrate and support wire bond pads for wire bond connections to the second upper die.

[0011] In this regard, in one example aspect, a package substrate is provided. The package substrate includes a first substrate including a first film metallization layer including a first surface and extending in a first direction. The first film metallization layer includes a first film insulating layer and a first metal layer including: a plurality of first metal interconnects exposed from the first surface in a first region of the first film metallization layer; and a plurality of second metal interconnects exposed from the first surface in a second region of the first film metallization layer adjacent the first region in the first direction. The package substrate also includes a second substrate including a first PPG metallization layer adjacent the first surface in the second region. The first PPG metallization layer includes a second surface and a second insulating layer including a PPG material and a second metal layer including: a plurality of first metal pads exposed from the second surface.

[0012] In another example aspect, a method of fabricating a package substrate is provided. The method includes forming a first substrate including forming a first film metallization layer including a first surface and extending in a first direction, forming the first film metallization layer including: forming a first film insulating layer; forming a first metal layer; forming a plurality of first metal interconnects in the first metal layer exposed from the first surface in a first region of the first film metallization layer; and forming a plurality of second metal interconnects in the first metal layer exposed from the first surface in a second region of the first film metallization layer adjacent the first region in the first direction. The method also includes forming a second substrate including forming a first PPG metallization layer having a second surface, forming the first PPG metallization layer including: forming a second insulating layer including a PPG material; forming a second metal layer; and forming a plurality of first metal pads from the second metal layer exposed from the second surface. The method further includes coupling the second substrate to the first substrate in the second region of the first film metallization layer in a second direction orthogonal to the first direction.

[0013] In another example aspect, an IC package is provided. The IC package includes a package substrate. The package substrate includes a first substrate including a first film metallization layer including a first surface and extending in a first direction. The first film metallization layer includes a first film insulating layer and a first metal layer including: a plurality of first metal interconnects exposed from the first surface in a first region of the first film metallization layer; and a plurality of second metal interconnects exposed from the first surface in a second region of the first film metallization layer adjacent the first region in the first direction. The package substrate further includes a second substrate including a first PPG metallization layer adjacent the first surface in the second region. The first PPG metallization layer includes a second surface and a second insulating layer including a PPG material and a second metal layer including: a plurality of first metal pads exposed from the second surface. The IC package further includes a first die including a plurality of die interconnects each connected to a first metal interconnect of the plurality of first metal interconnects. The IC package further includes a second die adjacent the first die such that the first die is between the second die and the package substrate in a second direction orthogonal to the first direction. The IC package further includes a plurality of wire bonds each connected to the second die and a first metal pad of the plurality of first metal pads. BRIEF DESCRIPTION OF DRAWINGS

[0014] FIG. 1A and FIG. 1B are side and close-up partial side views, respectively, of an example hybrid integrated circuit (IC) package including a cored package substrate including: a film substrate having one or more film metallization layers to support higher density bump pitch to enable die connections with a first bottom die in a first die region of the film substrate; and a pre-preg (PPG) substrate of one or more PPG metallization layers in a second region of the film substrate outside the die region to reinforce the film substrate and support wire bond connections with a second upper die in the hybrid IC package;

[0015] FIG. 1C is a side view of the hybrid IC package in FIG. 1A

[0016] FIG. 1D is a top view of the hybrid IC package in FIG. 1A ​​

[0017] FIG. 1E is FIG. 1A a top view of a hybrid IC package in

[0018] FIG. 2A and FIG. 2B are, respectively, a side view and a close-up partial side view of an example hybrid IC package including a coreless package substrate including a film substrate having one or more film metallization layers to support a higher density of bump pitch to enable die connections to a first bottom die in a first die area in the film substrate and a PPG substrate of one or more PPG metallization layers in a second area of the film substrate outside the die area to reinforce the film substrate and support wire bond connections to a second upper die in the hybrid IC package;

[0019] FIG. 2C is FIG. 2A a side view of a hybrid IC package in

[0020] FIG. 2D is FIG. 2A a top view of a hybrid IC package in

[0021] FIG. 2E is FIG. 2A a top view of a hybrid IC package in

[0022] FIG. 3A and FIG. 3B is a flowchart illustrating an example manufacturing process of manufacturing a package substrate including a film substrate having one or more film metallization layers to support a higher density of bump pitch to enable die connections to a first bottom die in a first die area in the film substrate and a PPG substrate of one or more PPG metallization layers in a second area of the film substrate outside the die area to reinforce the film substrate and support wire bond connections to a second upper die in the hybrid IC package, including but not limited to FIG. 1A through FIG. 1E and FIG. 2A through FIG. 2E a package substrate in

[0023] FIG. 4A through FIG. 4Dis a flowchart illustrating another exemplary manufacturing process of a core-in-package substrate including a film substrate with one or more film metallization layers to support higher density bump pitch to enable die connections to a first bottom die in a first die area in the film substrate and a PPG substrate with one or more PPG metallization layers in a second area of the film substrate outside the die area to reinforce the film substrate and support wire bond connections to a second upper die in a hybrid IC package, including but not limited to FIG. 1A through FIG. 1E ,

[0024] FIG. 5A through FIG. 5H is an exemplary manufacturing stage during manufacturing of a core-in-package substrate according to the manufacturing process in FIG. 4A through FIG. 4D ,

[0025] FIG. 6A through FIG. 6C is a flowchart illustrating another exemplary manufacturing process of a core-in-package substrate including a film substrate with one or more film metallization layers to support higher density bump pitch to enable die connections to a first bottom die in a first die area in the film substrate and a PPG substrate with one or more PPG metallization layers in a second area of the film substrate outside the die area to reinforce the film substrate and support wire bond connections to a second upper die in a hybrid IC package, including but not limited to FIG. 2A through FIG. 2E ,

[0026] FIG. 7A through FIG. 7F is an exemplary manufacturing stage during manufacturing of a core-in-package substrate according to the manufacturing process in FIG. 6A through FIG. 6C ,

[0027] FIG. 8 is a block diagram of an exemplary wireless communication device including a radio frequency (RF) assembly that can include a hybrid IC package including a package substrate including a film substrate with one or more film metallization layers to support higher density bump pitch to enable die connections to a first bottom die in a first die area in the film substrate and a PPG substrate with one or more PPG metallization layers in a second area of the film substrate outside the die area to reinforce the film substrate and support wire bond connections to a second upper die in a hybrid IC package, including but not limited to FIG. 1A through FIG. 1E , FIG. 2A through FIG. 2E , FIG. 5G and FIG. 5H and FIG. 7E and FIG. 7F and can be manufactured according to the exemplary manufacturing processes in FIG. 3A through FIG. 3B , FIG. 4A through FIG. 4D and FIG. 6A through FIG. 6C ; and

[0028] FIG. 9 is a block diagram of an exemplary processor-based system that can include a plurality of components that can include a hybrid IC package that includes a package substrate that includes a film substrate with one or more film metallization layers to support higher density bump pitch to enable die connections with a first bottom die in a first die area in the film substrate and a PPG substrate of one or more PPG metallization layers in a second area of the film substrate outside of the die area to reinforce the film substrate and support wire bond connections with a second upper die in the hybrid IC package, including but not limited to FIG. 1A through FIG. 1E 、 FIG. 2A through FIG. 2E 、 FIG. 5G and FIG. 5H and FIG. 7E and FIG. 7F package substrates and associated IC packages and can be manufactured according to FIG. 3A through FIG. 3B 、 FIG. 4A through FIG. 4D and FIG. 6A through FIG. 6C exemplary manufacturing processes. DETAILED DESCRIPTION

[0029] Reference now will be made to several exemplary aspects of the disclosure. The word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects.

[0030] Aspects disclosed herein include a package substrate that employs a film substrate and an external pre-impregnated (PPG) substrate to support high-density bump and wire bond connections of dies in an IC package. Related hybrid integrated circuit (IC) packages and methods of manufacture are also disclosed. The package substrate includes a film substrate having one or more film metallization layers each having a film insulating layer of a relatively soft flexible material that does not include a relatively hard reinforcing material such as PPG. As a result, the film insulating layer can be more easily patterned to support formation of high-density, reduced-pitch metal interconnects to support finer pitch bumping of higher-density dies. In this manner, the film metallization layers of the film substrate can support higher-density bumping connections with a first bottom die (e.g., flip-chip) having high-density bump connections (e.g., flip-chip ball grid array (FCBGA)). The softer material film insulating layer also supports compression bonding with the first bottom die. For example, the film metallization layers can be formed as an anisotropic conductive film (ABF) layer of a relatively soft polyimide material. The first bottom die can be coupled to first metal interconnects exposed from the external film metallization layers of the film substrate in a first die region of the package substrate to couple the first bottom die to the package substrate as part of a hybrid IC package. However, forming wire bond pads on the relatively soft material external film metallization layers of the film substrate to support wire bond connections with a second upper die of the package substrate in the hybrid IC package can not be feasible. This is due to material properties of the flexible, soft material used to form the film insulating layers in the film substrate can not support wire bonding techniques such as heat, pressure, and / or ultrasonic energy.

[0031] In this regard, in example aspects, to also support wire bond pads on the package substrate to support wire bond connections to a second upper die in the hybrid IC package, the package substrate also includes one or more PPG substrates in a second region of the film substrate that is outside of and laterally adjacent to the first die region of the package substrate. The PPG substrate is a substrate that includes a reinforcing material, such as woven fiberglass or other fibers, that is impregnated in a resin matrix, such as epoxy, to provide a more robust, stronger, and less flexible substrate. The combination of resin and fibers can be partially cured or "pre-impregnated" prior to use in the manufacturing process. The PPG substrate includes one or more PPG metallization layers coupled (e.g., formed) adjacent to the outer film metallization layers of the film substrate, where each PPG metallization layer includes a PPG insulating layer and a metal layer with metal interconnects. The PPG metallization layers not only reinforce the film metallization layers of the film substrate to increase strength and stability to reduce or minimize warpage, but also support the formation of wire bond pads in the second region adjacent to the first die region that can better withstand wire bonding techniques. In this regard, the wire bond pads can be formed as part of or in contact with the metal interconnects exposed from the outer PPG metallization layers in the PPG substrate to support wire bond connections between the second upper die of the hybrid IC package and its package substrate. The metal interconnects of the outer PPG metallization layers are coupled to the metal interconnects of the film metallization layers in the film substrate to facilitate electrical coupling of the second upper die to the film substrate of the package substrate. In this way, the package substrate is a hybrid substrate in that it includes a film substrate of softer material film metallization layers to support finer pitch metal interconnects for finer pitch bumps to connect to the first bottom die in the first die region, but also includes a PPG substrate of PPG metallization layers in a second region outside of the die region to provide strength and stability to the film substrate and support wire bond pads for wire bond connections to the second upper die.

[0032] In this regard, FIG. 8 and FIG. 8These are, respectively, a side view and a close-up partial side view of an exemplary hybrid IC package 100 (also referred to as "IC package 100"), which includes a package substrate 102, the package substrate including a first film substrate 104. The film substrate 104 is a substrate formed of one or more film insulating layers, which are stacked on top of each other during manufacturing to form corresponding metallization layers. In contrast to other types of insulating layers used in package substrates, such as laminated substrates comprising insulating layers formed separately and then laminated together, the film insulating layers may have reduced height or thickness that is available through additive manufacturing processes. As discussed in more detail below, the film substrate 104 of the package substrate 102 includes a plurality of film metallization layers 106(1)-106(8) to support a higher density bump pitch, thereby enabling die connection to a first bottom die 108(1) in a first die region 110(1) of the film substrate 104. The metallization layers 106(1)-106(8) extend in a first horizontal direction (X-axis direction and / or Y-axis direction). A “membrane” metallization layer refers to a metallization layer made of one or more membrane insulating layers of a dielectric material (e.g., plastic, polymer, ceramic) that is set as a membrane on a surface during manufacturing and then processed. A “membrane insulating layer” refers to a layer that is a sheet or coating of a dielectric insulating material, set as a layer on a surface and then processed. The first outer metallization layer 106(1) has a membrane insulating layer, which may be a thin film and made of a softer, more flexible material. For example, the first outer metallization layer 106(1) and any other metallization layers 106(2)-106(8) may be formed as an Ajinomoto stacked film (ABF) layer of a softer polyimide material. In this way, the first outer metallization layer 106(1) can support patterning of the first outer metallization layer 106(1) during manufacturing to support a higher density bump pitch. The packaging substrate 102 of the IC package 100 can support a first bottom die 108(1) with high-density die connectors. For example, the first bottom die 108(1) can be a flip chip (FC) with high-density bump connectors (e.g., FC ball grid array (BGA) (FCBGA)). The softer material of the first outer film metallization layer 106(1) can also better support compression bonding with the first bottom die 108(1).

[0033] Furthermore, as discussed in more detail below, FIG. 8The packaging substrate 102 in the IC package 100 also includes a first PPG substrate 112 (1) to better support wire bonding between the second upper die 108 (2) of the IC package 100 and the packaging substrate 102. The PPG substrate is a substrate comprising a reinforcing material (such as woven glass fiber or other fibers) impregnated in a resin matrix (such as epoxy resin) to provide a more robust, stronger, and less flexible substrate. The combination of resin and fibers may be partially cured or “pre-impregnated” prior to use in the manufacturing process. The second upper die 108 (2) is stacked on or adjacent to the first bottom die 108 (1) in a second vertical direction (Z-axis direction). As an example, the second upper die 108 (2) may be directly coupled or bonded to the first bottom die 108 (1). As another example, the second upper die 108 (2) may be indirectly coupled to the first bottom die 108 (1) via an intermediate layer 109 (such as an adhesive layer). Both the first bottom die 108(1) and the second top die 108(2) are surrounded by a mold layer 113. The first PPG substrate 112(1) includes a first PPG metallization layer 114(1) extending in a first horizontal direction (X-axis and / or Y-axis direction) and made of a more robust PPG material, such as a dielectric material impregnated with glass fiber. Therefore, the first PPG substrate 112(1) is able to support wire bonding connections with the second top die 108(2) better than the film substrate 104, because the material properties of the flexible, softer material used to form the first outer film metallization layer 106(1) may not support wire bonding techniques such as heat, pressure, and / or ultrasonic energy. The first PPG substrate 112(1) also reinforces the first outer film metallization layer 106(1) of the film substrate 104 to enhance and increase the strength of the film substrate 104, thereby increasing the stability of the encapsulation substrate 102 to reduce or minimize warpage. In this example, as discussed in more detail below, the first PPG metallization layer 114(1) of the first PPG substrate 104(1) is coupled to the first outer metallization layer 106(1) of the film substrate 104 in a second region 110(2) of the film substrate 112. This second region is outside the first die region 110(1) of the film substrate 104 and is laterally adjacent to the first die region of the film substrate in a first horizontal direction (X-axis and / or Y-axis direction). In this way, the first bottom die 108(1) has an unobstructed path to be directly coupled to the first outer metallization layer 106(1) of the film substrate 104 to provide signal routing between the first bottom die 108(1) and the packaging substrate 102. However, the first PPG substrate 112(1) supports metal pads that are supported by wire bonding connections through wire bonding members 116(1) and 116(2) between the first PPG substrate 112(1) and the film substrate 104, and the second upper die 108(2) in the IC package 100.

[0034] In this way, FIG. 9 The encapsulation substrate 102 is a hybrid substrate because it includes a film substrate 104 with a first outer film metallization layer 106(1) (and / or other film metallization layers 106(2)-106(8)) of a softer material to support finer pitch metal interconnects for finer bump pitch to enable connection to the first bottom die 108(1) in the first die region 110(1). However, including a first PPG substrate 112(1) on the film substrate 104 in the second region 110(2) better supports the metal pads for forming wire bonding connectors 116(1), 116(2), while also providing strength and additional stability to the film substrate 104. In this example, the film substrate 104 also includes a core layer 117, which provides strength and stability to the film substrate 104. However, including the first PPG substrate 112(1) provides additional strength and support to the film substrate 104.

[0035] FIG. 1A through FIG. 1E yes FIG. 2A through FIG. 2E A close-up partial side view of the IC package 100. (Reference) FIG. 5G In this example, each of the membrane metallization layers 106(1)-108(8) has a corresponding membrane insulating layer 118(1)-118(8) of a dielectric material (e.g., plastic, polymer, ceramic) that has insulating properties and is disposed as a membrane on a surface during manufacturing and then processed. A “membrane insulating layer” refers to a layer that is a sheet or coating of dielectric insulating material disposed as a layer on a surface and then processed to a desired thickness and metallized. In this example, the membrane insulating layers 118(1)-118(8) are thinner layers of a first thickness indicated by height H1 in a second vertical direction (Z-axis direction) orthogonal to a first horizontal direction (X-axis and / or Y-axis direction) and are made of a softer material membrane (such as polyimide). For example, the first thickness of the membrane insulating layers 118(1)-118(8) indicated by height H1 may be between fifteen (15) μm and thirty (30) μm. As another example, the elastic modulus of the insulating film layers 118(1)-118(8) can be between five (5) gigapascals (GPa) and twenty (20) GPa. For example, the insulating film layers 118(1)-118(8) can be formed to manufacture a film substrate 104 (as an additive process), wherein each insulating film layer 118(1)-118(8) is formed and then processed to form its corresponding metallization layer 106(1)-106(8), and then another insulating film layer 118(1)-118(8) is deposited and processed on the last manufactured metallization layer 106(1)-106(8).

[0036] Continue to refer toFIG. 5H In this example, each of the metallization layers 106(1)-106(8) further includes a corresponding metal layer 120(1)-120(8), which is disposed on or partially or completely embedded in the corresponding insulating layer 118(1)-118(8). The metal layer is a layer of metal material that is then processed to form a metal interconnect (e.g., a metal trace, a metal wire). In this example, each of the metal layers 120(1)-120(8) has a corresponding metal interconnect 122(1)-122(8), which is formed in the metal layers 120(1)-120(8) due to the manufacturing and patterning process of the metal layers 120(1)-120(8). Metal interconnects 122(1)-122(8) are exposed from the respective first outer surfaces 124(1)-124(8) of the film insulating layers 118(1)-118(8). In this example, the first metal interconnect 122(1)(1) is exposed from the first outer surface 124(1) of the first outer film insulating layer 118(1) in the first die region 110(1) of the film substrate 104 for coupling to the first bottom die 108(1), as shown. FIG. 7E As shown. This is also... FIG. 7F Reference in the top view of IC package 100 FIG. 3A through FIG. 3B A side view of the IC package 100 is shown. Furthermore, in this example, as... FIG. 4A through FIG. 4D As shown, the first metal interconnect 122(1)(2) is exposed from the first outer surface 124(1) of the first outer film insulating layer 118(1) in the second region 110(2) of the film substrate 104 for coupling to the first PPG substrate 112(1). In this way, the die interconnect 123 of the first bottom die 108(1) (as shown) FIG. 6A through FIG. 6C and FIG. 8 (As shown) can be coupled to the film substrate 104 for signal routing in the first die region 110(1) without obstruction by the first PPG substrate 112(1) to support the reduced bump pitch through the reduced first pitch P1 of the metal interconnects 122(1)(1) in the first die region 110(1). For example, the first pitch P1 of the metal interconnects 122(1)(1) in the first outer film metallization layer 106(1) in the first die region 110(1) can be less than or equal to five (5) micrometers (μm).

[0037] Continue to refer to FIG. 8The first PPG metallization layer 114(1) is adjacent to the first surface 124(1) of the film metallization layer 106(1) of the film substrate 104. In this example, the first PPG metallization layer 114(1) also includes a corresponding first metal layer 130(1) disposed on or partially or completely embedded in the first PPG insulating layer 132(1). In this example, the first metal layer 130(1) has a corresponding first metal pad 134(1) formed in the first metal layer 130(1) due to the manufacturing and patterning process of the first metal layer 130(1). The first metal pad 134(1) is exposed from the corresponding first outer surface 136(1) of the first PPG insulating layer 132(1) made of PPG material. As an example, the elastic modulus of the first PPG insulating layer 132(1) can be between fourteen (14) gigapascals (GPa) and twenty-five (25) GPa, and is greater than the elastic modulus of the first film insulating layer 118(1). In this example, the first PPG insulating layer 132(1) has a second thickness in the second vertical direction (Z-axis direction) as indicated by the height H2. The first PPG insulating layer 132(1) can have a second thickness H2 between fifteen (15) μm and forty-five (45) μm. The ratio of the second thickness H2 of the first PPG insulating layer 132(1) to the first thickness H1 of the first outer film insulating layer 118(1) can be at least 1.5.

[0038] like FIG. 8 As shown, in this example, the first metal pad 134(1) is exposed from the first outer surface 136(1) of the first PPG metallization layer 114(1) in the second region 110(2) of the film substrate 104 to support the ability to couple the first metal pad 134(1) to wire bonds 116(1), 116(2) for coupling to the second upper die 108(2). This is in FIG. 9 Reference in the top view of IC package 100 FIG. 1A through FIG. 1EA side view of the IC package 100 is shown. In this way, the second upper die 108(2) can be coupled to the first PPG substrate 112(1), which in turn is coupled to the film substrate 104 for signal routing in the second region 110(2) without obstruction by the first bottom die 108(1). The second pitch P2 of the first metal pads 134(1) in the first PPG metallization layer 114(1) may be widened relative to the pitch of the metal interconnects 122(1) in the first outer film metallization layer 106(1) because the multiple wire bonds 116(1), 116(2) may not require reduced pitch connections. For example, the second pitch P2 of the first metal pads 134(1) in the first PPG metallization layer 114(1) may be 150 (150) μm. A first metal pad 134(1) is exposed from a first solder mask 139(1) disposed on a first PPG substrate 112(1) and patterned with a first opening 141(1) during the manufacture of the IC package 100.

[0039] It should be noted that although the above example is discussed with regard to the reduced first pitch P1 of the metal interconnects 122(1)(1) in the first external film metallization layer 106(1) in the first die region 110(1), the metal interconnects 122(1)(2) in the first external film metallization layer 106(1) in the second region 110(2) can also be formed with a reduced first pitch P1. As another example, the metal interconnects 122(2)-122(8) in other film metallization layers 106(2)-106(8) can also be formed with a reduced first pitch P1 or a second pitch P2 as needed. It should also be noted that although the first PPG substrate 112(1) in the IC package 100 includes only one PPG metallization layer, the first PPG substrate 112(1) may be provided with multiple stacked PPG metallization layers.

[0040] like FIG. 2A through FIG. 2EAs shown, in order to provide a signal routing path between the wire bonds 116(1), 116(2) of the first metal pad 134(1) coupled to the first PPG substrate 112(1) and the film substrate 104, the first PPG metallization layer 114(1) has a first via 138(1) that couples the first metal pad 134(1) to the first outer film metallization layer 106(1). In this way, the via 140(1) in the first outer film metallization layer 106(1) and coupled to the metal interconnect 122(1) can extend the signal routing path from the first PPG substrate 112(1) to the other film metallization layers 106(2)-106(8) of the film substrate 104 through the vias 140(2)-140(8) to interconnect the metal interconnects 122(2)-122(8) in the adjacent film metallization layers 106(2)-106(8). In this example, core layer 117 includes metal pillars 144 extending from a fourth metallization layer 106(4) to a fifth metallization layer 106(5) to provide signal routing paths between coupled metal interconnects 122(4), 122(5) in these layers. These signal routing paths can provide die-to-die (D2D) connections from a second upper die 108(2) to a first bottom die 108(1) via connections through a first PPG substrate 112(1) and a film substrate 104. These signal routing paths can also provide external routing paths for the second upper die 108(2) and the first bottom die 108(1) to external interconnects 142 of the IC package 100.

[0041] In addition, such as FIG. 5G and 1B As shown, in this example, a second PPG substrate 112 (2) may also be included in the packaging substrate 102 and coupled to the film metallization layer 106 (8) of the film substrate 104 to further enhance the film substrate 104 and the packaging substrate 102. The second PPG substrate 112 (2) has a second PPG metallization layer 114 (2) having a second PPG insulating layer 132 (2) having a second via 138 (2) that couples the second metal pad 134 (2) to the metal interconnect 122 (8) of the film metallization layer 106 (8). In this way, the via 140 (8) in the film metallization layer 114 (8) and coupled to the metal interconnect 122 (8) can extend signal routing paths from the first PPG substrate 106 (1) and the film substrate 104 to the second PPG metallization layer 112 (2) and to the external interconnect 142. A second solder mask layer 139(2) is disposed on a second PPG metallization layer 114(2), wherein a second opening 141(2) is formed to expose a second metal pad 134(2) and couple the second metal pad 134(2) to an external interconnect 142.

[0042] FIG. 5H and FIG. 7E These are a side view and a close-up partial side view of an exemplary hybrid IC package 200 (referred to as "IC package 200"), which is similar to... FIG. 7F The IC package 100 is different from the film substrate 104, which is a coreless substrate. FIG. 3A through FIG. 3B and FIG. 4A through FIG. 4D The packaging substrate 202 and FIG. 6A through FIG. 6C Common components among the packaging substrates 100 are shown by common component numbers and are not described further.

[0043] In this respect, FIG. 9 and FIG. 9 These are a side view and a close-up partial side view of an exemplary hybrid IC package 200 (also referred to as "IC package 200"), which includes a package substrate 202 including a first film substrate 204. In this example, the film substrate 204 is coreless. The film substrate 204 is a substrate formed of one or more film insulating layers, which are stacked on top of each other during manufacturing to form corresponding metallization layers. In contrast to other types of insulating layers used in package substrates, such as laminated substrates comprising insulating layers formed separately and then laminated together, the film insulating layers may have reduced height or thickness that is available through an additive manufacturing process. The film substrate 204 of the package substrate 202 includes film metallization layers 106(1)-106(3), 106(8) to support a higher density bump pitch, thereby enabling die connection to a first bottom die 108(1) in a first die region 110(1) of the film substrate 204.

[0044] also, FIG. 9 The IC package 200 includes a packaging substrate 202 comprising a first PPG substrate 112 (1) to better support wire bonding between the second upper die 108 (2) of the IC package 200 and the packaging substrate 202. A first PPG metallization layer 114 (1) of the first PPG substrate 204 (1) is coupled in a second region 110 (2) of the film substrate 112 to a first outer film metallization layer 106 (1) of the film substrate 204. This second region is outside the first die region 110 (1) of the film substrate 204 and is laterally adjacent to the first die region of the film substrate in a first horizontal direction (X-axis and / or Y-axis direction). In this way, the first bottom die 108 (1) has unobstructed access to be directly coupled to the first outer film metallization layer 106 (1) of the film substrate 204 to provide signal routing between the first bottom die 108 (1) and the packaging substrate 202.

[0045] FIG. 1A through FIG. 1E yesFIG. 2A through FIG. 2E A close-up partial side view of the IC package 200. (See attached image.) FIG. 4A through FIG. 4D As shown, metal layers 120(1)-120(3), 120(8) are disposed on, or partially or completely embedded in, the respective film insulating layers 118(1)-118(3), 118(8). In this example, each of the metal layers 120(1)-120(3), 120(8) has a corresponding metal interconnect 122(1)-124(3), 122(8), which is formed in the metal layers 120(1)-120(3), 120(8) due to the manufacturing and patterning process of the metal layers 120(1)-120(3), 120(8). This also FIG. 1A through FIG. 1E Reference in the top view of IC package 200 FIG. 5A through FIG. 5H A side view of the IC package 200 is shown. Furthermore, in this example, as... FIG. 4A through FIG. 4D As shown, the first metal interconnect 122(1)(2) is exposed from the first outer surface 124(1) of the first outer film insulating layer 118(1) in the second region 110(2) of the film substrate 204 for coupling to the first PPG substrate 112(1). In this way, the die interconnect 123 of the first bottom die 108(1) (as shown) FIG. 1A through FIG. 1E and FIG. 5A through FIG. 5H (As shown) can be coupled to the film substrate 204 for signal routing in the first die region 110(1) without obstruction by the first PPG substrate 112(1) to support the reduced bump pitch through the reduced first pitch P1 of the metal interconnects 122(1)(1) in the first die region 110(1).

[0046] like FIG. 5A As shown, in this example, the metal pad 134(1) is exposed from the first outer surface 136(1) of the first PPG metallization layer 114(1) in the second region 110(2) of the film substrate 204 to support the ability to couple the metal pad 134(1) to wire bonds 116(1), 116(2) for coupling to the second upper die 108(2). This is in FIG. 4A Reference in the top view of IC package 200 FIG. 1AA side view of the IC package 200 is shown. In this way, the second upper die 108(2) can be coupled to the first PPG substrate 112(1), which in turn is coupled to the film substrate 204 for signal routing in the second region 110(2) without obstruction by the first bottom die 108(1). The second pitch P2 of the metal pads 134(1) in the first PPG metallization layer 114(1) may be relaxed relative to the pitch of the metal interconnects 122(1) in the first outer film metallization layer 106(1) because the multiple wire bonds 116(1), 116(2) may not require reduced pitch connections.

[0047] It should be noted that although the above example is discussed in relation to the reduced first pitch P1 of the metal interconnects 122(1)(1) in the first external film metallization layer 106(1) in the first die region 110(1), the metal interconnects 122(1)(2) in the first external film metallization layer 106(1) in the second die region 110(2) can also be formed with a reduced first pitch P1. As another example, the metal interconnects 122(2), 122(3), 122(8) in other film metallization layers 106(2), 106(3), 106(8) can also be formed by a reduced first pitch P1 or a second pitch P2 as needed. It should also be noted that although the first PPG substrate 112(1) in the IC package 200 includes only one PPG metallization layer, the first PPG substrate 112(1) may be provided with multiple stacked PPG metallization layers.

[0048] like FIG. 1BAs shown, in order to provide a signal routing path between the wire bonds 116(1), 116(2) of the metal pads 134(1) coupled to the first PPG substrate 112(1) and the film substrate 204, the first PPG metallization layer 114(1) has a first via 138(1) that couples the metal pads 134(1) to the first outer film metallization layer 106(1). In this way, vias 140(1) in the first outer metallization layer 106(1) and coupled to the metal interconnects 122(1) can extend signal routing paths from the first PPG substrate 112(1) to the other metallization layers 106(2)-106(3), 106(8) of the film substrate 204 through vias 140(2)-140(4) of the metal interconnects 122(2)-106(3), 122(8) in the adjacent metallization layers 106(2)-106(3), 122(8). These signal routing paths can provide die-to-die (D2D) connections from the second upper die 108(2) to the first bottom die 108(1) through the connection through the first PPG substrate 112(1) and the film substrate 204. These signal routing paths can also provide external routing paths for the second upper die 108(2) and the first bottom die 108(1) to the external interconnect 142 of the IC package 100.

[0049] In addition, such as FIG. 5B and FIG. 4A As shown, in this example, the second PPG substrate 112 (2) may also be included in the packaging substrate 202 and coupled to the film metallization layer 106 (8) of the film substrate 204 to further enhance the film substrate 204 and the packaging substrate 202. The second PPG substrate 112 (2) has a second PPG metallization layer 114 (2) having a second PPG insulating layer 132 (2) having a second via 138 (2) that couples the second metal pad 134 (2) to the metal interconnect 122 (8) of the film metallization layer 106 (8). In this way, the via 140 (8) in the film metallization layer 114 (8) and coupled to the metal interconnect 122 (8) can extend the signal routing path from the first PPG substrate 106 (1) and the film substrate 204 to the second PPG metallization layer 112 (2) and to the external interconnect 142. A second solder mask layer 139(2) is disposed on a second PPG metallization layer 114(2), wherein a second opening 141(2) is formed to expose a second metal pad 134(2) and couple the second metal pad 134(2) to an external interconnect 142.

[0050] The packaging substrate can be manufactured in different manufacturing processes. The packaging substrate includes: a film substrate having one or more film metallization layers to support higher density bump spacing for die connection to a first bottom die in a first die region of the film substrate; and a PPG substrate with one or more PPG metallization layers in a second region of the film substrate outside the die region to enhance the film substrate and support lead bonding connections to a second upper die in a hybrid IC package, including but not limited to: FIG. 1A and FIG. 5C The packaging substrate and associated IC package.

[0051] In this respect, FIG. 4B and FIG. 5D This is a flowchart illustrating an exemplary manufacturing process 300 for manufacturing a package substrate, the package substrate including: a film substrate having one or more film metallization layers to support higher density bump spacing for die connection to a first bottom die in a first die region of the film substrate; and a PPG substrate with one or more PPG metallization layers in a second region of the film substrate outside the die region to enhance the film substrate and support lead bonding connection to a second upper die in a hybrid IC package, including but not limited to... FIG. 4B and FIG. 5E The packaging substrate and associated IC packages will be combined in manufacturing. FIG. 4C Discussion of the packaging substrate 102 FIG. 5F and FIG. 4C The manufacturing process is described in 300, but note that this is not limiting. FIG. 4C and FIG. 5G The manufacturing process 300 can be used to manufacture other packaging substrates, including: a film substrate having one or more film metallization layers to support higher density bump spacing for die connection to a first bottom die in a first die region of the film substrate; and a PPG substrate with one or more PPG metallization layers in a second region of the film substrate outside the die region to enhance the film substrate and support lead bonding connections to a second top die in a hybrid IC package, including but not limited to: FIG. 4D The packaging substrate 202 in the middle.

[0052] In this respect, the first step of manufacturing process 300 in the process of manufacturing the packaging substrate 102 includes forming a first substrate 104 ( FIG. 4D (Frame 302 in the middle). Forming the first substrate 104 includes forming a first metallization layer 106 (1), the first metallization layer including a first surface 124 (1) and extending in a first direction (X-axis and / or Y-axis direction). FIG. 5G (in frame 304). Forming the first film metallization layer 106(1) includes: forming the first film insulating layer 118(1).FIG. 4D (in the frame 306); forming the first metal layer 120(1) ( FIG. 6A through FIG. 6C (in frame 308); a plurality of first metal interconnects 122(1)(1) are formed in the first metal layer 120(1), the plurality of first metal interconnects being exposed from the first surface 124(1) in the first region 110(1) of the first film metallization layer 106(1). FIG. 2A through FIG. 2E (in the frame 310); and a plurality of second metal interconnects 122(1)(2) are formed in the first metal layer 120(1), the plurality of second metal interconnects being exposed from the first surface 124(1) in the second region 110(2) adjacent to the first region 110(1) in the first direction (X-axis and / or Y-axis direction) of the first film metallization layer 106(1). FIG. 7A through FIG. 7F (Box 312 in the middle).

[0053] refer to FIG. 6A through FIG. 6C The manufacturing process 300, which forms the packaging substrate 102, also includes forming a second substrate 112 (1). FIG. 2A through FIG. 2E (Frame 314 in the middle). Forming the second substrate 112(1) includes forming a first PPG metallization layer 114(1) having a second surface 136(1). FIG. 7A through FIG. 7F (Frame 316 in the middle). Forming the first PPG metallization layer 114(1) includes: forming a second insulating layer 132(1), the second insulating layer comprising PPG material ( FIG. 7A (in frame 318); forming a second metal layer 130(1) ( FIG. 6A (in the frame 320); and a plurality of first metal pads 134(1) are formed from the second metal layer 130(1), the plurality of first metal pads being exposed from the second surface 136(1) ... FIG. 2A (See box 322 in the image). Forming the encapsulation substrate 102 further includes: coupling the second substrate 112(1) to the first substrate 104 in a second region 110(2) of the first film metallization layer 106(1) in a second direction (Z-axis direction) orthogonal to the first direction (X-axis and / or Y-axis direction). FIG. 2B (Box 324 in the middle).

[0054] Other manufacturing processes can also be used to manufacture the package substrate, which includes: a film substrate having one or more film metallization layers to support higher density bump spacing for die connection to a first bottom die in a first die region of the film substrate; and a PPG substrate with one or more PPG metallization layers in a second region of the film substrate outside the die region to enhance the film substrate and support lead bonding connection to a second upper die in a hybrid IC package, including but not limited to: FIG. 7B and FIG. 6A The packaging substrate and associated IC package.

[0055] In this respect, FIG. 2A This is a flowchart illustrating another exemplary manufacturing process 400 for manufacturing a chip-based package substrate, the chip-based package substrate comprising: a film substrate having one or more film metallization layers to support higher density bump spacing for die connection to a first bottom die in a first die region of the film substrate; and a PPG substrate with one or more PPG metallization layers in a second region of the film substrate outside the die region to enhance the film substrate and support lead bonding connection to a second upper die in a hybrid IC package, including but not limited to... FIG. 7B The packaging substrate 102 and the associated IC package 100 are included. FIG. 6A It is based on FIG. 7C Exemplary manufacturing stages 500A-500H during the manufacturing of the packaging substrate in manufacturing process 400. (See reference...) FIG. 6B The discussion of the core-packaged substrate 102 is as follows: FIG. 7D Manufacturing process 400 is shown in manufacturing stages 500A-500H. However, it should be noted that manufacturing process 400 can be used to manufacture another cored package substrate, which includes: a film substrate having one or more film metallization layers to support higher density bump spacing to achieve die connection with a first bottom die in a first die region in the film substrate; and a PPG substrate with one or more PPG metallization layers in a second region of the film substrate outside the die region to enhance the film substrate and support lead bonding connection with a second top die in a hybrid IC package.

[0056] In this respect, such as FIG. 6B As shown in manufacturing stage 500A, the first exemplary step of manufacturing process 400 is to provide film substrate 104 ( FIG. 7E (Box 402 in the previous section). As previously mentioned FIG. 6C and FIG. 6C The discussed film substrate 104 includes film metallization layers 106(1)-106(8), wherein a core layer 117 is disposed between these film metallization layers. The film substrate 104 can be formed by forming the film metallization layers 106(1)-106(8) one layer at a time as part of an additive process (e.g., a semi-additive process (SAP)). The film substrate 104 can also be formed as an embedded trace substrate (ETS). Then, as... FIG. 6C As shown in manufacturing stage 500B, the next exemplary step in manufacturing process 400 is to laminate the first PPG insulating layer 132(1) and the second PPG insulating layer 132(2) onto the corresponding first external film metallization layer 106(1) and film metallization layer 106(8) of the film substrate 104. FIG. 6C(See box 404 in the middle). An opening 502 is formed in the first PPG insulating layer 132(1) to provide a first die region 110(1) to provide an unobstructed passage to the film substrate 104 and its first outer film metallization layer 106(1), thereby enabling the first bottom die 108(1) (see box 404 in the middle) to be inserted into the first die region 110(1) to provide an unobstructed passage to the film substrate 104 and its first outer film metallization layer 106(1) to be inserted into the first bottom die 108(1) (see box 404 in the middle). FIG. 6C and 1B The opening 502 is coupled to the film substrate 104. The opening 502 may be pre-stamped in the first PPG insulating layer 132(1) before being disposed on the first outer film metallization layer 106(1) as a laminate. Alternatively, the opening 502 may be formed in the first PPG insulating layer 132(1) after being laminated onto the first outer film metallization layer 106(1).

[0057] Then, as FIG. 1A through FIG. 1E As shown in manufacturing stage 500C, the next exemplary step in manufacturing process 400 is to form a first PPG metallization layer 114(1) and a second PPG metallization layer 114(2) for the first PPG substrate 112(1) and the second PPG substrate 112(2) by forming openings 504(1), 504(2) in the first PPG insulating layer 132(1) and the second PPG insulating layer 132(2) up to the film metallization layers 106(1), 106(8) of the film substrate 104. FIG. 2A through FIG. 2E (in frame 406). For example, openings 504(1), 504(2) can be formed by drilling openings 504(1), 504(2) into the corresponding first PPG insulating layer 132(1) and second PPG insulating layer 132(2) through a drilling process. Alternatively, patterning and photolithography processes can be used to form openings 504(1), 504(2). This is so that openings 504(1), 504(2) can be filled with metal material, such as by a metal plating process, to form first metal pads 134(1) and second metal pads 134(2) in the corresponding first PPG insulating layer 132(1) and second PPG insulating layer 132(2), thereby forming first PPG metallization layer 114(1) and second PPG metallization layer 114(2) as part of first PPG substrate 112(1) and second PPG substrate 112(2), as FIG. 5G The manufacturing stage 500D is shown in the figure. FIG. 5H (in box 408). Metal pads 134(1), 134(2) can be formed by forming a metal layer on the first PPG insulating layer 132(1) and the second PPG insulating layer 132(2) and forming openings using a photolithography process to place metal material in the openings 504(1), 504(2).

[0058] Then, as FIG. 7EAs shown in manufacturing stage 500E, the next exemplary step in manufacturing process 400 is to form a first solder resist layer 139(1) and a second solder resist layer 139(2) on the respective first PPG metallization layer 114(1) and second PPG metallization layer 114(2). FIG. 7F (Box 410 in the middle). Then, as... FIG. 3A through FIG. 3B As shown in manufacturing stage 500F, the first solder mask 139(1) and the second solder mask 139(2) are processed to form an opening 506 in the first die region 110(1) to provide a pathway for bonding the bottom first die 108(1) to the film substrate 104. FIG. 4A through FIG. 4D (in box 412). A first opening 508(1) and a second opening 508(2) are also formed in the first solder mask layer 139(1) and the second solder mask layer 139(2) to expose certain first metal pads 134(1) and second metal pads 134(2), thereby enabling the connection of the corresponding wire connectors 116(1), 116(2) and the external interconnect 142. FIG. 6A through FIG. 6C (Box 412 in the middle).

[0059] Then, as FIG. 8 As shown in manufacturing stage 500G, the next exemplary step in manufacturing process 400 is to couple the first bottom die 108 (1) to the first outer film metallization layer 106 (1) of the film substrate 104 in the first die region 110 (1). FIG. 8 (in frame 414). The second upper die 108(2) is joined or otherwise coupled to the first bottom die 108(2). FIG. 8 (in frame 414). Wire connectors 116(1) and 116(2) are used to couple the second die 108(2) to the first metal pad 134(1) in the first PPG substrate 112(1). Then, as FIG. 9 As shown in manufacturing stage 500G, the next exemplary step in manufacturing process 400 is to place mold material 510 on the first die 108(1), the second die 108(2), and the first solder mask 139(1) to form a mold layer 113 on the first die 108(1), the second die 108(2), and the first solder mask 139(1), thereby forming an IC package 100. FIG. 1A through FIG. 1E (Box 416 in the middle).

[0060] FIG. 2A through FIG. 2EThis is a flowchart illustrating another exemplary manufacturing process 600 for manufacturing a coreless package substrate, the coreless package substrate comprising: a film substrate having one or more film metallization layers to support higher density bump spacing for die connection to a first bottom die in a first die region of the film substrate; and a PPG substrate with one or more PPG metallization layers in a second region of the film substrate outside the die region to enhance the film substrate and support lead bonding connection to a second upper die in a hybrid IC package, including but not limited to... FIG. 5G The packaging substrate 202 and the associated IC package 200 are included. FIG. 5H It is based on FIG. 7E Exemplary manufacturing stages 700A-700F during the manufacturing of the packaging substrate in manufacturing process 600. (See reference...) FIG. 7F Discussion of the coreless packaging substrate 202 in the middle as follows FIG. 3A through FIG. 3B Manufacturing process 600 is shown in manufacturing stages 700A-700F. However, it should be noted that manufacturing process 600 can be used to manufacture another coreless package substrate, which includes: a film substrate having one or more film metallization layers to support higher density bump spacing to achieve die connection with a first bottom die in a first die region in the film substrate; and a PPG substrate with one or more PPG metallization layers in a second region of the film substrate outside the die region to enhance the film substrate and support lead bonding connection with a second upper die in a hybrid IC package.

[0061] In this respect, such as FIG. 4A through FIG. 4D As shown in manufacturing stage 700A, the first exemplary step of manufacturing process 600 is to provide film substrate 204 ( FIG. 6A through FIG. 6C (Box 602 in the previous section). As previously mentioned FIG. 8 and FIG. 8 The discussed film substrate 204 includes coreless metallization layers 106(1)-106(3), 106(8). The film substrate 204 can be formed by forming the metallization layers 106(1)-106(3), 106(8) one layer at a time as part of an additive process (e.g., a semi-additive process (SAP)). The film substrate 204 can also be formed as an embedded trace substrate (ETS). Then, as... FIG. 8 As shown in manufacturing stage 700B, the next exemplary step in manufacturing process 400 is to laminate the first PPG insulating layer 132(1) and the second PPG insulating layer 132(2) onto the corresponding first external film metallization layer 106(1) and film metallization layer 106(8) of the film substrate 204. FIG. 9(See frame 604 in the image). An opening 502 is formed in the first PPG insulating layer 132(1) to provide a first die region 110(1) to provide an unobstructed passage to the film substrate 104 and its first outer film metallization layer 106(1), thereby enabling the first bottom die 108(1) (see frame 604 in the image) to be inserted into the first die region 110(1) to provide an unobstructed passage to the film substrate 104 and its first outer film metallization layer 106(1), thereby enabling the first bottom die 108(1) to be inserted into the film substrate 104 to be inserted into the first outer film metallization layer 106(1) to be inserted into the first outer film metallization layer 108 ... FIG. 9 and 2B The opening 502 is coupled to the film substrate 204. The opening 502 may be pre-stamped in the first PPG insulating layer 132(1) before being disposed on the first outer film metallization layer 106(1) as a laminate. Alternatively, the opening 502 may be formed in the first PPG insulating layer 132(1) after being laminated onto the first outer film metallization layer 106(1).

[0062] For example FIG. 9 As shown in manufacturing stage 700B, openings 504(1), 504(2) are formed in the first PPG insulating layer 132(1) and the second PPG insulating layer 132(2) up to the metal interconnects 122(1), 122(8) of the film metallization layers 106(1), 106(8) of the film substrate 104 to form the first PPG metallization layer 114(1) and the second PPG metallization layer 112(2). ​ (in frame 604). For example, openings 504(1), 504(2) can be formed by drilling openings 504(1), 504(2) into the corresponding first PPG insulating layer 132(1) and second PPG insulating layer 132(2) through a drilling process. Alternatively, patterning and photolithography processes can be used to form openings 504(1), 504(2). This is so that openings 504(1), 504(2) can be filled with metal material, such as by a metal plating process, to form first metal pads 134(1) and second metal pads 134(2) in the corresponding first PPG insulating layer 132(1) and second PPG insulating layer 132(2), thereby forming first PPG metallization layer 114(1) and second PPG metallization layer 114(2) as part of first PPG substrate 112(1) and second PPG substrate 112(2), as ​ The manufacturing stage 700C is shown in the figure. ​ (in box 606). Metal pads 134(1), 134(2) can be formed by forming a metal layer on the first PPG insulating layer 132(1) and the second PPG insulating layer 132(2) and forming openings using a photolithography process to place metal material in the openings 504(1), 504(2).

[0063] Then, as ​As shown in manufacturing stage 700D, the next exemplary step in manufacturing process 600 is to form a first solder resist layer 139(1) and a second solder resist layer 139(2) on the respective first PPG metallization layer 114(1) and second PPG metallization layer 114(2). ​ (Box 608 in the middle). Then, as... ​ As shown in manufacturing stage 700E, the first solder mask 139(1) and the second solder mask 139(2) are processed to form an opening 506(1) in the first die region 110(1) to provide a passage for bonding the bottom first die 108(1) to the film substrate 104. ​ (in frame 610). A first opening 508(1) and a second opening 508(2) are also formed in the first solder mask layer 139(1) and the second solder mask layer 139(2) to expose certain first metal pads 134(1) and second metal pads 134(2), thereby enabling the connection of the corresponding wire connectors 116(1), 116(2) and the external interconnect 142. ​ (Box 612 in the middle).

[0064] The first bottom die 108(1) is coupled to the first outer film metallization layer 106(1) of the film substrate 104 in the first die region 110(1). ​ (in frame 612). The second upper die 108(2) is joined or otherwise coupled to the first bottom die 108(1). ​ (Frame 612 in the middle). Wire connectors 116(1) and 116(2) are used to couple the second die 108(2) to the first metal pad 134(1) in the first PPG substrate 112(1). Then, mold material 510 is disposed on the first die 108(1), the second die 108(2), and the first solder mask 139(1) to form a mold layer 113 on the first die 108(1), the second die 108(2), and the first solder mask 139(1), thereby forming an IC package 200. ​ (Box 612 in the middle).

[0065] It should be noted that the terms “upper” and “top” as used herein are relative terms and do not imply a limitation or implication that an element referenced “top” must always be strictly oriented above an element referenced “bottom”, or vice versa. Similarly, the terms “lower” and “bottom” as used herein are relative terms and do not imply a limitation or implication that an element referenced “bottom” or “lower” must always be strictly oriented below an element referenced “top” or “upper”, or vice versa. Furthermore, it should be noted that the terms “above” and “below” as used herein are relative terms and do not imply a limitation or implication that an element referred to as “above” another referenced element must always be oriented relative to another referenced element, or an element referred to as “below” another referenced element must always be oriented relative to another referenced element.

[0066] As discussed in this article, object "adjacency" refers to an object being next to or adjacent to another object. Adjacent objects may not be directly physically coupled to each other. An object can be directly adjacent to another object, meaning that such objects are directly next to or adjacent to each other without any other object or layer situated between the directly adjacent objects. An object can be indirectly or indirectly adjacent to another object, meaning that such objects are not directly next to or adjacent to each other, but rather with an intermediate object or layer situated between the indirectly adjacent objects.

[0067] The packaging substrate can be provided in or integrated into an IC package in any processor-based device. The packaging substrate includes: a film substrate having one or more film metallization layers to support higher density bump spacing for die connection to a first bottom die in a first die region of the film substrate; and a PPG substrate with one or more PPG metallization layers in a second region of the film substrate outside the die region to enhance the film substrate and support lead bonding connections to a second upper die in a hybrid IC package, including but not limited to: ​ , ​ , ​ and ​ as well as ​ and ​ The packaging substrate and associated IC package in the package, and can be based on ​ , ​ and ​The exemplary manufacturing processes described herein and manufactured in accordance with any aspect disclosed herein. Examples not intended to be limiting include: set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablet computers, phablets, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multirotor aircraft.

[0068] In this respect, ​ An exemplary wireless communication device 800 is illustrated, comprising a radio frequency (RF) component formed of one or more IC packages 802(1), 802(2), wherein either of the IC packages 802(1), 802(2) includes a package substrate comprising: a film substrate having one or more film metallization layers to support higher density bump pitch for die connection to a first bottom die in a first die region of the film substrate; and a PPG substrate having one or more PPG metallization layers in a second region of the film substrate outside the die region to enhance the film substrate and support lead bonding connection to a second upper die in a hybrid IC package, including but not limited to... ​ , ​ , ​ and ​ as well as ​ and ​ The packaging substrate and associated IC package in the package, and can be based on ​ , ​ and ​ The exemplary manufacturing process described herein and manufactured in accordance with any aspect disclosed herein. As an example, wireless communication device 800 may include any of the devices mentioned above or be provided in any of the devices mentioned above. ​As shown, the wireless communication device 800 includes a transceiver 804 and a data processor 806. The data processor 806 may include memory for storing data and program code. The transceiver 804 includes a transmitter 808 and a receiver 810 supporting bidirectional communication. Generally, the wireless communication device 800 may include any number of transmitters 808 and / or receivers 810 for any number of communication systems and frequency bands. All or part of the transceiver 804 may be implemented on one or more analog ICs, RF ICs (RFICs), mixed-signal ICs, etc.

[0069] The transmitter 808 or receiver 810 can be implemented using either a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes multi-stage frequency conversion between RF and baseband; for example, for receiver 810, it is converted from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal is converted between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. ​ In the wireless communication device 800, the transmitter 808 and receiver 810 are implemented using a direct frequency conversion architecture.

[0070] In the transmission path, the data processor 806 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 808. In the exemplary wireless communication device 800, the data processor 806 includes digital-to-analog converters (DACs) 812(1) and 812(2) to convert the digital signals generated by the data processor 806 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0071] Within transmitter 808, low-pass filters 814(1) and 814(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 816(1) and 816(2) amplify the signals from low-pass filters 814(1) and 814(2), respectively, and provide I and Q baseband signals. Upconverter 818 upconverts the I and Q baseband signals from transmit (TX) local oscillator (LO) signal generator 822 using mixers 820(1) and 820(2) to provide upconverted signal 824. Filter 826 filters the upconverted signal 824 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 828 amplifies the upconverted signal 824 from filter 826 to obtain the desired output power level and provide the transmit RF signal. The RF signal is routed through the duplexer or switch 830 and transmitted via the antenna 832.

[0072] In the receiving path, antenna 832 receives signals transmitted by the base station and provides received RF signals, which are routed through duplexer or switch 830 and provided to low-noise amplifier (LNA) 834. Duplexer or switch 830 is designed to operate using a specific receive (RX) to TX duplexer frequency separation, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 834 and filtered by filter 836 to obtain the desired RF input signal. Downconversion mixers 838(1) and 838(2) mix the output of filter 836 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 840 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMP 842(1) and 842(2) and further filtered by low-pass filters 844(1) and 844(2) to obtain I and Q analog input signals, which are provided to data processor 806. In this example, the data processor 806 includes analog-to-digital converters (ADCs) 846(1) and 846(2) to convert analog input signals into digital signals to be further processed by the data processor 806.

[0073] exist ​ In the wireless communication device 800, a TX LO signal generator 822 generates I and Q TX LO signals for up-conversion, while an RX LO signal generator 840 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. A TX phase-locked loop (PLL) circuit 848 receives timing information from a data processor 806 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from the TX LO signal generator 822. Similarly, an RXILL circuit 850 receives timing information from a data processor 806 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from the RX LO signal generator 840.

[0074] ​ An example of a processor-based system 900 is illustrated, which includes circuitry available in IC packages 902, 902(1)-902(7), the IC package including a package substrate comprising: a film substrate having one or more film metallization layers to support higher density bump spacing for die connection to a first bottom die in a first die region of the film substrate; and a PPG substrate with one or more PPG metallization layers in a second region of the film substrate outside the die region to enhance the film substrate and support lead bonding connections to a second upper die in a hybrid IC package, including but not limited to... ​ , ​ ,​ and ​ as well as ​ and ​ The packaging substrate and associated IC package in the package, and can be based on ​ , ​ and ​ The exemplary manufacturing process described herein and manufactured according to any aspect disclosed herein. Any of the IC packages 902, 902(1)-902(6) may include a package substrate comprising: a film substrate having one or more film metallization layers to support higher density bump pitch for die connection to a first bottom die in a first die region of the film substrate; and a PPG substrate having one or more PPG metallization layers in a second region of the film substrate outside the die region to enhance the film substrate and support lead bonding connection to a second upper die in the hybrid IC package, including but not limited to ​ , ​ , ​ and ​ as well as ​ and ​ The packaging substrate and associated IC package in the package, and can be based on ​ , ​ and ​ The exemplary manufacturing process described herein and manufactured in accordance with any aspect disclosed herein.

[0075] In this example, the processor-based system 900 may be formed as IC 904 in IC package 902 and as a system-on-a-chip (SoC) 906. The processor-based system 900 includes a central processing unit (CPU) 908, which includes one or more processors 910, which may also be referred to as a CPU core or processor core. The CPU 908 may be included in IC package 902 (1). The CPU 908 may have a cache memory 912 coupled to the CPU 908 for fast access to temporarily stored data. The CPU 908 is coupled to a system bus 914 and may couple master and slave devices included in the processor-based system 900 to each other. As is well known, the CPU 908 communicates with these other devices by exchanging address, control, and data information via the system bus 914. For example, the CPU 908 may communicate a bus transaction request to a memory controller 916, which is an example of a slave device. Although in ​ Not illustrated, but multiple system buses 914 may be provided, each of which constitutes a different architecture.

[0076] Other master and slave devices can be connected to system bus 914. For example... ​As illustrated, by way of example, these devices may include a memory system 920, which may be in a separate IC package 902(2) and includes a memory controller 916 and a memory array 918, one or more input devices 922 (which may be in a separate IC package 902(3)), one or more output devices 924 (which may be in a separate IC package 902(4)), one or more network interface devices 926, and one or more display controllers 928. Each of the memory system 920, one or more input devices 922, one or more output devices 924, one or more network interface devices 926 (which may be in IC package 902(5)), and one or more display controllers 928 may be housed in the same or different IC packages. Input devices 922 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. Output devices 924 may include any type of output device, including but not limited to audio, video, other visual indicators, etc. Network interface devices 926 may be any device configured to allow data exchange to and from network 930. Network 930 can be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), and Bluetooth. ™ Networks and the Internet. The network interface device 926 can be configured to support any type of communication protocol desired.

[0077] CPU 908 may also be configured to access display controller 928 via system bus 914 to control information transmitted to one or more displays 932. Display controller 928 transmits information to be displayed to display 932 via one or more video processors 934, which process the information to be displayed into a format suitable for display 932. Display controller 928 and video processor 934 may be included as ICs in, for example, the same or different IC packages 902(5), 902(6), or the same or different IC packages 902, 902(1) containing CPU 908. Display 932 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc.

[0078] Those skilled in the art will further understand that the various exemplary logic blocks, modules, circuits, and algorithms described in connection with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium and executed by a processor or other processing device, or a combination of both. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, the functionality of the various exemplary components, blocks, modules, circuits, and steps has been generally described above. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the overall system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be construed as departing from the scope of this disclosure.

[0079] The various exemplary logic blocks, modules, and circuits described in conjunction with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic unit, discrete hardware component, or any combination thereof, designed to perform the functions described herein. The processor may be a microprocessor, but in alternative embodiments, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration).

[0080] The aspects disclosed herein may be embodied in hardware and instructions stored in the hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Alternatively, the storage medium may be integral with the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0081] It should also be noted that the operational steps described in any of the exemplary aspects of this document are described for the purpose of providing examples and discussion. The described operations may be performed in many different orders other than the order illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that, as will be apparent to those skilled in the art, many different modifications may be made to the operational steps illustrated in the flowcharts. Those skilled in the art will also understand that any of a variety of different techniques and arts can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0082] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0083] Specific implementation examples are described in the following numbered clauses:

[0084] 1. A packaging substrate, the packaging substrate comprising:

[0085] A first substrate, the first substrate comprising:

[0086] A first metallization layer, the first metallization layer including a first surface and extending in a first direction, the first metallization layer comprising:

[0087] First insulating layer; and

[0088] A first metal layer, the first metal layer comprising:

[0089] A plurality of first metal interconnects, the plurality of first metal interconnects being exposed from the first surface in a first region of the first film metallization layer; and

[0090] A plurality of second metal interconnects, the plurality of second metal interconnects being exposed from the first surface in a second region of the first film metallization layer adjacent to the first region in the first direction;

[0091] A second substrate, the second substrate comprising:

[0092] A first pre-impregnated (PPG) metallization layer, wherein the first pre-impregnated (PPG) metallization layer is adjacent to the first surface in the second region, the first PPG metallization layer comprising:

[0093] Second surface;

[0094] A second insulating layer, the second insulating layer comprising PPG material; and

[0095] A second metal layer, the second metal layer comprising:

[0096] A plurality of first metal pads are exposed from the second surface.

[0097] 2. The packaging substrate according to Clause 1, wherein the first substrate further comprises:

[0098] A second metallization layer, adjacent to the first metallization layer and extending in the first direction, the second metallization layer comprising:

[0099] Third surface;

[0100] Second insulating layer; and

[0101] A third metal layer, the third metal layer comprising:

[0102] A plurality of third metal interconnects, the plurality of third metal interconnects being exposed from the third surface; and

[0103] A plurality of fourth metal interconnects, the plurality of fourth metal interconnects being exposed from the third surface;

[0104] The first metallization layer further includes:

[0105] A plurality of first vias, each of the plurality of first metal interconnects coupling a first metal interconnect of the plurality of first metal interconnects to a third metal interconnect of the plurality of third metal interconnects; and

[0106] A plurality of second vias, each of the plurality of second metal interconnects coupling a second metal interconnect of the plurality of second metal interconnects to a fourth metal interconnect of the plurality of fourth metal interconnects.

[0107] 3. The packaging substrate according to clause 1 or 2, wherein the plurality of first metal interconnects have a first pitch of less than or equal to five (5) micrometers (μm).

[0108] 4. The packaging substrate according to any one of clauses 1 to 3, wherein the second substrate further comprises a plurality of first vias, each of the plurality of first vias coupling a first metal pad among the plurality of first metal pads to a second metal interconnect among the plurality of second metal interconnects.

[0109] 5. The packaging substrate according to any one of clauses 1 to 4, wherein:

[0110] The second substrate further includes a second PPG metallization layer, which is located in the second region and is adjacent to the first PPG metallization layer on the opposite side of the first PPG metallization layer.

[0111] The second PPG metallization layer includes:

[0112] Third surface;

[0113] A third PPG insulating layer, the third PPG insulating layer comprising PPG material; and

[0114] A third metal layer, the third metal layer comprising:

[0115] A plurality of third metal interconnects, the plurality of third metal interconnects being exposed from the third surface;

[0116] The first PPG metallization layer further includes:

[0117] Multiple first vias, each of the multiple first vias coupling a first metal pad among the multiple first metal pads to a third metal interconnect among the multiple third metal interconnects; and

[0118] The second PPG metallization layer further includes:

[0119] A plurality of second vias, each of the plurality of second vias coupling a third metal interconnect of the plurality of third metal interconnects to a second metal interconnect of the plurality of second metal interconnects.

[0120] 6. The packaging substrate according to any one of clauses 1 to 5, the packaging substrate further comprising a solder resist layer, the solder resist layer being adjacent to the first PPG metallization layer such that the first PPG metallization layer is located between the solder resist layer and the first substrate in a second direction orthogonal to the first direction;

[0121] The solder resist layer includes multiple openings; and

[0122] Each of the plurality of first metal pads is exposed from an opening in one of the plurality of openings.

[0123] 7. The packaging substrate according to any one of clauses 1 to 6, wherein the packaging substrate further comprises:

[0124] A third substrate, the third substrate comprising:

[0125] A second metallization layer, adjacent to the first metallization layer and extending in the first direction, the second metallization layer comprising:

[0126] Third surface;

[0127] Second insulating layer; and

[0128] A third metal layer, the third metal layer comprising:

[0129] A plurality of third metal interconnects, the plurality of third metal interconnects being exposed from the third surface; and

[0130] A plurality of fourth metal interconnects, the plurality of fourth metal interconnects being exposed from the third surface; and

[0131] A core layer, located between the first substrate and the third substrate in a second direction orthogonal to the first direction, the core layer comprising:

[0132] A plurality of metal pillars, each of the plurality of metal pillars being coupled to a first metal interconnect of a plurality of first metal interconnects, and coupled to a third metal interconnect of a plurality of third metal interconnects.

[0133] 8. The packaging substrate according to any one of clauses 1 to 6, wherein the packaging substrate does not include a core layer.

[0134] 9. The packaging substrate according to any one of clauses 1 to 8, wherein the first film insulating layer comprises polyimide.

[0135] 10. The packaging substrate according to any one of clauses 1 to 9, wherein the ratio of the second thickness of the second insulating layer in a second direction orthogonal to the first direction to the first thickness of the first film insulating layer in the second direction is at least 1.5.

[0136] 11. The packaging substrate according to any one of clauses 1 to 10, wherein:

[0137] The first insulating film has a first thickness between 10 micrometers (μm) and 35 μm in a second direction orthogonal to the first direction; and

[0138] The second insulating layer has a second thickness between 15 μm and 45 μm in the second direction.

[0139] 12. The packaging substrate according to any one of clauses 1 to 11, wherein:

[0140] The first insulating film layer has a first elastic modulus; and

[0141] The first PPG metallization layer has a second elastic modulus that is greater than the first elastic modulus.

[0142] 13. The packaging substrate according to any one of clauses 1 to 12, wherein:

[0143] The first insulating film layer has a first elastic modulus between 5 gigapascals (GPa) and 20 GPa; and

[0144] The first PPG metallization layer has a second elastic modulus between 14 GPa and 25 GPa.

[0145] 14. The packaging substrate according to any one of Clauses 1 to 13, wherein the packaging substrate is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.

[0146] 15. A method for manufacturing a packaging substrate, the method comprising:

[0147] Forming a first substrate, the process of forming the first substrate includes:

[0148] Forming a first metallization layer, the first metallization layer including a first surface and extending in a first direction, the formation of the first metallization layer includes:

[0149] Form the first insulating film layer;

[0150] Form the first metal layer;

[0151] A plurality of first metal interconnects are formed in the first metal layer, the plurality of first metal interconnects being exposed from the first surface in a first region of the first metallization layer; and

[0152] A plurality of second metal interconnects are formed in the first metal layer, and the plurality of second metal interconnects are exposed from the first surface in a second region of the first film metallization layer that is adjacent to the first region in the first direction;

[0153] Forming a second substrate, the process of forming the second substrate includes:

[0154] Forming a first pre-impregnated (PPG) metallization layer, the first pre-impregnated (PPG) metallization layer having a second surface, and forming the first PPG metallization layer includes:

[0155] A second insulating layer is formed, the second insulating layer comprising PPG material;

[0156] Forming a second metal layer; and

[0157] A plurality of first metal pads are formed from the second metal layer, the plurality of first metal pads being exposed from the second surface; and

[0158] In the second region of the first film metallization layer, the second substrate is coupled to the first substrate in a second direction orthogonal to the first direction.

[0159] 16. The method according to Clause 15, wherein:

[0160] Forming the second substrate further includes forming a plurality of first vias, each of the plurality of first vias being coupled to a first metal pad among the plurality of first metal pads; and

[0161] Coupling the second substrate to the first substrate further includes coupling a first via of the plurality of first vias to a second metal interconnect of the plurality of second metal interconnects.

[0162] 17. The packaging substrate according to clause 15 or 16, wherein coupling the second substrate to the first substrate in the second region further includes laminating the second substrate onto the first substrate.

[0163] 18. The packaging substrate according to any one of claims 15 to 17, the packaging substrate further comprising providing an opening in the second substrate such that coupling the second substrate to the first substrate in the second region of the first substrate will not couple the second substrate to the first die region of the first substrate.

[0164] 19. The method according to any one of clauses 16 to 18, the method further comprising:

[0165] A solder resist layer is formed adjacent to the first PPG metallization layer, such that the first PPG metallization layer is located between the solder resist layer and the first substrate in the second direction; and

[0166] Multiple openings are formed in the solder mask layer, each of the multiple openings exposing a first metal pad among the multiple first metal pads.

[0167] 20. The packaging substrate according to Clause 19, the packaging substrate further comprising forming a second opening in the solder mask layer to expose the plurality of first metal interconnects.

[0168] 21. An integrated circuit (IC) package, the integrated circuit (IC) package comprising:

[0169] Packaging substrate, the packaging substrate comprising:

[0170] A first substrate, the first substrate comprising:

[0171] A first metallization layer, the first metallization layer including a first surface and extending in a first direction, the first metallization layer comprising:

[0172] First insulating layer; and

[0173] A first metal layer, the first metal layer comprising:

[0174] A plurality of first metal interconnects, the plurality of first metal interconnects being exposed from the first surface in a first region of the first film metallization layer; and

[0175] A plurality of second metal interconnects, the plurality of second metal interconnects being exposed from the first surface in a second region of the first film metallization layer adjacent to the first region in the first direction;

[0176] A second substrate, the second substrate comprising:

[0177] A first pre-impregnated (PPG) metallization layer, wherein the first pre-impregnated (PPG) metallization layer is adjacent to the first surface in the second region, the first PPG metallization layer comprising:

[0178] Second surface;

[0179] A second insulating layer, the second insulating layer comprising PPG material; and

[0180] A second metal layer, the second metal layer comprising:

[0181] A plurality of first metal pads, the plurality of first metal pads being exposed from the second surface;

[0182] A first die, the first die including a plurality of die interconnects, each of the plurality of die interconnects being connected to a first metal interconnect among the plurality of first metal interconnects; and

[0183] A second die, adjacent to the first die, such that the first die is located between the second die and the packaging substrate in a second direction orthogonal to the first direction; and

[0184] Multiple lead connectors, each of the multiple lead connectors being connected to a first metal pad in the second die and the multiple first metal pads.

[0185] 22. The IC package according to Clause 21, wherein the second substrate further includes a plurality of first vias, each of the plurality of first vias coupling a first metal pad of the plurality of first metal pads to a second metal interconnect of the plurality of second metal interconnects.

[0186] 23. The IC package according to clause 21 or 22, wherein the package substrate further comprises:

[0187] A third substrate, the third substrate comprising:

[0188] A second metallization layer, adjacent to the first metallization layer and extending in the first direction, the second metallization layer comprising:

[0189] Third surface;

[0190] Second insulating layer; and

[0191] A third metal layer, the third metal layer comprising:

[0192] A plurality of third metal interconnects, the plurality of third metal interconnects being exposed from the third surface; and

[0193] A plurality of fourth metal interconnects, the plurality of fourth metal interconnects being exposed from the third surface; and

[0194] A core layer, located between the first substrate and the third substrate in a second direction orthogonal to the first direction, the core layer comprising:

[0195] A plurality of metal pillars, each of the plurality of metal pillars being coupled to a first metal interconnect of a plurality of first metal interconnects, and coupled to a third metal interconnect of a plurality of third metal interconnects.

[0196] 24. The IC package as described in Clause 21 or 22, wherein the IC package does not include a core layer.

[0197] 25. An IC package according to any one of clauses 21 to 24, wherein:

[0198] The first insulating film layer has a first elastic modulus; and

[0199] The first PPG metallization layer has a second elastic modulus that is greater than the first elastic modulus.

[0200] 26. An IC package according to any one of clauses 21 to 25, wherein:

[0201] The first insulating film layer has a first elastic modulus between 5 gigapascals (GPa) and 20 GPa; and

[0202] The first PPG metallization layer has a second elastic modulus between 14 GPa and 25 GPa.

[0203] 27. An IC package according to any one of Clauses 21 to 26, wherein the IC package is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multirotor aircraft.

Claims

1. A packaging substrate, the packaging substrate comprising: A first substrate, the first substrate comprising: A first metallization layer, the first metallization layer including a first surface and extending in a first direction, the first metallization layer comprising: First insulating layer; and A first metal layer, the first metal layer comprising: A plurality of first metal interconnects, the plurality of first metal interconnects being exposed from the first surface in a first region of the first film metallization layer; and A plurality of second metal interconnects, the plurality of second metal interconnects being exposed from the first surface in a second region of the first film metallization layer adjacent to the first region in the first direction; A second substrate, the second substrate comprising: A first pre-impregnated (PPG) metallization layer, wherein the first pre-impregnated (PPG) metallization layer is adjacent to the first surface in the second region, the first PPG metallization layer comprising: Second surface; A second insulating layer, the second insulating layer comprising PPG material; and A second metal layer, the second metal layer comprising: A plurality of first metal pads are exposed from the second surface.

2. The packaging substrate according to claim 1, wherein the first substrate further comprises: A second metallization layer, adjacent to the first metallization layer and extending in the first direction, the second metallization layer comprising: Third surface; Second insulating layer; and A third metal layer, the third metal layer comprising: A plurality of third metal interconnects, the plurality of third metal interconnects being exposed from the third surface; and A plurality of fourth metal interconnects, the plurality of fourth metal interconnects being exposed from the third surface; The first metallization layer further includes: A plurality of first vias, each of the plurality of first metal interconnects coupling a first metal interconnect of the plurality of first metal interconnects to a third metal interconnect of the plurality of third metal interconnects; and A plurality of second vias, each of the plurality of second metal interconnects coupling a second metal interconnect of the plurality of second metal interconnects to a fourth metal interconnect of the plurality of fourth metal interconnects.

3. The packaging substrate according to claim 1, wherein the plurality of first metal interconnects have a first spacing of less than or equal to five (5) micrometers (μm).

4. The packaging substrate according to claim 1, wherein the second substrate further includes a plurality of first vias, each of the plurality of first vias coupling a first metal pad among the plurality of first metal pads to a second metal interconnect among the plurality of second metal interconnects.

5. The packaging substrate according to claim 1, wherein: The second substrate further includes a second PPG metallization layer, which is located in the second region and is adjacent to the first PPG metallization layer on the opposite side of the first PPG metallization layer. The second PPG metallization layer includes: Third surface; A third PPG insulating layer, the third PPG insulating layer comprising PPG material; and A third metal layer, the third metal layer comprising: A plurality of third metal interconnects, the plurality of third metal interconnects being exposed from the third surface; The first PPG metallization layer further includes: Multiple first vias, each of the multiple first vias coupling a first metal pad among the multiple first metal pads to a third metal interconnect among the multiple third metal interconnects; and The second PPG metallization layer further includes: A plurality of second vias, each of the plurality of second vias coupling a third metal interconnect of the plurality of third metal interconnects to a second metal interconnect of the plurality of second metal interconnects.

6. The packaging substrate according to claim 1, wherein the packaging substrate further comprises a solder resist layer, the solder resist layer being adjacent to the first PPG metallization layer, such that the first PPG metallization layer is located between the solder resist layer and the first substrate in a second direction orthogonal to the first direction; The solder resist layer includes multiple openings; and Each of the plurality of first metal pads is exposed from an opening in one of the plurality of openings.

7. The packaging substrate according to claim 1, further comprising: A third substrate, the third substrate comprising: A second metallization layer, adjacent to the first metallization layer and extending in the first direction, the second metallization layer comprising: Third surface; Second insulating layer; and A third metal layer, the third metal layer comprising: A plurality of third metal interconnects, the plurality of third metal interconnects being exposed from the third surface; and A plurality of fourth metal interconnects, the plurality of fourth metal interconnects being exposed from the third surface; and A core layer, located between the first substrate and the third substrate in a second direction orthogonal to the first direction, the core layer comprising: A plurality of metal pillars, each of the plurality of metal pillars being coupled to a first metal interconnect of a plurality of first metal interconnects, and coupled to a third metal interconnect of a plurality of third metal interconnects.

8. The packaging substrate according to claim 1, wherein the packaging substrate does not include a core layer.

9. The packaging substrate according to claim 1, wherein the first film insulating layer comprises polyimide.

10. The packaging substrate of claim 1, wherein the ratio of the second thickness of the second insulating layer in a second direction orthogonal to the first direction to the first thickness of the first film insulating layer in the second direction is at least 1.

5.

11. The packaging substrate according to claim 1, wherein: The first insulating film has a first thickness between 10 micrometers (μm) and 35 μm in a second direction orthogonal to the first direction; and The second insulating layer has a second thickness between 15 μm and 45 μm in the second direction.

12. The packaging substrate according to claim 1, wherein: The first insulating film layer has a first elastic modulus; and The first PPG metallization layer has a second elastic modulus that is greater than the first elastic modulus.

13. The packaging substrate according to claim 1, wherein: The first insulating film layer has a first elastic modulus between 5 gigapascals (GPa) and 20 GPa; and The first PPG metallization layer has a second elastic modulus between 14 GPa and 25 GPa.

14. The packaging substrate of claim 1, wherein the packaging substrate is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.

15. A method for manufacturing a packaging substrate, the method comprising: Forming a first substrate, the process of forming the first substrate includes: Forming a first metallization layer, the first metallization layer including a first surface and extending in a first direction, the formation of the first metallization layer includes: Form the first insulating film layer; Form the first metal layer; A plurality of first metal interconnects are formed in the first metal layer, the plurality of first metal interconnects being exposed from the first surface in a first region of the first metallization layer; and A plurality of second metal interconnects are formed in the first metal layer, and the plurality of second metal interconnects are exposed from the first surface in a second region of the first film metallization layer that is adjacent to the first region in the first direction; Forming a second substrate, the process of forming the second substrate includes: Forming a first pre-impregnated (PPG) metallization layer, the first pre-impregnated (PPG) metallization layer having a second surface, and forming the first PPG metallization layer includes: A second insulating layer is formed, the second insulating layer comprising PPG material; Forming a second metal layer; and A plurality of first metal pads are formed from the second metal layer, the plurality of first metal pads being exposed from the second surface; and In the second region of the first film metallization layer, the second substrate is coupled to the first substrate in a second direction orthogonal to the first direction.

16. The method of claim 15, wherein: Forming the second substrate further includes forming a plurality of first vias, each of the plurality of first vias being coupled to a first metal pad among the plurality of first metal pads; and Coupling the second substrate to the first substrate further includes coupling a first via of the plurality of first vias to a second metal interconnect of the plurality of second metal interconnects.

17. The packaging substrate of claim 15, wherein coupling the second substrate to the first substrate in the second region further comprises laminating the second substrate onto the first substrate.

18. The packaging substrate of claim 15, further comprising providing an opening in the second substrate such that coupling the second substrate to the first substrate in the second region of the first substrate will not couple the second substrate to the first die region of the first substrate.

19. The method according to claim 16, further comprising: A solder resist layer is formed adjacent to the first PPG metallization layer, such that the first PPG metallization layer is located between the solder resist layer and the first substrate in the second direction; as well as Multiple openings are formed in the solder mask layer, each of the multiple openings exposing a first metal pad among the multiple first metal pads.

20. The packaging substrate of claim 19, further comprising forming a second opening in the solder mask layer to expose the plurality of first metal interconnects.

21. An integrated circuit (IC) package, the integrated circuit (IC) package comprising: Packaging substrate, the packaging substrate comprising: A first substrate, the first substrate comprising: A first metallization layer, the first metallization layer including a first surface and extending in a first direction, the first metallization layer comprising: First insulating layer; and A first metal layer, the first metal layer comprising: A plurality of first metal interconnects, the plurality of first metal interconnects being exposed from the first surface in a first region of the first film metallization layer; and A plurality of second metal interconnects, the plurality of second metal interconnects being exposed from the first surface in a second region of the first film metallization layer adjacent to the first region in the first direction; A second substrate, the second substrate comprising: A first pre-impregnated (PPG) metallization layer, wherein the first pre-impregnated (PPG) metallization layer is adjacent to the first surface in the second region, the first PPG metallization layer comprising: Second surface; A second insulating layer, the second insulating layer comprising PPG material; and A second metal layer, the second metal layer comprising: A plurality of first metal pads, the plurality of first metal pads being exposed from the second surface; A first die, the first die including a plurality of die interconnects, each of the plurality of die interconnects being connected to a first metal interconnect among the plurality of first metal interconnects; and A second die, adjacent to the first die, such that the first die is located between the second die and the packaging substrate in a second direction orthogonal to the first direction; and Multiple lead connectors, each of the multiple lead connectors being connected to a first metal pad in the second die and the multiple first metal pads.

22. The IC package of claim 21, wherein the second substrate further comprises a plurality of first vias, each of the plurality of first vias coupling a first metal pad among the plurality of first metal pads to a second metal interconnect among the plurality of second metal interconnects.

23. The IC package of claim 21, wherein the package substrate further comprises: A third substrate, the third substrate comprising: A second metallization layer, adjacent to the first metallization layer and extending in the first direction, the second metallization layer comprising: Third surface; Second insulating layer; and A third metal layer, the third metal layer comprising: A plurality of third metal interconnects, the plurality of third metal interconnects being exposed from the third surface; and A plurality of fourth metal interconnects, the plurality of fourth metal interconnects being exposed from the third surface; and A core layer, located between the first substrate and the third substrate in a second direction orthogonal to the first direction, the core layer comprising: A plurality of metal pillars, each of the plurality of metal pillars being coupled to a first metal interconnect of a plurality of first metal interconnects, and coupled to a third metal interconnect of a plurality of third metal interconnects.

24. The IC package of claim 21, wherein the IC package does not include a core layer.

25. The IC package according to claim 21, wherein: The first insulating film layer has a first elastic modulus; and The first PPG metallization layer has a second elastic modulus that is greater than the first elastic modulus.

26. The IC package according to claim 21, wherein: The first insulating film layer has a first elastic modulus between 5 gigapascals (GPa) and 20 GPa; and The first PPG metallization layer has a second elastic modulus between 14 GPa and 25 GPa.

27. The IC package of claim 21, wherein the IC package is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; global positioning system (GPS) devices; mobile phones; cellular phones; smartphones; session initiation protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.

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