Radar system, radar chip, signal processing method, integrated circuit, electromagnetic wave device and terminal device

Abstract

The invention relates to a radar system, a radar chip, a signal processing method, an integrated circuit, an electromagnetic wave device and terminal equipment, which can ensure computing power balance and real-time calculation of a cascade radar system. The radar system comprises at least two cascaded radar chips, and each radar chip comprises a preprocessing unit used for converting a received analog signal into a digital signal and carrying out fast Fourier transform processing on the digital signal; the storage unit is used for storing the data processed by the preprocessing unit; the signal processing unit is used for processing data processed by the radar chip and other radar chip preprocessing units so as to realize target detection of the radar chip; the system further comprises a data control unit, and the data control unit is connected with the storage unit and the signal processing unit of each radar chip, and is used for selecting data from the storage units of all the radar chips and distributing the data to the signal processing units of all the cascaded radar chips or part of the cascaded radar chips.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of sensor technology, particularly a radar system, radar chip, signal processing method, integrated circuit, electromagnetic wave device and terminal equipment. Background Technology

[0002] As one of the most important future development directions for automotive millimeter-wave radar, radar imaging often requires more transceiver channels and more powerful processing capabilities. Chip cascading is the main way to achieve this. Existing cascaded radar imaging systems often use multiple radar transceiver components cascaded at the front end, and then process the data uniformly on the central processing unit after acquisition. This processing method often requires a powerful central processing unit, which is not cost-effective for the system. Summary of the Invention

[0003] This application provides a radar system, including a radar chip, signal processing method, integrated circuit, electromagnetic wave device, and terminal equipment, which can ensure the computing power balance and real-time calculation of the cascaded radar system.

[0004] On one hand, embodiments of this application provide a radar system including at least two cascaded radar chips, each radar chip including a preprocessing unit, a storage unit, and a signal processing unit, wherein:

[0005] The preprocessing unit is used to convert the received analog signal into a digital signal and perform a fast Fourier transform on the digital signal.

[0006] The storage unit is used to store the data processed by the preprocessing unit;

[0007] The signal processing unit is used to process the data processed by the radar chip and other radar chip preprocessing units to achieve target detection by the radar chip.

[0008] The radar system also includes a data control unit, which is connected to the storage unit and signal processing unit of each radar chip, and is used to select data from the storage units of all radar chips and distribute it to the signal processing units of all or some of the cascaded radar chips.

[0009] On the other hand, this application also provides a radar chip as the main radar chip in a cascaded radar system. The radar chip includes a preprocessing unit, a storage unit, a signal processing unit, and a data control unit, wherein:

[0010] The preprocessing unit is used to convert the received analog signal into a digital signal and perform a fast Fourier transform on the digital signal.

[0011] The storage unit is used to store the data processed by the preprocessing unit;

[0012] The signal processing unit is used to receive and process the data processed by the radar chip and other radar chip preprocessing units.

[0013] The data control unit is connected to the storage unit and signal processing unit of each radar chip in the cascaded radar system, and is used to select data from the storage units of all radar chips and distribute it to the signal processing units of all or some of the cascaded radar chips.

[0014] On the other hand, this application also provides a signal processing method applied to a cascaded radar system, which selects range gate data or Doppler units from the storage units of all radar chips in the cascaded radar system and assigns them to all or some of the cascaded radar chips, wherein the range gate data sequence number or the Doppler unit sequence number assigned to a radar chip is the same.

[0015] In another aspect, embodiments of this application also provide an integrated circuit, including a radio frequency (RF) module, an analog signal processing module, and a digital signal processing module connected in sequence; the RF module is used to generate RF transmission signals and receive RF reception signals; the analog signal processing module is used to down-convert the RF reception signals to obtain intermediate frequency (IF) signals; the digital signal processing module is used to perform analog-to-digital conversion on the IF signals to obtain digital signals; and the digital signal processing module processes the digital signals based on the aforementioned signal processing method.

[0016] In another aspect, embodiments of this application also provide an electromagnetic wave device, comprising: a carrier; the aforementioned integrated circuit disposed on the carrier; an antenna disposed on the carrier, or the antenna and the integrated circuit being integrated into a single device disposed on the carrier; wherein the integrated circuit is connected to the antenna and is used to transmit the radio frequency transmission signal and / or receive the radio frequency reception echo signal.

[0017] Furthermore, embodiments of this application also provide a terminal device, including: a device body; and

[0018] The electromagnetic wave device as described in claim 22 is disposed on the device body; wherein the electromagnetic wave sensor is used for target detection and / or communication to provide reference information for the operation of the device body.

[0019] By adopting the solution in this embodiment, a data control unit is set up to uniformly allocate data, thereby realizing memory sharing and data allocation among multiple radar chips, ensuring balanced computing power and real-time calculation among multiple radar chips.

[0020] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0021] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0022] Figure 1 This is a schematic diagram of a radar system according to an embodiment of the present disclosure;

[0023] Figure 2 This is a schematic diagram of the signal processing flow according to an embodiment of the present disclosure;

[0024] Figure 3 This is a schematic diagram of the parallel processing architecture of the radar system according to an embodiment of the present disclosure;

[0025] Figure 4 This document compares the computational power of the method in the embodiments of this disclosure with that of other methods.

[0026] Figure 5 This is a schematic diagram illustrating the synchronization of LO signals of multiple radar chips according to an embodiment of this disclosure;

[0027] Figure 6 This is a schematic diagram of ADC synchronization for multiple radar chips according to an embodiment of this disclosure;

[0028] Figure 7 This is a timing diagram for ADC synchronization according to an embodiment of the present disclosure;

[0029] Figure 8 This is a flowchart of the signal processing process.

[0030] Figure 9 Flowchart of 2D-FFT signal processing for the main chip

[0031] Figure 10 Doppler spectrum distribution of DDM;

[0032] Figure 11 DDM Doppler aliasing for two targets;

[0033] Figure 12 DDM spectral overlay diagram for two targets;

[0034] Figure 13 Flowchart for solving the TX order;

[0035] Figure 14 This is a schematic diagram of a Peak grouping method according to an embodiment of the present disclosure;

[0036] Figure 15 This is a schematic diagram of an Azimuth DBF method according to an embodiment of the present disclosure;

[0037] Figure 16 This is the output detection map of DBF;

[0038] Figure 17 The DoA signal processing flow for coprime arrays;

[0039] Figure 18 The DBF spectrum is a coprime array with a Taylor window.

[0040] Figure 19 The DBF spectrum is a coprime array with a Taylor window.

[0041] Figure 20 Defuzzing coprime arrays;

[0042] Figure 21 A schematic diagram for a rough estimation of the number of signal sources for antenna array 1;

[0043] Figure 22 A schematic diagram for a rough estimation of the number of signal sources for antenna array 2;

[0044] Figure 23 It is a coprime array IAA spectrum;

[0045] Figure 24 Flowchart of 2DoA signal processing for antenna array;

[0046] Figure 25 3DoA estimation signal processing flow for antenna arrays;

[0047] Figure 26 The DBF spectrum of the antenna array consists of 3 main subarrays;

[0048] Figure 27 The FIAA angular ambiguity spectrum of the antenna array with 3 main subarrays;

[0049] Figure 28 The energy spectrum is projected from the subarray for antenna array 3;

[0050] Figure 29 A schematic diagram of the principle of antenna array 3_coasrse_RNE;

[0051] Figure 30 3FIAA spectrum for antenna array;

[0052] Figure 31 This is a signal processing flow with distributed data.

[0053] Figure 32 This is a 2D-FFT signal processing flow;

[0054] Figure 33 This describes the DA-CFAR signal processing flow.

[0055] Figure 34 Gain for different beams of DA-CFAR;

[0056] Figure 35 Gain for different beams of DA-CFAR;

[0057] Figure 36 Signal processing flow for the Peak Grouping module;

[0058] Figure 37 The signal processing flow of the Azimuth DBF module;

[0059] Figure 38 For DBF output detection;

[0060] Figure 39 Flowchart for Phase Shifter calibration;

[0061] Figure 40 This is a function-based signal processing method;

[0062] Figure 41 This is another function-based signal processing method;

[0063] Figure 42 This is a signal processing method based on distributed data. Detailed Implementation

[0064] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in various forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the content of this application.

[0065] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0066] Current radar systems with multiple cascaded System-on-a-Chip (SoC) chips, while not requiring expensive central processing units, lack consideration for the parallel architecture of distributed computing and the balancing of computing power, resulting in significant real-time performance issues.

[0067] The radar system in this embodiment includes at least two cascaded radar chips, such as two cascaded radar chips, three cascaded radar chips, four cascaded radar chips, five cascaded radar chips, or six cascaded radar chips. This includes one master chip and the remaining chips are slave chips, such as... Figure 1 As shown in the figure, only one chip is used as an example; each radar chip includes a preprocessing unit, a storage unit, and a signal processing unit, wherein:

[0068] The preprocessing unit is used to convert the received analog signal into a digital signal and perform Fast Fourier Transform (FFT) processing on the data signal;

[0069] The storage unit is used to store the data processed by the preprocessing unit. The storage unit is, for example, SRAM (Static RAM).

[0070] The signal processing unit is used to process the data processed by the radar chip and other radar chip preprocessing units to achieve target detection of the radar chip; including but not limited to constant false alarm rate (CFAR) detection, direction of arrival (DoA) estimation, etc., so as to obtain a data spectrum containing the target's distance (Rang), velocity (Velocity), angle (Angle) and other dimensions relative to the radar system.

[0071] The radar system also includes a data control unit, which is connected to the storage unit and signal processing unit of each radar chip. The data control unit is used to allocate data to the signal processing units of each radar chip to achieve a balance of computing power among the radar chips.

[0072] By setting up a data control unit to uniformly allocate data, memory sharing and data distribution among multiple radar chips are realized, ensuring balanced computing power and real-time calculation among multiple radar chips.

[0073] For example, in order to ensure high-speed data transmission between radar chips, the SRAM of each radar chip in the radar system is connected to the SRAM of other radar chips through a high-speed data interaction interface—the C2C interface (Chip-to-Chip Interface).

[0074] For example, all SRAMs can be arranged in a ring daisy chain, with each SRAM connected to the SRAM of the adjacent radar chip. This ring structure reduces the number of connection lines and simplifies wiring. Alternatively, in an exemplary embodiment, all SRAMs can be arranged in a mesh topology, with each SRAM connected to the SRAMs of the other radar chips, providing high reliability and redundancy.

[0075] Data sharing and unified resource allocation among radar chips can be achieved through the coordination of the data control unit. For example, the data control unit can be located on the main chip, such as by the CPU of the main chip.

[0076] The following is a detailed explanation of the data allocation in the data control unit.

[0077] Radar received data can be divided into three dimensions: range, Doppler, and channel (also known as angle). To achieve better angular resolution, data received from different channel dimensions typically needs to be merged. Furthermore, to balance the computing power of various radar chips, radar data can be split according to either the range or Doppler dimension and evenly distributed across different processors for processing; this can be simply referred to as range splitting or Doppler splitting. Figure 2 This diagram illustrates a multi-chip cascaded radar imaging system. Each radar chip's preprocessing unit includes, but is not limited to: an analog-to-digital converter (ADC) engine, a one-dimensional fast Fourier transform (1D FFT, or Range FFT) engine, and a two-dimensional fast Fourier transform (2D FFT, or Doppler FFT) engine. Each radar chip's ADC engine performs analog-to-digital conversion on the received data and outputs the processed data to the 1D FFT engine. The 1D FFT engine performs range FFT processing and stores the output in the chip's SRAM. The 2D FFT engine performs Doppler FFT processing on the 1D FFT engine's result and stores the output in the chip's SRAM. In this example, all SRAMs form a daisy-chain loop, with each SRAM connected to the SRAM of an adjacent radar chip.

[0078] For example, if split by distance, the data control unit can assign a set of distance gates to the Master and each Slave (Slave1, Slave2, ..., SlaveN) according to the following formula:

[0079] Ω(k)=[k:N+1:max_rng_gate] Formula (1)

[0080] Where k is the radar chip label, k∈(1,N+1), max_rng_gate is the maximum number of range gates, and Ω(k) physically means selecting range gates at intervals of N+1 starting from k, up to the last range gate. The data control unit instructs the corresponding SRAM to send all Doppler units and all channel data corresponding to the selected range gates to the corresponding radar chip. After obtaining the candidate range gate set according to the above formula, the SRAM can be controlled to send the relevant data of one range gate (all Doppler units and all channel data corresponding to the range gate). On the one hand, the radar chip can transmit the relevant data of the next range gate while the signal processing unit is processing, improving real-time performance through parallel processing. On the other hand, the data control unit can monitor the processing status of the signal processing units of each radar chip in a timely manner and adjust the candidate range gate set according to the processing status to achieve load balancing and computing power balancing.

[0081] In the example above, range gate data is assigned to all radar chips, so range gates at intervals of N+1 are considered as a set. If range gate data is assigned to only some radar chips, the interval number "N+1" can be modified to the number of radar chips M involved in signal processing, where M≤N+1.

[0082] Taking a three-radar chip cascaded system as an example, for the Master, assuming the maximum number of range gates on the Master is 18, according to the above formula (1), the data control unit allocates the 1st, 4th, 7th, ..., 16th range gates to the Master. The data control unit can instruct the Master's SRAM to send the relevant data of the 1st range gate to the Master's signal processing unit first. According to the above formula (1), the data control unit allocates the 2nd, 5th, 8th, ..., 17th range gates to Slave1. The data control unit can instruct the Master's SRAM to send the relevant data of the 2nd range gate to the Slave1's signal processing unit first. According to the above formula (1), the data control unit allocates the 3rd, 6th, 9th, ..., 18th range gates to Slave2. The data control unit can instruct the Master's SRAM to send the relevant data of the 3rd range gate to the Slave2's signal processing unit first. And so on. Similarly, for Slave1, assuming the maximum number of range gates on Slave1 is 17, the data control unit allocates the 1st, 4th, 7th, ..., 16th range gates to the Master. The data control unit can instruct Slave1's SRAM to first send the relevant data of the 1st range gate to the Master's signal processing unit for subsequent processing. The data control unit allocates the 2nd, 5th, 8th, ..., 17th range gates to Slave1. The data control unit can instruct Slave1's SRAM to first send the relevant data of the 2nd range gate to Slave1's signal processing unit. The data control unit allocates the 3rd, 6th, 9th, ..., 15th range gates to Slave2. The data control unit can instruct Slave1's SRAM to first send the relevant data of the 3rd range gate to Slave2's signal processing unit, and so on. Similarly, for Slave2, assuming the maximum number of range gates on Slave2 is 19, the data control unit assigns the 1st, 4th, 7th, ..., 19th range gates to the Master. The data control unit can instruct Slave2's SRAM to send the relevant data of the 1st range gate to the Master's signal processing unit first. Assigning the 2nd, 5th, 8th, ..., 17th range gates to Slave1, the data control unit can instruct Slave2's SRAM to send the relevant data of the 2nd range gate to Slave1's signal processing unit first. Assigning the 3rd, 6th, 9th, ..., 18th range gates to Slave2, the data control unit can instruct Slave2's SRAM to send the relevant data of the 3rd range gate to Slave2's signal processing unit first, and so on.

[0083] In terms of timing, the data control unit controls the Master to process data only after receiving all data with the same range gate number. Similarly, the data control unit controls Slave1 and Slave2 to process data only after receiving all data with the same range gate number. Since the radar needs to merge the processing of all transmit and receive channels to achieve the corresponding processing gain improvement, processing range gate data with the same sequence number on the same radar chip can achieve better gain. In addition, unified scheduling by the data control unit can ensure memory sharing and computing power balance among multiple chips.

[0084] The aforementioned phrase, "splitting radar data according to range or Doppler dimensions and distributing it evenly to different processors," refers to "evenly" as much as possible. For example, if the total number of range gates is not divisible by the number of radar chips involved in signal processing, complete evenness cannot be guaranteed. Furthermore, in data distribution, besides allocating data by single sequence number, multiple data sets can be allocated at once. For instance, in a dual-cascaded radar system, the master chip can be assigned range gates with odd-numbered sequence numbers, and the slave chips can be assigned range gates with even-numbered sequence numbers. Alternatively, two range gates can be assigned to the master chip at once, such as range gate 1 and range gate 2, and range gate 3 and range gate 4 to the slave chips, and so on.

[0085] In the above embodiments, taking the data control unit to distribute data equally among multiple cascaded radar chips in the radar system as an example, in other embodiments, the data control unit can be configured to distribute computing power equally among a subset of radar chips in the radar system. For example, for four cascaded radars, the computing power can be evenly distributed among three radar chips, while the other radar chip performs other processing.

[0086] For example, if based on Doppler splitting, the data control unit can be allocated a set of Doppler units for the Master and each Slave (Slave1, Slave2, ..., SlaveN) according to the following formula:

[0087] Ψ(n)=[n:N+1:max_doppler_bin] Formula (2)

[0088] Where n is the radar chip number, n∈(1,N+1), max_doppler_bin is the maximum number of Doppler units, and Ψ(n) physically means starting from n, selecting Doppler units at intervals of N+1 as a set, until the last Doppler unit, and sending all range gates and all channel data corresponding to the selected Doppler units to the corresponding radar chip. After obtaining the candidate range gate set according to the above formula, the SRAM can be controlled to send the relevant data of one range gate (all Doppler units and all channel data corresponding to the range gate). On the one hand, the radar chip can transmit the next range gate relevant data while the signal processing unit is processing, improving real-time performance through parallel processing. On the other hand, the data control unit can monitor the processing status of the signal processing units of each radar chip in a timely manner and adjust the candidate range gate set according to the processing status to achieve load balancing and computing power balancing.

[0089] In the example above, Doppler units are allocated to all radar chips, so each interval of N+1 Doppler units is considered as a set. If Doppler units are allocated to only some radar chips, the interval number "N+1" can be modified to the number of radar chips M involved in signal processing, where M≤N+1.

[0090] Similar to the allocation process for range gates (details omitted here), Doppler units with the same sequence number are assigned to the same signal processing unit for processing, which can achieve better gain. Furthermore, unified scheduling by the data control unit ensures memory sharing and balanced computing power among multiple chips.

[0091] In an exemplary embodiment, the aforementioned range splitting method can be used to allocate all range gate data. After collaborative processing by multiple cascaded radar chips, the processed data is returned to the original SRAM. After 2DFFT processing, the data control unit uses the Doppler splitting method to allocate all Doppler units, which are then collaboratively processed by multiple cascaded radar chips.

[0092] In exemplary embodiments, whether the splitting is done by range or by Doppler, there may be an imbalance in the processing load of multiple cascaded radar chips. To prevent this imbalance in computing power due to differences in the processing capabilities of the radar chips, a negative feedback mechanism can be introduced. The data control unit can monitor the processing status of each chip and dynamically adjust the data allocation based on the real-time status of each radar chip to optimize performance and resource utilization. For example, more data (range gates or Doppler units) can be allocated to radar chips that process the current batch faster, while less data can be allocated to radar chips that process the current batch slower. This adaptive adjustment can achieve a balanced processing load across multiple radar chips. Taking a three-radar chip cascaded system as an example, the Master is allocated data for the first range gate, Slave1 for the second range gate, and Slave2 for the third range gate. After the Master and Slave1 finish processing their current data, they can notify the data control unit by setting a processing completion flag. The data control unit periodically checks the processing completion flag. If, within a processing cycle, it finds that the Master and Slave1 have both finished processing, but Slave2 has not, the data control unit can allocate the data originally planned for Slave2 to a faster radar chip, such as selecting a faster chip from either the Master or Slave1. Through this negative feedback mechanism, the data control unit can adjust the data allocation strategy in real time, thereby ensuring a balanced computing power among the radar chips. For example, the data control unit can use existing adaptive algorithms for load balancing.

[0093] To ensure real-time radar processing, data transmission and processing can be executed in parallel by the data control unit. A parallel processing architecture is as follows: Figure 3 As shown. The specific processing varies slightly depending on how the data is split:

[0094] For the data allocation method based on range gates, for each radar chip, one range gate (here, one range gate refers to range gate data with the same sequence number) or multiple range gates can be selected as a batch. First, the data of one batch is allocated and transmitted, and then DA-CFAR (Doppler-Angle Constant False Alarm Rate) and DOA (Direction of Arrival) processing are performed. After the data transmission of one batch is completed, the data transmission of the next batch is started. In this way, the data transmission and signal processing are processed in parallel, which can significantly reduce the system's time consumption.

[0095] For data processing based on Doppler units, for each radar chip, one or more Doppler units (here, one Doppler unit refers to Doppler units with the same serial number) can be selected as a batch. First, the data of one batch is allocated and transmitted, and then RA-CFAR (Range-Angle Constant False Alarm Rate) and DOA processing are performed. After the data transmission of one batch is completed, the data transmission of the next batch is started. In this way, the data transmission and signal processing are processed in parallel, which can greatly reduce the system's time consumption.

[0096] Figure 4 The illustration shows the impact of different splitting methods on computing power for two cascaded radar chips. Compared to the scheme of dividing data according to distance or Doppler size, the method of dividing data according to range gate number and Doppler unit number in this embodiment, which involves uniform sampling and adaptive adjustment, can achieve a balance of computing power among different radar chips. This avoids the problem that the real-time performance of the radar is affected by the slowest radar chip due to the uneven distribution of signal processing.

[0097] In an exemplary embodiment, the cascaded multiple radar chips can share the LO (local oscillator) signal, and the LO signal connection between the multiple radar chips is as follows: Figure 5 As shown. The main chip generates a local oscillator signal and outputs a local oscillator (LO) signal through its LO output port (LOOUT). This LO signal serves as a common source for all radar chips, allowing multiple radar chips to share a single LO signal. For example, as shown... Figure 5 As shown, the Master's LO signal is output to the first node P. By setting the wire length from node P to the LO signal input port (LO IN) of each radar chip to be equal, it can be ensured that the phase of the LO signal input to each radar chip is the same.

[0098] In an exemplary embodiment, ADC sampling synchronization can be achieved among cascaded multiple radar chips, through methods such as... Figure 6 The ADC RSTN (Reset Negative) synchronization circuit shown is implemented as follows: The Master generates a common RSTN signal, which is output through the reset signal output port (RSTN OUT), and then sent to all radar chips, including this chip. Each radar chip synchronizes the sampling of each receiving channel based on the RSTN signal received at the reset signal input port (RSTN IN). The timing circuit is as follows. Figure 7As shown, a high-frequency clock (CLK) is used to trigger the synchronization of sampling start of different ADCs. Optionally, the RSTN signal output by the Master can first be output to the second node Q, and then input to the RSTN IN of each radar chip through multiple wires, or the RSTN signal output by the Master can be input to the RSTN IN of each radar chip through different wires.

[0099] This disclosure also provides a radar chip as the main radar chip in a cascaded radar system. The radar chip includes a preprocessing unit, a storage unit, a signal processing unit, and a data control unit, wherein:

[0100] The preprocessing unit is used to convert the received analog signal into a digital signal and perform a fast Fourier transform on the digital signal.

[0101] The storage unit is used to store the data processed by the preprocessing unit;

[0102] The signal processing unit is used to receive and process the data processed by the radar chip and other radar chip preprocessing units.

[0103] The data control unit is connected to the storage unit and signal processing unit of each radar chip in the cascaded radar system, and is used to select data from the storage units of all radar chips and distribute it to the signal processing units of all or some of the cascaded radar chips.

[0104] In this example, the data control unit is located on the main chip. Through the coordination of the data control unit, data sharing and unified resource allocation among various radar chips can be achieved, ensuring balanced computing power and real-time calculation among multiple radar chips.

[0105] In an exemplary embodiment, the data control unit selects range gate data or Doppler units from the storage units of all radar chips and assigns them to the signal processing units of all or some of the cascaded radar chips. The range gate data assigned to a single radar chip signal processing unit has the same sequence number, or the Doppler units assigned to a single radar chip signal processing unit have the same sequence number. By assigning the same sequence number of range gate or Doppler units to the same radar chip, better gain can be obtained. The specific allocation method is described above and will not be repeated here.

[0106] To improve real-time processing, the data control unit allocates data to the radar chip in batches, and the signal processing unit processes the received data from the previous batch while simultaneously receiving the current batch. Specifically, when the data allocated by the data control unit is a range gate, the signal processing unit performs Doppler-angle constant false alarm rate (CFAR) processing and direction-of-arrival (DOA) estimation. When the data allocated by the data control unit is a Doppler unit, the signal processing unit performs range-angle CFAR processing and DOA estimation. Parallel execution of data transmission and processing improves processing speed and shortens processing time.

[0107] In an exemplary embodiment, the radar chip may further include a local oscillator signal generation unit for generating a local oscillator signal. The generated local oscillator signal is output to a first node through the local oscillator signal output port of the radar chip, and input to the local oscillator signal input port of each radar chip in the cascaded radar system through the first node. The wires from the first node to the local oscillator signal input port of each radar chip are of the same length. This enables LO sharing among multiple chips, ensuring frequency and phase synchronization among all cascaded radar chips.

[0108] In an exemplary embodiment, the radar chip may further include a reset signal generation unit for generating a reset signal. The generated reset signal is output through the reset signal output port of the radar chip and input to the reset signal input port of each radar chip in the cascaded radar system through external wires. This enables synchronization of ADC sampling.

[0109] In summary, the embodiments of this disclosure propose a multi-SOC cascaded radar imaging system based on a parallel processing architecture, which can realize simple cascading of multiple radar SOCs, balanced computing power of multiple radar SOCs, and real-time calculation.

[0110] This disclosure also provides a signal processing method applied to a cascaded radar system, in which range gate data or Doppler units are selected from the storage units of all radar chips in the cascaded radar system and assigned to all or some of the cascaded radar chips, wherein the range gate data sequence number or the Doppler unit sequence number assigned to a radar chip is the same.

[0111] In an exemplary embodiment, during 2D-FFT and preceding operations, the processing of the master chip and the slave chip is the same. After the master chip performs constant false alarm rate (CFAR) processing, it inputs the result to the slave chip. After the slave chip completes its own CFAR processing of received data, it summarizes all the CFAR processing data. After the slave chip performs direction-of-arrival (DOA) estimation processing, the master chip performs target tracking processing.

[0112] In an exemplary embodiment, during the 1D-FFT and preceding operations, the processing of the master chip and the slave chip is the same. The master chip performs 2D-FFT processing and Doppler-angle constant false alarm rate processing, and outputs the processing results to the slave chip. The slave chip performs 2D-FFT processing based on the received data, and continues to perform direction-of-arrival estimation processing and target tracking processing.

[0113] In an exemplary embodiment, in the 1D-FFT and preceding operations, the master chip and slave chip perform the same processing. The master chip and slave chip exchange parity index data based on the distance gate, so that the master chip and slave chip each perform half or a preset division of data for the 2D-FFT operation. The master chip and slave chip each perform Doppler-angle constant false alarm rate processing and transmission sequence calculation processing, respectively. The result data are aggregated into one chip for peak aggregation, and then half or a preset division of data is performed for direction of arrival estimation processing and target tracking processing.

[0114] In an exemplary embodiment, the pre-processing procedure performed by the pre-processing unit can be based on: Figure 8 The flowchart shown illustrates preprocessing operations on the sampled data, such as interference detection, interference nulling, and 1D-FFT processing. The processing flow for a single chirp signal can be found in [reference needed]. Figure 8 The process involves the following steps: After the radar ADC data acquisition is complete, interference detection (CQM) can be performed on the Rx channel (default Rx0). Based on the CQM results, if no interference is present, range-dimensional windowing (e.g., a hanning window) and 1D-FFT calculations are directly performed. If interference is present, the interference region is zeroed out based on the CQM results, followed by range-dimensional windowing and 1D-FFT calculations. After the 1D-FFT, data compression is performed and the data is stored in SRAM; the data compression direction can be the antenna dimension. In this embodiment, the master and slave processes can be identical.

[0115] In an optional embodiment, for the 2D-FFT operation on the Master, see [link to documentation]. Figure 9 As shown (in the figure, A represents the angular dimension, D represents the Doppler dimension, and R represents the distance dimension), it can include:

[0116] The Master 2DFFT engine first retrieves all pulse-dimensional signals of the i-th range gate in a 4Rx array from SRAM, then performs velocity-dimensional windowing (e.g., a hanning window). The window length can be proportional to the number of pulses; for example, the window length for a 768-chirp array is 768, with a value range of 513–1024. Zeros are then padded at the end of the data to make the length 1024, followed by a 1024-point FFT operation. Finally, after the 2D-FFT of the 4Rx array is completed, non-coherent accumulation of the 4Rx array is performed to obtain the energy spectrum of the range cell. Operations such as statistical histograms are then performed to obtain the median as noise estimation. Simultaneously, the energy spectrum is output to a digital signal processing (DSP) chip, where it can be logarithmically quantized into a Uint8 value and output as debug data via Ethernet.

[0117] In the exemplary embodiment, the target can first be roughly detected by coarse CFAR, and then the target can be finely detected by CFAR algorithm with higher gain.

[0118] In an optional embodiment of this application, the processing of DDM Tx order can be performed using the Master chip after the CFAR detects the target. For example, the 2D-FFT result for a single target can be found here. Figure 10 As shown, the entire Doppler plane is divided into 16 sub-bands, and the corresponding antenna channels will appear in the [0,1,2,3,6,8,10,13] sub-bands. Specifically, the Tx order calculation algorithm can be as follows:

[0119] Let the energy of the target in each subband be [S0, S1, ..., S15]. Cyclic shifting yields the sum of 16 possible TX order combinations:

[0120] A0=S0+S1+S2+S3+S6+S8+S10+S13

[0121] A1=S1+S2+S3+S4+S7+S9+S11+S14

[0122] A2=S2+S3+S4+S5+S8+S10+S12+S15

[0123] A3=S3+S4+S5+S6+S9+S11+S13+S0

[0124] A4=S4+S5+S6+S7+S10+S12+S14+S1

[0125] A5=S5+S6+S7+S8+S11+S13+S15+S2

[0126] A6=S6+S7+S8+S9+S12+S14+S0+S3

[0127] A7=S7+S8+S9+S10+S13+S15+S1+S4

[0128] A8=S8+S9+S10+S11+S14+S0+S2+S5

[0129] A9=S9+S10+S11+S12+S15+S1+S3+S6

[0130] A10=S10+S11+S12+S13+S0+S2+S4+S7

[0131] A11=S11+S12+S13+S14+S1+S3+S5+S8

[0132] A12=S12+S13+S14+S15+S2+S4+S6+S9

[0133] A13=S13+S14+S15+S0+S3+S5+S7+S10

[0134] A14=S14+S15+S0+S1+S4+S6+S8+S11

[0135] A15=S15+S0+S1+S2+S5+S7+S9+S12

[0136] Find the maximum value in [A0, A1, ..., A15]. For example, if A5 is the maximum value, then TX order = 5, meaning subband 5 corresponds to the transmit channel TX0 of the antenna. Then, we can define max([A0, A1, ..., A15]) / Powsum as the confidence level of this algorithm, where... The confidence level 2 of the algorithm is defined as the ratio of the maximum signal value to the maximum leakage value under this Tx order, min(signal) / max(leakage). Optionally, for scenarios with Doppler aliasing between two targets, a Doppler aliasing resolution scheme can be added in subsequent operations.

[0137] In some alternative embodiments, when the following occurs... Figure 11 The Doppler spectrum scene shown when two targets exhibit Doppler aliasing can be eliminated using Doppler aliasing resolution methods, specifically including the following:

[0138] a. Iterate through all possible TX order combinations of the two targets and calculate the likelihood probability of each combination. The following explanation uses H1 (TX order = 0) and H2 (TX order = 1) as examples: If the energy of each received subband is as follows... Figure 11 As shown, the received energy P is: P = [p0, p1, ..., p15] T

[0139] b. If we ignore the energy of the aliased signal, that is, assuming target 1 is H1 and target 2 is H2, we need to ignore the aliased energy p2. Then the unaliased energy P can be:

[0140] P′=[p0,p4,p5,p6,p7,p8,p9,p10,p12,p13,p14,p15] T

[0141] c. Assuming the energy of target 1 is A1 and the energy of target 2 is A2, then P′ can be expressed as:

[0142] M[A1 A2]+N=P′

[0143] Where M is the superposition matrix assuming target 1 is H1 and target 2 is H2, i.e.:

[0144]

[0145] N is the noise matrix, representing the noise power received in each sub-band. Then the least squares estimates of A1 and A2 are:

[0146]

[0147] The maximum likelihood I given that objective 1 is H1 and objective 2 is H2 is defined as:

[0148]

[0149] Where L is the length of the un-overlapping spectral lines.

[0150] d. Repeat steps c through d, iterating through all possible bi-objective TX order combinations to find the combination with the highest likelihood probability I, such as... Figure 12 As shown, the unoverlapping spectral lines of the two targets under this combination are obtained respectively, which can be used for subsequent operations such as angle estimation.

[0151] In some optional embodiments, this application also provides a method for calculating Tx order, see [link to relevant documentation]. Figure 13As shown, the target 2DFFT data can be obtained based on the CFAR results. The DSP is then used to calculate the SISO combine result of the receiving antenna, and after obtaining the energy of each sub-band, the target SNR is determined. The following detailed explanation uses 16T4R as an example: the DSP calculates the 4Rx SISO combine result to obtain the energy of 16 sub-bands, and then determines whether the target SNR is greater than 20dB. If the target SNR is greater than 20dB, doppler aliasing calculation is performed, and it is determined whether the target is doppler aliased. If it is a doppler aliased target, the information of the two targets and the 2DFFT data (i.e., 8T4R) are retained after the calculation. If it is not a doppler aliased target, confidence level 1 and confidence level 2 are calculated, and the confidence level is determined. Similarly, if the target SNR is less than or equal to 20dB, confidence level 1 and confidence level 2 can also be calculated, and the confidence level is determined. If both confidence level 1 and confidence level 2 are greater than the threshold th, the information of that point can be updated and the 2DFFT data (i.e., 8T4R) can be retained; otherwise, the point is deleted.

[0152] In some optional embodiments, this application also provides a peak grouping method, which can be used to delete some unnecessary non-Peak CFAR points and retain some valid non-Peak CFAR points (VRU targets). Figure 14 As shown, taking the Master chip of a cascaded system as an example, this can be implemented in the Master DSP. The method may include:

[0153] A 3*1024 data sliding window space can be preset in the Master to store the CFAR power data of distance units [i-1, i, i+1]. Then, Peak Grouping calculation is performed in the DSP to obtain the CFAR list of the i-th unit of the Master. Subsequently, when the current Master is processing the 2D-FFT and CFAR data of the i+1 distance units, the Peak Grouping module outputs the detection results of the i distance units. That is, the Peak Grouping module causes a delay of one distance unit for its and subsequent processing. In a single data processing operation, the first and last distance units can be ignored.

[0154] In some optional embodiments, this application also provides an Azimuth DBF (digital beamforming) method, which can simultaneously perform Fine CFAR and coarse azimuth angle resolution operations, thereby effectively reducing the consumption of related computational processing resources. For details, please refer to... Figure 15 As shown, the method may include:

[0155] For 2D-FFT rearranged data, the antenna channel coupling calibration can be performed first using the DOA module, such as using a 64*64 matrix for calibration. Then, the 24 channels of the ULA can be filtered using the FFT mux function, for example, filtering out the MIMIO array composed of Tx0, Tx1, Tx6, Tx7 and Rx0~Rx5 (i.e., obtaining the ULA subarray from the sparse main subarray). Next, azimuth windowing is performed, for example, using a Kaiser window with a window length of 24. Then, DBF is performed, such as setting it to full peak mode, with a DBF steering vector length of 128, outputting a maximum of 4 targets. Finally, dynamic range and SNR detection are performed on the output 4 targets, and the targets that meet the dynamic range and SNR requirements are output, i.e., the output... Figure 16 The DBF output detection is shown.

[0156] In some optional embodiments, this application also provides a method for Direction of Arrival (DOA) estimation. For example, in an array design where the main subarray after MIMO has 32 elements (or array components), and it includes a 24-element ULA with an element spacing of one wavelength, and there is angular ambiguity, the DoA estimation process needs to obtain a list of possible ambiguous angles from the angle resolution results of the ULA portion of the main subarray. Orthogonal projection (DML) is then performed on the ambiguity angle list across the entire main subarray to obtain the combination corresponding to the highest likelihood probability, which is the final azimuth estimation list. This approach, by preserving the low sidelobe level of the ULA and allowing for the addition of traditional signal processing windows, makes it feasible to improve resolution and dynamic range. Furthermore, the FIAA algorithm can be used to accelerate the super-resolution algorithm, ensuring the frame rate of the entire radar signal processing.

[0157] For co-prime arrays (referred to as antenna array 1), the DoA estimation method can be: Figure 17 The illustrated process steps, specifically the DoA estimation signal processing flow for coprime arrays, can be implemented using a combined mode where azimuth and elevation angles are calculated separately. First, the azimuth angle is calculated using the primary subarray at the same elevation. Based on the obtained azimuth angle information, the elevation signals corresponding to targets at different azimuth angles are obtained through a signal decomposition module. Then, the DML algorithm is applied to these elevation signals to calculate the elevation angle. The azimuth angle calculation process can include several stages, such as DBF, coarse RNE, and Super Resolution. Specifically:

[0158] DBF stage may include:

[0159] In the DBF stage, the DBF algorithm can be applied to uniform linear arrays with coprime spacing between two array elements, along with a Taylor window, to reduce the sidelobes to -35 dB, thereby achieving the distinction between strong and weak targets. For example... Figure 18 as well as Figure 19 As shown. Since the main subarray is composed of two coprime arrays, the design of coprime arrays can increase the aperture and improve the resolution by using uniform linear arrays that are integer multiples of half the wavelength, while utilizing the coprime relationship between the two uniform linear arrays to solve the problem of angular blurring.

[0160] Optionally, during the DBF stage, after obtaining the angle calculation information of the two coprime arrays, deblurring can be performed based on the coprimity ratio of the two coprime arrays. The coprime arrays designed in this scheme can be 2 wavelengths and 2.5 ULAs respectively, with unblurred angle ranges of (-14.4775°, 14.4775°) and (-11.5370°, 11.5370°). Simulating a target located at 22°, the DBF spectra of the two coprime arrays are as follows: Figure 18 as well as Figure 19 As shown, based on the principle that the fuzzy multiples of two arrays are coprime (there is one and only one peak that overlaps in the fuzzy spectra of the two arrays, see [reference]), this can be achieved. Figure 20 (As shown) the angle ambiguity is solved.

[0161] The Coarse RNE Stage may include:

[0162] In the coarse RNE stage, a rough estimate of the number of sources can be made based on the DBF spectral peak information after windowing two coprime arrays. Simply put, the estimated rough source number is the number of spectral peaks above a certain SNR threshold and within the dynamic range of the maximum peak energy. For example... Figure 21 and Figure 22 As shown, the DBF spectra of two signals with incident angles of ±15° and SNRs of 55dB and 44dB are simulated. In the figure, the SNR threshold and the angular dynamic range are 25dB and 25dB, respectively. The source number estimation principle in the coarse RNE stage is that the number of spectral peaks above the SNR threshold and within the angular dynamic range is the estimated source number. Figure 21 and Figure 22 The number of information sources that meet the above conditions is 2.

[0163] Optionally, based on the estimated number of coarse signal sources, the CFAR target can be classified into three types: single target, dual target, and multi-target. For example, for a single target, subsequent multipath identification and angle super-resolution processing can be omitted, and the process can proceed directly to the final signal decomposition module. For dual targets and multi-target targets, multipath identification can be performed (the DBF spectrum of a multipath target generally presents as a multi-target spectrum; this characteristic can be used to reduce the number of target points in the multipath identification module, thereby reducing the overall system processing time). After this, dual-target solution is completed by a hardware DML engine, while multi-target solution is completed in parallel by the FIAA algorithm implemented on the DSP.

[0164] Super Resolution Stage may include:

[0165] The azimuth super-resolution algorithm module can consist of two parts: a hardware DML engine for solving dual-target problems, and a FIAA algorithm implemented on a DSP for solving signals from more than two azimuth targets. These two parts can be computed in parallel. Furthermore, due to the angular ambiguity of coprime arrays, both parts need to solve the two coprime arrays separately and perform angular de-ambiguation processing.

[0166] Optional, the FIAA spectrum of coprime arrays, such as Figure 23 As shown, simulations were performed with two incident angles of ±5° and SNRs of 55dB and 44dB, respectively. The IAA method offers higher resolution and dynamic range compared to DBF, and the coprime array design allows the FIAA algorithm to provide faster computation and more accurate angle estimation in multi-target scenarios.

[0167] The Elevation Signal Decomposition Stage may include:

[0168] In the Elevation Signal Decomposition module, based on the azimuth information, each subarray (array at the same elevation position) is decomposed into a signal to obtain the elevation solution signal corresponding to different azimuth angles (to compensate for the phase caused by the azimuth angle).

[0169] Assume the array receives signal X after K target MIMOs. M×1 for:

[0170] x M×1 =A M×K (θ,Φ)s K×1 +n M×1

[0171] Where M = M T ×M R M Tand M R Let θ and Φ represent the number of elements in the transmitting and receiving arrays, respectively. sK×1 represents the transmitted signal vector of dimension K. A(Θ, Φ) is the array manifold (a matrix formed by K steering vectors), Θ = {θ1, θ2, ..., θK} is the set of incident azimuth angles, Φ = {φ1, φ2, ..., φK} is the set of incident elevation angles, and n is the noise vector. Furthermore:

[0172] A M×K (θ, φ) = [a (θ1, φ1), a (θ2, φ2), ..., a (θ K , φ K )]

[0173] The guiding vector a(θ, φ) is:

[0174]

[0175] Where dxm and dym are the azimuth and elevation positions of the m-th array element, respectively.

[0176] The transmitted signal s is:

[0177] s = [s1, s2, ..., s K ] T

[0178] Where sk is the signal source of the k-th signal.

[0179] For the MIMO-following array, since the pitch phase term dyl sinφ is a fixed value, therefore

[0180] x (l) =A (l) (Θ,Φ)s+n (l)

[0181] =A (l) (θ)s ele(l) +n (l)

[0182] Where sele(l) can be considered as the synthesized transmitted signal of the first row of the array that contains elevation information but not azimuth information:

[0183]

[0184] Stack sele(l) l=1,2,…,L in rows to form the pitch solution signal sele, with a dimension of L×K, where L is the total number of rows in the MIMO array.

[0185]

[0186] As can be seen from (4.22), as long as sele Once recovered, the pitch angle can be estimated using any DoA estimation algorithm.

[0187] Observing the signal model in (4.21), from the preceding signal processing flow, we can obtain the set of incident angles Θ, and therefore we can obtain the array manifold A(Θ) corresponding to the set of incident angles. From orthogonal projection, we know that:

[0188]

[0189] In (4.23), signal decomposition is implemented (orthogonally projecting the signal to the directions corresponding to different target azimuths, compensating for the phase information of each azimuth angle, and separating the signals of different azimuth angles). Applying equations (4.23) and (4.22) to each row of the array yields the signal for pitch calculation and further processing.

[0190] The Elevation DML Stage may include:

[0191] In the Elevation DML module, the hardware DML engine can be invoked to achieve super-resolution of the pitch signal based on the pitch solution signal obtained in the previous stage.

[0192] Another DoA estimation signal processing procedure for coprime arrays (referred to as antenna array 2) can be as follows: Figure 24 As shown. The DoA estimation signal processing flow for coprime arrays can include separate calculations of azimuth and elevation angles (combined mode). First, the azimuth angle is calculated using the master subarray at the same elevation. Based on the obtained azimuth angle information, the elevation signals corresponding to targets at different azimuth angles are obtained through a signal decomposition module. Then, the DML algorithm is applied to these elevation signals to calculate the elevation angle. The azimuth angle calculation process can include the following stages: DBF, coarse RNE, multipath filter, elevation signal decomposition, and super resolution. The multi-target super-resolution algorithm for azimuth angles in the Super Resolution stage uses the RELAX algorithm.

[0193] DBF Stage may include:

[0194] When antenna array 2 is a sparse array, Taylor windows cannot be added. Therefore, the DBF engine of the hardware RSP can be called during the DBF stage to calculate the azimuth of the main subarray, outputting 4 target angles and 4 spectral peak energies for use in the subsequent coarse estimation stage of the number of sources. If the subsequent coarse estimation stage of the number of sources determines that a certain target point is a single target, the angle corresponding to the maximum energy is retained as the azimuth of that target.

[0195] The Coarse RNE Stage may include:

[0196] The process of roughly estimating the number of information sources can be basically the same as that of antenna array 1, and can be solved only on the main subarray instead of solving on both arrays at the same time. For specific implementation, please refer to the above-mentioned content, which will not be elaborated on here.

[0197] The Elevation DML Stage can use the pitch solution signal obtained in the previous stage to call the hardware DML engine to achieve super-resolution of the pitch signal.

[0198] In another optional embodiment of this application, a DoA estimation signal processing method applicable to ULA arrays (referred to as antenna array 3) is also provided, which can be referred to Figure 25 As shown, this method can be achieved by calculating the azimuth and elevation angles separately (combined mode). First, the azimuth angle is calculated using the main subarray on the same elevation. Then, based on the obtained azimuth angle information, the elevation signals corresponding to targets with different azimuth angles are obtained through the signal decomposition module. Finally, the DML algorithm is applied to these elevation signals to calculate the elevation angles.

[0199] Optionally, for antenna array 3 (ULA), by using a 32-element main subarray with an element spacing of one wavelength after MIMO, to address the angular ambiguity issue, the DoA estimation process requires the angle resolution results of the main subarray to obtain a list of possible ambiguities. This list can then be orthogonally projected (DML) onto the ambiguity angle list in subarray 1 to obtain the combination corresponding to the highest likelihood probability, resulting in the final azimuth estimation list. In this deambiguity method, the subarray does not undergo angle resolution; instead, deambiguity is achieved through projection energy relationships. Furthermore, this array design shares the advantages of antenna array 1. While retaining the low sidelobe level of ULA and the ability to add traditional signal processing windows, it increases the array aperture (compared to a half-wavelength array), making it feasible to improve resolution and dynamic range. Additionally, due to the characteristics of ULA, the FIAA algorithm can be used to accelerate the super-resolution algorithm, ensuring the frame rate of the entire radar signal processing.

[0200] Optionally, in this method, the azimuth calculation process may include several stages: DBF, Angledeambiguity, coarseRNE, Multipath filter, and Super Resolution. Specifically:

[0201] DBF Stage may include:

[0202] In the DBF stage, the DBF algorithm is applied to the principal subarray along with a Taylor window, reducing the sidelobes to -35 dB. This achieves coarse resolution of strong and weak targets, providing input information for subsequent Coarse RNE (coarse source number estimation). For details, please refer to [reference needed]. Figure 26 As shown.

[0203] Angledeambiguity Stage may include:

[0204] In the angle unambiguity stage, assuming the azimuth estimate set (list) obtained from the previous stage is: Θ={θ1,θ2,···,θK}, and the unambiguous angle range (sinθ) is ±n 1, the ambiguity list corresponding to each angle can be obtained from this:

[0205]

[0206] Based on the fuzzy list corresponding to each angle, the fuzzy matching list Ψ = {(γi,γj,···,γt)|γi∈Γ1,γj∈Γ2,···,γt∈ΓK} is obtained. On subarray 1, the signal is projected orthogonally onto the plane corresponding to each element Ψi in Ψ one by one. The angle combination corresponding to the element with the maximum projection energy is the defuzzified azimuth angle list, i.e.:

[0207]

[0208] Where tr represents finding the trace of the matrix, and the Ψi corresponding to the maximum projected energy uniquely corresponds to an angle list, which is the azimuth list after deblurring.

[0209] For example, simulating two incident angles of -45.0653° and 3° (corresponding to angles of 17° and 3° within the unambiguous range of the main subarray in array 3), with an SNR of 40dB, the FIAA spectrum of the 40dB signal is as follows. Figure 27 As shown in the figure, the SNR threshold and the dynamic range of the angle dimension are 25dB and 25dB, respectively. The number of sources estimated in the coarse RNE stage is 2, and the resulting angle estimation list Θ = {3°, 17°} has an unambiguous range (sinθ) of ±12. The ambiguity list corresponding to each angle is as follows:

[0210] Γ1 = {-71.3009°, 3.0229°}

[0211] Γ2={-45.0731°, 16.9773°} (4.26)

[0212] Based on the fuzzy list corresponding to each angle, obtain the angle fuzzy matching list:

[0213] Ψ={(-71.3009°, -45.0731°), (-71.3009°, 16.9773°), (3.0229°, -45.0731°), (3.0229°, 16.9773°)} (4.27)

[0214] From subarray 1, the signal is sent to each element Ψ in Ψ respectively. i The corresponding planes are each subjected to orthographic projection, and the projection energy is as follows: Figures 27-28 As shown in the figure, the maximum projected energy corresponds to Ψ3, which means the final angle obtained is (3.0229°, -45.0731°), matching the simulation parameters.

[0215] The Coarse RNE Stage may include:

[0216] In the coarse RNE stage, a rough estimate of the number of sources is made based on the DBF spectral peak information after windowing of the principal subarray. Simply put, the estimated rough number of sources is the number of spectral peaks above a certain SNR threshold and within the dynamic range of the maximum peak energy. For example... Figure 29 As shown, the DBF spectra of two signals with incident angles of +5° and SNRs of 55dB and 40dB are simulated. The SNR threshold and angular dynamic range are 25dB and 25dB, respectively. The source number estimation principle in the coarse RNE stage is that the number of spectral peaks above the SNR threshold and within the angular dynamic range is the estimated source number. Figure 29 The number of information sources that meet the above conditions is 2.

[0217] Optionally, based on the estimated coarse number of sources, the CFAR target can be classified into three types: single target, dual target, and multi-target. Single targets skip subsequent multipath identification and angle super-resolution processing and proceed directly to the final signal decomposition module. Dual targets and multi-target targets require multipath identification (the DBF spectrum of a multipath target generally resembles a multi-target spectrum; this characteristic can be used to reduce the number of target points in the multipath identification module, thus reducing the overall system processing time). After this, dual-target solving is performed by a hardware DML engine, while multi-target solving is performed in parallel using the FIAA algorithm implemented on the DSP.

[0218] The multipath target recognition algorithm in the Multipath filter Stage is the same as the algorithm described in Antenna Array 1, so it will not be repeated here.

[0219] Super Resolution Stage may include:

[0220] The azimuth super-resolution algorithm module can include two parts: a hardware DML engine for solving dual-target problems, and a FIAA algorithm implemented on the DSP for solving signals from more than two azimuth targets. These two parts can be computed in parallel. Furthermore, due to array angular ambiguity, both parts require angular deblurring processing; the angular deblurring algorithm can be found in the aforementioned Angledeambiguity section.

[0221] Optional, the FIAA spectrum of the ULA array is as follows Figure 30 As shown, the simulations of two incident angles of ±5° and SNRs of 55dB and 44dB respectively demonstrate that the IAA method offers higher resolution and dynamic range compared to DBF. Furthermore, the coprime array design enables the FIAA algorithm to provide faster computation and more accurate angle estimation in multi-target scenarios.

[0222] The Elevation Signal Decomposition Stage may include:

[0223] In the Elevation Signal Decomposition module, each subarray (an array at the same elevation position) is decomposed based on the azimuth information to obtain the elevation solution signal corresponding to different azimuth angles (compensating for the phase caused by the azimuth angle). This part of the algorithm can be referred to the related algorithms in Antenna Array 2, and will not be elaborated on further here.

[0224] The Elevation DML Stage may include:

[0225] In the Elevation DML module, the hardware DML engine can be invoked to achieve super-resolution of the pitch signal based on the pitch solution signal obtained in the previous stage.

[0226] In some optional embodiments, this application also provides a signal processing method based on data distribution. For example, in the MBC waveform mode, the process steps of this method may include... Figure 31 The content shown can include technologies such as Pre-Processing, 2D-FFT, DA-CFAR, Peak grouping, Azimuth DBF, and Super Resolution.

[0227] Specifically:

[0228] Optionally, the pre-processing in this method can refer to the pre-processing operation in the functionally distributed radar signal processing method described above, which will not be elaborated here.

[0229] Optionally, for 2D-FFT, the specific processing flow can be found in [link to documentation]. Figure 32 Perform, for example:

[0230] This allows the Master 2DFFT engine to first obtain the signal (4Rx*768 chirp) of the odd-numbered sequence distance unit in the Slave via C2C; the Slave 2DFFT engine to first obtain the signal (4Rx*768 chirp) of the even-numbered sequence distance unit in the Master via C2C. By using pingpongbufer in PBuf for buffering, assuming that the Master / Slave completes the processing of all Range Gate (256) signals within 30ms, C2C needs to complete the data transmission within the time of processing the current Range Gate. That is, the C2C transmission rate should be greater than 4(Rx)*768(chirp)*32(bit)*0.5(compress ratio) / (30ms / 256(Range Gate))=0.42Gbps. Then, windowing is applied to the velocity dimension (the default is a hanning window). The window length is roughly equal to the number of pulses; for example, the window length for 768 chirps is 768, with a range of 513 to 1024. Afterward, zeros are padded at the end of the data to make the length 1024, and then a 1024-point FFT is performed. Finally, after the 8Rx 2D-FFT is completed, non-coherent accumulation of 8Rx data is performed to obtain the energy spectrum of the range cell. Operations such as statistical histograms are then performed to obtain the median as the radar's estimated noise. Simultaneously, the energy spectrum is output to the DSP, where it is logarithmically quantized into a Uint8 value, which can be used as debug data for output via Ethernet.

[0231] Optionally, for DA-CFAR, the signal processing flow can be found in [reference needed]. Figure 33 As shown. For example:

[0232] After 2D-FFT, coherent accumulation of the antenna's 8Rx channels can be performed first. The number of angles for DA-CFAR is 40°, uniformly distributed in [-60°, 60°]. The CFAR gain for different beams is shown in [link to documentation]. Figure 34 As shown, the gain of DA-CFAR is shown in the figure. Figure 35As shown, the maximum and minimum gain difference can be within 1 dB. Then, after DA-CFAR, the detections of the same target on different sub-bands are merged. Afterwards, TX_order is calculated, and the calculation process can be consistent with the Tx_order calculation of functionally distributed radar, which will not be elaborated here, to sort the 2D-FFT data based on the Tx_order results. It should be noted that in this embodiment, for a cascaded dual-chip system, the processing flow of the Master and Slave can be exactly the same.

[0233] Optionally, for Peak Grouping, the signal processing method can be found in [reference needed]. Figure 36 As shown. For example, the PeakGrouping module is used to delete some unnecessary non-Peak CFAR points and retain some valid non-Peak CFAR points (VRU targets). Its process can be as follows:

[0234] The Peak Grouping module can be initially performed in the Master DSP. A 4*1024 data sliding window is allocated in the Master to store the CFAR power data for distance units [2i-1, 2i, 2i+1, 2i+2]. The data for 2i and 2i+2 are transmitted from the Slave. Then, Peak Grouping calculations are performed in the DSP to obtain the CFAR list for the Master's (2i+1)th distance unit and the Slave's (2i)th distance unit. The Slave's CFAR list for the 2ith distance unit is then transmitted to the Slave. Since the Master is currently processing 2D-FFT and CFAR data for 2i+3 distance units, and the Peak Grouping module outputs detection results for 2i+1 distance units, this results in a 2-distance-unit delay for both the Master and subsequent processing. Similarly, since the Slave is currently processing 2D-FFT and CFAR data for 2i+2 distance units, and the Peak Grouping module outputs detection results for 2i distance units, this also results in a 2-distance-unit delay for the Slave and subsequent processing. Specifically, when processing a single signal processing operation or a frame (or a group) of signals, the first and last distance units may not be processed.

[0235] Optionally, the Azimuth DBF operation can combine the Fine CFAR and coarse azimuth resolution into a single processing step to reduce related computations. For a detailed signal processing flow, please refer to [reference needed]. Figure 37 As shown. For example:

[0236] First, the DOAP module can be used to perform antenna channel coupling calibration, such as using a calibration matrix of size 64*64. Then, the 24 channels of the ULA can be selected using the FFT mux function, such as selecting the MIMIO array composed of Tx0, Tx1, Tx6, Tx7 and Rx0~Rx5. Next, azimuth windowing is performed, such as using a Kaiser window with a window length of 24. DBF is then performed, such as in full peak mode, with a DBF steering vector length of 128, outputting a maximum of 4 targets. Finally, dynamic range and SNR detection are performed on the output targets (e.g., 4 targets). Targets that meet the dynamic range and SNR requirements are output; for details, please refer to [link to documentation]. Figure 38 As shown.

[0237] This application also provides a calibration method, which involves acquiring ADC data using a calibration waveform to complete the calibration operation. For details, please refer to [link to relevant documentation]. Figure 39 As shown. For example:

[0238] 1. Perform range-dimensional FFT processing on the acquired ADC data (one phase calibration code and one amplitude calibration code) to obtain 1DFFT data;

[0239] 2. After obtaining the 1DFFT data corresponding to each set of calibration codes (one phase calibration code and one amplitude calibration code), the data needs to be processed and features extracted.

[0240] a. For each frame of 1DFFT data of the current calibration code, find the target's distance cell on each RX channel of the current TX pair, solve the absolute phase Ph for each chirp target's distance cell, and simultaneously solve the amplitude Po of the target's current position;

[0241] b. Based on the absolute phase of the target obtained from the first chirp in the RX channel, the phase values ​​of all chirp target locations are de-biased to obtain the phase step between chirps, i.e., the relative phase Ph′.

[0242] c. Repeat a to b for all RX;

[0243] d. After traversing all RX channels corresponding to the TX, the amplitude Po of the target on each chirp obtained by all RX channels corresponding to the TX is averaged across all RX channels to obtain the amplitude average Po_ave corresponding to the TX; for the target Ph′ of each chirp obtained by all RX channels corresponding to the TX, the phase error Ph_error between the phase and the theoretical phase needs to be calculated, and then the average of Ph_error across all RX channels is obtained to obtain the phase error average Ph_error_ave;

[0244] e. Repeat a through d for all TX;

[0245] f. Repeat a through e for all frames;

[0246] g. After traversing all frames, the average phase error Ph_error_ave and the average amplitude Po_ave obtained by each TX in each frame are averaged across frames to obtain the final average phase error Ph_error_final_ave and the average amplitude Po_final_ave of the TX. The lengths of Ph_error_final_ave and Po_final_ave are equal to the number of chirps.

[0247] h. Repeat a through g for all calibration codes;

[0248] i. For each set of calibration codes (one amplitude calibration code and one phase calibration code), after obtaining the above phase mean Ph_error_final_ave and amplitude mean Po_final_ave, it is necessary to calculate the mean square error of these two variables. This mean square error can represent the changes in phase and amplitude of the calibration code during the phase modulation process.

[0249] 3. Based on the above results, for each TX, it is necessary to select a set of phase codes corresponding to the minimum values ​​of phase mean square error and amplitude mean square error. This phase code can ensure the accuracy of the transmission phase of each TX during use, as well as the amplitude consistency between chirps, and can significantly improve the leakage level of the final DDM waveform.

[0250] like Figure 40 As shown in the embodiments of this application, a function-based signal processing method is also provided, which can be applied to a dual-chip cascaded radar system. Specifically, refer to the above description of the function-based signal processing method. That is, in the 2D-FFT and preceding operations, the processing between the master and slave is identical. Then, after batch CFA, the master inputs its results to the slave, and the slave, after completing its own CFA of received data, performs aggregation. Then, after the slave performs the corresponding batch DoA operation, the master performs tracking and other operations.

[0251] like Figure 41As shown, this application embodiment also provides another function-based signal processing method, which can also be applied to a dual-chip cascaded radar system. For details, please refer to the above description of the function-based signal processing method. That is, in the 1D-FFT and the preceding operations, the processing between the master and slave is exactly the same. Then the master performs 2D-FFT and DA-CFAR operations and outputs the results to the slave. The slave performs 2D-FFT based on the received data and continues to perform DoA, tracking and other operations in the slave.

[0252] like Figure 42 As shown in the embodiments of this application, another signal processing method based on distributed data is also provided, which can also be applied to dual-chip cascaded radar systems. Specifically, refer to the above description of the signal processing method based on distributed data. That is, in the 1D-FFT and preceding operations, the processing between the master and slave is identical. Then, the master and slave exchange parity index data based on a range gate, allowing each to perform a 2D-FFT operation with half or a preset data size. Then, each continues to perform DA-CFAR, Tx order, and other operations. Finally, the resulting data is aggregated into a single chip for peak grouping, followed by DoA, tracking, and other operations with half or a preset data size. In other words, the entire data signal processing process includes data exchange, data aggregation, and separate processing.

[0253] This application also provides an integrated circuit, which may include a radio frequency (RF) module, an analog signal processing module, and a digital signal processing module connected in sequence. The RF module is used to generate RF transmitted signals and receive RF received signals. The analog signal processing module is used to down-convert the RF received signals to obtain intermediate frequency (IF) signals. The digital signal processing module is used to perform analog-to-digital conversion on the IF signals to obtain digital signals. The RF received signals are echo signals formed by the RF transmitted signals being emitted and / or scattered by a target, or RF signals emitted by other devices. The waveform of the RF signal may be the MBC waveform provided in any embodiment of this application.

[0254] Optionally, the integrated circuit may further include a data processing module for processing digital signals to achieve target detection and / or wireless communication. For example, the integrated circuit may be a radar or a UWB chip (chip or die). The data processing module may be configured to implement digital signal processing operations such as the signal processing methods and / or calibration methods described in any embodiment of this application.

[0255] In an optional embodiment, when the integrated circuit is a millimeter-wave radar chip, the types of digital functional modules in the integrated circuit can be determined according to actual needs. For example, in a millimeter-wave radar chip, the data processing module can be used for range Vidoff transform, velocity Vidoff transform, constant false alarm rate detection, direction of arrival detection, point cloud processing, etc., to acquire information such as the target's range, horizontal angle, pitch angle, velocity, altitude, and micro-Doppler motion characteristics. It can also further generate information such as the target's shape, size, surface roughness, and dielectric properties based on the above-mentioned target-related information.

[0256] In some optional embodiments, the integrated circuit may be an AiP (Antenna-In-Package) chip structure, an AoP (Antenna on Package) chip structure, an AoC (Antenna on Chip) chip structure, or a RoP (Radiator on / through Package) structure. Optionally, the RoP structure can be formed by setting a radiator on the chip package and surrounding the radiator with solder balls to form an air waveguide structure. That is, the radio frequency (RF) signal generated by the chip can be transmitted to an external antenna through the aforementioned radiator structure, the air cavity waveguide structure surrounded by the solder balls, and the air waveguide built into the PCB board, so as to radiate towards the target area.

[0257] According to some other embodiments of this application, an electromagnetic wave device is also proposed. This electromagnetic wave device may include an antenna and an integrated circuit as described above. The integrated circuit is connected to the antenna and is used to transmit and receive electromagnetic wave signals. For example, the electromagnetic wave sensor may include: a carrier, an integrated circuit as described in any of the above embodiments, and an antenna, etc. The integrated circuit may be disposed on the carrier; the antenna may be disposed on the carrier (i.e., the antenna may be an antenna disposed on a PCB board in a structure such as RoP), or integrated with the integrated circuit as a single device disposed on the carrier (i.e., the antenna may be an antenna disposed in a structure such as AiP, AoP, or AoC); wherein the integrated circuit is connected to the antenna (i.e., the sensing chip or integrated circuit does not integrate an antenna, such as a conventional SoC), and is used to transmit and receive electromagnetic wave signals. The carrier may be a printed circuit board (PCB).

[0258] Optionally, the antenna may be an antenna array as described in any embodiment of this application or a virtual array as described in any embodiment of this application.

[0259] In some optional embodiments, the aforementioned electromagnetic wave signal can be a centimeter wave band or a millimeter wave band (such as 3.1GHz, 24GHz, 60GHz, 77GHz, 94GHz, 120GHz, 140GHz, 220GHz, 250GHz, etc.). Specifically, the 3.1GHz centimeter wave signal can include 3.1GHz to 10.6GHz, for example, 3.1GHz, 5GHz, 6GHz, 8GHz, 10.6GHz, etc., or it can be 7.163-8.812GHz, etc.; the 77GHz millimeter wave signal can include signals from 76GHz to 81GHz, for example, frequency ranges such as 76GHz to 77GHz, 77GHz to 79GHz, 79GHz to 81GHz, etc., or fixed frequency points such as 76GHz, 77GHz, 78GHz, 79GHz, 80GHz, 81GHz, etc.

[0260] This application also provides a terminal device, which may include: a device body; and an electromagnetic wave device as described above disposed on the device body; wherein the electromagnetic wave device can be used for target detection and / or communication to provide reference information to the device body, thereby assisting or even controlling the operation of the device body and / or other electronic devices disposed in the device body.

[0261] Specifically, based on the above embodiments, in some optional embodiments of this application, the electromagnetic wave device can be disposed outside the device body or inside the device body. In other optional embodiments of this application, the electromagnetic wave sensor can be partially disposed inside the device body and partially disposed outside the device body. This application does not limit this, and the specific arrangement depends on the circumstances.

[0262] In some alternative embodiments, the aforementioned device body can be a component or product applied in fields such as smart cities, smart homes, transportation, smart homes, consumer electronics, security monitoring, industrial automation, in-cabin detection (such as smart cockpits), medical devices, and healthcare. For example, the device body can be intelligent transportation equipment (such as automobiles, bicycles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as wristbands, glasses, watches, etc.), smart home devices (such as robot vacuum cleaners, door locks, televisions, air conditioners, smart lights, etc.), various communication and office equipment (such as mobile phones, tablets, computers, air mice, keyboards, projectors, etc.), as well as devices such as barriers, intelligent traffic lights, intelligent signs, traffic cameras, and various industrial robotic arms (or robots). It can also be various instruments used to detect vital signs parameters and various devices equipped with such instruments, such as in-cabin vital sign detection in automobiles, indoor personnel monitoring, smart medical devices, and consumer electronic devices.

[0263] For example, when the aforementioned device is a vehicle, the electromagnetic wave device, as an onboard sensor, can be used to assist ADAS systems in achieving onboard applications such as adaptive cruise control, automatic emergency braking (AEB), blind spot detection warning (BSD), lane change assist warning (LCA), rear cross traffic alert (RCTA), assisted / automatic parking assist, rear vehicle warning, collision avoidance, pedestrian detection, and door collision avoidance, automatic opening and closing of the trunk door, etc. It can also be used as a digital key for the vehicle. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0264] The above-described embodiments merely illustrate preferred embodiments of the present invention and the technical principles employed. While the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention. Those skilled in the art can make various obvious changes, readjustments, and substitutions without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the inventive concept, and the scope of protection of this patent is determined by the appended claims.

[0265] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

Claims

1. A radar system, characterized by The radar system comprises at least two radar chips connected in cascade, each radar chip comprising a preprocessing unit, a storage unit and a signal processing unit, wherein: the preprocessing unit is configured to convert a received analog signal into a digital signal and perform fast Fourier transform processing on the digital signal; the storage unit is configured to store data processed by the preprocessing unit; the signal processing unit is configured to process data processed by the preprocessing unit of the radar chip and data processed by the preprocessing units of other radar chips, so as to realize target detection of the radar chip; the radar system further comprises a data control unit connected with the storage unit and the signal processing unit of each radar chip, and configured to select data from the storage units of all radar chips and distribute the data to the signal processing units of all or part of the radar chips connected in cascade.

2. The radar system of claim 1, wherein, The data control unit selects range gate data or Doppler unit data from the storage units of all radar chips and distributes the data to the signal processing units of all or part of the radar chips connected in cascade, and the range gate data distributed to the signal processing unit of one radar chip has the same serial number, or the Doppler unit data distributed to the signal processing unit of one radar chip has the same serial number.

3. The radar system of claim 1, wherein, The data control unit distributes candidate range gate sets to the radar chips in the radar system according to the following formula: Ω(k)=[k:M:max_rng_gate] wherein k is the serial number of the radar chip, M is the number of radar chips participating in signal processing, max_rng_gate is the maximum number of range gates, and Ω(k) is a set of range gates selected every M from the range gate with the serial number k as the starting point until the maximum number of range gates.

4. The radar system of claim 1, wherein, The data control unit distributes candidate Doppler unit sets to the radar chips in the radar system according to the following formula: Ψ(n)=[n:M:max_doppler_bin] wherein n is the serial number of the radar chip, M is the number of radar chips participating in signal processing, max_doppler_bin is the maximum number of Doppler units, and Ψ(n) is a set of Doppler units selected every M from the Doppler unit with the serial number n as the starting point until the maximum number of Doppler units.

5. The radar system of claim 1, wherein, The storage units of the radar chips in the radar system are connected with the storage units of other radar chips through a high-speed data interaction interface.

6. The radar system of claim 1 or 5, wherein, The storage units of all radar chips in the radar system are connected in a ring type daisy chain or form a mesh topology.

7. The radar system according to claim 1 or 3 or 4, wherein: when distributing data to the radar chips, the data distributed each time is a batch, and the signal processing unit of the radar chip is configured to process the data of the previous batch while receiving the data of the current batch.

8. The radar system according to claim 7, wherein: when the data distributed by the data control unit is range gate data, the processing of the data by the signal processing unit of the radar chip comprises Doppler-angle constant false alarm processing and direction of arrival estimation processing. When the data distributed by the data control unit is Doppler unit, the signal processing unit of the radar chip processes the data including range-angle constant false alarm processing and direction of arrival estimation processing.

9. The radar system of claim 1, wherein, The radar system comprises a master chip and at least one slave chip, the master chip is configured to generate a local oscillator signal, the local oscillator signal generated by the master chip is output to a first node through a local oscillator signal output port, and is input to a local oscillator signal input port of each radar chip through the first node, and the length of the wire from the first node to the local oscillator signal input port of each radar chip is the same.

10. The radar system of claim 1, wherein, The radar system comprises a master chip and at least one slave chip, the master chip is configured to generate a reset signal, the reset signal generated by the master chip is output through a reset signal output port, and is input to a reset signal input port of each radar chip through an external wire of the radar chip.

11. A radar chip as a master radar chip in a cascaded radar system, the radar chip comprising a preprocessing unit, a storage unit, a signal processing unit and a data control unit, wherein: The preprocessing unit is configured to convert the received analog signal into a digital signal and perform fast Fourier transform processing on the digital signal; The storage unit is configured to store the data processed by the preprocessing unit; The signal processing unit is configured to receive and process the data processed by the preprocessing unit of the radar chip and other radar chips; The data control unit is connected with the storage unit and the signal processing unit of each radar chip in the cascaded radar system, and is configured to select data from the storage units of all radar chips and distribute the data to the signal processing units of all or part of the radar chips in the cascade.

12. The radar chip of claim 11, wherein, The data control unit selects data from the storage units of all radar chips and distributes the data to the signal processing units of all or part of the radar chips in the cascade, including: The data control unit selects range gate data or Doppler unit from the storage units of all radar chips and distributes the data to the signal processing units of all or part of the radar chips in the cascade, and the range gate data distributed to the signal processing unit of one radar chip has the same serial number, or the Doppler unit distributed to the signal processing unit of one radar chip has the same serial number.

13. The radar chip according to claim 11 or 12, wherein: The data control unit is further configured to distribute data as a batch each time when distributing data to the radar chip, and the signal processing unit is further configured to process the data of the previous batch received while receiving the data of the current batch; When the data distributed by the data control unit is range gate, the signal processing unit processes the data including Doppler-angle constant false alarm processing and direction of arrival estimation processing; when the data distributed by the data control unit is Doppler unit, the signal processing unit processes the data including range-angle constant false alarm processing and direction of arrival estimation processing.

14. The radar chip of claim 11, wherein, The radar chip further comprises a local oscillator signal generation unit for generating a local oscillator signal, the generated local oscillator signal is output to a first node through a local oscillator signal output port of the radar chip, and is input to a local oscillator signal input port of each radar chip in the cascaded radar system through a wire of the first node to the local oscillator signal input port of each radar chip.

15. The radar chip of claim 11, wherein, The radar chip further comprises a reset signal generation unit for generating a reset signal, the generated reset signal is output through a reset signal output port of the radar chip, and is input to a reset signal input port of each radar chip in the cascaded radar system through a wire outside the radar chip.

16. A signal processing method applied to a cascaded radar system, distance gate data or Doppler unit is selected from the storage units of all radar chips in the cascaded radar system, and is assigned to all radar chips or part of the radar chips in the cascaded radar system, and the distance gate data assigned to one radar chip has the same serial number or the Doppler unit has the same serial number.

17. The method of claim 16, wherein, In the 2D-FFT and its previous operations, the processing of the master chip and the slave chip is the same, the master chip inputs the results to the slave chip after the constant false alarm rate processing, and the slave chip collects all the constant false alarm rate processing data after completing the constant false alarm rate processing of its own received data, and the slave chip performs the direction of arrival estimation processing, and the master chip performs the target tracking processing.

18. The method of claim 16, wherein, In the 1D-FFT and its previous operations, the processing of the master chip and the slave chip is the same, the master chip performs the 2D-FFT processing and the Doppler-angle constant false alarm rate processing, and outputs the processing results to the slave chip, the slave chip performs the 2D-FFT processing based on the received data, and continues to perform the direction of arrival estimation processing and the target tracking processing.

19. The method of claim 16, wherein, In the 1D-FFT and its previous operations, the processing of the master chip and the slave chip is the same, the master chip and the slave chip exchange the odd-even serial number data based on the distance gate, so that the master chip and the slave chip each perform half or a preset divided data amount of 2D-FFT operation, the master chip and the slave chip each perform Doppler-angle constant false alarm rate processing and transmission sequence solving processing, and the results are collected into one chip to perform peak aggregation, and then perform half or a preset divided data amount of direction of arrival estimation processing and target tracking processing.

20. An integrated circuit, comprising: The integrated circuit comprises a radio frequency module, an analog signal processing module and a digital signal processing module connected in sequence; the radio frequency module is used to generate a radio frequency transmission signal and receive a radio frequency reception signal; the analog signal processing module is used to down-convert the radio frequency reception signal to obtain an intermediate frequency signal; the digital signal processing module is used to perform analog-to-digital conversion on the intermediate frequency signal to obtain a digital signal; and the digital signal processing module processes the digital signal based on the signal processing method of any one of claims 16-19.

21. The integrated circuit of claim 20, wherein, The integrated circuit is a radar chip or a UWB chip.

22. An electromagnetic wave device, characterized by comprising: It comprises: a carrier body; the integrated circuit according to claim 20 or 21 is arranged on the carrier body; an antenna arranged on the carrier body, or the antenna and the integrated circuit are arranged on the carrier body as an integrated device; The integrated circuit is connected with the antenna and used for transmitting the radio frequency transmitting signal and / or receiving the radio frequency receiving echo signal.

23. A terminal device, comprising: Comprise: A device body; And The electromagnetic wave device as claimed in claim 22 is arranged on the device body. The electromagnetic wave sensor is used for target detection and / or communication to provide reference information for the operation of the device body.

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