Linear voltage regulator circuit and PCB
By detecting changes in load current and dynamically adjusting the bias current of the error amplifier and the compensation capacitor, the slow response and stability issues of low-dropout linear regulators when the load condition changes are solved, achieving dynamic performance optimization and stability improvement over a wide load range.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-28
- Publication Date
- 2026-03-31
AI Technical Summary
Existing low dropout linear regulators (LDOs) suffer from slow response or reduced stability when the load condition changes. In particular, the excessively large compensation capacitor leads to slow response under light load, while the excessively small compensation capacitor leads to reduced stability under heavy load. Furthermore, there is a lack of coordinated optimization between the adjustment of the bias current and the compensation capacitor.
By detecting changes in load current, the bias current of the error amplifier is dynamically adjusted, and multiple sets of switched capacitors are used to achieve compensation, forming a linkage adjustment loop to synchronously adjust the bias current and compensation capacitors to adapt to changes in load conditions.
Under different load conditions, the loop bandwidth, conversion rate and phase margin are optimized to reduce response lag and oscillation, and improve the overall balance and stability of the working performance.
Smart Images
Figure CN121764280A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of linear voltage regulator technology, and in particular to a linear voltage regulator circuit and PCB board. Background Technology
[0002] Currently, there are many optimization schemes for the dynamic performance of low dropout linear regulators (LDOs). For example, by dynamically adjusting the bias current of the error amplifier or the parameters of the compensation network, a balance can be achieved between light-load power consumption and heavy-load response speed. However, these schemes have significant drawbacks: First, only the bias current is adjusted separately without simultaneously adapting the capacitance value of the compensation capacitor. This results in slow response due to an excessively large compensation capacitor under light load, or reduced stability due to an excessively small compensation capacitor under heavy load. Second, although a dynamic compensation capacitor is introduced, the control logic and bias current adjustment are independent of each other, lacking a linkage optimization mechanism between bias and compensation. This makes them prone to oscillation problems during the transient process of the load transitioning from a very light state to a very heavy state.
[0003] It is evident that existing technologies still need improvement and enhancement. Summary of the Invention
[0004] In view of the shortcomings of the prior art, the purpose of this invention is to provide a linear voltage regulator circuit that dynamically adjusts the bias current of the error amplifier by detecting changes in load current, and simultaneously achieves compensation in conjunction with multiple sets of switched capacitors.
[0005] To achieve the above objectives, the present invention adopts the following technical solution: A linear voltage regulator circuit includes a reference voltage generation unit, an error amplifier unit, a feedback resistor unit, a dynamic Miller compensation capacitor unit, an adaptive bias unit, and an output power transistor Mp. The output terminal of the reference voltage generation unit is connected to the input terminal of the error amplifier unit, and the output terminal of the error amplifier unit is connected to the gate of the output power transistor Mp. The feedback resistor unit is disposed between the input terminal of the error amplifier unit and the drain of the output power transistor Mp. The input terminal of the adaptive bias unit is connected to the source of the output power transistor Mp and the input terminal of the error amplifier unit. The output terminal of the adaptive bias unit is connected to the input terminal of the dynamic Miller compensation capacitor unit. The output terminal of the dynamic Miller compensation capacitor unit is connected to the gate of the output power transistor Mp; the reference voltage generation unit is used to generate a reference voltage to provide a reference signal for the error amplifier unit; the feedback resistor unit is used to acquire the output voltage of the output power transistor Mp and generate a feedback voltage based on the output voltage; the error amplifier unit is used to output a drive signal to the output power transistor Mp based on the reference voltage and the feedback voltage; the adaptive bias unit is used to detect the load current change of the output power transistor Mp and generate a bias control signal based on the load current change; the dynamic Miller compensation capacitor unit is used to adjust the Miller compensation capacitor value connected to the output power transistor Mp according to the bias control signal.
[0006] In the linear regulator circuit described above, the reference voltage generation unit includes a first reference resistor Rref1, a second reference resistor Rref2, a third reference resistor Rref3, a first transistor Q1, a second transistor Q2, and an operational amplifier U1. One end of the first reference resistor Rref1 is connected to an external power supply, and the other end of the first reference resistor Rref1 is connected to the collector of the first transistor Q1. The non-inverting input of the operational amplifier U1 is connected to the emitter of the first transistor Q1 and the input of the error amplifier unit. The output of the operational amplifier U1 is connected to the base of the first transistor Q1 and the base of the second transistor Q2. One end of the third reference resistor Rref3 and the collector of the second transistor Q2 are grounded. The other end of the third reference resistor Rref3, one end of the second reference resistor Rref2, and the inverting input of the operational amplifier U1 are connected. The other end of the second reference resistor Rref2 is connected to the emitter of the second transistor Q2.
[0007] In the linear regulator circuit described above, the error amplifier unit includes a first field-effect transistor (FET) M1, a second field-effect transistor (FET) M2, a third field-effect transistor (FET) M3, a fourth field-effect transistor (FET) M4, a fifth field-effect transistor (FET) M5, a sixth field-effect transistor (FET) M6, a ninth field-effect transistor (FET) M9, a first bias resistor Rbias1, and a fourth bias resistor Rbias4. One end of the first bias resistor Rbias1 is connected to an external power supply terminal. The first bias resistor Rbias1 is connected to the source of the sixth field-effect transistor (FET) M6. The drain of the sixth field-effect transistor (FET) M6 is grounded. The gate of the sixth field-effect transistor (FET) M6 and its drain, the gate of the first field-effect transistor (FET) M1, and the output terminal of the reference voltage generation unit are connected. The drain of the first field-effect transistor (FET) M1 is connected to the gate and drain of the third field-effect transistor (FET) M3, the gate and drain of the ninth field-effect transistor (FET) M9, the gate of the fourth field-effect transistor (FET) M4, and the gate of the fifth field-effect transistor (FET) M5. The fifth field-effect transistor M5 is connected to the drain of the output power transistor and the output terminal of the dynamic Miller compensation capacitor unit. The source of the fifth field-effect transistor M5 is connected to the external power supply. The gate of the second field-effect transistor M2 is connected to the feedback resistor unit. The drain of the second field-effect transistor M2 is connected to the drain of the fourth field-effect transistor M4. The sources of the third field-effect transistor M3, the fourth field-effect transistor M4, and the ninth field-effect transistor M9 are grounded. The drain of the ninth field-effect transistor M9 is connected to one end of the fourth bias resistor Rbias4. The other end of the fourth bias resistor Rbias4 is connected to the input terminal of the adaptive bias unit. The source of the first field-effect transistor M1 is connected to the source of the second field-effect transistor M2. The connection node between the sources of the first field-effect transistor M1 and the second field-effect transistor M2 is connected to the input terminal of the adaptive bias unit.
[0008] In the linear regulator circuit, the feedback resistor unit includes a first feedback resistor R1 and a second feedback resistor R2. One end of the first feedback resistor R1 is connected to the drain of the output power transistor Mp, and the other end of the first feedback resistor R1 is connected to one end of the second feedback resistor R2, the gate of the second field-effect transistor M2, and the input terminal of the dynamic Miller compensation capacitor unit. The other end of the second feedback resistor R2 is grounded.
[0009] In the linear regulator circuit, the adaptive bias unit detects the resistor Rs, the differential amplifier U2, the first comparator circuit, and the second comparator circuit. One end of the detection resistor Rs is connected to the source of the output power transistor MP and the non-inverting input of the differential amplifier U2. The other end of the detection resistor Rs and the inverting input of the differential amplifier U2 are connected to an external power supply. The output of the differential amplifier U2 is connected to the input of the first comparator circuit and the second comparator circuit. The connection node between the source of the first field-effect transistor M1 and the source of the second field-effect transistor M2 is connected to the input of the first comparator circuit and the second comparator circuit. The outputs of the first comparator circuit and the second comparator circuit are connected to the input of the dynamic Miller compensation capacitor unit.
[0010] In the linear regulator circuit described above, the first comparator circuit includes a first comparator U3, a first threshold resistor Rth1, a second threshold resistor Rth2, a second bias resistor Rbias2, a first switching transistor Ms1, a seventh field-effect transistor M7, and a tenth field-effect transistor M10. The non-inverting input of the first comparator U3 is connected to the output of the differential amplifier U2. One end of the first threshold resistor Rth1 is connected to an external power supply. The other end of the first threshold resistor Rth1 is connected to one end of the second threshold resistor Rth2 and the inverting input of the first comparator U3. The other end of the second threshold resistor Rth2 is grounded. One end of the second bias resistor Rbias2 is connected to the tenth field-effect transistor. The source of M10 is connected to an external power supply. The gate of the tenth field-effect transistor M10 is connected to the gate of the seventh field-effect transistor M7. The other end of the second bias resistor Rbias2 is connected to the source of the seventh field-effect transistor M7. The drain of the seventh field-effect transistor M7 is grounded. The gate of the seventh field-effect transistor M7 is connected to its drain. The output of the first comparator U3 is connected to the input of the dynamic Miller compensation capacitor unit and the gate of the first switching transistor Ms1. The source of the first switching transistor Ms1 is grounded. The connection node between the drain of the first switching transistor Ms1 and the source of the first field-effect transistor M1 and the source of the second field-effect transistor M2 is connected to the drain of the tenth field-effect transistor M10.
[0011] In the linear regulator circuit described above, the second comparator circuit includes a second comparator U4, a third threshold resistor Rth3, a fourth threshold resistor Rth4, a third bias resistor Rbias3, a second switching transistor Ms2, an eighth field-effect transistor M8, and an eleventh field-effect transistor M11. The non-inverting input of the second comparator U4 is connected to the output of the differential amplifier U2. One end of the third threshold resistor Rth3 is connected to an external power supply. The other end of the third threshold resistor Rth3 is connected to one end of the fourth threshold resistor Rth4 and the inverting input of the second comparator U4. The other end of the fourth threshold resistor Rth4 is grounded. One end of the third bias resistor Rbias3 is connected to the eleventh field-effect transistor. The source of M11 is connected to an external power supply. The gate of the eleventh field-effect transistor M11 is connected to the gate of the eighth field-effect transistor M8. The other end of the third bias resistor Rbias3 is connected to the source of the eighth field-effect transistor M8. The drain of the eighth field-effect transistor M8 is grounded. The gate of the eighth field-effect transistor M8 is connected to its drain. The output of the second comparator U4 is connected to the input of the dynamic Miller compensation capacitor unit and the gate of the second switching transistor Ms2. The source of the second switching transistor Ms2 is grounded. The connection node between the drain of the second switching transistor Ms2 and the source of the first field-effect transistor M1 and the source of the second field-effect transistor M2 is connected to the drain of the eleventh field-effect transistor M11.
[0012] In the linear regulator circuit, the dynamic Miller compensation capacitor unit includes a first compensation capacitor circuit, a second compensation capacitor circuit, and a third compensation capacitor circuit. The output terminals of the first, second, and third compensation capacitor circuits are respectively connected to the gate of the output power transistor Mp. The input terminal of the first compensation capacitor circuit is connected to the output terminal of the first comparator circuit. The input terminals of the second and third compensation capacitor circuits are respectively connected to the output terminal of the second comparator circuit. The gate of the second field-effect transistor M2 is connected to the input terminals of the first, second, and third compensation capacitor circuits.
[0013] In the linear regulator circuit described above, the first compensation capacitor circuit includes a first capacitor, a first capacitor switching transistor MC1, and a first inverter Uinv1; the second compensation capacitor circuit includes a second capacitor, a second capacitor switching transistor MC2, and a second inverter Uinv2; the third compensation capacitor circuit includes a third capacitor and a third capacitor switching transistor MC3; one end of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are respectively connected to the gate of the output power transistor Mp; the other end of the first capacitor C1 is connected to the drain of the first capacitor switching transistor MC1; the gate of the first capacitor switching transistor MC1 is connected to the output terminal of the first inverter Uinv1; and the first inverter Uinv1... The input terminal of v1 is connected to the output terminal of the first comparator circuit. The other end of the second capacitor C2 is connected to the drain of the second capacitor switch MC2. The gate of the second capacitor switch MC2 is connected to the output terminal of the second inverter Uinv2. The input terminal of the second inverter Uinv2 is connected to the output terminal of the second comparator circuit. The other end of the third capacitor C3 is connected to the drain of the third capacitor switch MC3. The gate of the second capacitor switch MC2 is connected to the output terminal of the second comparator circuit. The drains of the first capacitor switch MC1, the second capacitor switch MC2, and the third capacitor switch MC3 are respectively connected to the gate of the second field-effect transistor M2.
[0014] This application also provides a PCB board printed with the linear regulator circuit described above.
[0015] Beneficial effects: This invention provides a linear regulator circuit that, when load conditions change, does not independently adjust the bias current or compensation capacitor separately, but rather adjusts both in a matched manner based on the same load state information. This helps to achieve more coordinated optimization of key dynamic performance parameters such as loop bandwidth, slew rate, and phase margin under different load conditions. Under light load conditions, the bias current and compensation capacitor values can be reduced simultaneously, thereby reducing power consumption and improving transient response speed while maintaining necessary stability. Under heavy load conditions, the bias current and compensation capacitor values can be increased simultaneously, which supports improving loop gain bandwidth and ensuring system stability. This circuit structure can adaptively optimize the dynamic performance of the regulator over a wide load current range, mitigating potential response delays or oscillations during load transient changes and improving the overall balance of performance. Attached Figure Description
[0016] Figure 1 A circuit block diagram of the linear regulator circuit provided by the present invention; Figure 2A circuit diagram of the linear voltage regulator circuit provided by the present invention; Figure 3 A circuit diagram of the reference voltage generation unit of the linear regulator circuit provided by the present invention; Figure 4 The circuit structure diagram of the error amplifier unit of the linear regulator circuit provided by the present invention; Figure 5 The circuit structure diagram of the feedback resistor unit of the linear regulator circuit provided by the present invention; Figure 6 The circuit structure diagram of the dynamic Miller compensation capacitor unit of the linear regulator circuit provided by the present invention; Figure 7 The circuit structure diagram of the adaptive bias unit of the linear regulator circuit provided by the present invention.
[0017] Explanation of key component symbols: 1-Reference voltage generation unit, 2-Error amplifier unit, 3-Feedback resistor unit, 4-Dynamic Miller compensation capacitor unit, 5-Adaptive bias unit. Detailed Implementation
[0018] This invention provides a linear voltage regulator circuit and a PCB board. To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention.
[0019] In the description of this invention, it should be understood that the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.
[0020] Please see Figures 1 to 7This invention provides a linear voltage regulator circuit, including a reference voltage generation unit 1, an error amplifier unit 2, a feedback resistor unit 3, a dynamic Miller compensation capacitor unit 4, an adaptive bias unit 5, and an output power transistor Mp. The output terminal of the reference voltage generation unit 1 is connected to the input terminal of the error amplifier unit 2, and the output terminal of the error amplifier unit 2 is connected to the gate of the output power transistor Mp. The feedback resistor unit 3 is disposed between the input terminal of the error amplifier unit 2 and the drain of the output power transistor Mp. The input terminal of the adaptive bias unit 5 is connected to the source of the output power transistor Mp and the input terminal of the error amplifier unit 2. The output terminal of the adaptive bias unit 5 is connected to the gate of the dynamic Miller compensation capacitor unit 4. The input terminal is connected, and the output terminal of the dynamic Miller compensation capacitor unit 4 is connected to the gate of the output power transistor Mp; the reference voltage generation unit 1 is used to generate a reference voltage to provide a reference signal for the error amplifier unit 2; the feedback resistor unit 3 is used to acquire the output voltage of the output power transistor Mp and generate a feedback voltage based on the output voltage; the error amplifier unit 2 is used to output a drive signal to the output power transistor Mp based on the reference voltage and the feedback voltage; the adaptive bias unit 5 is used to detect the load current change of the output power transistor Mp and generate a bias control signal based on the load current change; the dynamic Miller compensation capacitor unit 4 is used to adjust the Miller compensation capacitor value connected to the output power transistor Mp according to the bias control signal.
[0021] In this embodiment, this application constructs a linkage adjustment loop with load current as a common criterion. When load conditions change, the circuit does not adjust the bias current or compensation capacitor independently and separately, but rather adjusts both in a matched manner based on the same load state information. This helps to achieve more coordinated optimization of key dynamic performance parameters such as loop bandwidth, slew rate, and phase margin under different load conditions. Under light load conditions, the bias current and compensation capacitor values can be reduced simultaneously, thereby reducing power consumption and improving transient response speed while maintaining necessary stability; under heavy load conditions, the bias current and compensation capacitor values can be increased simultaneously, which provides support for improving loop gain bandwidth and ensuring system stability. This circuit structure can adaptively optimize the dynamic performance of the regulator over a wide load current range, reducing the response sluggishness or oscillation that may occur during load transient changes, and improving the overall balance of operating performance.
[0022] The working principle of this application is as follows: Reference voltage generation unit 1 generates a stable reference voltage, which serves as the target value for system regulation. Error amplifier unit 2 compares and amplifies the reference voltage received at its input with the feedback voltage from feedback resistor unit 3. Feedback resistor unit 3 performs voltage division sampling on the output voltage at the drain of output power transistor Mp, thereby generating a feedback voltage proportional to the output voltage. The error amplifier compares the difference between these two voltages and generates a corresponding drive signal, which is applied to the gate of output power transistor Mp to regulate the conduction level of Mp, ultimately stabilizing the output voltage at a preset value.
[0023] The adaptive bias unit 5 is connected to the source of the output power transistor Mp through its input terminal, enabling it to directly or indirectly sense changes in the load current flowing through Mp. This unit converts the change in load current into a corresponding bias control signal. This control signal acts on two targets simultaneously: first, it is fed to the error amplifier unit 2 to dynamically adjust the bias current level of its internal amplifier; second, it is output to the input terminal of the dynamic Miller compensation capacitor unit 4.
[0024] The dynamic Miller compensation capacitor unit 4 adjusts its equivalent Miller compensation capacitor value connected between the error amplifier output (i.e., the power transistor gate) and the feedback node in real time according to the received bias control signal. Under light load, a large capacitance value is connected to meet the low power consumption requirements under light load; under heavy load, it switches to a small capacitance value to avoid overcompensation, so that the bandwidth of the error amplifier unit 2 matches the load requirements and maintains loop stability across the entire load range.
[0025] Furthermore, the quasi-voltage generation unit is used to generate a stable reference voltage to provide a reference signal for the error amplifier unit 2. In one embodiment, the reference voltage generation unit 1 includes a first reference resistor Rref1, a second reference resistor Rref2, a third reference resistor Rref3, a first transistor Q1, a second transistor Q2, and an operational amplifier U1. One end of the first reference resistor Rref1 is connected to an external power supply, and the other end is connected to the collector of the first transistor Q1. The non-inverting input of the operational amplifier U1 is connected to the emitter of the first transistor Q1 and the input of the error amplifier unit 2. The output of the operational amplifier U1 is connected to the base of the first transistor Q1 and the base of the second transistor Q2. One end of the third reference resistor Rref3 and the collector of the second transistor Q2 are grounded, and the other end of the third reference resistor Rref3 is connected to one end of the second reference resistor Rref2 and the inverting input of the operational amplifier U1. The other end of the second reference resistor Rref2 is connected to the emitter of the second transistor Q2. This structure uses resistor voltage division and operational amplifier feedback to form a stable reference voltage output, which helps to improve the accuracy of the reference voltage.
[0026] Specifically, transistors Q1 and Q2 form a pair of bipolar transistors with different current densities. A first reference resistor Rref1 is connected in series with transistor Q1, providing operating current. Operational amplifier U1 forms a negative feedback loop; its non-inverting input is connected to the emitter of transistor Q1 to sample its emitter voltage Vbe1. Its output drives the bases of transistors Q1 and Q2. Transistor Q2, along with second and third reference resistors Rref2 and Rref3, forms another path. The inverting input of operational amplifier U1 is connected to the series node of Rref2 and Rref3 to sample the voltage at that node. Under the closed-loop feedback, operational amplifier U1 continuously adjusts the base voltages of transistors Q1 and Q2 until the voltages at their non-inverting and inverting inputs are equal, achieving a virtual short. This makes the emitter potential of the first transistor Q1 the same as the potential at one end of the second reference resistor Rref2. Since the base voltages of the first transistor Q1 and the second transistor Q2 are the same, and their emitter junction areas are usually in a certain proportion, the collector current flowing through them is controlled by feedback, thereby generating a voltage difference ΔVbe across the second reference resistor Rref2 that is proportional to the absolute temperature. This voltage, combined with the transistor emitter junction voltage Vbe (which has a negative temperature coefficient), ultimately produces a voltage with an approximately zero temperature coefficient at the non-inverting input of the operational amplifier U1, i.e., the reference voltage output node Vref. The voltage across the third reference resistor Rref3 also constitutes part of Vref, and its resistance value can be used to fine-tune the final reference voltage value.
[0027] Further, the error amplifier unit 2 is used to output a drive signal to the output power transistor Mp according to the reference voltage and the feedback voltage. In one embodiment, the error amplifier unit 2 includes a first field-effect transistor M1, a second field-effect transistor M2, a third field-effect transistor M3, a fourth field-effect transistor M4, a fifth field-effect transistor M5, a sixth field-effect transistor M6, a ninth field-effect transistor M9, a first bias resistor Rbias1, and a fourth bias resistor Rbias4. One end of the first bias resistor Rbias1 is connected to an external power supply terminal, and it is connected to the source of the sixth field-effect transistor M6. The drain of the sixth field-effect transistor M6 is grounded, and its gate is connected to its drain, the gate of the first field-effect transistor M1, and the output terminal of the reference voltage generation unit 1. The drain of the first field-effect transistor M1 is connected to the gate and drain of the third field-effect transistor M3, the gate and drain of the ninth field-effect transistor M9, the gate of the fourth field-effect transistor M4, and the gate of the fifth field-effect transistor M5. The drain of the fifth field-effect transistor M5 is connected to the gate of the output power transistor Mp and the output terminal of the dynamic Miller compensation capacitor unit 4, while its source is connected to the external power supply. The gate of the second field-effect transistor M2 is connected to the feedback resistor unit 3, and its drain is connected to the drain of the fourth field-effect transistor M4. The sources of the third field-effect transistor M3, the fourth field-effect transistor M4, and the ninth field-effect transistor M9 are grounded. The drain of the ninth field-effect transistor M9 is connected to one end of the fourth bias resistor Rbias4, and the other end of the fourth bias resistor Rbias4 is connected to the input terminal of the adaptive bias unit 5. The source of the first field-effect transistor M1 and the source of the second field-effect transistor M2 are connected, and this connection node is connected to the input terminal of the adaptive bias unit 5. The error amplifier unit 2 compares the reference voltage with the feedback voltage through a differential pair structure and outputs a drive signal to control the output power transistor. To make the bias current adjustment more stable, a bias path connected to the adaptive bias unit 5 is also provided. The source connection node of the first MOSFET M1 and the second MOSFET M2 (i.e., the tail current source node of the differential pair) is directly connected to the input terminal of the adaptive bias unit 5. This means that the tail current of the entire differential amplifier stage is not fixed, but can be dynamically adjusted by the external circuit according to the load condition. When the adaptive bias unit 5 detects that the amplifier bandwidth needs to be increased, it can inject more current into this node to increase the tail current, thereby improving the transconductance and slew rate of the differential pair and improving the transient response speed; conversely, it can reduce the tail current under light load, which is beneficial to reducing static power consumption. Secondly, through another path formed by the ninth MOSFET M9 and the fourth bias resistor Rbias4, the adaptive bias unit 5 is connected to the reference branch (M3, M9) of the current mirror. This design allows the adaptive bias unit 5 to not only adjust the tail current of the input stage, but also to simultaneously affect the bias current level of the entire current mirror. This ensures that the current ratio between the branches of the current mirror remains relatively stable during the adjustment process, thereby maintaining the common-mode rejection ratio and other performance characteristics of the differential amplifier stage, and avoiding the misalignment or distortion that may be introduced due to drastic changes in the bias point.
[0028] The working principle is as follows: The first field-effect transistor (FET) M1 and the second FET M2 form a differential input pair. The gate of the first FET M1 receives a stable reference voltage Vref from the reference voltage generation unit 1, while the gate of the second FET M2 receives a feedback voltage Vfb from the feedback resistor unit 3. The third FET M3 and the fourth FET M4 form a current mirror, serving as the active load of the differential pair. The sixth FET M6, the first bias resistor Rbias1, and the ninth FET M9 and the fourth bias resistor Rbias4 together provide the basic bias for the amplifier. Specifically, the sixth FET M6 and the first bias resistor Rbias1 are connected in series between the power supply and ground. The gate-drain connection of the sixth FET M6 puts it in the saturation region, generating a reference current. This reference current is mirrored to the current mirror branch formed by the third FET M3, the fourth FET M4, and the ninth FET M9. The fifth field-effect transistor M5 serves as a common-source amplifier stage. Its gate is controlled by the output of the differential amplifier stage (i.e., the drain voltage of the first field-effect transistor M1), and its drain directly drives the gate of the output power transistor Mp.
[0029] The differential input pair transistors (M1 and M2) convert the voltage difference between Vref and Vfb into a differential current. This differential current flows through the active load current mirrors (M3 and M4), and is converted into a single-ended voltage change at the drain node of M1 (i.e., the drain of M3). This voltage change controls the gate of M5, thereby modulating the on-resistance of M5, and ultimately generating a voltage signal at the drain of M5 that strongly drives the gate capacitance of the power transistor Mp, thus amplifying the error and driving the output.
[0030] Further, the feedback resistor unit 3 is used to acquire the output voltage of the output power transistor Mp and generate a feedback voltage based on the output voltage. In one embodiment, the feedback resistor unit 3 includes a first feedback resistor R1 and a second feedback resistor R2. One end of the first feedback resistor R1 is connected to the drain of the output power transistor Mp, and the other end is connected to one end of the second feedback resistor R2, the gate of the second field-effect transistor M2, and the input terminal of the dynamic Miller compensation capacitor unit 4. The other end of the second feedback resistor R2 is grounded. This voltage divider network divides the output voltage and sends it to the error amplifier, forming a feedback loop.
[0031] Further, the adaptive bias unit 5 is used to detect the load current change of the output power transistor Mp and generate a bias control signal based on the load current change. In one embodiment, the adaptive bias unit 5 includes a detection resistor Rs, a differential amplifier U2, a first comparator circuit, and a second comparator circuit. One end of the detection resistor Rs is connected to the source of the output power transistor Mp and the non-inverting input of the differential amplifier U2, and the other end and the inverting input of the differential amplifier U2 are respectively connected to an external power supply. The output of the differential amplifier U2 is connected to the input of the first comparator circuit and the second comparator circuit. The connection node between the source of the first field-effect transistor M1 and the source of the second field-effect transistor M2 is connected to the input of the first comparator circuit and the second comparator circuit. The outputs of the first comparator circuit and the second comparator circuit are respectively connected to the input of the dynamic Miller compensation capacitor unit 4. The detection resistor Rs senses the load current change and converts it into a voltage signal, which is amplified by the differential amplifier and sent to the comparator circuit, thereby generating a control signal corresponding to the load state.
[0032] During operation, when the load current I_load flows through the output power transistor Mp and the sensing resistor Rs, a voltage drop V_rs proportional to the load current I_load is generated across the sensing resistor Rs. The non-inverting input of the differential amplifier U2 is connected to the node between the sensing resistor Rs and the source of the output power transistor Mp, while the inverting input is connected to the external power supply. This connection allows the differential amplifier U2 to amplify and output a sensing voltage signal V_sense that reflects the change in voltage drop V_rs, and is directly proportional to the load current I_load. The sensing voltage signal V_sense becomes the sole electrical characteristic for subsequent circuits to determine the load intensity.
[0033] The first and second comparator circuits are connected in parallel to receive the detected voltage signal V_sense. Each comparator circuit has a preset fixed threshold voltage (Vth1 and Vth2, with Vth2 typically > Vth1) set by a voltage divider resistor network. When the load current is small and the detected voltage signal V_sense is below the first threshold Vth1, the outputs of both the first and second comparator circuits are in an invalid state (e.g., logic low). As the load current increases, the detected voltage signal V_sense first exceeds the first threshold Vth1, triggering the first comparator circuit, whose output jumps to an valid state (e.g., logic high). This valid signal is sent to the dynamic Miller compensation capacitor unit 4 to control the connection of the first set of compensation capacitors; on the other hand, it controls the switching transistor inside the first comparator circuit to turn on, thereby injecting an additional bias current generated by the current mirror into the source connection node (i.e., the tail current node of the differential pair) of the first field-effect transistor M1 and the second field-effect transistor M2 in the error amplifier unit 2. This allows the quiescent operating current of the error amplifier to be initially increased.
[0034] If the load current continues to increase, causing the detected voltage signal V_sense to further exceed a higher second threshold Vth2, the second comparison circuit is also triggered. Its output also becomes valid, and this signal is sent to the dynamic Miller compensation capacitor unit 4 to control the access of an additional compensation capacitor; meanwhile, the switching transistor inside the second comparison circuit conducts, injecting another additional bias current into the tail current node of the error amplifier to achieve the second step increase in the amplifier bias current.
[0035] Specifically, the first comparison circuit includes a first comparator U3, a first threshold resistor Rth1, a second threshold resistor Rth2, a second bias resistor Rbias2, a first switching transistor Ms1, a seventh field-effect transistor M7, and a tenth field-effect transistor M10. The non-inverting input terminal of the first comparator U3 is connected to the output terminal of the differential amplifier U2. One end of the first threshold resistor Rth1 is connected to the external power supply terminal, and its other end is connected to one end of the second threshold resistor Rth2 and the inverting input terminal of the first comparator U3, and the other end of the second threshold resistor Rth2 is grounded. One end of the second bias resistor Rbias2 and the source of the tenth field-effect transistor M10 are respectively connected to the external power supply terminal, and the gate of the tenth field-effect transistor M10 is connected to the gate of the seventh field-effect transistor M7. The other end of the second bias resistor Rbias2 is connected to the source of the seventh field-effect transistor M7, the drain of the seventh field-effect transistor M7 is grounded, and its gate is connected to its drain. The output terminal of the first comparator U3 is connected to the input terminal of the dynamic Miller compensation capacitor unit 4 and the gate of the first switching transistor Ms1. The source of the first switching transistor Ms1 is grounded, and its drain is connected to the connection node of the sources of the first field-effect transistor M1 and the second field-effect transistor M2 and the drain of the tenth field-effect transistor M10. This circuit is triggered when the load current reaches the first threshold, and adjusts the tail current of the error amplifier through the switching transistor and the current mirror structure.
[0036] The working principle is as follows: The threshold setting and comparison link are realized by the first comparator U3 and its peripheral resistor network. The first threshold resistor Rth1 and the second threshold resistor Rth2 are connected in series between the power supply and the ground, forming a voltage divider to establish a fixed first reference threshold voltage Vth1 at the inverting input terminal of the first comparator U3. This voltage Vth1 corresponds to the first-stage load current threshold that is expected to be triggered. At the same time, the detected voltage V_sense, which represents the real-time load current and is output from the differential amplifier U2 in the adaptive bias unit 5, is sent to the non-inverting input terminal of the first comparator U3. When the load current is small and V_sense < Vth1, the output of the first comparator U3 is at a low level. This low-level signal, on the one hand, keeps the corresponding switch in the subsequent connected dynamic Miller compensation capacitor unit 4 off, and on the other hand, also keeps the first switching transistor Ms1 in the cut-off state, and the entire current injection branch does not work.
[0037] When the load current increases to the point that V_sense > Vth1, the comparator state flips, and its output becomes high. This high-level signal is the trigger signal, which is sent to two paths simultaneously: first, directly to the corresponding control terminal of the dynamic Miller compensation capacitor unit 4 as a switching command to turn on the first set of compensation capacitors; second, to the gate of the first switching transistor Ms1, causing it to switch from cutoff to conduction.
[0038] The current mirroring and bias injection circuit is jointly implemented by the seventh field-effect transistor M7, the tenth field-effect transistor M10, the second bias resistor Rbias2, and the first switching transistor Ms1. Specifically, the gate and drain of the seventh field-effect transistor M7 are shorted together and connected to the gate of the tenth field-effect transistor M10, forming a current mirror. The second bias resistor Rbias2 is connected between the power supply and the source of the seventh field-effect transistor M7, and together with the seventh field-effect transistor M7, it defines a reference current I_ref. When the output of the first comparator U3 is high and the first switching transistor Ms1 is turned on, the drain of the tenth field-effect transistor M10 (i.e., the current output terminal) is pulled down to ground potential through the first switching transistor Ms1, which activates the current mirror and turns on the tenth field-effect transistor M10. The tenth field-effect transistor M10 mirrors the reference current I_ref of the seventh field-effect transistor M7 and outputs this mirrored current I_bias_add1 from its drain. The additional current I_bias_add1 is directly injected into the common source node of the first field-effect transistor M1 and the second field-effect transistor M2 in the error amplifier unit 2, that is, the tail current source node of the differential input pair, thereby substantially increasing the static bias current of the error amplifier.
[0039] Specifically, the second comparison circuit includes a second comparator U4, a third threshold resistor Rth3, a fourth threshold resistor Rth4, a third bias resistor Rbias3, a second switching transistor Ms2, an eighth field-effect transistor M8, and an eleventh field-effect transistor M11. The non-inverting input terminal of the second comparator U4 is connected to the output terminal of the differential amplifier U2. One end of the third threshold resistor Rth3 is connected to an external power supply terminal, and the other end thereof is connected to one end of the fourth threshold resistor Rth4 and the inverting input terminal of the second comparator U4, and the other end of the fourth threshold resistor Rth4 is grounded. One end of the third bias resistor Rbias3 and the source electrode of the eleventh field-effect transistor M11 are respectively connected to an external power supply terminal, and the gate electrode of the eleventh field-effect transistor M11 is connected to the gate electrode of the eighth field-effect transistor M8. The other end of the third bias resistor Rbias3 is connected to the source electrode of the eighth field-effect transistor M8, the drain electrode of the eighth field-effect transistor M8 is grounded, and its gate electrode is connected to its drain electrode. The output terminal of the second comparator U4 is connected to the input terminal of the dynamic Miller compensation capacitor unit 4 and the gate electrode of the second switching transistor Ms2. The source electrode of the second switching transistor Ms2 is grounded, and its drain electrode is connected to the connection node of the source electrodes of the first field-effect transistor M1 and the second field-effect transistor M2 and the drain electrode of the eleventh field-effect transistor M11. This circuit is triggered when the load current reaches a higher second threshold, further adjusts the tail current, and realizes multi-level bias control.
[0040] The working principle is as follows: The threshold detection and comparison function of this circuit is completed by the resistor voltage division network composed of the second comparator U4, the third threshold resistor Rth3, and the fourth threshold resistor Rth4. The third threshold resistor Rth3 and the fourth threshold resistor Rth4 are connected in series between the power supply and the ground, and a fixed second reference threshold voltage Vth2 is established at the inverting input terminal of the second comparator U4, and Vth2 > Vthl (the threshold of the first comparison circuit). The detection voltage V_sense representing the load current is also sent to the non-inverting input terminal of the second comparator U4. When the load current does not reach the second-level threshold, that is, V_sense < Vth2, the output of the second comparator U4 is at a low level. This low-level signal makes the corresponding switch in the dynamic Miller compensation capacitor unit 4 controlled by it remain off, and at the same time makes the second switching transistor Ms2 cut off, and this stage current injection branch does not work.
[0041] When the load current continues to increase, resulting in V_sense > Vth2, the state of the second comparator U4 flips, and the output becomes a high level. This high-level trigger signal is sent in parallel to two targets: one is sent to the other control input terminal of the dynamic Miller compensation capacitor unit 4 as an instruction to access the second group (and possibly more) of compensation capacitors; the other is sent to the gate electrode of the second switching transistor Ms2 to make it turn from cut-off to conduction.
[0042] Its current injection mechanism is similar to that of the first comparator circuit, implemented by the eighth field-effect transistor M8, the eleventh field-effect transistor M11, the third bias resistor Rbias3, and the second switch Ms2. The gate-drain of the eighth field-effect transistor M8 is shorted and connected to the gate of the eleventh field-effect transistor M11 to form a current mirror. The third bias resistor Rbias3 is connected in series with the source of the eighth field-effect transistor M8, setting a reference current I_ref2. When the second switch Ms2 is turned on due to the comparator output high level, the drain path of the eleventh field-effect transistor M11 is established, and the current mirror starts to work. The eleventh field-effect transistor M11 mirrors the reference current I_ref2 of the eighth field-effect transistor M8, generating a second-stage additional bias current I_bias_add2, which is injected into the common node of the source of the first field-effect transistor M1 and the second field-effect transistor M2 in the error amplifier unit 2 through the second switch Ms2. At this point, the total tail current of the error amplifier is the sum of the base current, the first-stage additional current I_bias_add1, and the second-stage additional current I_bias_add2, achieving a step-wise increase in the bias current.
[0043] Furthermore, the dynamic Miller compensation capacitor unit 4 is used to adjust the Miller compensation capacitor value connected to the output power transistor Mp according to the bias control signal. In one embodiment, the dynamic Miller compensation capacitor unit 4 includes a first compensation capacitor circuit, a second compensation capacitor circuit, and a third compensation capacitor circuit. The output terminals of the first, second, and third compensation capacitor circuits are respectively connected to the gate of the output power transistor Mp. The input terminal of the first compensation capacitor circuit is connected to the output terminal of the first comparator circuit, and the input terminals of the second and third compensation capacitor circuits are respectively connected to the output terminal of the second comparator circuit. The gate of the second field-effect transistor M2 is connected to the input terminals of the first, second, and third compensation capacitor circuits.
[0044] Specifically, the first compensation capacitor circuit includes a first capacitor C1, a first capacitor switching transistor MC1, and a first inverter Uinv1; the second compensation capacitor circuit includes a second capacitor C2, a second capacitor switching transistor MC2, and a second inverter Uinv2; the third compensation capacitor circuit includes a third capacitor C3 and a third capacitor switching transistor MC3. One end of the first capacitor C1, the second capacitor C2, and the third capacitor C3 are respectively connected to the gate of the output power transistor Mp. The other end of the first capacitor C1 is connected to the drain of the first capacitor switching transistor MC1, the gate of the first capacitor switching transistor MC1 is connected to the output terminal of the first inverter Uinv1, and the input terminal of the first inverter Uinv1 is connected to the output terminal of the first comparator circuit. The other end of the second capacitor C2 is connected to the drain of the second capacitor switching transistor MC2, the gate of the second capacitor switching transistor MC2 is connected to the output terminal of the second inverter Uinv2, and the input terminal of the second inverter Uinv2 is connected to the output terminal of the second comparator circuit. The other end of the third capacitor C3 is connected to the drain of the third capacitor switching transistor MC3, and the gate of the third capacitor switching transistor MC3 is connected to the output of the second comparator circuit. The sources of the first capacitor switching transistor MC1, the second capacitor switching transistor MC2, and the third capacitor switching transistor MC3 are respectively connected to the gate of the second field-effect transistor M2. Through the control signal output by the comparator circuit, each capacitor switching transistor can be turned on or off, thereby dynamically changing the value of the connected compensation capacitor, so that the compensation capacitor is coordinated with the bias current adjustment.
[0045] In this embodiment, the capacitance of the first capacitor C1 can be 10pF, the capacitance of the second capacitor C2 can be 5pF, and the capacitance of the third capacitor C3 can be 2pF. When the first comparator U3 outputs a low level and the second comparator U4 outputs a low level, the first inverter Uinv1 outputs a high level, turning off the first capacitor switch MC1. The second inverter Uinv2 outputs a high level, turning off the second capacitor switch MC2. The third capacitor switch MC3 is turned on because its gate is connected to a low level (the third capacitor C3 is short-circuited). Since only the first capacitor C1 is needed to stabilize the loop under light load, logically the second capacitor C2 does not play a leading role in compensation. With a small capacitance value, its impact on light-load characteristics is weaker than that of the first capacitor C1. In this case, only the first capacitor C1 is connected, and the dynamic Miller compensation capacitor Cc is 10pF. When the first comparator U3 outputs a high level and the second comparator U4 outputs a low level, the first inverter Uinv1 outputs a low level, turning on the first capacitor switch MC1 (short-circuiting the first capacitor C1). The second inverter Uinv2 outputs a high level, turning off the second capacitor switch MC2, and turning on the third capacitor switch MC3 (short-circuiting the third capacitor C3). In this case, only the second capacitor C2 is connected, and the dynamic Miller compensation capacitor Cc is 5pF. When the first comparator U3... When the output is high and the second comparator U4 outputs a high level, the first inverter Uinv1 outputs a low level, turning on the first capacitor switch MC1 (short-circuiting the first capacitor C1). The second inverter Uinv2 outputs a low level, turning on the second capacitor switch MC2 (short-circuiting the second capacitor C2). The third capacitor switch MC3 is turned off because its gate is connected to a high level. At this time, only the third capacitor C3 is connected, and the dynamic Miller compensation capacitor Cc is 2pF. By detecting the load current through the comparator and adapting it to the PMOS switching characteristics through the inverter, dynamic switching (connecting a large capacitor under light load and a small capacitor under heavy load) is achieved, ensuring loop stability across the entire load range.
[0046] During operation, when the load current is low, the control signal output by the adaptive bias unit 5 causes the error amplifier to operate at a low bias current. Simultaneously, the dynamic Miller compensation capacitor unit 4 connects a smaller compensation capacitor, which helps reduce power consumption under light loads and avoids slow response. When the load current increases and exceeds the first threshold, the first comparator circuit is triggered, increasing the bias current of the error amplifier and connecting the first compensation capacitor circuit to increase the compensation capacitor, which helps improve the loop phase margin. When the load current further increases and exceeds the second threshold, the second comparator circuit is triggered, further increasing the bias current and connecting the second and third compensation capacitor circuits to connect a larger compensation capacitor, thereby improving stability under heavy load conditions. Through this linkage adjustment mechanism, the circuit can transition more smoothly during transient load changes, reducing oscillations and improving the overall dynamic performance of the linear regulator.
[0047] This application also provides a PCB board printed with the linear regulator circuit described above.
[0048] In summary, when load conditions change, the circuit does not adjust the bias current or compensation capacitor independently or separately. Instead, it performs matched adjustments based on the same load state information. This adjustment method helps to achieve more coordinated optimization of key dynamic performance parameters such as loop bandwidth, slew rate, and phase margin under different load conditions. Under light load conditions, the bias current and compensation capacitor values can be reduced simultaneously, thereby helping to reduce power consumption and improve transient response speed while maintaining necessary stability. Under heavy load conditions, the bias current and compensation capacitor values can be increased simultaneously, which provides support for improving loop gain bandwidth and ensuring system stability. This circuit structure can adaptively optimize the dynamic performance of the regulator over a wide load current range, mitigating response delays or oscillations that may occur during load transient changes and enhancing the overall balance of performance.
[0049] It is understood that those skilled in the art can make equivalent substitutions or modifications to the technical solution and inventive concept of the present invention, and all such substitutions or modifications should fall within the protection scope of the appended claims.
Claims
1. A linear voltage regulator circuit, characterized by, The reference voltage generating unit, the error amplifier unit, the feedback resistance unit, the dynamic Miller compensation capacitor unit, the adaptive bias unit and the output power tube Mp, the output end of the reference voltage generating unit is connected with the input end of the error amplifier unit, the output end of the error amplifier unit is connected with the gate of the output power tube Mp, the feedback resistance unit is arranged between the input end of the error amplifier unit and the drain of the output power tube Mp, the input end of the adaptive bias unit is connected with the source of the output power tube Mp and the input end of the error amplifier unit, the output end of the adaptive bias unit is connected with the input end of the dynamic Miller compensation capacitor unit, the output end of the dynamic Miller compensation capacitor unit is connected with the gate of the output power tube Mp; The reference voltage generating unit is used for generating a reference voltage, and providing a reference signal for the error amplifier unit; The feedback resistance unit is used for collecting the output voltage of the output power tube Mp, and generating a feedback voltage according to the output voltage; the error amplifier unit is used for outputting a driving signal to the output power tube Mp according to the reference voltage and the feedback voltage; the adaptive bias unit is used for detecting the load current change of the output power tube Mp, and generating a bias control signal according to the load current change; The dynamic Miller compensation capacitor unit is used for adjusting the Miller compensation capacitor value accessed to the output power tube Mp according to the bias control signal.
2. The linear voltage regulator circuit of claim 1, wherein, The reference voltage generating unit comprises a first reference resistance Rref1, a second reference resistance Rref2, a third reference resistance Rref3, a first triode Q1, a second triode Q2 and an operational amplifier U1, one end of the first reference resistance Rref1 is connected with an external power supply end, the other end of the first reference resistance Rref1 is connected with the collector of the first triode Q1, the non-inverting input end of the operational amplifier U1 is connected with the emitter of the first triode Q1 and the input end of the error amplifier unit, the output end of the operational amplifier U1 is connected with the base of the first triode Q1 and the base of the second triode Q2, one end of the third reference resistance Rref3 and the collector of the second triode Q2 are grounded, the other end of the third reference resistance Rref3 is connected with one end of the second reference resistance Rref2 and the inverting input end of the operational amplifier U1, the other end of the second reference resistance Rref2 is connected with the emitter of the second triode Q2.
3. The linear voltage regulator circuit of claim 1, wherein, The error amplifier unit comprises a first field effect transistor M1, a second field effect transistor M2, a third field effect transistor M3, a fourth field effect transistor M4, a fifth field effect transistor M5, a sixth field effect transistor M6, a ninth field effect transistor M9, a first bias resistor Rbias1 and a fourth bias resistor Rbias4, one end of the first bias resistor Rbias1 is connected with an external power supply end, the first bias resistor Rbias1 is connected with the source of the sixth field effect transistor M6, the drain of the sixth field effect transistor M6 is grounded, the gate of the sixth field effect transistor M6 is connected with the drain thereof, the gate of the first field effect transistor M1 and the output end of the reference voltage generating unit, the drain of the first field effect transistor M1 is connected with the gate and the drain of the third field effect transistor M3, the gate and the drain of the ninth field effect transistor M9, the gate of the fourth field effect transistor M4 and the gate of the fifth field effect transistor M5, the drain of the fifth field effect transistor M5 is connected with the gate of the output power transistor and the output end of the dynamic Miller compensation capacitor unit, the source of the fifth field effect transistor M5 is connected with an external power supply end, the gate of the second field effect transistor M2 is connected with the feedback resistance unit, the drain of the second field effect transistor M2 is connected with the drain of the fourth field effect transistor M4, the sources of the third field effect transistor M3, the fourth field effect transistor M4 and the ninth field effect transistor M9 are grounded, the drain of the ninth field effect transistor M9 is connected with one end of the fourth bias resistor Rbias4, the other end of the fourth bias resistor Rbias4 is connected with the input end of the adaptive bias unit, the source of the first field effect transistor M1 and the source of the second field effect transistor M2 are connected, and the connection node of the source of the first field effect transistor M1 and the source of the second field effect transistor M2 is connected with the input end of the adaptive bias unit.
4. The linear voltage regulator circuit of claim 3, wherein, The feedback resistance unit comprises a first feedback resistance R1 and a second feedback resistance R2, one end of the first feedback resistance R1 is connected with the drain of the output power transistor Mp, the other end of the first feedback resistance R1 is connected with one end of the second feedback resistance R2, the gate of the second field effect transistor M2 and the input end of the dynamic Miller compensation capacitor unit, and the other end of the second feedback resistance R2 is grounded.
5. The linear voltage regulator circuit of claim 3, wherein, The adaptive bias unit comprises a detection resistance Rs, a differential amplifier U2, a first comparison circuit and a second comparison circuit, one end of the detection resistance Rs is connected with the source of the output power transistor MP and the non-inverting input end of the differential amplifier U2, the other end of the detection resistance Rs and the inverting input end of the differential amplifier U2 are respectively connected with an external power supply end, the output end of the differential amplifier U2 is connected with the input end of the first comparison circuit and the second comparison circuit, the connection node of the source of the first field effect transistor M1 and the source of the second field effect transistor M2 is connected with the input end of the first comparison circuit and the second comparison circuit, and the output ends of the first comparison circuit and the second comparison circuit are respectively connected with the input end of the dynamic Miller compensation capacitor unit.
6. The linear voltage regulator circuit of claim 5, wherein, The first comparison circuit comprises a first comparator U3, a first threshold resistor Rth1, a second threshold resistor Rth2, a second bias resistor Rbias2, a first switch tube Ms1, a seventh field effect tube M7 and a tenth field effect tube M10, the noninverting input terminal of the first comparator U3 is connected with the output terminal of the differential amplifier U2, one end of the first threshold resistor Rth1 is connected with an external power supply terminal, the other end of the first threshold resistor Rth1 is connected with one end of the second threshold resistor Rth2 and the inverting input terminal of the first comparator U3, the other end of the second threshold resistor Rth2 is grounded, one end of the second bias resistor Rbias2 and the source electrode of the tenth field effect tube M10 are respectively connected with an external power supply terminal, the gate electrode of the tenth field effect tube M10 is connected with the gate electrode of the seventh field effect tube M7, the other end of the second bias resistor Rbias2 is connected with the source electrode of the seventh field effect tube M7, the drain electrode of the seventh field effect tube M7 is grounded, the gate electrode of the seventh field effect tube M7 is connected with the drain electrode thereof, the output terminal of the first comparator U3 is connected with the input terminal of the dynamic Miller compensation capacitor unit and the gate electrode of the first switch tube Ms1, the source electrode of the first switch tube Ms1 is grounded, and the drain electrode of the first switch tube Ms1 is connected with the connection node of the source electrode of the first field effect tube M1 and the source electrode of the second field effect tube M2 and the drain electrode of the tenth field effect tube M10.
7. The linear voltage regulator circuit of claim 5, wherein, The second comparison circuit comprises a second comparator U4, a third threshold resistor Rth3, a fourth threshold resistor Rth4, a third bias resistor Rbias3, a second switch tube Ms2, an eighth field effect tube M8 and an eleventh field effect tube M11, the noninverting input terminal of the second comparator U4 is connected with the output terminal of the differential amplifier U2, one end of the third threshold resistor Rth3 is connected with an external power supply terminal, the other end of the third threshold resistor Rth3 is connected with one end of the fourth threshold resistor Rth4 and the inverting input terminal of the second comparator U4, the other end of the fourth threshold resistor Rth4 is grounded, one end of the third bias resistor Rbias3 and the source electrode of the eleventh field effect tube M11 are respectively connected with an external power supply terminal, the gate electrode of the eleventh field effect tube M11 is connected with the gate electrode of the eighth field effect tube M8, the other end of the third bias resistor Rbias3 is connected with the source electrode of the eighth field effect tube M8, the drain electrode of the eighth field effect tube M8 is grounded, the gate electrode of the eighth field effect tube M8 is connected with the drain electrode thereof, the output terminal of the second comparator U4 is connected with the input terminal of the dynamic Miller compensation capacitor unit and the gate electrode of the second switch tube Ms2, the source electrode of the second switch tube Ms2 is grounded, and the drain electrode of the second switch tube Ms2 is connected with the connection node of the source electrode of the first field effect tube M1 and the source electrode of the second field effect tube M2 and the drain electrode of the eleventh field effect tube M11.
8. The linear voltage regulator circuit of claim 5, wherein, The dynamic Miller compensation capacitor unit comprises a first compensation capacitor circuit, a second compensation capacitor circuit and a third compensation capacitor circuit, the output ends of the first compensation capacitor circuit, the second compensation capacitor circuit and the third compensation capacitor circuit are connected with the gate of the output power tube Mp respectively, the input end of the first compensation capacitor circuit is connected with the output end of the first comparison circuit, the input ends of the second compensation capacitor circuit and the third compensation capacitor circuit are connected with the output end of the second comparison circuit respectively, and the gate of the second field effect tube M2 is connected with the input ends of the first compensation capacitor circuit, the second compensation capacitor circuit and the third compensation capacitor circuit.
9. The linear voltage regulator circuit of claim 8, wherein, The first compensation capacitor circuit comprises a first capacitor, a first capacitor switching tube MC1 and a first inverter Uinv1; the second compensation capacitor circuit comprises a second capacitor, a second capacitor switching tube MC2 and a second inverter Uinv2; the third compensation capacitor circuit comprises a third capacitor and a third capacitor switching tube MC3; one end of the first capacitor C1, the second capacitor C2 and the third capacitor C3 is connected with the gate of the output power tube Mp respectively, the other end of the first capacitor C1 is connected with the drain of the first capacitor switching tube MC1, the gate of the first capacitor switching tube MC1 is connected with the output end of the first inverter Uinv1, the input end of the first inverter Uinv1 is connected with the output end of the first comparison circuit, the other end of the second capacitor C2 is connected with the drain of the second capacitor switching tube MC2, the gate of the second capacitor switching tube MC2 is connected with the output end of the second inverter Uinv2, the input end of the second inverter Uinv2 is connected with the output end of the second comparison circuit, the other end of the third capacitor C3 is connected with the drain of the third capacitor switching tube MC3, the gate of the second capacitor switching tube MC2 is connected with the output end of the second comparison circuit, and the drains of the first capacitor switching tube MC1, the second capacitor switching tube MC2 and the third capacitor switching tube MC3 are connected with the gate of the second field effect tube M2 respectively.
10. A PCB board characterized by, The PCB is printed with the linear voltage regulator circuit as claimed in any one of claims 1-9.