BootROM architecture for storage control chip

Abstract

The embodiment of the invention provides a BootROM architecture for a storage control chip, and relates to the technical field of storage. The BootROM architecture comprises a function library, a hardware abstraction layer, a Boot module and a processor driving module, the function library is used for storing various basic processing functions; the hardware abstraction layer comprises a hardware operation function, and the hardware operation function is used for operating various hardware units of a control component of the storage equipment; the Boot module is used for loading and operating a loading guider and setting a hardware driving function interface according to the identified guiding mode; the processor driving module comprises a processor driving function; and a basic processing function of a hardware unit which is provided by the function library and needs to operate the control component calls a hardware operation function provided by the hardware abstraction layer through a hardware driving function interface provided by the Boot module so as to operate the hardware unit in the storage equipment. According to the BootROM architecture, after a chip is upgraded, a function interface of operation hardware is set by modifying a Boot module to adapt to an invariable function library and a changed hardware abstraction layer.

Description

Technical Field

[0001] This application relates to the field of storage technology, and in particular to a BootROM architecture for storage control chips. Background Technology

[0002] Figure 1A A schematic diagram of a storage device structure is shown. For example... Figure 1A As shown, the storage device includes a host interface component, a control component, an NVM chip (such as NAND flash memory), NOR flash memory / static random access memory SRAM0 and SRAM1. Figure 1B Another schematic diagram of a storage device structure is shown. (For example...) Figure 1B As shown, the storage device includes a control unit and an NVM chip (such as NAND flash memory), and is connected to the host via interfaces such as UART (Universal Asynchronous Receiver / Transmitter), PCIe (Peripheral Component Interconnect Express), and jumpers. The control unit controls data transfer between the host interface and the NVM chip, and is also used for storage management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, the control unit can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit may also include a processor or controller, in which software executes to manipulate the hardware of the control unit to process I / O (Input / Output) commands. The control unit can also be coupled to DRAM and can access the data in the DRAM. The DRAM can store FTL tables and / or cache data for I / O commands (commands sent by the host to the storage device are called I / O commands).

[0003] Figure 1C A schematic diagram of the control component is shown. (For example...) Figure 1CAs shown, the control unit includes a host interface, a host command processing unit, a storage command processing unit, a media interface controller, and a storage media management unit. The host interface receives I / O commands from the host. The host command processing unit generates storage commands based on the I / O commands and provides them to the storage command processing unit. The storage media management unit maintains a logical address to physical address translation for each storage command. For example, the storage media management unit includes an FTL table (explained below). For read commands, the storage media management unit outputs the physical address corresponding to the logical address (LBA) accessed by the storage command. For write commands, the storage media management unit allocates an available physical address and records the mapping between the accessed logical address (LBA) and the allocated physical address. The storage media management unit also maintains functions required for managing the NVM chip, such as garbage collection and wear leveling. Based on the physical address provided by the storage media management unit, the storage command processing unit operates the media interface controller to issue storage media access commands to the NVM chip.

[0004] In storage devices, the FTL (Flash Translation Layer) is used to maintain the mapping information from logical addresses (LBAs) to physical addresses. Logical addresses constitute the storage space of the solid-state storage device as perceived by upper-layer software such as the operating system. Physical addresses are the addresses used to access the physical storage units of the solid-state storage device. In related technologies, intermediate address formats can also be used for address mapping. For example, a logical address can be mapped to an intermediate address, and then the intermediate address can be further mapped to a physical address. The table structure that stores the mapping information from logical addresses to physical addresses is called the FTL table. The FTL table is important metadata in the storage device. The data items in the FTL table record the address mapping relationships in the storage device, unit by unit.

[0005] exist Figure 1A and Figure 1BIn this system, the host interface is compatible with various communication methods, including SATA (Serial Advanced Technology Attachment), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), SAS (Serial Attached SCSI), Ethernet, and Fibre Channel, for exchanging data with the host. The control unit controls data transfer between the host interface, the NVM chip, and SRAM. It is also used for storage management, mapping host logical addresses to flash physical addresses, erase leveling, and bad block management. The control unit issues commands to the NVM chip according to the NVM chip's interface protocol to operate the NVM chip and receives the command execution results from the NVM chip. Known NVM chip interface protocols include "Toggle" and "ONFI".

[0006] like Figure 1A and Figure 1B As shown, the BootROM is a program embedded within the control unit. It contains the first piece of program code executed by the control unit upon power-on or reset. It can load a bootloader from different devices depending on the boot mode. When the chip's control unit is fabricated, the BootROM is burned into a fixed address space of the chip's ROM (Read-Only Memory). After chip fabrication, the BootROM cannot be modified or upgraded; that is, it cannot be modified during chip use.

[0007] A bootloader is a program that executes during chip startup and is used to load firmware. For storage devices that have not yet been activated or opened, which do not contain a bootloader or firmware (drivers), the BootROM needs to obtain an externally input bootloader and then run it to acquire the firmware. For storage devices that already contain a bootloader and firmware, the BootROM needs to load the bootloader from the storage medium and then run it to load the firmware. This allows the bootloader to be modified or upgraded. Due to the limited capabilities of the BootROM, loading the bootloader needs to be relatively simple so that the BootROM can load the bootloader with a small amount of code. Optional, such as... Figure 1AThe diagram shows a NOR flash memory chip configured in the storage device, where the bootloader image is stored. The bootROM reads the bootloader image from the NOR flash memory. Still optional, such as... Figure 1A As shown, bootloader images are stored in both NAND flash and NOR flash memory. The bootROM reads the bootloader image from either the NAND flash or NOR flash memory. Figure 1B In this example, NOR flash memory was omitted to reduce the cost of the storage device, and the BootROM reads the bootloader image from NAND flash memory.

[0008] Firmware is the program that runs when a control component is functioning properly. Firmware images are much larger than bootloader images. For example... Figure 1A and Figure 1B As shown, the firmware image can be stored in NAND flash memory or NOR flash memory. Optionally, the firmware image can also be sent to the control unit by the host at runtime, and can be upgraded or modified by the user through a specific firmware update process.

[0009] The firmware of a storage device uses the FTL (Flash Translation Layer, a table structure that stores mapping information from logical addresses to physical addresses) to manage the physical storage space provided by NAND flash or NOR flash memory, translating it into read and write operations on a contiguous logical address space. The FTL table itself also needs to be stored in NAND flash or NOR flash memory, and it needs to be read from NAND flash or NOR flash memory for the firmware to function properly. The storage device also uses other metadata not managed by the FTL table. This type of metadata, along with the FTL table, is collectively referred to as configuration data, such as... Figure 1A and Figure 1B As shown, the configuration data stored in NAND flash memory or NOR flash memory is called a configuration image.

[0010] Because of its crucial characteristics of being unalterable and capable of complete booting, once the BootROM is embedded in the ROM, its booting function is fixed. Furthermore, the BootROM cannot be aware of the status of other components on the storage device besides the control unit during operation, thus limiting its usable functions. Since the BootROM is stored in the ROM within the control unit, it is limited by the ROM's capacity. Therefore, the design principle of the BootROM is to be as simple as possible, including completing the necessary work with as little code as possible. Due to these limitations, the BootROM is typically only applicable to specific chips or chips within the same series, and cannot be used with other chips. Summary of the Invention

[0011] In view of this, embodiments of this application provide a boot system. The core function of this boot system is to adapt to changes in the hardware abstraction layer caused by chip upgrades and to adapt to processor updates. Furthermore, this boot system loads a boot loader during chip startup and provides multiple backup boot methods to ensure normal startup even in unexpected situations involving the storage device.

[0012] In a first aspect, embodiments of this application provide a boot system, including: a function library, a hardware abstraction layer, a boot module, and a processor driver module;

[0013] The function library is coupled to the hardware abstraction layer, the boot module, and the processor driver module, respectively, and the function library is used to store various basic processing functions;

[0014] The hardware abstraction layer is coupled to the function library, the boot module, and the processor driver module, respectively. The hardware abstraction layer includes hardware operation functions, which are used to operate various hardware units of the control component of the storage device.

[0015] The bootloader module is coupled to the function library, the hardware abstraction layer, and the processor driver module respectively. The bootloader module is used to load and run the loadloader according to the identified boot mode, and to set the hardware driver function interface.

[0016] The processor driver module includes processor driver functions;

[0017] The basic processing functions provided by the function library for the hardware units that require operation of the control components call the hardware operation functions provided by the hardware abstraction layer through the hardware driver function interface provided by the boot module, in order to operate the hardware units of the control components of the storage device.

[0018] Optionally, the boot mode includes one or more of the following: wake-up module, SPI loading mode, NAND loading mode, UART card activation mode, and NVMe card activation mode;

[0019] The wake-up mode indicates that in response to a wake-up operation detected while the storage device is in a sleep state, the already loaded bootloader is run directly;

[0020] The SPI load mode indicates that a load bootloader is retrieved from the NOR flash memory of the storage device and the load bootloader is run;

[0021] The NAND loading mode instructs the initialization of the media interface controller and NAND flash memory, the acquisition of the loading bootloader from the NAND flash memory, and the execution of the loading bootloader;

[0022] The UART activation mode instruction initializes the asynchronous universal transceiver, receives the load bootloader from the asynchronous universal transceiver, and runs the load bootloader;

[0023] The NVMe activation mode instruction initializes the host interface and host command processing unit, connects to the host interface to load the bootloader, and runs the bootloader.

[0024] Optionally, the boot module determines whether the boot mode is a wake-up mode based on the value of a specified register of the control component. If it is determined that the boot mode is not the wake-up mode, the boot mode is determined based on the value of a specified input / output pin of the control component.

[0025] Optionally, the boot module is also used to configure the program runtime environment and set a default exception handling function, which is used to handle exceptions generated during the startup of the storage device.

[0026] Optionally, the bootloader module further includes: a function table required by the hardware unit of the drive control component and function pointers corresponding to the function table; the basic processing functions provided by the function library that need to operate the hardware unit of the control component are isolated from the hardware abstraction layer through the function table and the function pointers.

[0027] Optionally, the bootloader module further includes attaching hardware operation functions from the hardware abstraction layer to the function pointer; the basic processing functions provided by the function library that require operation of the control component hardware unit obtain the function table and the hardware operation functions through the function pointer.

[0028] Optionally, the bootloader module further includes attaching a callback function to the function pointer; the basic processing functions provided by the function library that require operation of the control component hardware unit call the hardware operation function through the callback function to operate the hardware.

[0029] Optionally, the bootloader system further includes Lib.h; Lib.h includes function interfaces corresponding to the basic processing functions provided by the function library; the bootloader module calls the basic processing functions provided by the function library through the function interfaces provided by Lib.h.

[0030] Optionally, the boot system further includes CPU_port.h; CPU_port.h includes function interfaces corresponding to the processor driver functions provided by the processor driver module; the hardware abstraction layer and the function library call the processor driver functions provided by the processor driver module through the function interfaces provided by CPU_port.h.

[0031] Optionally, the boot module includes a processor boot assembly submodule, a C code entry submodule, a boot submodule, and a hardware unit driver submodule;

[0032] The processor startup assembly submodule is coupled to the C code entry submodule. The processor startup assembly submodule provides the assembly code that the processor executes after power-on and configures the program running environment according to the assembly code.

[0033] The C code entry submodule is coupled to the processor startup assembly submodule and the boot submodule. The C code entry submodule includes a function table required by the driver control component hardware unit and function pointers corresponding to the function table.

[0034] The boot submodule is coupled to the C code entry submodule and the hardware unit driver submodule. The boot submodule is used to load and run the load bootloader according to the identified boot mode.

[0035] The hardware unit driver submodule is coupled to the bootstrap submodule, and the hardware unit driver submodule is the function pointer with a callback function attached.

[0036] Optionally, the processor startup assembly submodule is also used to set the default exception handling function.

[0037] Optionally, the processor startup assembly submodule is located in a first specified address range of the ROM in the storage device, and the first specified address range is mapped to a second specified address range of the processor's memory address space.

[0038] Secondly, embodiments of this application provide a boot method for a storage device, applicable to the boot system provided in any embodiment of this application; the method includes:

[0039] In response to the power-on startup of the storage device, the bootloader is loaded and run according to the identified boot mode;

[0040] The boot system includes a function library that provides basic processing functions for operating the hardware units of the storage device. Through the hardware driver function interface provided by the boot module included in the boot system, the system calls the hardware operation functions provided by the hardware abstraction layer included in the boot system to operate the hardware units of the control components of the storage device.

[0041] Optionally, the method further includes: in response to the power-on startup of the storage device, the processor startup assembly submodule included in the startup boot module configures the program execution environment and sets the default exception handling function; the C code entry submodule included in the startup boot module sets the function table required by the driver control unit hardware unit and the function pointers corresponding to the function table; the boot submodule included in the startup boot module identifies the boot mode, and loads and runs the loader bootloader according to the identified boot mode.

[0042] Optionally, loading and running the bootloader according to the identified boot mode includes:

[0043] If the boot module is identified as being in wake-up mode, the already loaded bootloader will be run directly.

[0044] If the boot mode is identified as SPI loading mode, a loading bootloader is obtained from the NOR flash memory of the storage device and the loading bootloader is run.

[0045] If the boot mode is identified as NAND loading mode, the media interface controller and NAND flash memory are initialized, the loading bootloader is obtained from the NAND flash memory, and the loading bootloader is run.

[0046] If the boot mode is identified as UART card activation mode, initialize the asynchronous universal transceiver, receive the load bootloader from the asynchronous universal transceiver, and run the load bootloader;

[0047] If the boot mode is identified as NVMe activation mode, the host interface and host command processing unit are initialized, the bootloader is loaded from the host interface, and the bootloader is run.

[0048] Optionally, the method further includes: determining whether the boot mode is a wake-up mode based on the value of a designated register of the control unit; and if it is determined that the boot mode is not the wake-up mode, determining the boot mode based on the value of a designated input / output pin of the control unit.

[0049] Thirdly, embodiments of this application provide a storage device, the storage device including a first control component and a second control component, the first control component and the second control component being coupled through an inter-chip interconnect unit, and both the first control component and the second control component including the boot system provided in any embodiment of this application.

[0050] Fourthly, embodiments of this application provide a boot method for a storage device, applied to the storage device provided in the third aspect of embodiments of this application, wherein the storage device includes a first control component and a second control component; the method includes:

[0051] In response to the power-on startup of the storage device, the first control unit and the second control unit respectively determine whether they are the main control unit;

[0052] Once it is determined that it is the primary control component, identify the boot mode;

[0053] If it determines that it is a slave control unit, it waits for the ready signal sent by the master control unit;

[0054] When the main control unit detects that the boot mode is a wake-up mode, the main control unit sends a ready signal to the slave control unit, and the main control unit and the slave control unit respectively run the loaded bootloader;

[0055] When the master control unit recognizes that the boot mode is SPI loading mode, the master control unit obtains the loading bootloader from the NOR flash memory of the storage device, and sets the loading bootloader for the slave control unit; the master control unit sends a ready signal to the slave control unit through the chip interconnect unit, and the master control unit runs the loading bootloader; the slave control unit runs the loading bootloader in response to receiving the ready signal from the master control unit.

[0056] When the main control unit recognizes the boot mode NAND loading mode, it initializes the media interface controller and NAND flash memory, and obtains the loading bootloader from the NAND flash memory; the main control unit sets the loading bootloader for the slave control unit and sets a ready signal to the slave control unit; the main control unit runs the loading bootloader, and the slave control unit runs the loading bootloader in response to receiving the ready signal from the main control unit.

[0057] When the master control unit detects that the boot mode is UART card activation mode, the master control unit initializes the asynchronous universal transceiver and receives the loading bootloader from the asynchronous universal transceiver; the master control unit sets the loading bootloader for the slave control unit and sets a ready signal to the slave control unit; the master control unit runs the loading bootloader, and the slave control unit runs the loading bootloader in response to receiving the ready signal from the master control unit.

[0058] When the main control unit recognizes that the boot mode is NVMe activation mode, the main control unit initializes the host interface and host command processing unit, and receives the loading bootloader from the host interface; the main control unit sets the loading bootloader for the slave control unit and sets a ready signal to the slave control unit; the main control unit runs the loading bootloader, and the slave control unit runs the loading bootloader in response to receiving the ready signal from the main control unit.

[0059] Fifthly, embodiments of this application provide an information processing device, including a memory, a processor, and a program stored in the memory and executable on the processor. When the processor executes the program, it implements the boot method for the storage device provided in any embodiment of this application. Attached Figure Description

[0060] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0061] Figure 1A This diagram illustrates the structure of a storage device in the prior art.

[0062] Figure 1B This diagram illustrates another structural schematic of a storage device in prior art;

[0063] Figure 1C A schematic diagram of the control component is shown;

[0064] Figure 2 This paper shows a schematic diagram of the architecture of the boot system provided in an embodiment of this application;

[0065] Figure 3 This invention provides a schematic diagram of another boot system according to an embodiment of the present application.

[0066] Figure 4 This paper shows a schematic diagram of the structure of the boot module of the boot system provided in an embodiment of the present application;

[0067] Figure 5 A schematic diagram of the process of booting a storage device based on the boot system provided in the embodiments of this application is shown;

[0068] Figure 6 A schematic diagram of the structure of the storage device provided in an embodiment of this application is shown;

[0069] Figure 7 A schematic diagram of the process of booting a storage device based on the boot system provided in the embodiments of this application is shown. Detailed Implementation

[0070] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0071] Figure 2 This paper illustrates the architecture of the boot ROM provided in an embodiment of this application.

[0072] like Figure 2 As shown, the boot system 200 includes: a function library 201, a hardware abstraction layer 202, a boot module (hereinafter referred to as the Boot module) 203, and a processor driver module 204. The function library 201 is coupled to the Boot module 203, the hardware abstraction layer 202, and the processor driver module 204. The hardware abstraction layer 202 is coupled to the function library 201, the Boot module 203, and the processor driver module 204. The Boot module 203 is coupled to the function library 201, the hardware abstraction layer 202, and the Boot module 203. The processor driver module 204 is coupled to the Boot module 203, the function library 201, and the hardware abstraction layer 202.

[0073] Function library 201 stores various basic processing functions. As an optional example, these basic processing functions may provide features such as character processing and security algorithms. The basic processing functions stored in function library 201 have been verified through tape-out and possess stable and independent characteristics, making them compatible with various versions of boot systems. The basic processing functions provided by function library 201 include functions that require operation of storage device hardware units (such as accelerators implementing security algorithms) as well as functions that do not require operation of storage device hardware units.

[0074] The hardware abstraction layer 202 includes hardware operation functions for operating various hardware units in the storage device. As an optional example, the hardware operation functions configured in the hardware abstraction layer 202 may be used for: reading values ​​from one-time programmable memory (efuse), initializing hardware units, accessing various queues (e.g., operating on certain hardware units through queues and obtaining operation results provided by the hardware units), and reading and writing NAND flash memory through the media interface controller.

[0075] Boot module 203 is used to load and run the bootloader according to the identified boot mode, and to set up the hardware driver function interface.

[0076] In optional embodiments, the boot system provides one or more of the following boot modes: wake-up mode, SPI loading mode, NAND loading mode, UART unlocking mode, and NVMe unlocking mode. These boot modes are used to distinguish different operating modes after the control unit is started. Wake-up mode indicates that the control unit previously went into hibernation and needs to be started upon waking from hibernation. SPI loading mode and NAND loading mode occur after the storage device is powered on, and are distinguished based on the location of the bootloader. NAND loading mode is executed when the bootloader is located in NAND flash memory, and SPI loading mode is executed when the bootloader needs to be obtained via the SPI interface. UART unlocking mode and NVMe unlocking mode occur after the storage device is manufactured at the factory and a bootloader needs to be installed, and are distinguished based on the interface used to transmit the bootloader.

[0077] Boot module 203 identifies whether it is in wake-up mode by accessing the value of a designated register inside the chip. If the value of the designated register indicates that it is not in wake-up mode, Boot module 203 identifies the boot mode by the value of a designated I / O pin. The boot system of this embodiment provides multiple boot modes to ensure the normal boot of the storage device and to ensure normal boot even if the storage device encounters unexpected situations.

[0078] Wake-up mode indicates that if a wake-up operation is detected while the chip is in sleep mode, the bootloader within the chip will be run directly. SPI load mode indicates that the bootloader is obtained from NOR flash memory and run. NAND load mode indicates that the media interface controller and NAND flash memory are initialized, the bootloader is obtained from NAND flash memory, and run. UART unlock mode indicates that the UART is initialized, the bootloader is received via the UART, and run. NVMe unlock mode indicates that the host interface and host command processing unit are initialized, the bootloader is received via the host interface, and run. Optionally, if the boot mode identified by the Boot module 201 is SPI load mode or NAND load mode, it will be processed according to the SPI load mode or NAND load mode. If the operation fails, it indicates that no bootloader is installed in the storage device or the bootloader is faulty, and then it will switch to UART mode or NVMe unlock mode to obtain the bootloader again.

[0079] Boot module 203 provides the function interface required by function library 201 to operate hardware units. Function library 201 calls hardware operation functions in hardware abstraction layer 202 through the function interface provided by Boot module 203.

[0080] In optional embodiments, the chip may be upgraded. After the chip is upgraded, the types and operating methods of the hardware units within the chip may change, resulting in a change in the hardware abstraction layer. Consequently, it is necessary to modify the functions in the function library that need to operate on the hardware. To avoid changing the function library, a hardware driver function interface is provided to the function library at runtime through the Boot module, allowing the functions in the function library to operate on the required hardware units, thus adapting the unchanged function library to the changed hardware abstraction layer.

[0081] In an optional embodiment, the Boot module 203 is also used to configure the program runtime environment and set a default exception handling function. This exception handling function is used to handle exceptions that occur during device startup. Under normal circumstances, the storage device should not generate exceptions during startup. Therefore, exceptions that need to be handled by this default exception handling function represent a failure that has occurred during the startup of the storage device, and the corresponding handling may be, for example, shutdown or alarm, to protect the storage device from damage.

[0082] In an optional embodiment, the Boot module 203 is further configured to configure the function table required to drive the hardware unit and the corresponding function pointers. Functions in the function library 201 that need to operate the hardware are isolated from the hardware abstraction layer through the function table and function pointers. The Boot module 203 also attaches functions or callback functions to the function pointers in the function table. The attached functions are, for example, hardware operation functions in the hardware abstraction layer. Functions in the function library that need to operate the hardware obtain the function table and hardware operation functions through function pointers, thereby enabling hardware operation. For example, after obtaining the operation result from the hardware, the operation result is used by calling a callback function.

[0083] The processor driver module 204 includes processor driver functions. As an optional example, the processor driver functions managed by the processor driver module 204 may be used for: obtaining the processor ID, waking up the processor core, obtaining the processor frequency, etc. Optionally, the processor driver functions managed by the processor driver module 204 may be written in assembly language.

[0084] After upgrading the control component chip or updating its processor core, it is usually necessary to modify the functions in the function library according to the new processor core. To avoid changing the function library, according to the embodiments of this application, the processor driver functions provided by the processor driver module are modified to adapt the unchanged function library to the changed processor core.

[0085] The boot ROM provided in this application embodiment includes a function library that provides various basic processing functions and functions that require hardware operation, a hardware abstraction layer that provides functions for operating the hardware units of the storage device, and a processor driver module that provides processor driver functions and a boot module that sets up function interfaces for operating the hardware. This allows the system to adapt to the unchanged function library and the changed hardware abstraction layer by modifying the function interfaces for operating the hardware in the boot module after chip upgrades or processor updates, and to adapt to the unchanged function library and the changed processor by modifying the processor driver functions configured in the processor driver module.

[0086] Figure 3 A schematic diagram of the boot system provided in another embodiment of this application is shown. For example... Figure 3 As shown, the boot system 300 includes: a function library 301, a hardware abstraction layer 302, a boot module 303, a processor driver module 304, lib.h 305, and cpu_port.h 306. The functions of the function library 301, hardware abstraction layer 302, boot module 303, and processor driver module 304 are similar to... Figure 2 The embodiments shown are the same, and will not be repeated here to avoid repetition.

[0087] lib.h305 is used to configure the function interfaces corresponding to the functions provided by function library 301. The bootstrap module 303 calls the functions in function library 302 through the function interfaces configured in lib.h305.

[0088] cpu_port.h306 is used to configure the function interface corresponding to the processor driver functions in the processor driver module 304. The hardware abstraction layer 302 and the function library 301 call the processor driver functions in the processor driver module through the function interface configured by the processor driver interface configuration module 307.

[0089] Figure 4 A schematic diagram of the bootloader module provided in an embodiment of this application is shown. The function library 401, hardware abstraction layer 402, processor driver module 404, lib.h 405, and cpu_port.h 406 can be referenced. Figure 3 The embodiments shown are not described in detail here to avoid repetition.

[0090] like Figure 4As shown, the boot module 401 includes a processor boot assembly submodule 4031, a C code entry submodule 4032, a boot submodule 4033, and a hardware unit driver submodule 4034. The processor boot assembly submodule 4031 provides assembly code executed by the processor after power-on, used to initialize the processor and configure the program execution environment, such as configuring the C language program execution environment. Optionally, the processor boot assembly submodule 4031 is also used to set a default exception handling function. This exception handling function is used to handle exceptions that occur during device startup. Under normal circumstances, the storage device should not generate exceptions during startup. An exception in the storage device is determined when the execution of the default exception handling function is detected. Optionally, the code of the processor boot assembly submodule is located in a specified address range in ROM, which is mapped to a specified address range in the CPU's memory address space (e.g., an address range starting from 0x0). After the storage device is powered on or reset, the program executes starting from address 0x0.

[0091] The C code entry submodule 4032 is used to configure the function table required by the function library to operate the hardware unit, as well as the function pointers corresponding to the function table. The basic processing functions in the function library that need to operate the hardware are isolated from the hardware abstraction layer through function pointers. The hardware operation functions provided by the hardware abstraction layer can be obtained and called through the function pointers.

[0092] The boot submodule 4033 is used to identify the boot mode selected by the user for the storage device. Based on the selected boot mode, it initializes the corresponding hardware unit and loads and runs the bootloader through the corresponding hardware unit. In optional embodiments, the boot system provides one or more of the following boot modes: wake-up mode, SPI loading mode, NAND loading mode, UART card activation mode, and NVMe card activation mode. The boot submodule 4033 identifies whether it is in wake-up mode by accessing the value of a specified register inside the chip. If the boot submodule 4033 determines that it is not in wake-up mode based on the value of the specified register inside the chip, it identifies the boot mode by the value of a specified I / O pin.

[0093] The wake-up mode indicates that if a wake-up operation is detected while the chip is in sleep mode, the on-chip bootloader will be run directly. The SPI wake-up mode indicates that the bootloader is obtained from the NOR flash memory and run. The NAND boot mode indicates that the media interface controller and NAND flash memory are initialized, the bootloader is obtained from the NAND flash memory, and run. The UART activation mode indicates that the UART is initialized, the bootloader is received via the UART, and run. The NVMe activation mode indicates that the host interface and host command processing unit are initialized, the bootloader is received from the host interface, and run. Optionally, if the boot submodule 403 identifies the boot mode as SPI boot mode or NAND boot mode, it will process according to the SPI boot mode or NAND boot mode. If the process fails, it will switch to UART mode or NVMe activation mode and process according to the UART mode or NVMe activation mode.

[0094] The hardware unit driver submodule 4034 is used to mount callback functions. These callback functions are used, for example, to call functions from a function library. The callback function is invoked after the operation result is obtained from the hardware. This callback function isolates the hardware abstraction layer from the function library.

[0095] Figure 5 A schematic diagram illustrating the process of booting a storage device using a boot system provided in an embodiment of this application is shown. Figure 5 As shown, the method includes:

[0096] Step S501: In response to the power-on of the storage device, the processor in the boot module starts the assembly submodule to configure the program's runtime environment and set the default exception handling function.

[0097] Step S502: Start the C code entry submodule in the boot module to set up the function table required to drive the hardware unit and the function pointers corresponding to the function table.

[0098] Step S503: The boot submodule identifies whether it is in wake-up mode by accessing the value of a specified register inside the chip. If it is determined that it is not in wake-up mode based on the value of the specified register inside the chip, the boot mode is identified by the value of a specified I / O pin.

[0099] Step S504-1: When the boot mode is wake-up mode, run the loaded bootloader.

[0100] Step S504-2: When the boot mode is SPI loading mode, obtain the loading bootloader from the NOR flash memory and run the loading bootloader.

[0101] Step S504-3: When the boot mode is NAND loading mode, initialize the media interface controller and NAND flash memory, obtain the loading bootloader from NAND, and run the loading bootloader.

[0102] Step S504-4: When the boot mode is UART card opening mode, initialize UART, obtain the loading bootloader from the UART interface, and run the loading bootloader.

[0103] Step S504-5: When the boot mode is NVMe card opening mode, initialize the host interface and host command processing unit, receive the loading bootloader from the host interface, and run the loading bootloader.

[0104] In an optional embodiment, to meet the demand for higher performance and larger capacity storage devices, the storage device may include multiple control components that are coupled through inter-chip interconnect links to collaboratively process I / O commands sent by the host.

[0105] Figure 6 A schematic diagram of a storage device is shown. Figure 6 As shown, the storage device includes two control components, namely control component 0 and control component 1. Control component 0 and control component 1 have identical structures and are coupled via an inter-chip interconnect unit (e.g., Chinese patents 2023112407535 / 2023112408006 / 2023112408218 provide a technical solution based on inter-chip interconnect technology to enable two or more control components (chips) to work collaboratively to improve the I / O processing capability of the storage device). Both control component 0 and control component 1 contain a boot system. This boot system is connected to... Figure 2 , Figure 3 or Figure 4 The boot and boot system shown is the same. One of the two master controllers acts as the master control unit, while the other is the slave control unit. Figure 6 In this example, control unit 0 is the master control unit, and control unit 1 is the slave control unit. As an example, the control unit is indicated as either a master or slave control unit by connecting its I / O pins to a specified voltage state via jumpers.

[0106] Figure 7 It shows that according to Figure 6 A schematic diagram of the boot process for a storage device. (Example) Figure 7 As shown, the boot process of a storage device, which includes two control units, includes:

[0107] Step S701: In response to power-on startup, the processor startup assembly submodules in control unit 0 and control unit 1 configure the program runtime environment and set the default exception handling function, respectively.

[0108] Step S702: The C code entry submodules in control unit 0 and control unit 1 set up the function table required to drive the hardware unit and the function pointers corresponding to the function table.

[0109] Step S703: Control unit 0 and control unit 1 initialize their respective inter-chip interconnection units.

[0110] Step S704: Control unit 0 and control unit 1 determine whether they are the main control unit.

[0111] Step S705: If it is determined that it is the main control unit, identify the boot mode.

[0112] Step S706: If it is determined that it is a slave control unit, wait for a ready signal. Optionally, if control unit 0 is the master control unit, the boot submodule of control unit 0 identifies the boot mode, and control unit 1 waits for a ready signal. The ready signal is sent from the master control unit to the slave control unit.

[0113] Step S707-1: When the boot mode is wake-up mode, the main control unit and the loaded bootloader are running.

[0114] Step S707-2: In SPI load mode, the master control unit obtains the load bootloader from the NOR flash memory. The master control unit sets the load bootloader for the slave control unit. The master control unit sends a ready signal to the slave control unit through the inter-chip interconnect unit. The master control unit runs the load bootloader, and the slave control unit, in response to receiving the ready signal from the master control unit, runs the load bootloader.

[0115] Step S707-3: When the boot mode is NAND loading mode, the master control unit initializes the media interface controller and NAND flash memory, and obtains the loading bootloader from the NAND flash memory. The master control unit sets the loading bootloader for the slave control unit and sets a ready signal to the slave control unit. The master control unit runs the loading bootloader. In response to receiving the ready signal from the master control unit, the slave control unit runs the loading bootloader.

[0116] Step S707-4: When the boot mode is UART card opening mode, the main control unit initializes the UART and receives the loading bootloader from the UART. The main control unit sets the loading bootloader for the slave control unit and sets a ready signal to the slave control unit. The main control unit runs the loading bootloader, and the slave control unit, in response to receiving the ready signal from the main control unit, runs the loading bootloader.

[0117] Step S707-5: When the boot mode is NVMe card opening mode, the main control unit initializes the host interface and host command processing unit, and receives the load bootloader from the host interface. The main control unit sets the load bootloader for the slave control unit and sets a ready signal to the slave control unit. The main control unit runs the load bootloader, and the slave control unit, in response to receiving the ready signal from the main control unit, runs the load bootloader.

[0118] In an optional embodiment, when the boot mode is NAND loading mode, since the BootROM is unaware of the configuration of the NAND flash memory used, the NAND flash memory can be initialized and the loading bootloader can be obtained from the NAND according to the solution provided by Chinese Patent CN202211736976.6.

[0119] In an optional embodiment, the boot system also verifies the bootloader during the process of obtaining the bootloader.

[0120] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A startup boot system, characterized by, include: Function libraries, hardware abstraction layer, bootloader module, and processor driver module; The function library is coupled to the hardware abstraction layer, the boot module, and the processor driver module, respectively, and the function library is used to store various basic processing functions; The hardware abstraction layer is coupled to the function library, the boot module, and the processor driver module, respectively. The hardware abstraction layer includes hardware operation functions, which are used to operate various hardware units of the control component of the storage device. The bootloader module is coupled to the function library, the hardware abstraction layer, and the processor driver module respectively. The bootloader module is used to load and run the loadloader according to the identified boot mode, and to set the hardware driver function interface. The processor driver module includes processor driver functions; The basic processing functions provided by the function library for the hardware units that require operation of the control components call the hardware operation functions provided by the hardware abstraction layer through the hardware driver function interface provided by the boot module, in order to operate the hardware units of the control components of the storage device.

2. The system of claim 1, wherein, The boot mode includes one or more of the following: wake-up module, SPI loading mode, NAND loading mode, UART card activation mode, and NVMe card activation mode; The wake-up mode indicates that in response to a wake-up operation detected while the storage device is in a sleep state, the already loaded bootloader is run directly; The SPI load mode indicates that a load bootloader is retrieved from the NOR flash memory of the storage device and the load bootloader is run. The NAND loading mode instructs the initialization of the media interface controller and NAND flash memory, the acquisition of the loading bootloader from the NAND flash memory, and the execution of the loading bootloader; The UART activation mode instruction initializes the asynchronous universal transceiver, receives the load bootloader from the asynchronous universal transceiver, and runs the load bootloader; The NVMe activation mode instruction initializes the host interface and host command processing unit, connects to the host interface to load the bootloader, and runs the bootloader.

3. The system of claim 1 or 2, wherein, The boot module determines whether the boot mode is a wake-up mode based on the value of a specified register of the control component. If the boot mode is not the wake-up mode, the boot mode is determined based on the value of a specified input / output pin of the control component.

4. The system according to any of claims 1-3, characterized in that, The startup and boot module also includes: a function table required by the hardware unit of the drive control component and function pointers corresponding to the function table; The basic processing functions provided by the function library that require operation and control of hardware units are isolated from the hardware abstraction layer through the function table and the function pointer.

5. The system of claim 4, wherein, The boot module also includes attaching hardware operation functions from the hardware abstraction layer to the function pointer; The basic processing functions provided by the function library that require operation of the hardware unit of the control component can obtain the function table and the hardware operation functions through the function pointer.

6. The system according to any one of claims 1-5, characterized in that, The boot module includes a processor boot assembly submodule, a C code entry submodule, a boot submodule, and a hardware unit driver submodule; The processor startup assembly submodule is coupled to the C code entry submodule, and the processor startup assembly submodule provides assembly code executed by a processor after power-on startup and configures a program running environment according to the assembly code; The C code entry submodule is coupled to the processor startup assembly submodule and the boot submodule, and the C code entry submodule includes a function table required by a hardware unit of a drive control component and a function pointer corresponding to the function table; The boot submodule is coupled to the C code entry submodule and the hardware unit drive submodule, and the boot submodule is configured to load and run a loader booter according to an identified boot mode; The hardware unit drive submodule is coupled to the boot submodule, and the hardware unit drive submodule mounts a callback function for the function pointer.

7. A boot-up guide method of a storage device, characterized by, The method is applied to the startup boot system of any one of claims 1-12, and the method comprises: In response to power-on startup of the storage device, a loader booter is loaded and run according to an identified boot mode; A hardware operation function provided by a hardware abstraction layer included in the startup boot system is called through a hardware drive function interface provided by a startup boot module included in the startup boot system, so as to operate a hardware unit of a control component of the storage device.

8. A storage device, comprising: The storage device includes a first control component and a second control component, the first control component is coupled to the second control component through an inter-chip interconnection unit, and the first control component and the second control component each include the startup boot system of any one of claims 1-6.

9. A booting method of a storage device, characterized by, The method is applied to the storage device of claim 88, and the storage device includes a first control component and a second control component; the method comprises: In response to power-on startup of the storage device, the first control component and the second control component respectively determine whether they are master control components; In a case where it is determined that the control component is a master control component, a boot mode is identified; In a case where it is determined that the control component is a slave control component, a ready signal sent by the master control component is waited for; In a case where the master control component identifies that the boot mode is a wake-up mode, the master control component sends a ready signal to the slave control component, and the master control component and the slave control component respectively run the loaded loader booter; In a case where the master control component identifies that the boot mode is an SPI loading mode, the master control component acquires a loader booter from a NOR flash memory of the storage device, sets the loader booter for the slave control component, and sends a ready signal to the slave control component through the inter-chip interconnection unit, and the master control component runs the loader booter, and the slave control component runs the loader booter in response to receiving the ready signal of the master control component; In a case where the master control component identifies that the boot mode is an SPI loading mode, the master control component acquires a loader booter from a NOR flash memory of the storage device, sets the loader booter for the slave control component, and sends a ready signal to the slave control component through the inter-chip interconnection unit, and the master control component runs the loader booter, and the slave control component runs the loader booter in response to receiving the ready signal of the master control component; The main control component initializes the media interface controller and the NAND flash memory in case that the boot mode is identified as the NAND loading mode, and obtains the loading booter from the NAND flash memory; the main control component sets the loading booter for the slave control component, and sets the ready signal for the slave control component; the main control component runs the loading booter, and the slave control component runs the loading booter in response to receiving the ready signal of the main control component. The main control component initializes the asynchronous universal transceiver in case that the boot mode is identified as the UART card opening mode, and receives the loading booter from the asynchronous universal transceiver; the main control component sets the loading booter for the slave control component, and sets the ready signal for the slave control component; the main control component runs the loading booter, and the slave control component runs the loading booter in response to receiving the ready signal of the main control component. The main control component initializes the host interface and the host command processing unit in case that the boot mode is identified as the NVMe card opening mode, and receives the loading booter from the host interface; the main control component sets the loading booter for the slave control component, and sets the ready signal for the slave control component; the main control component runs the loading booter, and the slave control component runs the loading booter in response to receiving the ready signal of the main control component.

10. An information processing apparatus comprising a storage, a processor, and a program stored on the storage and capable of running on the processor, characterized by The processor implements the method in claim 7 or 9 when executing the program. The processor implements the method in claim 7 or 9 when executing the program.

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