Integrated circuit layout design method and integrated circuit

Abstract

An integrated circuit layout design method and an integrated circuit, the method comprising: designing a circuit structure of at least one first component and a circuit structure of at least one second component having a function equivalent to that of the first component, the circuit structure of the first component and the circuit structure of the second component each comprising at least two signal pins, the layout of the at least two signal pins in the circuit structure of the first component is symmetrical to the layout of the at least two signal pins in the circuit structure of the second component; at least one side of each signal pin in the circuit structure of the first component and the second component is provided with a distribution forbidding area used for forbidding wiring of signal lines, and the distribution forbidding areas are adjacent to the positions, corresponding to the signal pins, in the first component and / or the second component or partially cover the positions, corresponding to the signal pins, in the first component and / or the second component; and selecting at least one first component and / or second component according to the direction of the signal line to form one or more modules of the integrated circuit.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of integrated circuit technology, and in particular to an integrated circuit layout design method and an integrated circuit. Background Technology

[0002] Standard cells are pre-designed, verified, and reusable logic functional modules in integrated circuit physical design, used to build complex circuits. They encapsulate complex transistor-level designs into reusable, model-accurate "building blocks," enabling the design and manufacture of complex chips containing billions of transistors through a highly automated Electronic Design Automation (EDA) toolchain.

[0003] In related designs, standard cells are typically unidirectional, meaning that blocks containing these cells can only be translated during placement and cannot be flipped, thus limiting the flexibility of adjusting input / output pin positions. This limitation increases the complexity and difficulty of the physical design (Place and Route, PR) phase, impacting overall design efficiency. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides an integrated circuit layout design method, including: Design a circuit structure for at least one first component and a circuit structure for at least one second component that is functionally equivalent to the first component, wherein the circuit structures of the first component and the second component each include at least two signal pins, and the layout of the at least two signal pins in the circuit structure of the first component is symmetrical to the layout of the at least two signal pins in the circuit structure of the second component. In the circuit structure of the first component and the second component, at least one side of each signal pin is designed with a no-route area to prevent signal line routing, wherein the no-route area is adjacent to or partially covers the position of the corresponding signal pin in the first component and / or the second component. At least one of the first component and / or the second component is selected according to the signal line direction to form one or more modules of the integrated circuit.

[0006] This disclosure also provides an integrated circuit, which includes multiple modules, at least one of which is designed using the integrated circuit layout design method as described in any embodiment of this disclosure.

[0007] The integrated circuit layout design method and integrated circuit provided in this disclosure, by designing a circuit structure of at least one first component and a circuit structure of at least one second component with the same function as the first component, ensure that at least two signal pins are symmetrically arranged in the circuit structures of the first and second components. In the circuit structures of the first and second components, at least one side of each signal pin is designed with a no-route area to prevent signal line routing. The no-route area is adjacent to or partially covers the position of the corresponding signal pin in the first and / or second component, effectively supporting the interchange of signal pin positions. During use, one component can be selected according to circuit connection and layout requirements to meet the layout requirements of different signal line directions, realizing flexible arrangement of signal pin positions in the integrated circuit module. This improves the flexibility of the module in the overall layout, significantly reducing the workload and iterative burden of the physical design stage, shortening the design cycle, reducing manual intervention costs, and improving the overall efficiency of physical design. Simultaneously, it can optimize signal routing, reduce winding length, and further improve circuit performance.

[0008] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0009] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0010] Figure 1 This is a schematic diagram of the layer layout of an exemplary component.

[0011] Figure 2 This is a flowchart illustrating an exemplary embodiment of an integrated circuit layout design method.

[0012] Figure 3 According to Figure 1 A schematic diagram of the layer layout of the first component in the component design.

[0013] Figure 4 According to Figure 1 A schematic diagram of the layer layout of the first and second components of the component design.

[0014] Figure 5 This is a schematic diagram of a module composition method as an exemplary embodiment of the present disclosure.

[0015] Figure 6 This is a schematic diagram of the layer layout (second metal layer only) for another exemplary component.

[0016] Figure 7 According to Figure 6 A schematic diagram of the layer layout of the first and second components of the component design. Detailed Implementation

[0017] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments and features described herein can be combined arbitrarily.

[0018] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" indicate that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, but do not exclude other elements or objects.

[0019] Figure 1 This is a schematic diagram of an exemplary component structure. As shown in Figure 1, the power ground network and critical metal traces on the upper and lower sides of the component are physically fixed. Any flipping operation will inevitably lead to serious power ground (PG) short circuit, signal short circuit, and signal open circuit, thereby compromising the electrical correctness of the circuit. Figure 1 In the diagram, V1 represents the first layer via, which is a conductive channel vertically connecting the first metal layer (Metal1) and the second metal layer (Metal2). Both VDD and VSS power supplies are located on the first metal layer and are used to provide power and ground connections for the chip. Figure 1 The gate layer (GT), VPW (P-type well), VNW (N-type well), and Fin (vertical conductive channel between the source and drain, resembling a fish fin) in the semiconductor process are non-metallic layers used to form fin field-effect transistors (FinFETs).

[0020] like Figure 2 As shown, this disclosure provides an integrated circuit layout design method, including: Step 201: Design a circuit structure of at least one first component and a circuit structure of at least one second component that is functionally equivalent to the first component, wherein the circuit structures of the first component and the second component each include at least two signal pins, and the layout of the at least two signal pins in the circuit structure of the first component is symmetrical to the layout of the at least two signal pins in the circuit structure of the second component. Step 202: In the circuit structure of the first component and the second component, at least one side of each signal pin is designed with a no-route area to prevent signal line routing, wherein the no-route area is adjacent to or partially covers the position of the corresponding signal pin in the first component and / or the second component. Step 203: Select at least one first component and / or a second component according to the signal line direction to form one or more modules of the integrated circuit.

[0021] To achieve flexible swapping of module signal pin positions, this disclosure adopts a "pairing design" scheme, which involves preparing two functionally equivalent but symmetrically arranged first and second components. When the signal line direction of the module changes, the goal is achieved by directly replacing the components rather than flipping them.

[0022] This disclosure embodiment, through the precise design and implementation of two symmetrically laid-out components, ensures seamless verification after replacement. After component replacement, related physical verification (PV, including DRC and LVS) and timing verification can be directly passed without additional, time-consuming iterative corrections. This guarantees the reliability and efficiency of the replacement process. Furthermore, by precisely designing and implementing two symmetrically laid-out components, this disclosure embodiment ensures the consistency of routing resources after replacing different components. That is, through the symmetry of the components, it ensures that the entry and exit positions of all related signal lines are completely consistent with the metal layer after replacing different components. This consistency brings significant engineering benefits: system-level automated routing tools do not need to reroute for this partial replacement. This not only greatly saves design time but also fundamentally avoids the new risks of global timing disorders and signal integrity problems caused by local modifications, thus directly and non-destructively achieving the goal of interchangeable signal pin positions.

[0023] In some exemplary embodiments, the method further includes: when the signal line direction is changed, selecting a second component that is functionally equivalent to at least one first component to replace at least one first component, and / or selecting a first component that is functionally equivalent to at least one second component to replace at least one second component.

[0024] In this embodiment of the disclosure, when it is necessary to change the direction of the signal line, the position arrangement of the key signal pins can be adjusted by replacing one or more first components and / or second components during the Engineering Change Order (ECO) stage, thereby improving the flexibility of the module in the overall layout.

[0025] In some exemplary implementations, such as Figure 3 and Figure 4As shown, at least two signal pins include a first pin and a second pin. In the circuit structure of the first component, both the first pin and the second pin extend along a first direction D1 and are arranged sequentially along a second direction D2, with the first direction D1 and the second direction D2 intersecting. In the circuit structure of the second component, which is functionally equivalent to the first component, both the first pin and the second pin extend along the first direction D1 and are arranged sequentially in the opposite direction of the second direction D2.

[0026] like Figure 3 As shown, the no-closing zone in this embodiment of the disclosure is implemented through M2B (Metal2 Blockage); however, this disclosure does not limit it.

[0027] Figure 3 In the first direction D1 and the second direction D2, they are perpendicular to each other; however, this disclosure does not limit this.

[0028] In some exemplary embodiments, the first pin can be an input pin and the second pin can be an output pin; however, this disclosure is not limiting in this regard. In other exemplary embodiments, the first pin can be an output pin and the second pin can be an input pin.

[0029] like Figure 4 As shown, the length of the first pin in the first component is the same as the length of the first pin in the second component, and the length of the second pin in the first component is the same as the length of the second pin in the second component. However, the first pin and the second pin in the first component are arranged sequentially along the second direction D2, while the first pin and the second pin in the second component are arranged sequentially in the opposite direction of the second direction D2.

[0030] like Figure 4 As shown, the positions of the first pins in the first component and the second component are symmetrical about the circuit structure of the first component (or the second component) along the center line (i.e., the X-axis in the figure) in the second direction D2, and the positions of the second pins in the first component and the second component are symmetrical about the circuit structure of the first component (or the second component) along the center line (i.e., the X-axis in the figure) in the second direction D2.

[0031] In this embodiment of the disclosure, the length of the first pin and the length of the second pin may be equal or unequal, and this disclosure does not impose any restrictions on this.

[0032] In some exemplary embodiments, the length of the first pin is greater than the length of the second pin, and the cloth-gap region includes a first cloth-gap region and a second cloth-gap region. In the circuit structure of the first component, the first cloth-gap region is disposed on both sides of the first pin extending along the first direction D1 and covers a portion of the first pin, and the second cloth-gap region is disposed on both sides of the second pin extending along the first direction D1. In the circuit structure of the second component, the first cloth-gap region is disposed on both sides of the second pin extending along the first direction D1, and the second cloth-gap region is disposed on both sides of the first pin extending along the first direction D1 and covers a portion of the first pin.

[0033] like Figure 4 As shown, since the positions of the pins in the first component and the second component are swapped, the position of the first pin in the second component is the same as the position of the second pin in the first component, and the length of the first pin is greater than the length of the second pin. If the first hold-out area in the first component is only set in the two sides of the first pin extending along the first direction D1, then after the pin positions are swapped, the first hold-out area will be separated from the second pin in the second component by a certain distance, which may cause a short circuit risk due to upper layer routing. This embodiment of the present disclosure sets the first hold-out area in the two sides of the first pin extending along the first direction D1 and covers part of the first pin area. In this way, after the pin positions are swapped, the first hold-out area can still be adjacent to the position of the second pin in the second component, thereby eliminating the short circuit risk caused by upper layer routing.

[0034] In some exemplary embodiments, in the circuit structure of the first component, the portion of the first pin not covered by the first keep-out region is symmetrical about the circuit structure of the first component along the center line (i.e., the Y-axis) of the second direction D2; in the circuit structure of the second component, the portion of the first pin not covered by the second keep-out region is symmetrical about the circuit structure of the second component along the center line (i.e., the Y-axis) of the second direction D2. By rationally planning the symmetry of the signal pins, the reliability and anti-interference capability of the integrated circuit can be improved.

[0035] In some exemplary embodiments, the lengths of the first and second restricted areas are equal or approximately equal; however, this disclosure does not limit this.

[0036] For example, such as Figure 5As shown, Block A and Block B are completely identical in circuit function and internal structure, differing only in the direction of the feedthrough signal. However, due to limitations imposed by the overall signal routing and Block multiplexing rules, Block A can only support translation operations during layout and cannot directly generate the required direction through Y-axis mirroring. Designing a separate Block B with Y-axis mirror symmetry in the input / output signal pin definitions would meet the functional requirements, but would significantly increase the physical design workload, severely impacting development efficiency.

[0037] This disclosure solves the problem of limited signal pin layout flexibility caused by the inability to flip Block A by designing a second component functionally equivalent to the first component, thereby improving the overall efficiency of integrated circuit physical design. For example, Figure 5 Layout a and layout b in this embodiment are a set of layout components conforming to the symmetrical layout standard of this disclosure. Based on the original Block A, simply replacing layout a with layout b allows for the efficient derivation of Block B with different signal flows without reconstructing the overall circuit, thereby enabling flexible interchange of input and output signals between Block A and Block B. This method significantly reduces design redundancy and improves layout efficiency and module reusability while ensuring functional correctness.

[0038] In some exemplary embodiments, at least two signal pins include a third pin and a fourth pin. In the circuit structure of the first component, both the third pin and the fourth pin extend along the first direction D1 and are arranged sequentially along the first direction D1. The first direction D1 intersects with the second direction D2.

[0039] In the circuit structure of the second component, which is functionally equivalent to the first component, both the third and fourth pins extend along the first direction D1 and are arranged sequentially in the opposite direction of the first direction D1.

[0040] like Figure 6 and Figure 7 As shown, the third pin is labeled D and the fourth pin is labeled Q. In the circuit structure of the first component, the third pin D is on the left and the fourth pin Q is on the right; in the circuit structure of the second component, the third pin D is on the right and the fourth pin Q is on the left. That is, in the circuit structures of the first component and the second component, the positions of the third pin D and the fourth pin Q are exactly interchanged.

[0041] In some exemplary embodiments, the length of the third pin D is equal to the length of the fourth pin Q, and the third pin D and the fourth pin Q are symmetrical about the circuit structure of the first component along the center line (i.e., the Y-axis) of the first direction D1; the kill zone includes a third kill zone, which is located in the area between the third pin D and the fourth pin Q in the circuit structures of the first component and the second component.

[0042] In some exemplary embodiments, the circuit structure of at least one first component and a second component that is functionally equivalent to at least one first component both include a fifth pin, which extends along a first direction D1; the kill zone includes a fourth kill zone, in the circuit structure of the first component and the second component, the fourth kill zone is disposed on both sides of the fifth pin extending along the first direction D1 and covers a portion of the fifth pin, and the portion of the fifth pin not covered by the fourth kill zone is symmetrical about the circuit structure of the first component or the second component along the center line of the first direction D1.

[0043] For example, such as Figure 6 and Figure 7 As shown, the fifth pin is labeled CK. In the circuit structure of the first component, the metal trace corresponding to the fifth pin CK covers the middle and left areas of the corresponding trace. In the circuit structure of the second component, the metal trace corresponding to the fifth pin CK covers the middle and right areas of the corresponding trace. This embodiment of the present disclosure sets a fourth keep-out area on both sides of the fifth pin extending along the first direction D1 and covering a portion of the fifth pin CK. The portion of the fifth pin CK not covered by the fourth keep-out area is symmetrical about the circuit structure of the first or second component along the center line (i.e., the Y-axis) of the first direction D1. Thus, when replacing components, the connection position between the upper layer trace and the fifth pin CK does not need to be changed to ensure a normal connection.

[0044] In some exemplary embodiments, the circuit structures of at least one first component and a second component functionally equivalent to the at least one first component both include a first internal trace extending along a first direction D1; the keep-out region includes a fifth keep-out region disposed on both sides of the first internal trace extending along the first direction D1. Since the internal trace does not need to be connected to the upper layer trace, the keep-out layer does not need to be symmetrically arranged.

[0045] For example, such as Figure 6 and Figure 7As shown, this component includes three key signal pins: D (pin 3), Q (pin 4), and CK (pin 5). The effective metal layers of these three pins are symmetrically distributed about the Y-axis. However, looking at the overall second metal layer routing structure, the metal traces of the CK pin and other internal signal lines are not symmetrical. Directly replacing the component under these conditions would cause a short circuit between the internal metal traces and the existing windings at the Block level due to the local asymmetry of the metal traces.

[0046] like Figure 7 As shown, a third hold area JBQ3 is set between the third pin D and the fourth pin Q, and a fourth hold area JBQ4 is set on both sides of the fifth pin CK extending along the first direction D1. Since the length of the fifth pin CK on the left side of the Y-axis is greater than its length on the right side of the Y-axis in the circuit structure of the first component, the fourth hold area JBQ4 is designed to cover part of the fifth pin CK on the left side of the Y-axis in the circuit structure of the first component. A fifth hold area JBQ5 is designed on both sides of each first internal trace L. The fifth hold area JBQ5 only needs to be adjacent to the corresponding first internal trace L and does not need to cover the corresponding first internal trace L.

[0047] This disclosure introduces a third, fourth, and fifth keep-out zone to structurally complete the non-effective wiring area, achieving strict symmetry of the component within the overall "effective wiring area." Specifically, the metal wiring of critical signals requiring symmetry (such as the fifth pin CK) within the effective area is made symmetrical, while keep-out layers are used to fill the routing channels required by other internal signals, thereby physically forming a complete and symmetrical wiring no-go zone. This design ensures that after component replacement, the automatic routing tool at the block level will actively avoid these areas defined by the keep-out zones, fundamentally eliminating the risk of short circuits caused by overlapping traces and achieving seamless replacement.

[0048] In some exemplary embodiments, the pins (or traces) in each trace and the fabric hold-out layer in that trace fill the entire trace; however, this disclosure is not limited to this. In the embodiments of this disclosure, the fabric hold-out layer of each trace is sufficient to ensure that the edges of the pins (or traces) are covered by the fabric hold-out layer before and after the pins (or traces) are swapped.

[0049] The embodiments disclosed herein utilize keep-out zones to fill traces, reflecting a deep consideration of circuit performance. While directly filling the entire trace with a metal layer could solve the symmetry problem, it would introduce additional metal loads, passively increasing signal line length and significantly enhancing parasitic wiring parameters (such as parasitic capacitance and resistance), thereby adversely affecting signal integrity, timing performance, and power consumption. The embodiments disclosed herein employ keep-out zones for non-functional structural completion, achieving the optimal balance between ensuring physical symmetry, avoiding short circuits, and optimizing electrical performance.

[0050] This disclosure also provides an integrated circuit including multiple modules, at least one of which is designed according to the integrated circuit layout design method as described in any embodiment of this disclosure.

[0051] This disclosure utilizes the advantages of modular design in integrated circuits to complete the layout design of integrated circuits, and has the beneficial effects of the integrated circuit layout design method described in any of the above embodiments, which will not be repeated here.

[0052] Although this application has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art based on a reading and understanding of this specification and the accompanying drawings. This application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the aforementioned components, the terminology used to describe such components is intended to correspond to any component (unless otherwise indicated) that performs the specified function of said component (e.g., is functionally equivalent to it), even if structurally not equivalent to the disclosed structure performing the functions in the exemplary implementations of this specification shown herein.

[0053] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0054] Furthermore, it should be understood that in the description of this application, the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Additionally, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. Moreover, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0055] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to implement and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed herein.

Claims

1. An integrated circuit layout design method, characterized in that, include: Design a circuit structure for at least one first component and a circuit structure for at least one second component that is functionally equivalent to the first component, wherein the circuit structures of the first component and the second component each include at least two signal pins, and the layout of the at least two signal pins in the circuit structure of the first component is symmetrical to the layout of the at least two signal pins in the circuit structure of the second component. In the circuit structure of the first component and the second component, at least one side of each signal pin is designed with a no-route area to prevent signal line routing, wherein the no-route area is adjacent to or partially covers the position of the corresponding signal pin in the first component and / or the second component. At least one of the first component and / or the second component is selected according to the signal line direction to form one or more modules of the integrated circuit.

2. The method according to claim 1, characterized in that, The method further includes: When the direction of the signal line is changed, a second component that is functionally equivalent to at least one of the first components is selected to replace at least one of the first components, and / or a first component that is functionally equivalent to at least one of the second components is selected to replace at least one of the second components.

3. The method according to claim 1, characterized in that, The at least two signal pins include a first pin and a second pin. In the circuit structure of the first component, both the first pin and the second pin extend along a first direction and are arranged sequentially along a second direction, with the first direction and the second direction intersecting. In the circuit structure of the second component, which is functionally equivalent to the first component, both the first pin and the second pin extend along the first direction and are arranged sequentially in the opposite direction of the second direction.

4. The method according to claim 3, characterized in that, The length of the first pin is greater than the length of the second pin. The blackout area includes a first blackout area and a second blackout area. In the circuit structure of the first component, the first blackout area is disposed on both sides of the first pin extending along the first direction and covers part of the first pin. The second blackout area is disposed on both sides of the second pin extending along the first direction. In the circuit structure of the second component, the first blackout area is disposed on both sides of the second pin extending along the first direction, and the second blackout area is disposed on both sides of the first pin extending along the first direction and covers a portion of the first pin.

5. The method according to claim 4, characterized in that, In the circuit structure of the first component, the portion of the first pin not covered by the first gag area is symmetrical about the center line of the circuit structure of the first component along the second direction; in the circuit structure of the second component, the portion of the first pin not covered by the second gag area is symmetrical about the center line of the circuit structure of the second component along the second direction.

6. The method according to claim 1, characterized in that, The at least two signal pins include a third pin and a fourth pin. In the circuit structure of the first component, the third pin and the fourth pin both extend along a first direction and are arranged sequentially along the first direction. In the circuit structure of the second component, which is functionally equivalent to the first component, the third and fourth pins both extend along the first direction and are arranged sequentially in the opposite direction to the first direction.

7. The method according to claim 6, characterized in that, The length of the third pin is equal to the length of the fourth pin, and the third pin and the fourth pin are symmetrical about the center line of the circuit structure of the first component along the first direction; the blackout area includes a third blackout area, which is located in the area between the third pin and the fourth pin in the circuit structure of the first component and the second component.

8. The method according to claim 1, characterized in that, The circuit structure of at least one of the first components and a second component that is functionally equivalent to at least one of the first components both include a fifth pin, which extends along a first direction; the guard area includes a fourth guard area, in the circuit structures of the first component and the second component, the fourth guard area is disposed on both sides of the fifth pin extending along the first direction and covers a portion of the fifth pin, and the portion of the fifth pin not covered by the fourth guard area is symmetrical about the centerline of the circuit structure of the first component or the second component along the first direction.

9. The method according to claim 1, characterized in that, The circuit structure of at least one of the first components and a second component that is functionally equivalent to at least one of the first components both include a first internal trace extending along a first direction; the blackout area includes a fifth blackout area disposed on both sides of the first internal trace extending along the first direction.

10. An integrated circuit, characterized in that, It includes multiple modules, at least one of which is designed according to the integrated circuit layout design method as described in any one of claims 1 to 9.

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