Semiconductor memory device

Abstract

A semiconductor memory device includes: a pair of first power supply voltage pads; a second power supply voltage pad; a first data input / output pad connected to the first data output driver; and a second data input / output pad connected to the second data output driver. The first data output driver is connected to one of the pair of first power supply voltage pads, and the second data output driver is connected to the other of the pair of first power supply voltage pads. The first data input / output pad is disposed between one of the pair of first power supply voltage pads and the second power supply voltage pad, and the second data input / output pad is disposed between the other of the pair of first power supply voltage pads and the second power supply voltage pad.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0129688, filed with the Korean Intellectual Property Office on September 25, 2024, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The embodiments of this disclosure generally relate to a semiconductor memory device. Background Technology

[0004] The semiconductor memory device receives write data from the memory controller and transmits read data to the memory controller.

[0005] In synchronous semiconductor memory devices, both the memory controller and the semiconductor memory device operate synchronously with the system clock. When data is transferred between the memory controller and the semiconductor memory device, skew may occur between the data and the system clock because the data and system clock loads and trajectories are different, and because the system clock and the semiconductor memory device are located at different positions.

[0006] To reduce skew, a data strobe signal is transmitted along with the data when transferring data between the memory controller and the semiconductor memory device. Because the data strobe signal has the same load and trajectory as the data, skew can be minimized by using the data strobe signal in the semiconductor memory device to strobe the data.

[0007] The timing parameter tDQSQ represents the timing characteristics specified by JEDEC (Joint Electron Devices Engineering Committee) and is associated with the skew between the read data strobe signal and the read data. Reducing the tDQSQ skew between the read data can stabilize the read data characteristics. Summary of the Invention

[0008] Various embodiments of this disclosure aim to provide a semiconductor memory device that can reduce tDQSQ and tDVW (data valid window) deviations between read data by uniformly distributing power and a reference voltage generation circuit (DAC) and by reducing the setup time deviation of the reference voltage for reading data.

[0009] In an embodiment, a semiconductor memory device may include: a pair of first power supply voltage pads; a second power supply voltage pad; a first data input / output pad connected to a first data output driver; and a second data input / output pad connected to a second data output driver, wherein the first data output driver is connected to one of the pair of first power supply voltage pads, the second data output driver is connected to the other of the pair of first power supply voltage pads, and wherein the first data input / output pad is disposed between one of the pair of first power supply voltage pads and the second power supply voltage pad, and the second data input / output pad is disposed between the other of the pair of first power supply voltage pads and the second power supply voltage pad.

[0010] In an embodiment, a semiconductor memory device may include: a plurality of first power supply voltage pads; a plurality of second power supply voltage pads; and a plurality of data input / output pads, each connected to a plurality of data output drivers. Among the plurality of first power supply voltage pads and the plurality of second power supply voltage pads, the first power supply voltage pads are disposed between a pair of adjacent second power supply voltage pads. Among the plurality of data input / output pads, the first data input / output pads are disposed between one of the pair of second power supply voltage pads and the first power supply voltage pad, and the second data input / output pads are disposed between the other of the pair of second power supply voltage pads and the first power supply voltage pad. Furthermore, the data output drivers connected to the first data input / output pads and the data output drivers connected to the second data input / output pads are both connected to the first power supply voltage pads.

[0011] In an embodiment, a semiconductor memory device may include: a first data input / output pad and a second data input / output pad, defined in a pad layer on a substrate; a first data input circuit, defined in the substrate and connected to the first data input / output pad; a second data input circuit, defined in the substrate and connected to the second data input / output pad; a first reference voltage generation circuit, defined in the substrate and providing a reference voltage to the first data input circuit; a second reference voltage generation circuit, defined in the substrate and providing a reference voltage to the second data input circuit; and a first power supply voltage pad, defined in the pad layer and disposed between the first data input / output pad and the second data input / output pad, wherein, when viewed in a plan view, the first reference voltage generation circuit and the second reference voltage generation circuit are disposed between the first data input / output pad and the second data input / output pad.

[0012] According to embodiments of this disclosure, a semiconductor memory device capable of reducing tDQSQ and tDVW (data valid window) deviations between read data can be provided by uniformly distributing power.

[0013] According to embodiments of the present disclosure, a semiconductor memory device can be provided that can shorten the setup time of the reference voltage and reduce the setup time deviation between reference voltages for reading data by uniformly distributing the reference voltage generation circuit (DAC). Attached Figure Description

[0014] Figure 1 This is a schematic plan view of a semiconductor memory device according to an embodiment of the present disclosure.

[0015] Figure 2 This is a block diagram of a data output driver according to an embodiment of the present disclosure.

[0016] Figure 3 This is a schematic plan view of a semiconductor memory device according to an embodiment of the present disclosure.

[0017] Figure 4 This is a perspective view showing the pads and reference voltage generation circuit of a semiconductor memory device according to an embodiment of the present disclosure.

[0018] Figure 5 This is a schematic plan view of a semiconductor memory device according to an embodiment of the present disclosure. Detailed Implementation

[0019] Embodiments of this disclosure are described in detail with reference to the accompanying drawings. Specific structural or functional descriptions of the embodiments are provided as examples to illustrate the concepts disclosed in this application. Examples or embodiments based on the concepts may be implemented in various forms, and the scope of this disclosure is not limited to the examples or embodiments described in this specification.

[0020] Crosshairs across a figure indicate corresponding or similar areas between figures, rather than indicating material associated with a region.

[0021] When one element is marked "connected" or "attached" to another element, these elements can be directly connected or attached, or connected or attached through one or more intermediate elements. When two elements are marked "directly connected" or "directly attached," one element is directly connected or attached to the other element without any intermediate elements.

[0022] When one element is identified as being "above", "over", "below", or "below" another element, these elements can be in direct contact with each other, or an intermediate element can be placed between these elements.

[0023] Terms such as “vertical,” “parallel,” “top,” “bottom,” “above,” “below,” “lower,” “lower part,” “upper part,” “above,” “side,” “upper,” “topmost,” “lower,” “lowest,” “front,” “back,” “left,” “right,” “column,” “row,” and “horizontal,” as well as other terms that suggest relative spatial relationships or directions, are used for the purpose of description or reference to the accompanying drawings only, and are not intended to limit the scope. Within the scope of this disclosure, other spatial relationships or directions may exist that are not shown in the accompanying drawings or described in the specification.

[0024] Terms such as "first" and "second" are used to distinguish various elements and do not imply the size, order, priority, number, or importance of the elements. For example, in one example, the first element may be referred to as the second element, while in another example, the second element may be referred to as the first element.

[0025] In the specification, when an element included in an embodiment is described in the singular, the element can be interpreted as including multiple elements that perform the same or similar functions.

[0026] Figure 1 This is a schematic plan view of a semiconductor memory device according to an embodiment of the present disclosure.

[0027] Reference Figure 1 The semiconductor memory device includes first to eighth data input / output pads DQ0 to DQ7, a plurality of first power supply voltage pads VCCQ1 to VCCQ7, a plurality of second power supply voltage pads VCCQL1 to VCCQL6, first to eighth data output drivers DQ0_OUT to DQ7_OUT, first to eighth data input circuits DQ0_IN to DQ7_IN, and first to eighth reference voltage generation circuits DAC0 to DAC7. According to an embodiment, the semiconductor memory device may further include a plurality of ground pads VSSI1 to VSSI11, data strobe pads DQS_t and DQS_c, read enable pads RE_t and RE_c, a data mask pad DBI, a third power supply voltage pad VCC, and a data strobe signal input circuit DQS_IN.

[0028] The semiconductor memory device has a pad region PR. In an embodiment, the pad region PR may be located on one side of an edge region of the semiconductor memory device.

[0029] The pad area PR can include a first area R1 to a third area R3. The first area R1 to the third area R3 can be arranged in a row. The first area R1 and the second area R2 can be spaced apart from each other, and the third area R3 can be located between the first area R1 and the second area R2.

[0030] The first data input / output pads DQ0 to the eighth data input / output pads DQ7 can be divided into two groups, which are respectively located in the first region R1 and the second region R2. Specifically, the first data input / output pads DQ0 to the fourth data input / output pads DQ3 can be divided into the first group and located in the first region R1, and the fifth data input / output pads DQ4 to the eighth data input / output pads DQ7 can be divided into the second group and located in the second region R2.

[0031] In the first region R1, four data input / output pads DQ0 to DQ3, three first power supply voltage pads VCCQ1 to VCCQ3, two second power supply voltage pads VCCQL1 and VCCQL2, and four ground pads VSSI1 to VSSI4 can be set.

[0032] In the first region R1, two data input / output pads can be positioned between two adjacent first power supply voltage pads. A second power supply voltage pad can be positioned between the two data input / output pads, and the two data input / output pads are positioned between two adjacent first power supply voltage pads. For example, first data input / output pad DQ0 and second data input / output pad DQ1 are positioned between first power supply voltage pads VCCQ1 and VCCQ2, and second power supply voltage pad VCCQL1 is positioned between first data input / output pad DQ0 and second data input / output pad DQ1. Third data input / output pad DQ2 and fourth data input / output pad DQ3 are positioned between first power supply voltage pads VCCQ2 and VCCQ3, and second power supply voltage pad VCCQL2 is positioned between third data input / output pad DQ2 and fourth data input / output pad DQ3.

[0033] In the first region R1, a ground pad is positioned between the data input / output pad and the first power supply voltage pad. For example, in Figure 1 In this configuration, ground pad VSSI1 is positioned between the first data input / output pad DQ0 and the first power supply voltage pad VCCQ1; ground pad VSSI2 is positioned between the second data input / output pad DQ1 and the first power supply voltage pad VCCQ2; ground pad VSSI3 is positioned between the third data input / output pad DQ2 and the first power supply voltage pad VCCQ2; and ground pad VSSI4 is positioned between the fourth data input / output pad DQ3 and the first power supply voltage pad VCCQ3.

[0034] The spacing between the first data input / output pad DQ0 and the first power supply voltage pad VCCQ1, the spacing between the second data input / output pad DQ1 and the first power supply voltage pad VCCQ2, the spacing between the third data input / output pad DQ2 and the first power supply voltage pad VCCQ2, and the spacing between the fourth data input / output pad DQ3 and the first power supply voltage pad VCCQ3 can be the same.

[0035] In the second region R2, four data input / output pads DQ4 to DQ7, three first power supply voltage pads VCCQ5 to VCCQ7, two second power supply voltage pads VCCQL5 and VCCQL6, and four ground pads VSSI8 to VSSI11 can be provided. The arrangement of these components and the pad layout in the second region R2 are similar to those in the first region R1, so a repeated description will be omitted.

[0036] In the third region R3, you can set the data strobe pads DQS_t and DQS_c, the read enable pads RE_t and RE_c, a first power supply voltage pad VCCQ4, two second power supply voltage pads VCCQL3 and VCCQL4, and three ground pads VSSI5 to VSSI7.

[0037] The first data input / output pads DQ0 through the eighth data input / output pads DQ7 can be used to receive data, commands, and addresses from the memory controller. The first data input / output pads DQ0 through the eighth data input / output pads DQ7 can also be used to output data to the memory controller. Figure 1 This includes, for example, eight data input / output pads DQ0 to DQ7, but other embodiments are not limited to this. The number of data input / output pads can vary depending on the type of semiconductor memory device.

[0038] The first data output drivers DQ0_OUT to the eighth data output drivers DQ7_OUT can be connected to the first data input / output pads DQ0 to the eighth data input / output pads DQ7, respectively. The first data output drivers DQ0_OUT to the eighth data output drivers DQ7_OUT can output data read from a memory region (not shown) within a semiconductor memory device to the first data input / output pads DQ0 to the eighth data input / output pads DQ7 in response to a data strobe signal, and thus can transmit the read data to the memory controller.

[0039] Each of the first data output drivers DQ0_OUT through the eighth data output driver DQ7_OUT can be configured to be adjacent to the corresponding data input / output pad. For example, the first data output driver DQ0_OUT can be configured to be adjacent to the first data input / output pad DQ0, and the second data output driver DQ1_OUT can be configured to be adjacent to the second data input / output pad DQ1.

[0040] Because the data output driver is configured to be adjacent to the corresponding data input / output pad, the length of the signal lines connecting the data output driver and the data input / output pad can be minimized, and the time delay between reading data from the data output driver and transferring the read data to the data input / output pad can be reduced.

[0041] The first data output driver DQ0_OUT can be connected to the first power supply voltage pad VCCQ1 via a power line and can be supplied with the first power supply voltage from the first power supply voltage pad VCCQ1. The second data output driver DQ1_OUT and the third data output driver DQ2_OUT can be connected to the first power supply voltage pad VCCQ2 via a power line and can be supplied with the first power supply voltage from the first power supply voltage pad VCCQ2. The fourth data output driver DQ3_OUT can be connected to the first power supply voltage pad VCCQ3 via a power line and can be supplied with the first power supply voltage from the first power supply voltage pad VCCQ3.

[0042] The fifth data output driver, DQ4_OUT, can be connected to the first power supply voltage pad VCCQ5 via a power supply line and can be supplied with the first power supply voltage from the first power supply voltage pad VCCQ5. The sixth data output driver, DQ5_OUT, and the seventh data output driver, DQ6_OUT, can both be connected to the first power supply voltage pad VCCQ6 via a power supply line and can be supplied with the first power supply voltage from the first power supply voltage pad VCCQ6. The eighth data output driver, DQ7_OUT, can be connected to the first power supply voltage pad VCCQ7 via a power supply line and can be supplied with the first power supply voltage from the first power supply voltage pad VCCQ7.

[0043] Data input / output pads and a first power supply voltage pad are shared with one of the first data output drivers DQ0_OUT to the eighth data output driver DQ7_OUT. The spacing between a data input / output pad shared with one of the first data output drivers DQ0_OUT to the eighth data output driver DQ7_OUT and the first power supply voltage pad can be substantially similar to the spacing between a data input / output pad shared with the other of the first data output drivers DQ0_OUT to the eighth data output driver DQ7_OUT and the first power supply voltage pad VCCQ1. For example, the spacing between the first data input / output pad DQ0 shared with the first data output driver DQ0_OUT and the first power supply voltage pad VCCQ1 can be the same as the spacing between the second data input / output pad DQ1 shared with the second data output driver DQ1_OUT and the first power supply voltage pad VCCQ2.

[0044] Therefore, the distances between the first data output drivers DQ0_OUT to the eighth data output driver DQ7_OUT and the corresponding first power supply voltage pads VCCQ1 to VCCQ3 and VCCQ5 to VCCQ7 can be the same or similar to each other. Thus, the deviation in the length of the power lines connecting the first data output drivers DQ0_OUT to the eighth data output driver DQ7_OUT and the first power supply voltage pads in the first region R1 and the second region R2 can be eliminated or minimized.

[0045] When there is a deviation in tDQSQ between the read data output from a semiconductor memory device, the characteristics of the read data may deteriorate. One factor that may cause tDQSQ deviation between read data is a mismatch in the power distribution network (PDN) of the VCCQ voltage between the read data.

[0046] For example, when a read data transition occurs and the pull-up or pull-down transistors of the data output driver are turned on / off, the VCCQ voltage fluctuates due to instantaneous current consumption, and therefore the timing of the output read data changes. If the settling times of the VCCQ voltage differ due to PDN mismatch between the read data, the timing of the output read data may also differ, potentially leading to tDQSQ deviation between the read data.

[0047] According to embodiments of this disclosure, since the deviation in the length of the power line connecting the data output driver and the first power supply voltage pad can be eliminated or minimized, the PDN mismatch of the VCCQ voltage between read data can be eliminated or minimized, and the tDQSQ deviation between read data can be reduced, thereby improving read characteristics.

[0048] The first data output driver DQ0_OUT and the second data output driver DQ1_OUT can be connected to the second power supply voltage pad VCCQL1, and the second power supply voltage can be supplied from the second power supply voltage pad VCCQL1. The third data output driver DQ2_OUT and the fourth data output driver DQ3_OUT can be connected to the second power supply voltage pad VCCQL2, and the second power supply voltage can be supplied from the second power supply voltage pad VCCQL2.

[0049] The fifth data output driver DQ4_OUT and the sixth data output driver DQ5_OUT can be connected to the second power supply voltage pad VCCQL5, and the second power supply voltage can be supplied from the second power supply voltage pad VCCQL5. The seventh data output driver DQ6_OUT and the eighth data output driver DQ7_OUT can be connected to the second power supply voltage pad VCCQL6, and the second power supply voltage can be supplied from the second power supply voltage pad VCCQL6.

[0050] The first data input circuit DQ0_IN to the eighth data input circuit DQ7_IN can be connected to the first data input / output pads DQ0 to the eighth data input / output pads DQ7, respectively. The first data input circuits DQ0_IN to the eighth data input / output circuit DQ7_IN can receive external data from the memory controller through the first data input / output pads DQ0 to the eighth data input / output pads DQ7. The external data can be a single-ended signal.

[0051] Each of the first data input circuits DQ0_IN to the eighth data input circuit DQ7_IN can be located in an area adjacent to the corresponding data input / output pad. Therefore, the length of the signal lines connecting the data input / output pads and the data input circuits can be configured to be as short as possible, and the time delay occurring when data received through the data input / output pads is transmitted to the data input circuits can be reduced.

[0052] The first data input circuit DQ0_IN to the eighth data input circuit DQ7_IN can be connected to the first reference voltage generation circuit DAC0 to the eighth reference voltage generation circuit DAC7, respectively. Each of the first data input circuits DQ0_IN to the eighth data input circuit DQ7_IN can receive a reference voltage from the corresponding reference voltage generation circuit. The reference voltage can be used as a reference signal to distinguish whether the value of external data is 0 or 1.

[0053] Each of the first reference voltage generation circuit DAC0 to the eighth reference voltage generation circuit DAC7 can be configured to be adjacent to the corresponding data input circuit. Therefore, the reference voltage transmission path can be constructed to be as short as possible, and thus the reference voltage settling time can be shortened.

[0054] Each of the first data input circuits DQ0_IN to the eighth data input circuit DQ7_IN generates internal data by comparing external data with a reference voltage. When the external data exceeds the reference voltage, the internal data value is set to 1; when the external data does not exceed the reference voltage, the internal data value is set to 0.

[0055] The first data input circuit DQ0_IN to the eighth data input circuit DQ7_IN can output internal data to the memory area within the semiconductor memory device in response to a data strobe signal, and thus, data can be written to the memory area.

[0056] Each of the first reference voltage generation circuits DAC0 to DAC7 can generate a reference voltage according to a voltage setting code. Each of the first reference voltage generation circuits DAC0 to DAC7 can generate a reference voltage with a voltage level corresponding to the voltage setting code. The target level of the reference voltage can be, for example, the middle level of the swing range of data transmitted via a transmission line connecting the memory controller and the semiconductor memory device. Each of the first reference voltage generation circuits DAC0 to DAC7 can change the level of the reference voltage according to the voltage setting code. The voltage setting code can be transmitted from the memory controller. The voltage setting code can be information stored in an information storage area such as a mode register in the semiconductor memory. The voltage setting code can be changed through training operations between the memory controller and the semiconductor memory device. Each of the first reference voltage generation circuits DAC0 to DAC7 can be configured using a digital-to-analog converter.

[0057] The data strobe pads may include a first differential data strobe pad DQS_t and a second differential data strobe pad DQS_c. A first signal received by the first differential data strobe pad DQS_t and a second signal received by the second differential data strobe pad DQS_c may have the same amplitude and opposite phase. The data strobe signal input circuit DQS_IN can use the first and second signals to generate a data strobe signal. For example, the rising edge of the data strobe signal may correspond to the time point when the first and second signals intersect. Each of the first data input circuits DQ0_IN to the eighth data input circuit DQ7_IN can generate internal data using the rising edge of the data strobe signal.

[0058] As described above, because the first data input / output pads DQ0 to the fourth data input / output pads DQ3 are located in the first region R1, the fifth data input / output pads DQ4 to the eighth data input / output pads DQ7 are located in the second region R2, and the data strobe pads DQS_t and DQS_c are located in the third region R3 between the first region R1 and the second region R2, the skew of the data strobe signals between the first data input / output pads DQ0 to the fourth data input / output pads DQ3 included in the first region R1 and the fifth data input / output pads DQ4 to the eighth data input / output pads DQ7 included in the second region R2 can be shortened compared to a device where the data strobe pads are located in regions other than the first region R1, the second region R2, and the third region R3. Therefore, the deviation of the tDVW (data valid window) between read data can be reduced.

[0059] The read enable pad may include a first differential read enable pad RE_t and a second differential read enable pad RE_c. The first read enable signal input via the first differential read enable pad RE_t and the second read enable signal input via the second differential read enable pad RE_c can have the same amplitude and opposite phase. The first and second read enable signals can be enabled when data is transmitted via a transmission line in a semiconductor memory device.

[0060] Figure 2 This is a block diagram of a data output driver according to an embodiment of the present disclosure.

[0061] Reference Figure 2 The data output driver DQ_OUT may include the trigger control unit TRCON, the pull-up predriver PUPD, the pull-down predriver PDPD, and the main driver Tx MD.

[0062] The trigger control unit TRCON can receive and read data from the memory area via column lines, and can generate pull-up and pull-down pulses based on the received data.

[0063] The pull-up pre-driver PUPD can generate a pull-up code including pull-up data in response to a pull-up pulse provided by the trigger control unit TRCON. The pull-down pre-driver PDPD can generate a pull-down code including pull-down data in response to a pull-down pulse provided by the trigger control unit TRCON.

[0064] The master driver Tx MD can include pull-up master drivers and pull-down master drivers. The pull-up master driver can output high output data to the data input / output pad DQ in response to pull-up data and pull-up codes provided from the pull-up pre-driver PUPD. For example, when receiving low pull-up data, the pull-up master driver can output high output data to the data input / output pad DQ. When receiving high pull-up data, the pull-up master driver may not output any data. The pull-down master driver can output low output data to the data input / output pad DQ in response to pull-down data and pull-down codes provided from the pull-down pre-driver PDPD. For example, when receiving high pull-down data, the pull-down master driver can output low output data to the data input / output pad DQ. When receiving low pull-down data, the pull-down master driver may not output any data.

[0065] The trigger control unit TRCON, pull-up pre-driver PUPD, and pull-down pre-driver PDPD use VCCQ voltage as their power supply voltage. To reduce power consumption, the main driver Tx MD uses VCCQL voltage instead of VCCQ voltage as its power supply voltage. VCCQ voltage is a first constant voltage, and VCCQL voltage can be selected from a second or third constant voltage. The second constant voltage can have the same value as the first constant voltage, and the third constant voltage can have a value less than the first constant voltage. For example, the first and second constant voltages can be 1.2V, and the third constant voltage can be 0.6V.

[0066] Figure 3 This is a schematic plan view of a semiconductor memory device according to an embodiment of the present disclosure.

[0067] Reference Figure 3 The first reference voltage generation circuit DAC0 can be connected to the first data input circuit DQ0_IN and can provide a reference voltage to the first data input circuit DQ0_IN. The second reference voltage generation circuit DAC1 can be connected to the second data input circuit DQ1_IN and can provide a reference voltage to the second data input circuit DQ1_IN.

[0068] When viewed in a plan view, the first reference voltage generation circuit DAC0 and the second reference voltage generation circuit DAC1 can be disposed between the first data input / output pad DQ0 and the second data input / output pad DQ1. In an embodiment, at least a portion of each of the first reference voltage generation circuit DAC0 and the second reference voltage generation circuit DAC1 can vertically overlap with the second power supply voltage pad VCCQL1, which is disposed between the first data input / output pad DQ0 and the second data input / output pad DQ1 in the plan view.

[0069] The third reference voltage generation circuit DAC2 can be connected to the third data input circuit DQ2_IN and can provide a reference voltage to the third data input circuit DQ2_IN. The fourth reference voltage generation circuit DAC3 can be connected to the fourth data input circuit DQ3_IN and can provide a reference voltage to the fourth data input circuit DQ3_IN.

[0070] When viewed in a plan view, the third reference voltage generation circuit DAC2 and the fourth reference voltage generation circuit DAC3 can be positioned between the third data input / output pad DQ2 and the fourth data input / output pad DQ3. In an embodiment, at least a portion of each of the third reference voltage generation circuit DAC2 and the fourth reference voltage generation circuit DAC3 can vertically overlap with the second power supply voltage pad VCCQL2, which is positioned between the third data input / output pad DQ2 and the fourth data input / output pad DQ3 in the plan view.

[0071] According to embodiments of this disclosure, because the first reference voltage generation circuit DAC0 and the second reference voltage generation circuit DAC1 are disposed between the first data input / output pad DQ0 and the second data input / output pad DQ1, the length deviation between the signal lines connecting the first reference voltage generation circuit DAC0 and the first data input circuit DQ0_IN and the signal lines connecting the second reference voltage generation circuit DAC1 and the second data input circuit DQ1_IN can be eliminated or minimized. Because the third reference voltage generation circuit DAC2 and the fourth reference voltage generation circuit DAC3 are disposed between the third data input / output pad DQ2 and the fourth data input / output pad DQ3, the length deviation between the signal lines connecting the third reference voltage generation circuit DAC2 and the third data input circuit DQ2_IN and the signal lines connecting the fourth reference voltage generation circuit DAC3 and the fourth data input circuit DQ3_IN can be eliminated or minimized. Therefore, by reducing the setup time mismatch between the reference voltages, write characteristics can be improved.

[0072] Figure 4 This is a perspective view showing the pads and reference voltage generation circuit of a semiconductor memory device according to an embodiment of the present disclosure.

[0073] Reference Figure 4 The semiconductor memory device may include a substrate 10 and a pad layer 20 disposed on the substrate 10.

[0074] The first reference voltage generation circuit DAC0 and the second reference voltage generation circuit DAC1 can be configured in the substrate 10. Although not shown, the data input circuit, the data output driver, and the data gating input circuit can be further configured in the substrate 10.

[0075] In the pad area PR of pad layer 20, a first power supply voltage pad VCCQ1, a ground pad VSSI1, a first data input / output pad DQ0, a second power supply voltage pad VCCQL1, a second data input / output pad DQ1, a ground pad VSSI2, and a first power supply voltage pad VCCQ2 can be configured. Although not shown, Figure 1 The pads can be configured in the pad area PR.

[0076] A portion of the first reference voltage generation circuit DAC0 may vertically overlap with the second power supply voltage pad VCCQL1, which is located in pad layer 20 between the first data input / output pad DQ0 and the second data input / output pad DQ1. A portion of the second reference voltage generation circuit DAC1 may also vertically overlap with the second power supply voltage pad VCCQL1, which is located in pad layer 20 between the first data input / output pad DQ0 and the second data input / output pad DQ1.

[0077] Figure 5 This is a schematic plan view of a semiconductor memory device according to an embodiment of the present disclosure.

[0078] Reference Figure 5 The pad area PR may include a first area R1 to a fourth area R4. The first area R1 to the fourth area R4 may be arranged in a row. A third area R3 may be located between the first area R1 and the second area R2, and the fourth area R4 may be located outside the first area R1, the second area R2, and the third area R3. In an embodiment, the fourth area R4 may be located on the side of the second area R2 opposite to the third area R3.

[0079] The read enable pads RE_t and RE_c can be set in the fourth region R4. Because the read enable pads RE_t and RE_c are set in the fourth region R4, the skew of the data strobe signals between the first data input / output pads DQ0 to the fourth data input / output pads DQ3 included in the first region R1 and the fifth data input / output pads DQ4 to the eighth data input / output pads DQ7 included in the second region R2 can be reduced compared to the structure where the read enable pads are set in the third region R3.

[0080] While specific embodiments of the present disclosure have been disclosed herein, those skilled in the art will understand that various modifications, additions, and substitutions related to these embodiments can be made without departing from the scope and technical concept of the present disclosure. Therefore, the scope of the present disclosure should not be limited to the foregoing embodiments. All variations within the equivalent meaning and scope of the claims are included within its scope.

Claims

1. A semiconductor memory device comprising: a pair of first power voltage pads; a second power voltage pad; a first data input / output pad connected to a first data output driver; and a second data input / output pad connected to a second data output driver, wherein the first data output driver is connected to one of the pair of first power voltage pads and the second data output driver is connected to the other of the pair of first power voltage pads, and the first data input / output pad is disposed between the one of the pair of first power voltage pads and the second power voltage pad, and the second data input / output pad is disposed between the other of the pair of first power voltage pads and the second power voltage pad. a pitch between the one of the pair of first power voltage pads and the first data input / output pad is the same as a pitch between the other of the pair of first power voltage pads and the second data input / output pad.

2. The semiconductor memory device according to claim 1, wherein, 3. The semiconductor memory device according to claim 1, further comprising: a first ground pad disposed between the one of the pair of first power voltage pads and the first data input / output pad; and a second ground pad disposed between the other of the pair of first power voltage pads and the second data input / output pad. the first data output driver and the second data output driver are commonly connected to the second power voltage pad.

5. The semiconductor memory device according to claim 1, wherein 4. The semiconductor memory device according to claim 1, wherein, a first constant voltage is supplied to the pair of first power voltage pads, and a second constant voltage or a third constant voltage is supplied to the second power voltage pad. the second constant voltage is the same as the first constant voltage, and the third constant voltage is lower than the first constant voltage.

7. A semiconductor memory device comprising:

6. The semiconductor memory device of claim 5, wherein, a plurality of first power voltage pads; a plurality of second power voltage pads; and a plurality of data input / output pads respectively connected to a plurality of data output drivers, wherein, among the plurality of first power voltage pads and the plurality of second power voltage pads, a first power voltage pad is disposed between a pair of adjacent second power voltage pads, among the plurality of data input / output pads, a first data input / output pad is disposed between one of the pair of second power voltage pads and the first power voltage pad, and a second data input / output pad is disposed between the other of the pair of second power voltage pads and the first power voltage pad, and a data output driver connected to the first data input / output pad and a data output driver connected to the second data input / output pad are commonly connected to the first power voltage pad. a pitch between the first data input / output pad and the first power voltage pad is the same as a pitch between the second data input / output pad and the first power voltage pad.

9. The semiconductor memory device according to claim 7, further comprising: ​ 8. The semiconductor memory device of claim 7, wherein, ​ ​ a first ground pad disposed between the first power voltage pad and the first data input / output pad; and a second ground pad disposed between the first power voltage pad and the second data input / output pad.

10. The semiconductor memory device according to claim 7, further comprising: a data strobe pad, wherein the plurality of data input / output pads are divided into two groups, respectively disposed in a first region and a second region, and the data strobe pad is disposed in a third region between the first region and the second region.

11. The semiconductor memory device according to claim 10, further comprising: a read enable pad, wherein the read enable pad is disposed in a fourth region outside the first region, the second region, and the third region.

12. A semiconductor memory device, comprising: first and second data input / output pads defined in a pad layer on a substrate; first data input circuitry defined in the substrate and connected to the first data input / output pad; second data input circuitry defined in the substrate and connected to the second data input / output pad; first reference voltage generation circuitry defined in the substrate and providing a reference voltage to the first data input circuitry; second reference voltage generation circuitry defined in the substrate and providing a reference voltage to the second data input circuitry; and a first power voltage pad defined in the pad layer and disposed between the first and second data input / output pads, wherein the first and second reference voltage generation circuitry are disposed between the first and second data input / output pads when viewed in a plan view. At least a portion of each of the first and second reference voltage generation circuitry vertically overlaps the first power voltage pad on the plan view.

13. The semiconductor memory device of claim 12, wherein, 14. The semiconductor memory device according to claim 12, further comprising: first data output drivers defined in the substrate and connected to the first data input / output pad; second data output drivers defined in the substrate and connected to the second data input / output pad; and a pair of second power voltage pads defined in the pad layer, wherein the first data output drivers are connected to one of the pair of second power voltage pads and the second data output drivers are connected to the other of the pair of second power voltage pads, and the first data input / output pad is disposed between the first power voltage pad and one of the pair of second power voltage pads, and the second data input / output pad is disposed between the first power voltage pad and the other of the pair of second power voltage pads. ​ 15. The semiconductor memory device of claim 14, wherein, A spacing between one of the pair of second power voltage pads and the first data input / output pad is the same as a spacing between the other of the pair of second power voltage pads and the second data input / output pad.

16. The semiconductor memory device of claim 14, further comprising: a first ground pad disposed between one of the pair of second power voltage pads and the first data input / output pad; and a second ground pad disposed between the other of the pair of second power voltage pads and the second data input / output pad. The first data output driver and the second data output driver are commonly connected to the first power voltage pad.

17. The semiconductor memory device of claim 14, wherein, ​

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