Memory and operating method thereof

Abstract

The present disclosure provides a memory and an operating method thereof, the operating method of the memory including: in response to a write command, determining whether to perform a sensing operation on a target memory cell of the memory based on a target value of a write operation; if the target value is a first value, in a first stage, executing the sensing operation on the target storage unit to obtain a storage value of the target storage unit, and determining whether to execute the write-in operation or not according to a matching result of the storage value and the target value; and if the target value is a second value, not executing the sensing operation on the target storage unit in the first stage, and directly executing the write-in operation after the first stage.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory and its operation method. Background Technology

[0002] To bridge the performance gap between Dynamic Random Access Memory (DRAM) and NAND flash memory, Storage Class Memory (SCM) has been proposed as a new storage medium technology. Mainstream SCM media include Phase-Change Memory (PCM), Resistive Random Access Memory (ReRAM), and Magnetic Random Access Memory (MRAM). Among these, PCM exhibits significant advantages over flash memory in many aspects, such as read / write speed, read / write cycles, data retention time, and cell area. However, PCM still faces several challenges in practical applications, leaving considerable room for optimization. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory and a method for operating the same.

[0004] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows: In a first aspect, this disclosure provides a method for operating a memory, including: In response to a write command, a sensing operation is performed on the target storage cell of the memory based on the target value of the write operation; If the target value is a first value, in the first stage, the sensing operation is performed on the target storage unit to obtain the storage value of the target storage unit, and based on the matching result between the storage value and the target value, it is determined whether to perform the write operation; If the target value is the second value, the sensing operation is not performed on the target storage unit in the first stage, and the write operation is performed directly after the first stage.

[0005] In one alternative implementation, the threshold voltage of the storage cell storing the first value is greater than the threshold voltage of the storage cell storing the second value.

[0006] In one optional implementation, determining whether to perform the write operation based on the matching result between the stored value and the target value includes: If the stored value is the first value, the write operation is not performed; if the stored value is not the first value, the write operation is performed.

[0007] In one alternative implementation, performing the write operation includes: In the second stage following the first stage, the first driving voltage of the target memory cell is increased, and the second driving voltage of the target memory cell is maintained, wherein the first driving voltage is greater than the second driving voltage.

[0008] In one alternative implementation, not performing the write operation includes: At the end of the first stage, both the first driving voltage and the second driving voltage of the target storage cell are set to ground voltage.

[0009] In one optional implementation, the first stage includes a first sub-stage and a maintenance stage following the first sub-stage; the first sub-stage belongs to the read stage; the operation method further includes: During the maintenance phase, the first drive voltage and the second drive voltage of the target storage cell are maintained in the first sub-phase.

[0010] In one optional embodiment, the read phase further includes a second sub-phase preceding the first sub-phase; in the second sub-phase, the difference between the first driving voltage and the second driving voltage of the target storage cell is less than the difference between the first driving voltage and the second driving voltage of the target storage cell in the first sub-phase.

[0011] In one optional implementation, if the target value is the first value, in the first stage, the difference between the first driving voltage and the second driving voltage of the target memory cell is the first difference. If the target value is the second value, in the first stage, the difference between the first driving voltage and the second driving voltage of the target storage cell is the second difference; the first difference is greater than the second difference.

[0012] In one optional implementation, if the target value is the second value, performing the write operation further includes: In the third stage following the second stage, the first drive voltage of the target memory cell is reduced while the second drive voltage of the target memory cell is maintained.

[0013] In a second aspect, this disclosure provides a memory including a memory array and peripheral circuitry coupled to the memory array, the peripheral circuitry being configured to perform the operation method described in any of the above embodiments.

[0014] In the technical solution provided in this disclosure, upon receiving a write command, a write operation is not immediately performed on the target storage unit, nor is a read operation immediately performed on the target storage unit. Instead, a sensing operation is first performed on the target storage unit based on the target value of the write operation. If the target value is a first value, a sensing operation is performed on the target storage unit in the first stage to obtain the stored value of the target storage unit, and a write operation is performed based on the matching result between the stored value and the target value. If the target stored value is a second value, a sensing operation is not performed on the target storage unit in the first stage, and a write operation is performed directly after the first stage. Thus, on the one hand, when the target value is a first value, the write operation can be omitted when the target value and the stored value are the same, thereby reducing the number of write operations performed on the target storage unit and saving power consumption for the write operation; on the other hand, when the target value is a second value, the sensing operation can be omitted, thereby saving power consumption for the sensing operation. Attached Figure Description

[0015] Figure 1 A schematic diagram of a memory provided for an embodiment of this disclosure; Figure 2 This is a three-dimensional structural diagram of a portion of the storage array provided in an embodiment of the present disclosure; Figure 3 A flowchart illustrating the operation method of the memory provided in this embodiment of the disclosure; Figure 4 A schematic diagram of the threshold voltage distribution of a memory cell provided in an embodiment of this disclosure; Figure 5 Voltage curve 1 for the operation process of the memory provided in the embodiments of this disclosure; Figure 6 Voltage curve two for the operation process of the memory provided in this embodiment of the disclosure; Figure 7 Voltage curve three for the operation process of the memory provided in the embodiments of this disclosure; Figure 8 Voltage curve four for the operation process of the memory provided in the embodiments of this disclosure Figure 9 A logic block diagram of a memory operation method provided in an embodiment of this disclosure. Detailed Implementation

[0016] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0017] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0018] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0019] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0021] Figure 1 Schematic diagram of the composition of the memory provided in this disclosure Figure 1 , Figure 2 This is a three-dimensional structural diagram of a portion of the memory provided in an embodiment of the present disclosure. (Referring to...) Figure 1 and Figure 2The memory includes a memory array 10 and peripheral circuitry 20 coupled to the memory array 10. The memory array 10 includes multiple memory cells 100. The memory cells 100 are located between a first driving line 121 and a second driving line 120 in a first direction. Multiple memory cells 100 arranged along a second direction are coupled to a first driving line 121, and multiple memory cells 100 arranged along a third direction are coupled to a second driving line 120. Here, the first direction is taken as the Z direction, the second direction as the X direction, and the third direction as the Y direction, as an example.

[0022] It should be noted that the number of first drive lines, second drive lines, and memory cells shown in the figure are merely examples, and this disclosure does not impose any specific limitations on them. Furthermore, Figure 1 and Figure 2 Taking the storage array 10 as an example, which includes only one layer of storage cells 100, this disclosure is not limited to this. In other embodiments, the storage array 10 may include multiple storage layers stacked along the Z direction, and each storage layer includes multiple first drive lines, multiple second drive lines, and multiple storage cells located between the first drive lines and the second drive lines in the Z direction.

[0023] In some embodiments, refer to Figure 2 The memory cell 100 includes a gating element 102 and a phase-change element 104 stacked along a first direction, with the gating element 102 located between the first driving line 121 and the phase-change element 104. Furthermore, the memory cell 100 also includes a first electrode 101, a second electrode 103, and a third electrode 105. The first electrode 101 is located between the gating element 102 and the first driving line 121, the second electrode 103 is located between the gating element 102 and the phase-change element 104, and the third electrode 105 is located between the phase-change element 104 and the second driving line 120. Here, the first driving line 121 can be a word line (WL), and the second driving line 120 can be a bit line (BL).

[0024] In some specific examples, the first electrode 101, the second electrode 103, and the third electrode 105 may include conductive materials and may serve as conductive paths. Here, the conductive material may be at least one of the following: doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., tungsten, titanium, tantalum, aluminum, copper, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0025] In some specific examples, the second electrode 103 may also include a thermally insulating material, thereby reducing thermal crosstalk between the gating element 102 and the phase change element 104. For example, the second electrode 103 may include amorphous carbon.

[0026] In some specific examples, the resistance of the gating element 102 can vary in response to a change in the selection voltage applied between the first electrode 101 and the second electrode 103. In some embodiments, the gating element 102 may comprise a material having an Ovonic Threshold Switch (OTS) property, which may include at least one element selected from oxygen, sulfur, selenium, tellurium, germanium, antimony, silicon, and arsenic, such as Zn. x Te y 、Ge x Te y 、Nb x O y Si x As y Te z When the voltage applied between the first electrode 101 and the second electrode 103 is lower than its threshold voltage, the gating element 102 can be in a high-resistance state that prevents current from flowing through, and when the voltage applied between the first electrode 101 and the second electrode 103 is higher than its threshold voltage, the gating element 102 can be in a low-resistance state that allows current to flow through.

[0027] In one specific example, the phase change element 104 may include a chalcogenide component, such as at least one of binary compounds such as GaSb, InSb, InSe, SbTe and GeTe, ternary compounds such as GeSbTe, GaSeTe, InSbTe, SnSbTe and InSbGe, and quaternary compounds such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe) and TeGeSbS.

[0028] In some embodiments, the phase change element 104 can reversibly switch between a crystalline and amorphous state, and can utilize the difference in resistivity between its crystalline and amorphous states to achieve data storage. The crystalline phase of the phase change element 104 can be changed through set and reset operations. Specifically, the set operation may include heating the phase change element 104 above the recrystallization temperature by the Joule heat generated by the voltage applied between the first drive line 121 and the second drive line 120, and then slowly decreasing the voltage applied between the first drive line 121 and the second drive line 120, thereby slowly cooling the phase change element 104 to a low-resistivity crystalline state; the reset operation may include heating the phase change element 104 above the melting point by the Joule heat generated by the voltage applied between the first drive line 121 and the second drive line 120, and then rapidly decreasing the voltage applied between the first drive line 121 and the second drive line 120, thereby rapidly cooling the phase change element 104 to a high-resistivity amorphous state. When storage cell 100 is in the set state after a set operation, the data stored in storage cell 100 can be either "0" or "1". When storage cell 100 is in the reset state after a reset operation, the data stored in storage cell 100 can be either "0" or "1". In this embodiment of the present disclosure, the data stored in storage cell 100 in the set state is "1", and the data stored in storage cell 100 in the reset state is "0" is taken as an example.

[0029] When writing data to memory cell 100 via the aforementioned set or reset operations, the set operation requires applying voltage to memory cell 100 for a relatively long time, and the reset operation requires applying a large voltage to memory cell 100. Therefore, when writing data to the memory array 10, which includes multiple memory cells 100, via the write operation, the write operation lasts for a long time and consumes a lot of power. In addition, due to the limitations of thermal fatigue and structural degradation of phase change materials, the write endurance is usually much shorter than the read endurance. Therefore, both write endurance and the power consumption of the write operation are among the bottlenecks limiting the performance of phase change memory.

[0030] In some embodiments, for a storage cell that has already been written to, when new data needs to be written, a read-then-write operation can be used to avoid repeatedly writing to the storage cell. This can extend the lifespan of the storage cell and save power consumption. Specifically, when the data to be written is the same as the data read, the write operation to the storage cell can be omitted; only when the data to be written is different from the data read, is a write operation required for the storage cell.

[0031] However, in a read-before-write operation, if the data to be written differs from the data read, the voltage applied to the memory cell needs to be restored to its idle state after the read operation is completed. For example, the voltages on the word line and bit line need to be restored to ground before the write operation can be performed. Furthermore, the memory cell needs to be turned on before the write operation so that the current in the write operation can be concentrated in the target memory cell. In this case, on the one hand, the overall operation time of the read-before-write operation is relatively long, which will lead to a longer response time of the memory to the write command and a decrease in data write performance. On the other hand, the power consumption of the read-before-write operation is relatively high, which will lead to a decrease in the energy efficiency of the memory. Moreover, for memory cells with low threshold voltages, they will be turned on during both the read and write operations, causing them to withstand the inrush current during the two turns, which will negatively affect the lifespan of the memory cell.

[0032] In view of the above problems, the present disclosure provides the following implementation methods.

[0033] This disclosure provides a method for operating a memory. Figure 3 This is a flowchart illustrating a method for operating a memory according to an embodiment of the present disclosure. The method for operating the memory includes the following steps: Step S301: In response to the write command, determine whether to perform a sensing operation on the target storage cell of the memory based on the target value of the write operation; Step S302: If the target value is a first value, in the first stage, the sensing operation is performed on the target storage unit to obtain the storage value of the target storage unit, and the write operation is determined based on the matching result between the storage value and the target value. Step S303: If the target value is the second value, in the first stage, the sensing operation is not performed on the target storage unit, and the write operation is performed directly after the first stage.

[0034] In this embodiment of the disclosure, upon receiving a write command, a write operation is not immediately performed on the target storage unit, nor is a read operation immediately performed on the target storage unit. Instead, a sensing operation is first performed on the target storage unit based on the target value of the write operation. If the target value is a first value, a sensing operation is performed on the target storage unit in the first stage to obtain the storage value of the target storage unit, and a write operation is performed based on the matching result between the storage value and the target value. If the target storage value is a second value, no sensing operation is performed on the target storage unit in the first stage, and the write operation is performed directly after the first stage. Thus, on the one hand, when the target value is a first value, the write operation can be omitted when the target value and the storage value are the same, thereby reducing the number of write operations performed on the target storage unit and saving power consumption for the write operation; on the other hand, when the target value is a second value, the sensing operation can be omitted, thereby saving power consumption for the sensing operation. This will be explained below with reference to specific examples.

[0035] In some embodiments, Figure 4 This is a schematic diagram of the threshold voltage distribution of storage cells in a memory provided in an embodiment of the present disclosure. The threshold voltage of the storage cell storing the first value is greater than the threshold voltage of the storage cell storing the second value. Specifically, the threshold voltage of the storage cell storing the first value can be within the range of the first threshold voltage distribution 201, the storage cell storing the first value can be in a reset state, and the first value can be "0"; the threshold voltage of the storage cell storing the second value can be within the range of the second threshold voltage distribution 202, the storage cell storing the second value can be in a set state, and the second value can be "1".

[0036] In some embodiments, if the target value is a first value, in step S302, determining whether to perform a write operation based on the matching result between the stored value and the target value includes: if the stored value is the first value, that is, the stored value is the same as the target value, then no write operation is performed; if the stored value is not the first value, that is, the stored value is different from the target value, then a write operation is performed.

[0037] In some embodiments, when the target value is a first value and the stored value is a second value (i.e., the stored value differs from the target value), a write operation is required to write the first value to the target storage unit. Figure 5 Voltage curves for the operation of the memory provided in the embodiments of this disclosure.

[0038] Reference Figure 5If the target value is a first value, in the first stage P1, a sensing operation is performed on the target memory cell. During the sensing operation, the first driving voltage of the target memory cell is V1, and the second driving voltage is V2. Here, the first driving voltage of the target memory cell is the voltage applied to the first driving line WL coupled to the target memory cell, and the second driving voltage of the target memory cell is the voltage applied to the second driving line BL coupled to the target memory cell. The first driving voltage is greater than the second driving voltage, V1 can be a positive voltage, and V2 can be a negative voltage.

[0039] In some specific examples, performing a sensing operation on the target memory cell includes sensing the magnitude of the current or the rate of change of the current on the second driving line BL coupled to the target memory cell through a sensing amplifier circuit. When the current on the second driving line BL is less than a preset current or the rate of change of the current is less than a preset rate, the result of the sensing operation can be "0", that is, the storage value of the target memory cell is a first value; when the current on the second driving line BL is greater than or equal to the preset current or the rate of change of the current is greater than or equal to the preset rate, the result of the sensing operation can be "1", that is, the storage value of the target memory cell is a second value. Here, refer to... Figure 5 If the storage value of the target storage unit obtained through the sensing operation is the second value, then a write operation needs to be performed after the sensing operation.

[0040] In some specific examples, refer to Figure 4 When performing a sensing operation on the target memory cell, the voltage V1-V2 applied to the target memory cell can be greater than the minimum threshold voltage of the memory cell storing the first value. In this case, when the target memory cell is in the set state and its threshold voltage drifts in the positive direction, the stored value obtained by the sensing operation can be the second value regardless of the degree of drift. Thus, the positive drift of the threshold voltage can be compensated, improving the reliability of the sensing operation and thereby improving the reliability of the write operation.

[0041] Continue to refer to Figure 5 The first stage P1 may include a first sub-stage Pr1 and a maintenance stage H following the first sub-stage Pr1, wherein the first sub-stage Pr1 may be a stage for performing a sensing operation and the first sub-stage Pr1 belongs to the reading stage R; the memory operation method further includes: in the maintenance stage H, maintaining the first driving voltage and the second driving voltage of the target memory cell in the first sub-stage Pr1.

[0042] In this embodiment of the disclosure, the sensing operation can be performed in the reading phase R, and after the reading phase R ends, it is not necessary to restore the first driving voltage and the second driving voltage of the target memory cell to the idle state, that is, it is not necessary to discharge the voltage on the first driving line WL and the voltage on the second driving line BL to the ground voltage Vss, thereby reducing the waste of power consumption.

[0043] In some specific examples, refer to Figure 5 The read phase R also includes a second sub-phase Pr2 located before the first sub-phase Pr1. The difference V4-V2 between the first and second driving voltages of the target memory cell in the second sub-phase Pr2 is less than the difference V1-V2 between the first and second driving voltages of the target memory cell in the first sub-phase Pr1. Therefore, if the target memory cell is in the set state, it can be turned on in the second sub-phase Pr2, i.e., turned on when the voltage difference across it is close to its threshold voltage. This avoids a large current surge when the target memory cell is turned on, reducing the probability of damage to the selection element or unexpected phase transitions due to localized overheating of the phase-change element, thus extending the write life of the target memory cell.

[0044] Continue to refer to Figure 5 When the target value is the first value and the stored value is the second value, the write operation includes: in the second stage P2 after the first stage P1, increasing the first driving voltage of the target memory cell and maintaining the second driving voltage of the target memory cell. Specifically, the first driving voltage of the target memory cell can be increased from V1 to V3, and the second driving voltage of the target memory cell can be maintained at V2. Here, the write operation is a reset operation. By increasing the voltage difference across the target memory cell, a larger current can be applied to the target memory cell. Then, at the end of the second stage P2, the voltage and current applied to the target memory cell are cut off. As a result, the phase change element can be rapidly heated above its melting point and rapidly cooled, thereby transforming into a high-resistivity amorphous state. The target memory cell is then configured to store the first value.

[0045] In this embodiment, if the target value of the write operation is a first value, a read-then-write operation can be performed on the target memory cell, and the read and write operations can be combined to improve the efficiency of the read-then-write operation. Specifically, the read phase R can directly connect to the subsequent write operation through the maintenance phase H, without needing to restore to an idle state after the read phase R ends before performing the write operation. On the one hand, for memory cells that have been turned on in the read phase R, their on state can be maintained, without needing to be turned on again in the write operation, thereby reducing the number of times the target memory cell is turned on, which is beneficial to optimizing its write lifespan; on the other hand, after the read phase R ends, it is not necessary to discharge the voltage on the first drive line WL and the voltage on the second drive line BL to the ground voltage Vss, and in the second phase P2, the first drive voltage can directly rise from V1 to V3, thereby compressing the voltage setup time, improving the efficiency of the read-then-write operation, and reducing power consumption waste.

[0046] In some embodiments, when both the target value and the stored value are the first value, i.e., when the stored value is the same as the target value, no write operation is required. In this case, Figure 6 Voltage curves for the operation of the memory provided in embodiments of this disclosure. (Refer to...) Figure 6 If the stored value obtained through the sensing operation in the first stage P1 is the first value, then no write operation is performed. Specifically, this includes setting both the first driving voltage and the second driving voltage of the target memory cell to the ground voltage Vss at the end of the first stage P1. Here, the first stage P1 can still include a first sub-stage Pr1 and a sustaining stage H, so that at the end of the sustaining stage H, both the first driving voltage and the second driving voltage of the target memory cell are set to the ground voltage Vss.

[0047] In other embodiments, when both the target value and the stored value are first values, Figure 7 Voltage curves for the operation of the memory provided in embodiments of this disclosure. (Refer to...) Figure 7 If the stored value obtained through the sensing operation in the first stage P1 is the first value, then no write operation is performed. Specifically, this includes setting both the first driving voltage and the second driving voltage of the target storage cell to the ground voltage Vss at the end of the first stage P1. Here, the first stage P1 may also only include the first sub-stage Pr1, in which case both the first driving voltage and the second driving voltage of the target storage cell will be set to the ground voltage Vss at the end of the read stage R.

[0048] In this embodiment of the disclosure, if the target value of the write operation and the stored value obtained through the sensing operation in the first stage are both the first value, the write operation of writing the first value can be omitted. As a result, the response time of the write command can be shortened, and the number of write operations performed on the target storage unit can be reduced, which is beneficial to improve the write performance of the memory while optimizing the write life of the memory.

[0049] In some embodiments, when the target value is a second value... Figure 8 The voltage curve of the memory operation process provided in the embodiments of this disclosure. Step S303 may include: in the first stage P1, no sensing operation is performed on the target memory cell, and a write operation is performed directly after the first stage P1.

[0050] In this embodiment of the disclosure, when the target value of the write operation is the second value, the sensing operation can be omitted from the target memory cell. Since the threshold voltage drift direction of the memory cell in the set state and the memory cell in the reset state is both positive, when a higher voltage V1-V2 is applied to the target memory cell during the sensing operation, the memory cell with a threshold voltage greater than V1-V2 is definitely in the reset state, but the memory cell with a threshold voltage less than V1-V2 is not necessarily in the set state. This is because there may be a situation where the threshold voltage of the memory cell in the reset state is still less than V1-V2 due to the short time interval between the two write operations. Therefore, in order to improve the reliability of the write operation, when the target value is the second value, the sensing operation can be omitted and the write operation can be performed directly on the target memory cell. This can improve the reliability of the write operation and save the power consumption of using the sensing amplifier circuit to perform the sensing operation on the target memory cell.

[0051] In some specific examples, refer to Figure 5 If the target value is the first value, in the first stage P1, the difference between the first driving voltage and the second driving voltage of the target memory cell is the first difference V1-V2; refer to Figure 8 If the target value is the second value, in the first stage P1, the difference between the first driving voltage and the second driving voltage of the target memory cell is the second difference V5-V2; the first difference V1-V2 is greater than the second difference V5-V2.

[0052] Continue to refer to Figure 8 When the target value is the second value, the write operation includes: in the second stage P2 after the first stage P1, increasing the first driving voltage of the target memory cell and maintaining the second driving voltage of the target memory cell. Specifically, the first driving voltage can be increased from V5 to V6, and the second driving voltage can be maintained at V2.

[0053] In some specific examples, refer to Figure 8In the fourth stage P4, which precedes the first stage P1, the first driving voltage of the target memory cell is V8, the second driving voltage is V2, and V8 is less than V5.

[0054] In this embodiment, the voltage difference across the target memory cell can be gradually increased during the fourth stage P4, the first stage P1, and the second stage P2. This allows the target memory cell to conduct at a voltage difference slightly greater than its threshold voltage, avoiding a large current surge when the target memory cell is turned on and reducing the probability of damage to the selection element or unexpected phase transitions due to local overheating of the phase-change element. Furthermore, in the first stage P1, without performing a sensing operation, the voltage difference V5-V2 across the target memory cell can be smaller than the voltage difference V1-V2 when performing a sensing operation. This allows the target memory cell, which is in the set state and has a relatively high threshold voltage, to be turned on at a relatively lower voltage, further reducing the current surge during turn-on and improving the write lifespan of the memory.

[0055] Continue to refer to Figure 8 When the target value is the second value, the write operation further includes: in the third stage P3 after the second stage P2, reducing the first driving voltage of the target memory cell and maintaining the second driving voltage of the target memory cell. Specifically, the first driving voltage can be reduced from V6 to V7, and the second driving voltage can be maintained at V2. Here, the write operation is a set operation, which may include adjusting the current applied to the target memory cell through a programmable current mirror array coupled to the second driving line BL, so that the phase change element in the target memory cell can go through four stages of preheating, nucleation, growth and annealing to transform into a low-resistance crystalline state, and the target memory cell is configured to store the second value. Since the target memory cell has been turned on before the write operation, the voltage across its terminals can quickly be reversed from the threshold voltage to the sustaining voltage, and the sustaining voltage is less than its threshold voltage. Therefore, after the target memory cell is turned on, applying a relatively lower voltage V7-V2 can also maintain its conduction state and ensure sufficient voltage margin, so that the current of the write operation can be concentrated in the target memory cell and maintain linear steady current.

[0056] The above embodiments describe the specific operation methods for three cases: when the target value is a first value and the storage value obtained through sensing operation is a second value; when the target value is a first value and the storage value obtained through sensing operation is a first value; and when the target value is a second value. Below, these three cases are integrated into the same logic block diagram to systematically summarize the operation methods of the memory provided in this disclosure.

[0057] In some specific examples, Figure 9A logic block diagram of the memory operation method provided in the embodiments of this disclosure, in conjunction with reference to... Figure 5 and Figure 9 The memory operation method includes: in step S401, in response to a write command, the operation begins; in step S402, it is determined whether the target value in the write command is a first value; if the determination result of step S402 is "yes", that is, if the target value is the first value, then step S403 is executed, and a sensing operation is performed on the target memory cell in the first stage P1 to obtain the stored value of the target memory cell; in step S404, it is determined whether the stored value of the target memory cell is the first value; if the determination result in step S404 is "no", that is, if the stored value is not the first value, then step S405 is executed, and the first driving voltage and the second driving voltage of the target memory cell are maintained in the maintenance stage H; in step S406, the first value is written to the target memory cell; in step S409, the first driving voltage and the second driving voltage of the target memory cell are set to the ground voltage Vss, and a write command completion response information is generated. Therefore, when the target value is the first value, a read-then-write operation can be performed. When the stored value obtained through the sensing operation is the second value, the reading phase of the sensing operation and the write operation of writing the first value can be directly connected through the maintenance phase H. That is, the first driving voltage and the second driving voltage when performing the sensing operation can be directly connected to the first driving voltage and the second driving voltage when performing the write operation. This can compress the voltage setup time and the response time of the write command, reduce the waste of power consumption, and reduce the number of times the target storage cell is turned on, which is beneficial to optimizing the write life of the memory.

[0058] In some specific examples, in conjunction with reference Figure 7 and Figure 9 The memory operation method includes: if the judgment result in step S404 is "yes", that is, if the stored value is the first value, then step S409 is executed, setting the first driving voltage and the second driving voltage of the target memory cell to the ground voltage Vss, and generating a write command completion response information. Therefore, when the target value is the first value and the stored value obtained through sensing is the first value, the write operation to write the first value can be omitted, shortening the write command response time, reducing power consumption, and reducing the number of write operations performed on the target memory cell, which is beneficial for optimizing the memory's write lifespan.

[0059] In some specific examples, in conjunction with reference Figure 8 and Figure 9 The memory operation method includes: if the judgment result of step S402 is "no", that is, if the target value is the second value, then step S407 is executed to turn on the target memory cell, which may specifically include Figure 8The fourth stage P4, the first stage P1, and the second stage P2 are executed; step S408 is performed to write the second value into the target storage unit, which may specifically include... Figure 8 In the third stage P3, step S409 is executed, setting the first and second driving voltages of the target memory cell to ground voltage Vss and generating a write command completion response. Therefore, when the target value is the second value, the sensing operation can be omitted, saving power consumption during the sensing operation and improving the reliability of writing the second value to the target memory cell.

[0060] In this embodiment of the disclosure, when a write command is received, a write operation will not be performed directly on the target storage unit, nor will a read operation be performed directly on the target storage unit. Instead, a sensing operation will be performed on the target storage unit based on the target value of the write operation. If the target value is the first value, a sensing operation will be performed on the target storage unit. If the target value is the second value, a sensing operation will not be performed on the target storage unit. Furthermore, if the target value is a first value and the stored value obtained through the sensing operation is a second value, the read phase of the sensing operation can be directly connected to the write operation through the maintenance phase. This reduces power consumption waste, decreases the number of times the target memory cell is turned on, and improves the efficiency of the write operation. If the target value is a first value and the stored value of the target memory cell obtained through the sensing operation is also a first value, the write operation can be omitted. This reduces the number of write operations performed on the target memory cell and improves the efficiency of the write operation. If the target value is a second value, the write operation can be performed directly, and the voltage difference across the target memory cell can be sequentially increased in multiple phases so that the target memory cell is turned on at a voltage difference close to its threshold voltage. This reduces the current surge generated on the target memory cell during turn-on, saves power consumption generated by the sensing operation, and improves the reliability of writing the second value. In summary, the memory operation method provided by this disclosure has high flexibility and is beneficial for optimizing the memory's write performance, energy efficiency, and write lifespan.

[0061] Based on a concept similar to the operation method of the aforementioned memory, this disclosure also provides a memory, referring to... Figure 1 The memory includes a memory array 10 and peripheral circuitry 20 coupled to the memory array, the peripheral circuitry 20 being configured to perform the operating methods provided in any of the above embodiments.

[0062] In some embodiments, the peripheral circuit 20 is configured to: in response to a write command, determine whether to perform a sensing operation on a target storage cell of the memory based on a target value of the write operation; if the target value is a first value, in a first stage, perform the sensing operation on the target storage cell to obtain a storage value of the target storage cell, and determine whether to perform the write operation based on a matching result between the storage value and the target value; if the target value is a second value, in the first stage, do not perform the sensing operation on the target storage cell, and directly perform the write operation after the first stage.

[0063] In some embodiments, the threshold voltage of the storage cell storing the first value is greater than the threshold voltage of the storage cell storing the second value.

[0064] In some embodiments, the peripheral circuit 20 is specifically configured to: if the stored value is the first value, then not perform the write operation; if the stored value is not the first value, then perform the write operation.

[0065] In some embodiments, the peripheral circuit 20 is specifically configured to: if the stored value is not the first value, perform the write operation, including in a second stage after the first stage, increasing the first driving voltage of the target storage cell and maintaining the second driving voltage of the target storage cell, wherein the first driving voltage is greater than the second driving voltage.

[0066] In some embodiments, the peripheral circuit 20 is specifically configured to: if the stored value is the first value, then not perform the write operation, including setting both the first drive voltage and the second drive voltage of the target memory cell to ground voltage at the end of the first stage.

[0067] In some embodiments, the first stage includes a first sub-stage and a sustaining stage following the first sub-stage; the first sub-stage belongs to the read stage; the peripheral circuit 20 is further configured to: maintain a first drive voltage and a second drive voltage of the target memory cell in the first sub-stage during the sustaining stage.

[0068] In some embodiments, the read phase further includes a second sub-phase preceding the first sub-phase; in the second sub-phase, the difference between the first driving voltage and the second driving voltage of the target memory cell is less than the difference between the first driving voltage and the second driving voltage of the target memory cell in the first sub-phase.

[0069] In some embodiments, if the target value is the first value, in the first stage, the difference between the first driving voltage and the second driving voltage of the target memory cell is a first difference; if the target value is the second value, in the first stage, the difference between the first driving voltage and the second driving voltage of the target memory cell is a second difference; the first difference is greater than the second difference.

[0070] In some embodiments, if the target value is the second value, the peripheral circuit 20 is further configured to: in a third stage after the second stage, reduce the first drive voltage of the target memory cell and maintain the second drive voltage of the target memory cell.

[0071] In this embodiment of the disclosure, when the peripheral circuit in the memory receives a write command, it will not directly perform a write operation on the target memory cell, nor will it directly perform a read operation on the target memory cell. Instead, it will first determine whether to perform a sensing operation on the target memory cell based on the target value of the write operation. If the target value is the first value, a sensing operation will be performed on the target memory cell. If the target value is the second value, a sensing operation will not be performed on the target memory cell. Furthermore, if the target value is a first value and the stored value obtained through the sensing operation is a second value, the read phase of the sensing operation can be directly connected to the write operation through the maintenance phase. This reduces power consumption waste, decreases the number of times the target memory cell is turned on, and improves the efficiency of the write operation. If the target value is a first value and the stored value of the target memory cell obtained through the sensing operation is also a first value, the write operation can be omitted. This reduces the number of write operations performed on the target memory cell and improves the efficiency of the write operation. If the target value is a second value, the write operation can be performed directly, and the voltage difference across the target memory cell can be sequentially increased in multiple phases so that the target memory cell is turned on at a voltage difference close to its threshold voltage. This reduces the current surge generated on the target memory cell during turn-on, saves power consumption generated by the sensing operation, and improves the reliability of writing the second value. In summary, the memory provided by this disclosure has high flexibility in performing operations on the target memory cell in response to a write command, which is beneficial for optimizing its write performance, energy efficiency, and write lifespan.

[0072] The features disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0073] The methods disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0074] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for operating a memory, characterized in that, include: In response to a write command, a sensing operation is performed on the target storage cell of the memory based on the target value of the write operation; If the target value is a first value, in the first stage, the sensing operation is performed on the target storage unit to obtain the storage value of the target storage unit, and based on the matching result between the storage value and the target value, it is determined whether to perform the write operation; If the target value is the second value, the sensing operation is not performed on the target storage unit in the first stage, and the write operation is performed directly after the first stage.

2. The operating method according to claim 1, characterized in that, The threshold voltage of the storage cell storing the first value is greater than the threshold voltage of the storage cell storing the second value.

3. The operating method according to claim 1, characterized in that, The step of determining whether to perform the write operation based on the matching result between the stored value and the target value includes: If the stored value is the first value, the write operation is not performed; if the stored value is not the first value, the write operation is performed.

4. The operating method according to claim 3, characterized in that, Performing the write operation includes: In the second stage following the first stage, the first driving voltage of the target memory cell is increased, and the second driving voltage of the target memory cell is maintained, wherein the first driving voltage is greater than the second driving voltage.

5. The operating method according to claim 3, characterized in that, The statement that the write operation is not performed includes: At the end of the first stage, both the first driving voltage and the second driving voltage of the target storage cell are set to ground voltage.

6. The operating method according to claim 4, characterized in that, The first stage includes a first sub-stage and a maintenance stage following the first sub-stage; the first sub-stage is a read stage; the operation method further includes: During the maintenance phase, the first drive voltage and the second drive voltage of the target storage cell are maintained in the first sub-phase.

7. The operating method according to claim 6, characterized in that, The read phase further includes a second sub-phase preceding the first sub-phase; in the second sub-phase, the difference between the first driving voltage and the second driving voltage of the target storage cell is less than the difference between the first driving voltage and the second driving voltage of the target storage cell in the first sub-phase.

8. The operating method according to claim 7, characterized in that, If the target value is the first value, then in the first stage, the difference between the first driving voltage and the second driving voltage of the target storage cell is the first difference. If the target value is the second value, then in the first stage, the difference between the first driving voltage and the second driving voltage of the target storage cell is the second difference. The first difference is greater than the second difference.

9. The operating method according to claim 4, characterized in that, If the target value is the second value, performing the write operation further includes: In the third stage following the second stage, the first drive voltage of the target memory cell is reduced while the second drive voltage of the target memory cell is maintained.

10. A memory, characterized in that, It includes a storage array and peripheral circuitry coupled to the storage array, the peripheral circuitry being configured to perform the operating method as described in any one of claims 1 to 9.

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