Memory and operating method thereof

Abstract

The present disclosure provides a memory and an operating method thereof, the operating method of the memory including: in response to a write command, performing a sensing operation on a target memory cell at a first stage before a write operation; the result of the sensing operation indicates whether the target storage unit is conducted or not; and in a second stage after the first stage, according to the conduction state of the target storage unit, increasing or reducing the voltage difference between the two ends of the target storage unit.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a memory and its operation method. Background Technology

[0002] To bridge the performance gap between Dynamic Random Access Memory (DRAM) and NAND flash memory, Storage Class Memory (SCM) has been proposed as a new storage medium technology. Mainstream SCM media include Phase-Change Memory (PCM), Resistive Random Access Memory (ReRAM), and Magnetic Random Access Memory (MRAM). Among these, PCM exhibits significant advantages over flash memory in many aspects, such as read / write speed, read / write cycles, data retention time, and cell area. However, PCM still faces several challenges in practical applications, leaving considerable room for optimization. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a memory and a method for operating the same.

[0004] To achieve the above objectives, the technical solution of this disclosure embodiment is implemented as follows: In a first aspect, this disclosure provides a method for operating a memory, including: In response to a write command, a sensing operation is performed on the target storage cell in a first stage prior to the write operation; the result of the sensing operation indicates whether the target storage cell is powered on. In the second stage following the first stage, the voltage difference across the target memory cell is increased or decreased depending on the conduction state of the target memory cell.

[0005] In one optional implementation, increasing or decreasing the voltage difference across the target memory cell based on its on-state includes: If the result of the sensing operation indicates that the target memory cell is turned on, reduce the voltage difference across the target memory cell; If the result of the sensing operation indicates that the target memory cell is not turned on, the voltage difference across the target memory cell is increased.

[0006] In one optional implementation, increasing the voltage difference across the target memory cell includes: Increase the voltage on the first drive line coupled to the target memory cell, and maintain the voltage on the second drive line coupled to the target memory cell.

[0007] In one optional implementation, reducing the voltage difference across the target memory cell includes: Reduce the voltage on the first drive line coupled to the target memory cell, and maintain the voltage on the second drive line coupled to the target memory cell.

[0008] In one optional implementation, the operation method further includes: While increasing the voltage difference across the target memory cell, the voltage on the second drive line coupled to the non-target memory cell coupled to the first drive line is also increased. While reducing the voltage difference across the target memory cell, the voltage on the second drive line coupled to the non-target memory cell is maintained at the ground voltage.

[0009] In one optional implementation, if the result of the sensing operation indicates that the target storage unit is turned on, the target storage unit is configured to store first data or second data before the first stage; if the result of the sensing operation indicates that the target storage unit is not turned on, the target storage unit is configured to store second data before the first stage; the operation method further includes: After the first stage, the write operation is performed on the target storage unit to write the first data into the target storage unit.

[0010] In one optional implementation, performing the write operation on the target storage unit includes: In the first sub-stage of the write operation, a first current is applied to the target memory cell; In the second sub-stage of the write operation, a second current is applied to the target memory cell; the second current is greater than the first current. In the third sub-stage of the write operation, a ramp current, which is uniformly reduced from the second current to the third current, is applied to the target memory cell. In the fourth sub-stage of the write operation, the third current is applied to the target memory cell.

[0011] In one optional implementation, the operation method further includes: In the second and third sub-stages, the voltage applied to the first drive line coupled to the target memory cell is determined based on the electrical distance of the target memory cell; the target memory cell is coupled to the first drive circuit via the first drive line and to the second drive circuit via the second drive line; the electrical distance of the target memory cell is the sum of the length of the first drive line between the target memory cell and the first drive circuit and the length of the second drive line between the target memory cell and the second drive circuit.

[0012] In one alternative implementation, determining the voltage applied to the first drive line coupled to the target memory cell based on the electrical distance of the target memory cell includes: If the electrical distance of the target storage cell is greater than a preset value, the magnitude of the voltage applied to the first driving line is the first voltage value; If the electrical distance of the target storage cell is less than the preset value, the voltage applied to the first driving line is a second voltage value; the first voltage value is greater than the second voltage value.

[0013] In a second aspect, this disclosure provides a memory including a memory array and peripheral circuitry coupled to the memory array; the peripheral circuitry is configured to perform the operation method described in any of the above embodiments.

[0014] In the technical solution provided in this disclosure, before performing a write operation on the target storage cell, a sensing operation can be performed on the target storage cell in the first stage to determine whether the target storage cell is turned on. In the second stage after the first stage, the voltage difference across the target storage cell can be increased or decreased based on the on-state of the target storage cell determined by the sensing operation. Thus, the voltage difference applied across the target storage cell in the second stage can be flexibly set, which helps to improve the reliability of turning on the target storage cell before the write operation and reduce the waste of power consumption. Attached Figure Description

[0015] Figure 1 A schematic diagram of a memory provided for an embodiment of this disclosure; Figure 2 This is a three-dimensional structural diagram of a portion of the storage array provided in an embodiment of the present disclosure; Figure 3 A schematic diagram of the threshold voltage distribution of a memory cell provided in an embodiment of this disclosure; Figure 4 A flowchart illustrating the operation method of the memory provided in this embodiment of the disclosure; Figure 5 Voltage curve 1 for the operation process of the memory provided in the embodiments of this disclosure; Figure 6Voltage curve two for the operation process of the memory provided in this embodiment of the disclosure; Figure 7 Voltage curve three for the operation process of the memory provided in the embodiments of this disclosure; Figure 8 Voltage and current curves for the operation of the memory provided in this embodiment of the present disclosure; Figure 9 A schematic diagram of some peripheral circuits in a memory provided in an embodiment of this disclosure; Figure 10 Voltage and current curves for the operation of the memory provided in this embodiment of the present disclosure. Detailed Implementation

[0016] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0017] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0018] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0019] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0020] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0021] Figure 1 Schematic diagram of the composition of the memory provided in this disclosure Figure 1 , Figure 2 This is a three-dimensional structural diagram of a portion of the memory provided in an embodiment of the present disclosure. (Referring to...) Figure 1 and Figure 2 The memory includes a memory array 10 and peripheral circuitry 20 coupled to the memory array 10. The memory array 10 includes multiple memory cells 100. The memory cells 100 are located between a first driving line 121 and a second driving line 120 in a first direction. Multiple memory cells 100 arranged along a second direction are coupled to a first driving line 121, and multiple memory cells 100 arranged along a third direction are coupled to a second driving line 120. Here, the first direction is taken as the Z direction, the second direction as the X direction, and the third direction as the Y direction, as an example.

[0022] It should be noted that the number of first drive lines, second drive lines, and memory cells shown in the figure are merely examples, and this disclosure does not impose any specific limitations on them. Furthermore, Figure 1 and Figure 2 Taking the storage array 10 as an example, which includes only one layer of storage cells 100, this disclosure is not limited to this. In other embodiments, the storage array 10 may include multiple storage layers stacked along the Z direction, and each storage layer includes multiple first drive lines, multiple second drive lines, and multiple storage cells located between the first drive lines and the second drive lines in the Z direction.

[0023] In some embodiments, refer to Figure 2The memory cell 100 includes a gating element 102 and a phase-change element 104 stacked along a first direction, with the gating element 102 located between the first driving line 121 and the phase-change element 104. Furthermore, the memory cell 100 also includes a first electrode 101, a second electrode 103, and a third electrode 105. The first electrode 101 is located between the gating element 102 and the first driving line 121, the second electrode 103 is located between the gating element 102 and the phase-change element 104, and the third electrode 105 is located between the phase-change element 104 and the second driving line 120. Here, the first driving line 121 can be a word line (WL), and the second driving line 120 can be a bit line (BL).

[0024] In some specific examples, the first electrode 101, the second electrode 103, and the third electrode 105 may include conductive materials and may serve as conductive paths. Here, the conductive material may be at least one of the following: doped semiconductor materials (e.g., doped silicon, doped germanium, etc.), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), metallic materials (e.g., tungsten, titanium, tantalum, aluminum, copper, etc.), and metal semiconductor compounds (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0025] In some specific examples, the second electrode 103 may also include a thermally insulating material, thereby reducing thermal crosstalk between the gating element 102 and the phase change element 104. For example, the second electrode 103 may include amorphous carbon.

[0026] In some specific examples, the resistance of the gating element 102 can vary in response to a change in the selection voltage applied between the first electrode 101 and the second electrode 103. In some embodiments, the gating element 102 may comprise a material having an Ovonic Threshold Switch (OTS) property, which may include at least one element selected from oxygen, sulfur, selenium, tellurium, germanium, antimony, silicon, and arsenic, such as Zn. x Te y 、Ge x Te y 、Nb x O y Si x As y Te z When the voltage applied between the first electrode 101 and the second electrode 103 is lower than its threshold voltage, the gating element 102 can be in a high-resistance state that prevents current from flowing through, and when the voltage applied between the first electrode 101 and the second electrode 103 is higher than its threshold voltage, the gating element 102 can be in a low-resistance state that allows current to flow through.

[0027] In one specific example, the phase change element 104 may include a chalcogenide component, such as at least one of binary compounds such as GaSb, InSb, InSe, SbTe and GeTe, ternary compounds such as GeSbTe, GaSeTe, InSbTe, SnSbTe and InSbGe, and quaternary compounds such as AgInSbTe, (GeSn)SbTe, GeSb(SeTe) and TeGeSbS.

[0028] In some embodiments, the phase change element 104 can reversibly switch between a crystalline and amorphous state, and can utilize the difference in resistivity between its crystalline and amorphous states to achieve data storage. The crystalline phase of the phase change element 104 can be changed through set and reset operations. Specifically, the set operation may include heating the phase change element 104 above the recrystallization temperature by the Joule heat generated by the voltage applied between the first drive line 121 and the second drive line 120, and then slowly decreasing the voltage applied between the first drive line 121 and the second drive line 120, thereby slowly cooling the phase change element 104 to a low-resistivity crystalline state; the reset operation may include heating the phase change element 104 above the melting point by the Joule heat generated by the voltage applied between the first drive line 121 and the second drive line 120, and then rapidly decreasing the voltage applied between the first drive line 121 and the second drive line 120, thereby rapidly cooling the phase change element 104 to a high-resistivity amorphous state. When storage cell 100 is in the set state after a set operation, the data stored in storage cell 100 can be either "0" or "1". When storage cell 100 is in the reset state after a reset operation, the data stored in storage cell 100 can be either "0" or "1". In this embodiment of the present disclosure, the data stored in storage cell 100 in the set state is "1", and the data stored in storage cell 100 in the reset state is "0" is taken as an example.

[0029] In some embodiments, Figure 3This is a schematic diagram of the threshold voltage distribution of the memory cell provided in this embodiment. The threshold voltage of the memory cell in the set state is within the range of the first threshold voltage distribution 201, and the threshold voltage of the memory cell in the reset state is within the range of the second threshold voltage distribution 202. Furthermore, the threshold voltage of the memory cell in the set state is less than the threshold voltage of the memory cell in the reset state. Before writing data to the target memory cell through the aforementioned set operation, the target memory cell needs to be turned on first so that the current during the set operation can be concentrated in the target memory cell. Here, target cell conduction refers to the voltage across the gating element in the target cell being higher than its threshold voltage. The gating element is in the conduction state, and a significant current change can be sensed on the bit line side. When the target cell is in the set state, because the phase-change element is in a low-resistance crystalline state, its voltage division is small, and the voltage proportion of the gating element is high. Therefore, applying a relatively low voltage across the target cell will turn it on, meaning the cell in the set state exhibits a low threshold voltage. When the target cell is in the reset state, because the phase-change element is in a high-resistance amorphous state, its voltage division is large, and the voltage proportion of the gating element is low. Therefore, applying a higher voltage across the target cell will turn it on, meaning the cell in the reset state exhibits a high threshold voltage. Furthermore, slight differences in the fabrication processes of different memory cells may lead to differences in the threshold voltage of the gating element. The resistance of the phase-change element in different memory cells may also differ even in the same state. In other words, different memory cells in the set state may have different threshold voltages, and memory cells in the reset state may also have different threshold voltages.

[0030] In some embodiments, the target memory cell may have already stored data before the set operation is performed. Its threshold voltage may then be within the range of a first threshold voltage distribution 201 or a second threshold voltage distribution 202. To turn on the target memory cell, a voltage can be applied sequentially to the target memory cell in multiple stages, with the voltage applied to the target memory cell increasing sequentially, so that the target memory cell can be turned on at a voltage close to its threshold voltage. To ensure that the target memory cell can be turned on even with the maximum threshold voltage, a higher voltage needs to be applied to the target memory cell in the last stage. However, if the target memory cell has already been turned on before the last stage, applying a higher voltage in the last stage would result in wasted power consumption, and the higher voltage would interfere with other memory cells. For example, the higher voltage might cause non-target memory cells coupled to the same first drive line as the target memory cell to be mis-turned on, thereby reducing the reliability of the data stored in the non-target memory cells.

[0031] In view of the above problems, the present disclosure provides the following implementation methods.

[0032] This disclosure provides a method for operating a memory. Figure 4 This is a flowchart illustrating a method for operating a memory according to an embodiment of the present disclosure. The method for operating the memory includes the following steps: Step S301: In response to the write command, in the first stage before the write operation, a sensing operation is performed on the target storage cell; the result of the sensing operation indicates whether the target storage cell is on. Step S302: In the second stage following the first stage, the voltage difference across the target memory cell is increased or decreased according to the conduction state of the target memory cell.

[0033] Here, the write command can instruct a write operation to be performed on the target storage cell, which can be any storage cell 100 in the storage array 10. The voltage difference across the target storage cell can be the difference between the voltage on the first drive line 121 coupled to the target storage cell and the voltage on the second drive line 120.

[0034] In this embodiment of the disclosure, before performing a write operation on the target memory cell, a sensing operation can be performed on the target memory cell in a first stage to determine whether the target memory cell is turned on. In a second stage following the first stage, based on the on-state of the target memory cell determined by the sensing operation, the voltage difference across the target memory cell can be increased or decreased. This allows for flexible setting of the voltage difference applied across the target memory cell in the second stage, which helps improve the reliability of turning on the target memory cell before the write operation and reduces power consumption waste. This will be explained below with reference to specific examples.

[0035] In some embodiments, Figure 5 Voltage curve 1 for the operation process of the memory provided in this embodiment of the disclosure. Figure 6 Voltage curve two for the operation process of the memory provided in this embodiment of the disclosure. (Referring to...) Figure 5 and Figure 6 The specific process of executing step S301 may include: in response to a write command, in a first stage P1 before the write operation, applying a first voltage V1 to the first driving line WL coupled to the target memory cell, applying a second voltage V2 to the second driving line BL1 coupled to the target memory cell, and performing a sensing operation on the target memory cell; the first voltage V1 is greater than the second voltage V2; the result of the sensing operation indicates whether the target memory cell is turned on. Here, taking the first driving line WL as a word line and the second driving line BL1 as a bit line as an example, the first driving line WL can be any first driving line 121 in the memory array 10, and the second driving line BL1 can be any second driving line 120 in the memory array 10.

[0036] In some specific examples, performing a sensing operation on the target memory cell includes comparing the rate of change of the current on the second drive line BL1 with a preset rate, or comparing the current on the second drive line BL1 with a preset current. When the rate of change of the current on the second drive line BL1 is greater than or equal to the preset rate, or when the current on the second drive line BL1 is greater than or equal to the preset current, the result of the sensing operation can be "1", indicating that the target memory cell is turned on; when the rate of change of the current on the second drive line BL1 is less than the preset rate, or when the current on the second drive line BL1 is less than the preset current, the result of the sensing operation can be "0", indicating that the target memory cell is not turned on.

[0037] In some embodiments, step S302, increasing or decreasing the voltage difference across the target memory cell according to the conduction state of the target memory cell, includes: if the result of the sensing operation indicates that the target memory cell is turned on, decreasing the voltage difference across the target memory cell; if the result of the sensing operation indicates that the target memory cell is not turned on, increasing the voltage difference across the target memory cell.

[0038] In some embodiments, refer to Figure 5 If the sensing operation indicates that the target memory cell is not turned on, increasing the voltage difference across the target memory cell includes increasing the voltage on the first driving line WL coupled to the target memory cell and maintaining the voltage on the second driving line BL1 coupled to the target memory cell. Specifically, in the second stage P2, the voltage on the first driving line WL can be increased from the first voltage V1 to the third voltage V3a, and the voltage on the second driving line BL1 can be maintained at the second voltage V2. Here, the second voltage V2 can be a negative voltage, and the first voltage V1 and the third voltage V3a can both be positive voltages.

[0039] In some embodiments, refer to Figure 6 If the sensing operation indicates that the target memory cell is turned on, reducing the voltage difference across the target memory cell includes: reducing the voltage on the first driving line WL coupled to the target memory cell, and maintaining the voltage on the second driving line BL1 coupled to the target memory cell. Specifically, in the second stage P2, the voltage on the first driving line WL can be reduced from the first voltage V1 to the third voltage V3b, and the voltage on the second driving line BL1 can be maintained at the second voltage V2. Here, for a target memory cell including a gating element and a phase-change element, when it is turned on, the voltage across its terminals can quickly fold back from the threshold voltage to the sustaining voltage, and the sustaining voltage is less than its threshold voltage. Therefore, after the target memory cell is turned on, reducing the voltage difference across its terminals can also maintain its on-state and ensure sufficient voltage margin, so that the current of subsequent write operations can be concentrated in the target memory cell and maintain linear steady current.

[0040] In some specific examples, the third voltage V3a ranges from 5V to 5.5V; the third voltage V3b ranges from 3V to 3.3V; and the second voltage V2 ranges from -3.8V to -3.5V.

[0041] In this embodiment, during the first stage before the write operation, a sensing operation can be performed on the target memory cell while applying a voltage to turn it on to determine whether the target memory cell is already on. If the target memory cell is not on, in the second stage following the first stage, the voltage difference across the target memory cell needs to be increased to turn it on. If the target memory cell is already on, in the second stage, the voltage difference across the target memory cell can be decreased. Therefore, while keeping the voltage on the second drive line BL1 constant, a lower voltage can be applied to the first drive line WL. This saves power consumption from applying voltage to the first drive line WL. Furthermore, it avoids applying a higher voltage to the target memory cell when it is already on, thus reducing the voltage load on the target memory cell and extending its lifespan. Additionally, it reduces the interference of the voltage applied to the first drive line WL on non-target memory cells coupled to the first drive line WL, improving the reliability of data stored in non-target memory cells.

[0042] In some embodiments, in conjunction with reference Figure 5 and Figure 6 The memory operation methods also include: referencing Figure 5 While increasing the voltage difference across the target memory cell, the voltage on the second drive line BL2, which is coupled to the non-target memory cell coupled to the first drive line WL, is also increased. Specifically, the voltage on the second drive line BL2 can be increased from the ground voltage Vss to a fourth voltage V4; refer to Figure 6 While reducing the voltage difference across the target memory cell, the voltage on the second drive line BL2 coupled to the non-target memory cell is maintained at the ground voltage Vss. Here, there can be multiple non-target memory cells coupled to the first drive line WL, and therefore, there can also be multiple second drive lines BL2 coupled to the non-target memory cells.

[0043] In this embodiment of the disclosure, in addition to determining the voltage applied to the first drive line WL in the second stage P2 based on the result of the sensing operation, the voltage applied to the second drive line BL2 coupled to the non-target memory cell in the second stage P2 can also be determined based on the result of the sensing operation. Specifically, if the result of the sensing operation indicates that the target memory cell is not turned on, in the second stage P2, while increasing the voltage on the first drive line WL, the voltage on the second drive line BL2 coupled to the non-target memory cell can also be increased. This reduces the voltage difference across the non-target memory cell coupled to the first drive line WL, preventing the non-target memory cell from being mistakenly turned on and thus reducing the reliability of the data stored in the non-target memory cell. If the result of the sensing operation indicates that the target memory cell is turned on, in the second stage P2, while decreasing the voltage on the first drive line WL, the voltage on the second drive line BL2 can be maintained at the ground voltage Vss. This reduces both the power consumption generated by applying voltage to the first drive line WL and the power consumption generated by applying voltage to the second drive line BL2 coupled to the non-target memory cell, thereby reducing the power consumption required to turn on the target memory cell before the write operation.

[0044] In some embodiments, in conjunction with reference Figure 5 and Figure 6 The memory operation method further includes: in response to a write command, in a third stage P3 prior to the first stage P1, applying a sixth voltage V6 to the first drive line WL and applying a second voltage V2 to the first bit line BL1; the sixth voltage V6 is greater than the second voltage V2 and the sixth voltage V6 is less than the first voltage V1.

[0045] Here, in conjunction with reference Figure 3 , Figure 5 and Figure 6If the target memory cell is in a set state before the write operation and its threshold voltage is relatively low within the range of the first threshold voltage distribution 201, it can be turned on in the third stage P3. If the target memory cell is in a set state before the write operation and its threshold voltage is relatively high within the range of the first threshold voltage distribution 201, or if the target memory cell is in a reset state before the write operation and its threshold voltage is relatively low within the range of the second threshold voltage distribution 202, the target memory cell can be turned on in the first stage P1. If the target memory cell is in a reset state before the write operation and its threshold voltage is relatively high within the range of the second threshold voltage distribution 202, the target memory cell can be turned on in the second stage P2. By gradually increasing the voltage difference across the target memory cell before the write operation, the target memory cell can be turned on at a voltage difference slightly greater than its threshold voltage. This avoids a large current surge during turn-on and reduces the probability of damage to the selection element or unexpected phase transitions caused by local overheating of the phase-change element.

[0046] In some embodiments, if the result of the sensing operation indicates that the target storage cell is turned on, the threshold voltage of the target storage cell is less than or equal to V1-V2, the threshold voltage of the target storage cell is within the range of the first threshold voltage distribution 201, or the threshold voltage of the target storage cell is relatively low within the range of the second threshold voltage distribution 202, then before the first stage P1, the target storage cell is configured to store first data or second data; if the result of the sensing operation indicates that the target storage cell is not turned on, the threshold voltage of the target storage cell is greater than V1-V2, the threshold voltage of the target storage cell is relatively high within the range of the second threshold voltage 202, then before the first stage, the target storage cell is configured to store second data; the memory operation method further includes: after the first stage P1, performing a write operation on the target storage cell to write the first data into the target storage cell. Here, taking the data stored in the storage cell in the set state as the first data and the data stored in the storage cell in the reset state as the second data as an example, the first data can be "1" and the second data can be "0". (Refer to reference...) Figure 5 and Figure 6 The write operation can be a set operation and can be performed in the fourth stage S.

[0047] In some embodiments, refer to Figure 6 If the result of the sensing operation performed in the first stage P1 indicates that the target memory cell has been turned on, then in the second stage P2, a third voltage V3b can be applied to the first drive line WL, and in the fourth stage S after the second stage P2, a write operation is performed on the target memory cell. In the fourth stage S, the voltage applied to the first drive line WL can be equal to the third voltage V3b.

[0048] In other embodiments, Figure 7 The voltage curve three of the memory operation process provided in the embodiments of this disclosure indicates that the target memory cell has been turned on if the result of the sensing operation performed in the first stage P1 indicates that the target memory cell has been turned on. Then, in the second stage P2, a third voltage V3b can be applied to the first drive line WL, and in the fourth stage S after the first stage P1, a write operation is performed on the target memory cell. The second stage P2 can belong to the fourth stage S. Thus, the total time for turning on the target memory cell and performing a write operation on the target memory cell can be shortened, which is beneficial to improving the efficiency of the write operation.

[0049] In some embodiments, Figure 8 The voltage and current curves of the memory operation process provided in this embodiment of the present disclosure are shown in Figure 1. Here, we take the target memory cell being turned on in the first stage P1 as an example. (Refer to...) Figure 8 The write operation on the target memory cell includes: in the first sub-stage S1, applying a first current I1 to the target memory cell, the Joule heat generated by the first current I1 preheats the phase change element in the target memory cell; in the second sub-stage S2, applying a second current I2 to the target memory cell, the second current I2 being greater than the first current I1, the Joule heat generated by the second current I2 further raising the temperature of the phase change element and rapidly forming a high-density crystal nucleus; in the third sub-stage S3, applying a ramp current Ir that uniformly decreases from the second current I2 to the third current I3 to the target memory cell, the temperature of the phase change element uniformly decreasing and the crystal nucleus growing uniformly and controllably; in the fourth sub-stage S4, applying a third current I3 to the target memory cell, the Joule heat generated by the third current I3 annealing the phase change element, releasing residual stress, and reducing lattice defects. Through the application of current in the four sub-stages, the phase change element can be transformed into a low-resistivity crystalline state, thereby configuring the target memory cell to store the first data.

[0050] In some specific examples, Figure 9 This is a schematic diagram of some peripheral circuits in a memory provided in an embodiment of the present disclosure, in conjunction with reference to... Figure 1 , Figure 8 and Figure 9 The peripheral circuitry 20 in the memory may include a first driving circuit 211, a second driving circuit 212, and a programmable current mirror array 213. Any memory cell 100 in the memory array 10 can be coupled to the first driving circuit 211 via a first driving line 121 and to the second driving circuit 212 via a second driving line 120. Here, the first driving circuit 211 can be a word line driving circuit, and the second driving circuit 212 can be a bit line driving circuit.

[0051] In some specific examples, for a target memory cell, the first driving circuit 211 can transmit a first driving voltage to the target memory cell through the first driving line WL, and the second driving circuit 212 can transmit a second driving voltage to the target memory cell through the second driving line BL1. During the write operation, a programmable current mirror array 213 coupled to the second driving line BL1 via the second driving circuit 212 can adjust the current on the second driving line BL1, allowing different currents to be applied to the target memory cell at different sub-stages of the write operation. Here, the programmable current mirror array 213 can include multiple parallel PMOS transistors. The sources of the multiple PMOS transistors are coupled to the power supply voltage, and their drains are coupled to the input terminal of the second driving circuit 212 through a common-gate transistor. By controlling the number of PMOS transistors that are turned on, the magnitude of the drain current output by the common-gate transistor can be adjusted, thereby regulating the current on the second driving line BL1.

[0052] In some embodiments, Figure 10 The voltage and current curves of the memory operation process provided in this embodiment of the present disclosure are shown in reference to [reference needed]. Figure 8 , Figure 9 and Figure 10 The memory operation method further includes: in the second sub-stage S2 and the third sub-stage S3, determining the voltage applied to the first driving line WL coupled to the target memory cell based on the electrical distance of the target memory cell; the electrical distance of the target memory cell is the sum of the length of the first driving line WL between the target memory cell and the first driving circuit 211 and the length of the second driving line BL1 between the target memory cell and the second driving circuit 212.

[0053] It is understandable that the longer the length of the first driving line WL between the target storage cell and the first driving circuit 211, the greater the voltage drop of the first driving voltage transmitted from the first driving circuit 211 to the target storage cell. Similarly, the longer the length of the second driving line BL2 between the target storage cell and the second driving circuit 212, the greater the voltage drop of the second driving voltage transmitted from the second driving circuit 212 to the target storage cell. Therefore, when the magnitudes of the first driving voltage output by the first driving circuit 211 and the second driving voltage output by the second driving circuit 212 remain unchanged, the voltage difference across the target storage cell is negatively correlated with its electrical distance.

[0054] In some embodiments, refer to Figure 10 If the electrical distance to the target memory cell is greater than a preset value, i.e., the target memory cell is located at a far end with a large voltage drop, the magnitude of the voltage applied to the first drive line WL is the first voltage value V5b; refer to Figure 8If the electrical distance of the target memory cell is less than a preset value, that is, the target memory cell is located at the near end with a smaller voltage drop, the magnitude of the voltage applied to the first drive line WL is the second voltage value V5a; the first voltage value V5b is greater than the second voltage value V5a.

[0055] In this embodiment of the disclosure, since a high current needs to be applied to the target memory cell in the second sub-stage S2 and the third sub-stage S3 of the write operation, if the target memory cell is a memory cell located at a far end, the sum of the length of the first driving line WL between it and the first driving circuit 211 and the length of the second driving line BL1 between it and the second driving circuit 212 is large. This results in a large voltage drop of the first driving voltage transmitted from the first driving circuit 211 to the target memory cell and / or a large voltage drop of the second driving voltage transmitted from the second driving circuit 212 to the target memory cell. Consequently, the actual voltage difference across the target memory cell is small, the conduction degree of the target memory cell is reduced, and the voltage on the second driving line BL2 side cannot maintain the minimum drain saturation voltage of the PMOS transistor in the programmable current mirror array 213. This causes the PMOS transistor to enter the linear region and cannot provide a sufficiently large current to the target memory cell. The phase change element does not receive enough Joule heat and crystallization is incomplete, thereby reducing the reliability of the write operation. When the magnitude of the voltage applied to the first driving line WL in the second sub-stage S2 and the third sub-stage S3 is determined based on the electrical distance of the target memory cell, the voltage on the first driving line WL can be compensated when the target memory cell is a memory cell located at a far end. This allows the PMOS transistor in the programmable current mirror array 213 to remain in the saturation region and provide a stable large current to the target memory cell, thereby improving the reliability of the write operation.

[0056] In this embodiment, in a first stage before performing a write operation on the target memory cell, a sensing operation is performed on the target memory cell to determine whether the target memory cell is turned on in the first stage. The voltage difference across the target memory cell in the second stage can be determined based on the on-state of the target memory cell. When the sensing operation indicates that the target memory cell is turned on, the voltage difference across the target memory cell can be reduced, thereby reducing the power consumption to turn on the target memory cell, reducing the voltage load on the target memory cell, extending the lifespan of the target memory cell, and reducing interference to non-target memory cells. When the sensing operation indicates that the target memory cell is not turned on, the voltage difference across the target memory cell can be increased, thereby ensuring that the target memory cell can be turned on even with a higher threshold voltage, improving the reliability of turning on the target memory cell. Furthermore, after turning on the target memory cell, when performing a write operation on the target memory cell, if the target memory cell is at a far end with a large voltage drop, the voltage difference across the target memory cell can be compensated, so that the current applied to the target memory cell can remain a stable large current, thereby improving the reliability of the write operation.

[0057] Based on a concept similar to the memory described above, this disclosure also provides a memory, referring to... Figure 1 The memory includes a memory array 10 and peripheral circuitry 20 coupled to the memory array 10; the peripheral circuitry 20 is configured to execute the memory operation method provided in any of the above embodiments. The memory can achieve all the effects achievable by the memory operation methods in the above embodiments.

[0058] In some embodiments, the peripheral circuit 20 is configured to: in response to a write command, perform a sensing operation on the target memory cell in a first stage before the write operation; the result of the sensing operation indicates whether the target memory cell is on; and in a second stage after the first stage, increase or decrease the voltage difference across the target memory cell according to the on state of the target memory cell.

[0059] In some embodiments, the peripheral circuit 20 is specifically configured to: if the result of the sensing operation indicates that the target memory cell is turned on, reduce the voltage difference across the target memory cell; if the result of the sensing operation indicates that the target memory cell is not turned on, increase the voltage difference across the target memory cell.

[0060] In some embodiments, the peripheral circuit 20 is specifically configured to: if the result of the sensing operation indicates that the target memory cell is not turned on, increase the voltage on the first driving line coupled to the target memory cell, and maintain the voltage on the second driving line coupled to the target memory cell, so as to increase the voltage difference across the target memory cell.

[0061] In some embodiments, the peripheral circuit 20 is specifically configured to: if the result of the sensing operation indicates that the target memory cell has been turned on, reduce the voltage on the first driving line coupled to the target memory cell and maintain the voltage on the second driving line coupled to the target memory cell, so as to reduce the voltage difference across the target memory cell.

[0062] In some embodiments, the peripheral circuit 20 is further configured to: increase the voltage on the second drive line coupled to the non-target memory cell while increasing the voltage difference across the target memory cell; and maintain the voltage on the second drive line coupled to the non-target memory cell at ground voltage while decreasing the voltage difference across the target memory cell.

[0063] In some embodiments, if the result of the sensing operation indicates that the target storage unit is turned on, the target storage unit is configured to store first data or second data before the first stage; if the result of the sensing operation indicates that the target storage unit is not turned on, the target storage unit is configured to store the second data before the first stage; the peripheral circuit 20 is further configured to: after the first stage, perform the write operation on the target storage unit to write the first data into the target storage unit.

[0064] In some embodiments, the peripheral circuit 20 is specifically configured to: apply a first current to the target memory cell in a first sub-stage of the write operation; apply a second current to the target memory cell in a second sub-stage of the write operation; the second current is greater than the first current; apply a ramp current to the target memory cell in a third sub-stage of the write operation, the second current being uniformly reduced to a third current; and apply the third current to the target memory cell in a fourth sub-stage of the write operation.

[0065] In some embodiments, the peripheral circuit 20 is further configured to: determine, in the second sub-stage and the third sub-stage, a voltage applied to a first drive line coupled to the target memory cell based on the electrical distance of the target memory cell; the target memory cell is coupled to a first drive circuit via the first drive line and to a second drive circuit via a second drive line; the electrical distance of the target memory cell is the sum of the length of the first drive line between the target memory cell and the first drive circuit and the length of the second drive line between the target memory cell and the second drive circuit.

[0066] In some embodiments, the peripheral circuit 20 is specifically configured to: apply a voltage of a first voltage value to the first driving line if the electrical distance of the target memory cell is greater than a preset value; apply a voltage of a second voltage value to the first driving line if the electrical distance of the target memory cell is less than the preset value; wherein the first voltage value is greater than the second voltage value.

[0067] In this embodiment, the peripheral circuitry of the memory can be configured to perform a sensing operation on the target memory cell in a first stage before performing a write operation on the target memory cell, to determine whether the target memory cell is turned on in the first stage, and to determine the voltage difference across the target memory cell in a second stage after the first stage based on the on-state of the target memory cell. When the sensing operation indicates that the target memory cell is turned on, the voltage difference across the target memory cell can be reduced, thereby reducing the power consumption to turn on the target memory cell, reducing the voltage load on the target memory cell, extending the lifespan of the target memory cell, and reducing interference to non-target memory cells. When the sensing operation indicates that the target memory cell is not turned on, the voltage difference across the target memory cell can be increased, thereby ensuring that the target memory cell can be turned on even with a higher threshold voltage, improving the reliability of turning on the target memory cell. Furthermore, the peripheral circuitry can also be configured to increase the voltage difference across the target memory cell when the target memory cell is at a far end with a large voltage drop during a write operation, so that the current applied to the target memory cell can remain a stable large current, thereby improving the reliability of the write operation.

[0068] The features disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0069] The methods disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0070] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for operating a memory, characterized in that, include: In response to a write command, a sensing operation is performed on the target storage cell in the first stage before the write operation. The result of the sensing operation indicates whether the target storage unit is powered on; In the second stage following the first stage, the voltage difference across the target memory cell is increased or decreased depending on the conduction state of the target memory cell.

2. The operating method according to claim 1, characterized in that, The step of increasing or decreasing the voltage difference across the target memory cell based on its conduction state includes: If the result of the sensing operation indicates that the target memory cell is turned on, reduce the voltage difference across the target memory cell; If the result of the sensing operation indicates that the target memory cell is not turned on, the voltage difference across the target memory cell is increased.

3. The operating method according to claim 2, characterized in that, Increasing the voltage difference across the target memory cell includes: Increase the voltage on the first drive line coupled to the target memory cell, and maintain the voltage on the second drive line coupled to the target memory cell.

4. The operating method according to claim 3, characterized in that, The reduction of the voltage difference across the target memory cell includes: Reduce the voltage on the first drive line coupled to the target memory cell, and maintain the voltage on the second drive line coupled to the target memory cell.

5. The operating method according to claim 4, characterized in that, The operation method further includes: While increasing the voltage difference across the target memory cell, the voltage on the second drive line coupled to the non-target memory cell coupled to the first drive line is also increased. While reducing the voltage difference across the target memory cell, the voltage on the second drive line coupled to the non-target memory cell is maintained at the ground voltage.

6. The operating method according to claim 1, characterized in that, If the result of the sensing operation indicates that the target storage unit is turned on, the target storage unit is configured to store first data or second data before the first stage; if the result of the sensing operation indicates that the target storage unit is not turned on, the target storage unit is configured to store second data before the first stage. The operation method further includes: After the first stage, the write operation is performed on the target storage unit to write the first data into the target storage unit.

7. The operating method according to claim 6, characterized in that, The step of performing the write operation on the target storage unit includes: In the first sub-stage of the write operation, a first current is applied to the target memory cell; In the second sub-stage of the write operation, a second current is applied to the target memory cell; the second current is greater than the first current. In the third sub-stage of the write operation, a ramp current, which is uniformly reduced from the second current to the third current, is applied to the target memory cell. In the fourth sub-stage of the write operation, the third current is applied to the target memory cell.

8. The operating method according to claim 7, characterized in that, The operation method further includes: In the second and third sub-stages, the voltage applied to the first drive line coupled to the target memory cell is determined based on the electrical distance of the target memory cell; the target memory cell is coupled to the first drive circuit via the first drive line and to the second drive circuit via the second drive line; the electrical distance of the target memory cell is the sum of the length of the first drive line between the target memory cell and the first drive circuit and the length of the second drive line between the target memory cell and the second drive circuit.

9. The operating method according to claim 8, characterized in that, The determination of the voltage applied to the first drive line coupled to the target memory cell based on the electrical distance of the target memory cell includes: If the electrical distance of the target storage cell is greater than a preset value, the magnitude of the voltage applied to the first driving line is the first voltage value; If the electrical distance of the target storage cell is less than the preset value, the voltage applied to the first driving line is a second voltage value; the first voltage value is greater than the second voltage value.

10. A memory, characterized in that, It includes a storage array and peripheral circuitry coupled to the storage array; the peripheral circuitry is configured to perform the operating method according to any one of claims 1 to 9.

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