UPS (Uninterrupted Power Supply) parallel operation synchronous phase circuit and control method thereof

Abstract

The invention discloses a UPS (Uninterrupted Power Supply) parallel operation synchronous phase circuit and a control method thereof, the UPS parallel operation synchronous phase circuit comprises a plurality of UPS controllers which are connected in parallel, and all the UPS controllers are in cascade connection through synchronous control pins; the UPS controller generates a PWM signal to control on or off of a UPS switching tube of the UPS controller, captures a falling edge interrupt signal at the same time, shifts the output phase of the UPS to 0 degree according to the falling edge interrupt signal, and achieves phase synchronization of all the UPSs. There is no master-slave control system; a decentralized logic control system is adopted, and a plurality of uninterrupted power supplies (UPS) operate in parallel; when a fault occurs, a fault module is automatically cut off, and normal output of other UPSs is not affected; and the rest modules bear all loads, so that seamless switching is realized. Hot plug is supported, and capacity expansion is facilitated; the output phase is synchronized before the UPS is powered on, the dynamic response is fast, and the reliability is high.

Description

Technical Field

[0001] This invention belongs to the field of UPS uninterruptible power supply circuits, specifically relating to a UPS uninterruptible power supply parallel synchronous phase circuit and its control method. Background Technology

[0002] A UPS (Uninterruptible Power Supply) is characterized by its uninterrupted power output and consists of main components such as batteries, inverters, and static switches. Currently, in existing technologies, parallel operation of UPS systems typically relies on the master unit for load distribution and synchronization, with slave units following the master unit's output. A failure of the master unit can lead to system paralysis; therefore, reliability depends on the master unit. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a parallel synchronous phase circuit for UPS uninterruptible power supply and its control method, which solves the problem of unstable reliability in the master-slave device management of UPS uninterruptible power supply in the prior art.

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0005] A UPS uninterruptible power supply parallel synchronization phase circuit includes several UPS uninterruptible power supply controllers connected in parallel. All UPS uninterruptible power supply controllers are cascaded through synchronization control pins. Each UPS uninterruptible power supply controller generates a PWM signal to control the on or off of its own UPS uninterruptible power supply switching transistor, and simultaneously captures a falling edge interrupt signal. Based on the falling edge interrupt signal, the output phase of the UPS uninterruptible power supply is shifted to 0 degrees to achieve phase synchronization of all UPS uninterruptible power supplies.

[0006] The UPS uninterruptible power supply controller includes two operating modes: single-unit operation mode and multi-unit synchronous operation mode. In single-unit operation mode, the timer of the UPS uninterruptible power supply controller generates a PWM signal to control the on or off of the UPS uninterruptible power supply switching transistors. In multi-unit synchronous operation mode, multiple UPS uninterruptible power supply controllers simultaneously generate PWM signals to control the on or off of their respective UPS uninterruptible power supply switching transistors, and perform phase synchronization control according to the phase synchronization signal.

[0007] The UPS has a hot-swappable port, and the newly connected UPS completes phase synchronization settings upon power-up.

[0008] The UPS uninterruptible power supply controller simultaneously receives and sends synchronization signals. After synchronization is completed, the control output relay closes.

[0009] The synchronization signal is a PWM signal, which is received and transmitted through the same pin of the UPS uninterruptible power supply controller.

[0010] The UPS uninterruptible power supply parallel synchronous phase control method includes single-unit operation mode control and multi-unit synchronous operation mode control; wherein, the single-unit operation mode control includes the following steps:

[0011] Step 1: The timer of the UPS uninterruptible power supply controller generates a PWM signal and outputs it to the control terminal of the UPS uninterruptible power supply switching transistor.

[0012] Step 2: The UPS uninterruptible power supply controller captures the falling edge interrupt signal at the output of the UPS uninterruptible power supply switching transistor and inputs it to the phase synchronization control terminal.

[0013] Step 3: The phase synchronization control terminal shifts the output phase of the UPS uninterruptible power supply to 0 degrees based on the falling edge signal;

[0014] Multi-machine synchronous operation mode control includes the following steps:

[0015] Step a: The timers of multiple UPS uninterruptible power supply controllers simultaneously generate PWM signals and output them to the control terminals of their respective UPS uninterruptible power supply switching transistors;

[0016] Step b: Each UPS controller captures the falling edge interrupt signal at the output of the UPS uninterruptible power supply switching transistor, and sets the timer count value that generates the PWM signal to 0 based on the falling edge signal.

[0017] Step c: Each UPS controller shifts the output phase of the UPS to 0 degrees based on the falling edge signal;

[0018] Step d: Real-time synchronization control of the output phase of all UPS uninterruptible power supplies using synchronization signals.

[0019] The duty cycle of the PWM signal generated by the timer and the PWM signal of the synchronization signal of the UPS uninterruptible power supply controller are both 50%.

[0020] Compared with the prior art, the present invention has the following beneficial effects:

[0021] 1. There is no master-slave control system; a distributed logic control system is adopted, with multiple UPS uninterruptible power supplies operating in parallel; in case of a fault, the faulty module is automatically disconnected without affecting the normal output of other UPSs; the remaining modules bear the entire load, achieving seamless switching.

[0022] 2. Convenient to add parallel UPS at any time to increase output capacity, supports hot-swapping, and facilitates capacity expansion; the output phase is synchronized before the UPS is powered on and started, with fast dynamic response and high reliability. Attached Figure Description

[0023] Figure 1This is a schematic diagram of the phase synchronization circuit for multiple parallel units in this invention.

[0024] Figure 2 This is a PWM control circuit diagram for the UPS uninterruptible power supply controller of the present invention.

[0025] Figure 3 This is a circuit diagram of the UPS uninterruptible power supply parallel control circuit of the present invention.

[0026] Figure 4 This is a simulation waveform diagram of the PWM control signal for parallel operation of the UPS uninterruptible power supply according to the present invention. Detailed Implementation

[0027] The structure and working process of the present invention will be further described below with reference to the accompanying drawings.

[0028] A UPS uninterruptible power supply parallel synchronization phase circuit includes several UPS uninterruptible power supply controllers connected in parallel. All UPS uninterruptible power supply controllers are cascaded through synchronization control pins. Each UPS uninterruptible power supply controller generates a PWM signal to control the on or off of its own UPS uninterruptible power supply switching transistor, and simultaneously captures a falling edge interrupt signal. Based on the falling edge interrupt signal, the output phase of the UPS uninterruptible power supply is shifted to 0 degrees to achieve phase synchronization of all UPS uninterruptible power supplies.

[0029] Specific embodiments, such as Figures 1 to 4 As shown:

[0030] This embodiment uses the parallel operation of two UPS uninterruptible power supplies as an example to provide a detailed explanation of the specific solution.

[0031] A UPS uninterruptible power supply parallel synchronous phase circuit includes two UPS uninterruptible power supply controllers connected in parallel, namely U1 and U2. Pin 1 of U1 and U2 is cascaded as a synchronous control pin. The timer of U1 is connected to the control terminal of transistor Q1 through pin 2, and the timer of U2 is connected to the control terminal of transistor Q2 through pin 2.

[0032] The UPS uninterruptible power supply controller generates a PWM signal to control the on or off of its own UPS uninterruptible power supply switching transistor. At the same time, it captures the falling edge interrupt signal and shifts the output phase of the UPS uninterruptible power supply to 0 degrees according to the falling edge interrupt signal, so as to achieve phase synchronization of all UPS uninterruptible power supplies.

[0033] The UPS uninterruptible power supply controller includes two operating modes: single-unit operation mode and multi-unit synchronous operation mode. In single-unit operation mode, the timer of the UPS uninterruptible power supply controller generates a PWM signal to control the on or off of the UPS uninterruptible power supply switching transistors. In multi-unit synchronous operation mode, multiple UPS uninterruptible power supply controllers simultaneously generate PWM signals to control the on or off of their respective UPS uninterruptible power supply switching transistors, and perform phase synchronization control according to the phase synchronization signal.

[0034] The UPS (Uninterruptible Power Supply) has a hot-swappable port, and a newly connected UPS completes phase synchronization settings upon power-up. The specific control circuit is as follows: Figure 3 As shown, this machine simultaneously receives and sends synchronization signals, without a master-slave distinction. After synchronization is complete, the output relay KV1 is closed via GPIO control.

[0035] The UPS uninterruptible power supply parallel synchronous phase control method includes single-unit operation mode control and multi-unit synchronous operation mode control; wherein, the single-unit operation mode control includes the following steps:

[0036] Step 1: The timer of the UPS uninterruptible power supply controller generates a PWM signal and outputs it to the control terminal of the UPS uninterruptible power supply switching transistor.

[0037] Step 2: The UPS uninterruptible power supply controller captures the falling edge interrupt signal at the output of the UPS uninterruptible power supply switching transistor and inputs it to the phase synchronization control terminal.

[0038] Step 3: The phase synchronization control terminal shifts the output phase of the UPS uninterruptible power supply to 0 degrees based on the falling edge signal;

[0039] Multi-machine synchronous operation mode control includes the following steps:

[0040] Step a: The timers of multiple UPS uninterruptible power supply controllers simultaneously generate PWM signals and output them to the control terminals of their respective UPS uninterruptible power supply switching transistors;

[0041] Step b: Each UPS controller captures the falling edge interrupt signal at the output of the UPS uninterruptible power supply switching transistor, and sets the timer count value that generates the PWM signal to 0 based on the falling edge signal.

[0042] Step c: Each UPS controller shifts the output phase of the UPS to 0 degrees based on the falling edge signal;

[0043] Step d: Real-time synchronization control of the output phase of all UPS uninterruptible power supplies using synchronization signals.

[0044] The working principle of the UPS uninterruptible power supply parallel synchronous phase control circuit is as follows:

[0045] The synchronization signal generated by U1-MCU and the synchronization signal generated by U2-MCU are synchronized, such as Figure 2 As shown:

[0046] The main signals are as follows:

[0047] PWM1: PWM1 is a PWM signal with a 50% duty cycle and a frequency of 50Hz issued by the microcontroller of this machine;

[0048] PWM2: PWM2 is an externally input PWM signal with a 50% duty cycle and a 50Hz frequency (PWM2 signal has two states: low level and high impedance).

[0049] CAP_IO: CAP_IO is the input capture pin of the microcontroller used to capture falling edge signals.

[0050] 1. Considering only the local signal PWM1 and ignoring the external signal PWM2 (PWM2 is in high impedance by default)

[0051] 1.1 PWM1 is a PWM signal with a 50% duty cycle and a frequency of 50Hz emitted by the microcontroller. When PWM1 is in a low-level state, it can be used to... Figure 2 It was found that the voltage at pin 7 of U1A is higher than the voltage at pin 6 of U1A. According to the comparator principle, the CAP_IO signal is at a high level at this time. When PWM1 is at a high level, it can be... Figure 2 It was found that the voltage at pin 7 of U1A was lower than that at pin 6 of U1A. According to the comparator principle, the CAP_IO signal is at a low level at this time. When CAP_IO changes from a high level to a low level, this signal can be captured by the falling edge capture interrupt of the microcontroller's timer input capture function.

[0052] 1.2 Processing of captured falling edge signals:

[0053]

[0054] Variables in the above code

[0055] Pid.PHA1_Ang represents the real-time phase angle. Taking a 50Hz output as an example, with a sampling frequency of 12.8kHz, one cycle of 360° is divided into 128000 / 50 = 256 discrete points. At each sampling point, Pid.PHA1_Ang is incremented by 360° / 256 = 1.40625° until if(Pid.PHA1_Ang>=360) Pid.PHA1_Ang-=360. The code above slowly moves Pid.PHA1_Ang towards 180° each time input capture is entered, ensuring that the value of Pid.PHA1_Ang is around 180° each time an interrupt occurs during capture.

[0056] __HAL_TIM_SET_COUNTER(&htim3,44); This code rewrites the count value of the TIM3 timer; the parameter 44 is an empirical value;

[0057] TIM3 is the timer mentioned above that outputs the PWM1 (50% duty cycle 50Hz PWM signal). After each input capture, the timer counter value is refilled to make the timer more synchronized.

[0058] 2. Figure 2 PWM2 signal:

[0059] 2.1 The PWM2 signal is both a local output and an external input; it is equivalent to the PWM2 signal of other machines (which can be multiple devices) being connected to the PWM2 signal of this machine.

[0060] 2.2 From Figure 2 It can be seen that when PWM1 is in a high-level state or the PWM2 signal is in a low-level state, CAP_IO is in a low-level state. CAP_IO is in a high-level state only when PWM1 is in a low-level state and the PWM2 signal is in a high-level state (or high-impedance state).

[0061] 3. Multi-machine synchronous operation mode, such as Figure 3 As shown: Multiple UPS units simultaneously generate a 50Hz phase synchronization signal. Figure 3 In the diagram, the 50Hz PWM signal for device #1 is a signal generated by the device itself; the 50Hz PWM signal for device #2 is an external signal; and the processed signal is the CAP_IO signal.

[0062] 3.1 Timer U1 generates a 50Hz PWM high / low level signal with a 50% duty cycle via pin 2 to control the on / off state of transistor Q1; timer U2 generates a 50Hz PWM high / low level signal with a 50% duty cycle via pin 2 to control the on / off state of transistor Q2.

[0063] 3.2 When U1 captures a falling edge signal via pin 1 input falling edge interrupt, the timer count value for generating the PWM signal via pin 2 will be reduced to 0; when U2 captures a falling edge signal via pin 1 input falling edge interrupt, the timer count value for generating the PWM signal via pin 2 will be reduced to 0.

[0064] 3.3 When U1 captures a falling edge signal through the falling edge interrupt input at pin 1, the UPS will slowly shift the output phase to 0 degrees. When U2 captures a falling edge signal through the falling edge interrupt input at pin 1, the UPS will slowly shift the output phase to 0 degrees.

[0065] 3.4 Real-time synchronization of the output phase of multiple UPS units is achieved by synchronizing the 50HZ PWM signal emitted by pin 2 of the MCU in real time using a synchronization signal.

[0066] This machine simultaneously receives and sends synchronization signals, without a master-slave distinction. After synchronization is complete, the output relay KV1 is closed via GPIO control.

[0067] This UPS power supply solution supports hot-swapping: for example, if one or more devices are already running in the system, the logic for connecting another device without interrupting power is as follows:

[0068] 1. The PWM1 signal output is not enabled when the device is powered on. Figure 2 If the PWM1 signal is not entered within 2 seconds (i.e., the CAP_IO input capture is not changed), the timer for the PWM1 signal output is enabled to output a PWM signal with a 50% duty cycle of 50Hz.

[0069] 2. Within 2 seconds, CAP_IO captures a falling edge interrupt and executes the code mentioned above to adjust the phase angle (i.e., the value of Pid.PHA1_Ang). At the same time, it changes the counter value of the timer for the output PWM1 signal. After the timer synchronization is completed and the delay time (the aforementioned 2-second delay) is reached, the timer outputs the PWM1 signal. When the Pid.PHA1_Ang value adjustment is complete and the output voltage is equal to the parallel voltage, the output relay closes.

[0070] It should be understood that this solution is not limited to the specific embodiments described above. Devices and structures not described in detail herein should be understood as being implemented in a manner common to the art. Any person skilled in the art can make many possible variations and modifications to this solution, or modify it into equivalent embodiments, without departing from the scope of this solution, using the methods and techniques disclosed above. This does not affect the substantive content of this solution. Therefore, any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this solution, without departing from its scope, still fall within the protection scope of this solution.

Claims

1. A UPS uninterruptible power supply parallel synchronization phase circuit, characterized in that: The UPS uninterruptible power supply controller includes several parallel connected UPS uninterruptible power supply controllers, which are connected in cascade through a synchronization control pin; the UPS uninterruptible power supply controller generates a PWM signal to control the conduction or turn-off of the UPS uninterruptible power supply switch tube, and simultaneously captures a falling edge interrupt signal, and according to the falling edge interrupt signal, the output phase of the UPS uninterruptible power supply is shifted to 0 degrees, so as to realize the phase synchronization of all the UPS uninterruptible power supplies.

2. The UPS uninterruptible power supply parallel synchronization phase circuit of claim 1, wherein: The UPS uninterruptible power supply controller includes two working modes, namely, single machine operation mode and multi-machine synchronous operation mode; in the single machine operation mode, the timer of the UPS uninterruptible power supply controller generates a PWM signal to control the conduction or turn-off of the UPS uninterruptible power supply switch tube; in the multi-machine synchronous operation mode, multiple UPS uninterruptible power supply controllers simultaneously generate PWM signals to control the conduction or turn-off of the respective UPS uninterruptible power supply switch tubes, and perform phase synchronization control according to a phase synchronization signal.

3. The UPS uninterruptible power supply parallel synchronization phase circuit of claim 2, wherein: The UPS uninterruptible power supply has a hot plug port, and the newly connected UPS uninterruptible power supply completes phase synchronization setting when powered on.

4. The UPS uninterruptible power supply parallel synchronization phase circuit of claim 1, wherein: The UPS uninterruptible power supply controller simultaneously receives and sends a synchronization signal, and after synchronization is completed, controls the output relay to be closed.

5. The UPS uninterruptible power supply parallel synchronization phase circuit of claim 4, wherein: The synchronization signal is a PWM signal, and the receiving and sending functions are realized through the same pin of the UPS uninterruptible power supply controller.

6. A method for synchronizing the phase of parallel connected UPSs, characterized in that: The single machine operation mode control and the multi-machine synchronous operation mode control are included; the single machine operation mode control includes the following steps: Step 1: The timer of the UPS uninterruptible power supply controller generates a PWM signal and outputs to the control end of the UPS uninterruptible power supply switch tube; Step 2: The UPS uninterruptible power supply controller captures the falling edge interrupt signal of the output end of the UPS uninterruptible power supply switch tube and inputs to the phase synchronization control end; Step 3: The phase synchronization control end shifts the output phase of the UPS uninterruptible power supply to 0 degrees according to the falling edge signal; The multi-machine synchronous operation mode control includes the following steps: Step a: The timers of multiple UPS uninterruptible power supply controllers simultaneously generate PWM signals and output to the control ends of the respective UPS uninterruptible power supply switch tubes; Step b: Each UPS uninterruptible power supply controller captures the falling edge interrupt signal of the output end of the UPS uninterruptible power supply switch tube, and according to the falling edge signal, sets the count value of the PWM signal generating timer to 0; Step c: Each UPS uninterruptible power supply controller shifts the output phase of the UPS uninterruptible power supply to 0 degrees according to the falling edge signal; Step d: Through the synchronization signal, the output phases of all the UPS uninterruptible power supplies are synchronously controlled in real time.

7. The method of claim 6, wherein the method further comprises: The duty cycle of the PWM signal generated by the timer of the UPS uninterruptible power supply controller and the PWM signal of the synchronization signal is 50%.

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