Trench structure, trench capacitor and manufacturing method of trench capacitor

Abstract

The embodiment of the invention discloses a trench structure, a trench capacitor and a manufacturing method of the trench capacitor. The trench capacitor includes a trench structure. The trench structure includes a semiconductor region, a trench, a dielectric, and a first electrode region. A dielectric covers the bottom wall and at least a portion of the inner sidewalls of the trench. A first electrode region is filled in the trench including the dielectric. The inner side wall comprises at least two continuous sub-side walls, the sub-side wall of the uppermost section is basically perpendicular to the upper surface of the semiconductor region, and the sub-side walls of the remaining sections are inclined to the sub-side wall of the uppermost section. The semiconductor region includes a semiconductor substrate, a first well region, and a second electrode region. The first well region is formed on the semiconductor substrate and has a first conductive type. The second electrode region is formed in the first well region, surrounds the contour of the trench, and has the first conductivity type. The inclined sub-side walls improve the forming quality of the second electrode region, thereby improving the performance of the trench capacitor.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, specifically to a trench structure, a trench capacitor, and a method for manufacturing a trench capacitor. Background Technology

[0002] Deep trench capacitors (DTCs) offer advantages such as high capacitance density, small area, ease of high-density implementation, good frequency characteristics, and compatibility with CMOS, BCD, and other processes. They are widely used as on-chip capacitors in integrated circuits. Improving the performance and reliability of trench capacitors has become a pressing issue in this field. Summary of the Invention

[0003] This application provides a trench structure, a trench capacitor, and a method for manufacturing the trench capacitor.

[0004] According to one aspect of this application, a trench structure is provided, comprising: Semiconductor region; A trench extends from the upper surface of the semiconductor region into its interior; A dielectric material covering the bottom wall and at least part of the inner sidewall of the trench; and The first electrode region is filled in a trench including the dielectric. The inner sidewall includes at least two continuous sub-sidewalls, the uppermost sub-sidewall being substantially perpendicular to the upper surface of the semiconductor region, and the remaining sub-sidewalls being inclined to the uppermost sub-sidewall.

[0005] In some embodiments, along the direction from the upper surface of the semiconductor region to the lower surface of the semiconductor region, the angle between the sub-sidewalls of the remaining segments and the sub-sidewalls of the uppermost segment increases sequentially.

[0006] In some embodiments, the inner sidewall includes two sub-sidewalls, wherein the two sub-sidewalls include a first sub-sidewall located in the upper segment and a second sub-sidewall located in the lower segment, and the height of the first sub-sidewall is greater than or equal to two to three times the height of the second sub-sidewall.

[0007] In some embodiments, the inclination angle between the second sub-sidewall and the direction perpendicular to the first sub-sidewall is 60-90 degrees.

[0008] According to another aspect of this application, a trench capacitor is provided, including the above-described trench structure, wherein the semiconductor region includes: Semiconductor substrate; A first well region is formed on the semiconductor substrate, the first well region having a first conductivity type; and A second electrode region is formed in the first well region and surrounds the contour of the trench, the second electrode region having a first conductivity type.

[0009] In some embodiments, the dielectric is silicon oxide, a silicon oxide-silicon nitride-silicon oxide stack, or a high-k dielectric material.

[0010] In some embodiments, the first electrode region is polycrystalline silicon, which has a first conductivity type or a second conductivity type.

[0011] In some embodiments, the first electrode region is metal, and a titanium layer and a titanium nitride layer are included between the dielectric and the first electrode region.

[0012] In some embodiments, the metal is tungsten.

[0013] In some embodiments, the semiconductor substrate has a second conductivity type, the first conductivity type is N-type, the second conductivity type is P-type, and the doping concentration of the second electrode region is greater than the doping concentration of the first well region.

[0014] In some embodiments, the trench capacitor further includes a buried layer having a first conductivity type, the buried layer being located between the first well region and the semiconductor substrate.

[0015] In some embodiments, the bottom wall of the trench is located in the buried layer or the first well region.

[0016] In some embodiments, the second electrode region is grounded.

[0017] In some embodiments, the semiconductor substrate has a first conductivity type, which is P-type, and a second conductivity type, which is N-type, and the doping concentration of the second electrode region is greater than the doping concentration of the first well region.

[0018] In some embodiments, the trench capacitor further includes a second well region located on the substrate, wherein the first well region is located within the second well region, and the second well region has a second conductivity type.

[0019] In some embodiments, the trench capacitor further includes a buried layer having a second conductivity type, the buried layer being located between the first well region and the substrate.

[0020] In some embodiments, the bottom wall of the trench is located within the buried layer.

[0021] In some embodiments, the bottom wall of the trench is located in the first well region.

[0022] According to another aspect of this application, a method for manufacturing a trench capacitor is provided, comprising: Trenches are formed in a semiconductor region by at least two etching processes, the trenches extending from the upper surface of the semiconductor region into its interior; A dielectric material is formed covering the inner sidewalls and bottom wall of the trench; and A first electrode region is formed and filled in a trench including the dielectric. The inner sidewall comprises at least two continuous sub-sidewall segments, the uppermost sub-sidewall segment being substantially perpendicular to the upper surface of the semiconductor region, and the remaining sub-sidewall segments being inclined to the uppermost sub-sidewall segment. The at least two sub-sidewalls are formed by the at least two etching processes, with different etching angles for the at least two etching processes. The sub-sidewalls inclined to the uppermost sub-sidewall are formed by controlling the etching angles.

[0023] In some embodiments, by controlling the etching angle, the angle between the sub-sidewalls of the remaining segments and the sub-sidewall of the uppermost segment increases sequentially along the direction from the upper surface of the semiconductor region to the lower surface of the semiconductor region.

[0024] In some embodiments, the semiconductor region includes a semiconductor substrate. The manufacturing method further includes: A first well region is formed in the semiconductor substrate, the first well region having a first conductivity type; and A second electrode region is formed in the first well region, the second electrode region surrounding the contour of the trench and having a first conductivity type.

[0025] In some embodiments, the inner sidewall comprises two sub-sidewall segments, wherein the two sub-sidewall segments include a first sub-sidewall located in the upper segment and a second sub-sidewall located in the lower segment, and the height of the first sub-sidewall is greater than or equal to two to three times the height of the second sub-sidewall. The process of forming a trench in a semiconductor region by at least two etching operations includes: forming a first sub-sidewall of the trench by a first etching operation, and forming a second sub-sidewall of the trench by a second etching operation.

[0026] In some embodiments, the etching angle is controlled such that the tilt angle between the second sub-sidewall and the direction perpendicular to the first sub-sidewall is 60-90 degrees.

[0027] In some embodiments, the first and second etchings may be configured as RAP etching or SSP etching.

[0028] In some embodiments, the semiconductor region includes a semiconductor substrate. The manufacturing method further includes: A first well region is formed in a semiconductor substrate, the first well region having a first conductivity type; A first portion of the second electrode region surrounding the first sub-sidewall of the trench is formed by a first ion implantation; and A second portion of the second electrode region is formed by a second ion implantation, surrounding the second sub-sidewall of the trench. The second electrode region has a first conductivity type.

[0029] In some embodiments, the first ion implantation is an inclined implantation, and the second ion implantation is a vertical implantation.

[0030] In some embodiments, the trench is formed in a preceding process. The dielectric forming the inner and bottom walls of the trench includes forming an oxide layer on the inner and bottom walls of the trench by thermal oxidation. The first electrode region is polycrystalline silicon.

[0031] In some embodiments, the trench is formed in a subsequent process. The dielectric forming the inner and bottom walls of the trench includes forming a silicon oxide-silicon nitride-silicon oxide stack by a low-temperature process. The formation of the first electrode region in the trench including the dielectric includes filling the trench including the dielectric with metal.

[0032] In some embodiments, the cryogenic process includes in-situ water vapor generation or cryogenic chemical vapor deposition.

[0033] In some embodiments, the manufacturing method further includes forming a titanium layer and a titanium nitride layer on the inner side of the dielectric.

[0034] This application provides a trench structure, a trench capacitor, and a method for manufacturing a trench capacitor. The trench structure includes a semiconductor region, a trench, a dielectric, and a first electrode region. The trench extends from the upper surface of the semiconductor region into its interior. The dielectric covers the inner sidewalls and the bottom wall of the trench. The first electrode region fills the trench including the dielectric. The inner sidewall includes at least two continuous sub-sidewall segments, the uppermost sub-sidewall being substantially perpendicular to the upper surface of the semiconductor region, and the remaining sub-sidewall segments inclined to the uppermost sub-sidewall. The trench capacitor includes this trench structure. The semiconductor region includes a semiconductor substrate, a first well region, and a second electrode region. The first well region is formed on the semiconductor substrate and has a first conductivity type. The second electrode region is formed on the first well region and surrounds the contour of the trench, and the second electrode region has a first conductivity type.

[0035] By setting the inner sidewall as at least two continuous sub-sidewalls, with the uppermost sub-sidewall being substantially perpendicular to the upper surface of the semiconductor region and the remaining sub-sidewalls inclined to the uppermost sub-sidewall, a uniformly doped second electrode region can be formed on the outside of the trench, and a good interface between the dielectric and the trench can be formed on the inside of the trench, thereby improving the performance and reliability of the trench capacitor. Attached Figure Description

[0036] The above and other objects, features, and advantages of this application will become clearer from the following description of embodiments with reference to the accompanying drawings, in which: Figure 1 This is a cross-sectional view of a trench capacitor from the prior art; Figure 2 This is a cross-sectional view of the trench capacitor according to an embodiment of this application; Figure 3 This is a cross-sectional view of an exemplary trench structure; Figure 4 This is a cross-sectional view of an exemplary trench; Figure 5 This is a cross-sectional view of another trench capacitor according to an embodiment of this application; Figure 6 This is a cross-sectional view of another trench capacitor according to an embodiment of this application; Figure 7 This is a cross-sectional view of another trench capacitor according to an embodiment of this application; Figure 8 This is a cross-sectional view of another trench capacitor according to an embodiment of this application; Figures 9-16 A method for manufacturing trench capacitors is shown; Figures 17-24 Another method for manufacturing trench capacitors is shown. Detailed Implementation

[0037] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0038] Those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

[0039] It should be understood that although this document uses terms such as "first," "second," and "third" to describe various elements, regions, layers, or segments, these elements, regions, layers, or segments are not limited by these terms. Rather, these terms are only used to distinguish one element, region, layer, or segment from another. Therefore, the first element, region, layer, or segment discussed below may also be referred to as the second element, region, layer, or segment without departing from the teachings of this application.

[0040] The terminology used herein is for describing specific exemplary embodiments only and is not intended to limit the concept of the invention. In this document, the singular forms “a” and “the” as used herein may also include the plural forms unless explicitly indicated by the content. It should be further understood that when the word “comprising” is used in this specification, it indicates the presence of the stated feature, step, operation, element, or component, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, or groups thereof.

[0041] Figure 1 This is a cross-sectional view of a trench capacitor in the prior art. The trench capacitor includes a substrate 10, a buried layer 20 formed in the substrate 10, a well region 30 formed in the substrate 10, a trench formed in the substrate 10, a dielectric layer 40 located inside the trench, a first electrode region 50, and a second electrode region 32 located outside the trench. The first electrode region 50, the dielectric layer 40, and the second electrode region 32 constitute the trench capacitor. The well region 30 includes a heavily doped region 31. The second electrode region 32, the well region 30, and the heavily doped region 31 have the same conductivity type. The first electrode region 50 is led out through an electrode 61, and the second electrode region 32 is led out through an electrode 62. The second electrode region 32 is usually formed by ion implantation. When the trench capacitor has a large aspect ratio, the ion implantation effect at the bottom of the trench is poor, and the doping concentration of the second electrode region 32 is uneven, which leads to poor interface quality between the dielectric layer 40 and the second electrode region 32, affecting the performance of the trench capacitor.

[0042] This application provides a trench structure and a trench capacitor. Trench capacitors are used, for example, in DRAM and DC-DC circuits. DC-DC circuits include, for example, Boost circuits.

[0043] Figure 2 This is a cross-sectional view of an exemplary trench capacitor of this application. Figure 4 yes Figure 2A cross-sectional view of a trench capacitor. The trench capacitor includes a trench structure. The trench structure includes: a semiconductor region, a trench, a dielectric 400, and a first electrode region 500. The trench extends from the upper surface of the semiconductor region into the interior of the semiconductor region. The opening of the trench is located on the upper surface of the semiconductor region. The trench includes an inner sidewall 331 and a bottom wall 332. The bottom wall 332 of the trench is located inside the semiconductor region. From a top view, the trench may be, for example, circular, elliptical, or rounded rectangular. This application does not limit the specific shape of the trench. The dielectric 400 covers the bottom wall 332 and at least a portion of the inner sidewall 331 of the trench. The first electrode region 500 is filled in the trench including the dielectric 400.

[0044] The dielectric 400 is an insulating material, such as silicon oxide, silicon nitride, a stacked structure composed of silicon oxide and silicon nitride, or other high-k dielectric materials. The first electrode region 500 is, for example, polycrystalline silicon or a metal. The polycrystalline silicon may be doped to have a first conductivity type or a second conductivity type. Exemplary metals include tungsten, aluminum, nickel, copper, silver, gold, etc. When the first electrode region 500 is a metal, a stacked layer consisting of a barrier layer and an adhesive layer is also included between the first electrode region 500 and the dielectric 400. The adhesive layer is located between the first electrode region 500 and the barrier layer, and the barrier layer is located between the adhesive layer and the dielectric 400. Exemplarily, the adhesive layer is a titanium layer, and the barrier layer is a titanium nitride layer.

[0045] The inner sidewall 331 includes at least two continuous sub-sidewall segments. The uppermost sub-sidewall segment is substantially perpendicular to the upper surface of the semiconductor region, and the remaining sub-sidewall segments are inclined to the uppermost sub-sidewall segment. The remaining sub-sidewall segments are not the uppermost sub-sidewall segments. The lowermost sub-sidewall segment connects to the bottom wall.

[0046] The groove portions defined by the uppermost sub-sidewall have substantially the same inner diameter, while the inner diameters of the groove portions defined by the remaining sub-sidewalls are smaller than the inner diameter of the groove portion defined by the uppermost sub-sidewall, with the inner diameters defined by each remaining sub-sidewall gradually decreasing. When the inner sidewall includes at least three sub-sidewalls, the inner diameters defined by the multiple remaining sub-sidewalls gradually decrease.

[0047] exist Figure 2 In this embodiment, the inner sidewall 331 includes an uppermost sub-sidewall 3311 and a sub-sidewall 3312. Sub-sidewall 3311 is the uppermost sub-sidewall. Sub-sidewall 3311 is substantially perpendicular to the upper surface of the semiconductor region and extends from the upper surface of the semiconductor region into the interior of the semiconductor region. Sub-sidewall 3312 connects the sub-sidewall 3311 and the bottom wall 332. Sub-sidewall 3312 is inclined relative to sub-sidewall 3311.

[0048] In some embodiments, the inner sidewall includes two sub-sidewall segments, wherein the two sub-sidewall segments include a first sub-sidewall located in the upper segment and a second sub-sidewall located in the lower segment, and the height of the first sub-sidewall is greater than or equal to two to three times the height of the second sub-sidewall. For example... Figure 2 and 4 As shown, the inner sidewall 331 includes a first sub-sidewall 3311 and a second sub-sidewall 3312. The height of the first sub-sidewall 3311 in the Y direction is h1, and the height of the second sub-sidewall 3312 in the Y direction is h2. h1 is greater than or equal to N times h2, and N is greater than or equal to 2 and less than or equal to 3. Figure 4 As shown, the inner diameter of the trench portion defined by the first sub-sidewall 3311 is D1, and the inner diameter of the trench portion defined by the second sub-sidewall 3312 is D2. D1 is greater than D2, and D2 gradually decreases in the direction Y. The direction Y is the direction from the upper surface of the semiconductor region to the lower surface of the semiconductor region. In some embodiments, the inclination angle A between the second sub-sidewall 3312 and the direction X perpendicular to the first sub-sidewall 3311 is 60 degrees to 90 degrees.

[0049] In some embodiments, the inner sidewall includes at least three sub-sidewalls along the direction Y from the upper surface of the semiconductor region to the lower surface of the semiconductor region, and the angle between the remaining sub-sidewalls and the uppermost sub-sidewall increases sequentially. Figure 3 This is a cross-sectional view of another exemplary trench structure. The inner sidewall 331 includes a sub-sidewall 3311, a sub-sidewall 3312, and a sub-sidewall 3313. The sub-sidewall 3311 is the uppermost sub-sidewall, and the angle between the sub-sidewall 3313 and the sub-sidewall 3311 is greater than the angle between the sub-sidewall 3312 and the sub-sidewall 3311.

[0050] like Figure 2 and Figure 3 As shown, a trench structure is formed in a semiconductor stack. The semiconductor region includes a semiconductor substrate 100, a first well region 300, and a second electrode region 320. The semiconductor substrate may include a substrate, or include a substrate and an epitaxial layer thereon. The semiconductor substrate 100 is, for example, a silicon substrate. The first well region 300 is formed on the semiconductor substrate 100 and has a first conductivity type. The second electrode region 320 is formed on the first well region 300 and surrounds the contour of the trench, and has a first conductivity type. The doping concentration of the second electrode region 320 is greater than that of the first well region 300. The first electrode region 500, the dielectric 400, and the second electrode region 320 constitute a capacitor. The first electrode region 500 is the upper electrode of the capacitor, and the second electrode region 320 is the lower electrode of the capacitor. The first well region 300 also includes a heavily doped region 310. The second electrode region 320 is electrically connected to an electrode 620 through the first well region 300 and the heavily doped region 310. The first electrode region 500 is led out through the electrode 610. The second electrode region 320 is led out through electrode 620.

[0051] In some embodiments, the semiconductor region further includes a buried layer 200 located between the first well region 300 and the semiconductor substrate 100, below the first well region 300. The buried layer 200 has a first conductivity type.

[0052] exist Figure 2 In this embodiment, the semiconductor substrate 100 is P-type doped, the second electrode region 320 and the first well region 300 are N-type doped, the buried layer 200 is N-type doped, and the trench capacitor is fabricated in the N-well. That is, the first conductivity type is N-type doped, and the second conductivity type is P-type doped.

[0053] When the trench capacitor is used as a boost capacitor in circuits such as buck / boost, the second electrode region 320 is grounded through electrode 620.

[0054] exist Figure 2 In one embodiment, the bottom wall 320 of the trench is located in the first well region 300, and the second electrode region 320 is substantially formed in the first well region 300. Figure 5 This is a cross-sectional view of another trench capacitor according to an embodiment of this application. Figure 5 In one embodiment, the bottom wall 320 of the trench is located in the buried layer 200, and the second electrode region 320 extends from the first well region 300 into the buried layer 200.

[0055] In the above embodiments, the inner sidewall of the trench is configured as at least two continuous sub-sidewall segments, with the uppermost sub-sidewall segment substantially perpendicular to the upper surface of the semiconductor region, and the remaining sub-sidewall segments inclined to the uppermost sub-sidewall segment. This allows for the formation of a uniformly doped second electrode region in the first well region outside the trench via ion implantation, and the formation of a dielectric with a good interface on the inner side of the trench, thereby improving the performance and reliability of the trench capacitor.

[0056] Figure 6 This is a cross-sectional view of another trench capacitor according to an embodiment of this application. The trench capacitor includes a trench structure. The trench structure includes: a semiconductor region, a trench, a dielectric 400, and a first electrode region 500. The semiconductor region includes: a semiconductor substrate 100, a first well region 300, a second electrode region 320, a buried layer 200, and a second well region 700.

[0057] The semiconductor substrate 100, the second electrode region 320, and the first well region 300 have a first conductivity type. The second well region 700 and the buried layer 200 have a second conductivity type. The doping concentration of the first well region 300 is greater than the doping concentration of the semiconductor substrate 100, and the doping concentration of the second electrode region 320 is greater than the doping concentration of the first well region 300.

[0058] A second well region 700 and a buried layer 200 are formed in the semiconductor substrate 100. A first well region 300 is formed in the second well region 700. The buried layer 200 is located below the first well region 300. A trench is formed in the first well region 300. Figure 6 The trench in the illustrated embodiment can be referenced Figure 2 The example shown.

[0059] In this embodiment, the second well region 700 and the buried layer 200 are N-type doped, the semiconductor substrate 100, the second electrode region 320 and the first well region 300 are P-type doped, and the trench is formed in the P-well.

[0060] like Figure 6 As shown, the trench capacitor also includes a shallow trench isolation region (STI) 630. The shallow trench isolation region 630 is filled with insulating material. In top view, the shallow trench isolation region 630 overlaps with the trench, overlaps with the dielectric 400, and overlaps with the first electrode region 500.

[0061] exist Figure 6 In one embodiment, the bottom wall 320 of the trench is located in the first well region 300, and the second electrode region 320 is substantially formed in the first well region 300.

[0062] The first well region 300 includes a heavily doped region 310, which is connected to the electrode 620. The second electrode region 320 is electrically connected to the electrode 620 through the first well region 300 and the heavily doped region 310. The second well region 700 includes a heavily doped region 710, which is connected to the electrode 640.

[0063] for Figure 6 The trench capacitor shown has a first electrode region 500 as the lower electrode plate and a second electrode region 320 as the upper electrode plate.

[0064] exist Figure 2 In the illustrated embodiment, the semiconductor substrate 100 is P-type doped, and the buried layer 200 and the first well region 300 are N-type doped. The first well region 300 and the semiconductor substrate 100 constitute a parasitic diode. Charge carriers may be injected into the semiconductor substrate 100 through the parasitic diode, causing current noise. Figure 6 In the embodiment shown, the semiconductor substrate 100 and the first well region 300 are P-type doped, the buried layer 200 is N-type doped, and the second well region 700 is N-type doped and surrounds the first well region 300 with the buried layer 200, so that the first well region 300 is isolated from the substrate, avoiding current noise caused by carrier injection into the semiconductor substrate 100. Figure 7This is a cross-sectional view of another trench capacitor according to an embodiment of this application. In this embodiment, the bottom wall 320 of the trench is located in the buried layer 200, and the second electrode region 320 extends from the first well region 300 into the buried layer 200.

[0065] Figure 8 This is a cross-sectional view of another trench capacitor according to an embodiment of this application. In this embodiment, from a top view, the shallow trench isolation region 630 does not overlap with the trench, the shallow trench isolation region 630 does not overlap with the dielectric 400, and the shallow trench isolation region 630 does not overlap with the first electrode region 500. That is, the trench capacitor is formed between the shallow trench isolation regions 630.

[0066] exist Figure 8 In one embodiment, the bottom wall 320 of the trench is located in the buried layer 200, and the second electrode region 320 extends from the first well region 300 into the buried layer 200. It can be understood that both the trench and the second electrode region 320 may be entirely located within the first well region 300.

[0067] exist Figure 7 and Figure 8 In this embodiment, the second well region 700 and the buried layer 200 are N-type doped, and the semiconductor substrate 100, the second electrode region 320 and the first well region 300 are P-type doped. The trench is formed in the P-well. The parasitic diode formed by the semiconductor substrate 100 and the buried layer 200 has no risk of conduction, thus avoiding current noise caused by carrier injection into the semiconductor substrate 100.

[0068] for Figure 7 and Figure 8 The trench capacitor shown has a first electrode region 500 as the lower electrode plate and a second electrode region 320 as the upper electrode plate.

[0069] In this application, Figure 2 , Figure 5 , Figure 6 , Figure 7 and Figure 8 The connection relationship between the first electrode region 500 and the second electrode region 320 after being led out through their respective electrodes in the trench capacitor shown is determined according to the actual circuit in which the trench capacitor is located, and is not limited here.

[0070] for Figure 6 , Figure 7 and Figure 8 The trench capacitor shown has its second sub-sidewall 3312 angled relative to the first sub-sidewall 3311, which facilitates ion implantation for forming the second electrode region 320 and ensures the uniformity of doping concentration in each part of the second electrode region 320. This improves the interface quality between the dielectric 320 formed on the uniformly doped surface of the second electrode region 320 and the second electrode region 320. Therefore, the performance and reliability of the trench capacitor are improved.

[0071] for Figure 6 , Figure 7 and Figure 8 The trench capacitor shown is an example of a trench capacitor. Trench capacitors can be formed in either the front-end of line (FEOL) or the back-end of line (BEOL) process.

[0072] When the trench capacitor is formed in the subsequent BEOL process, the dielectric 400 is, for example, a silicon oxide-silicon nitride-silicon oxide stack formed by a low-temperature process. A stack consisting of a barrier layer and an adhesive layer is also formed between the dielectric 400 and the first electrode region 500. The first electrode region 500 is metal. Since the trench capacitor is formed later than the shallow trench isolation region 630, from a top-view perspective, the shallow trench isolation region 630 does not overlap with the trench, the shallow trench isolation region 630 does not overlap with the dielectric 400, and the shallow trench isolation region 630 does not overlap with the first electrode region 500.

[0073] When the trench capacitor is formed in the front-end process FEOL, the dielectric 400 is, for example, an oxide layer formed by thermal oxidation (e.g., a silicon dioxide layer), and the first electrode region 500 is polysilicon having a second conductivity type. The trench capacitor can be formed later than or earlier than the shallow trench isolation region 630. When the trench capacitor is formed later than the shallow trench isolation region 630, from a top-view perspective, the shallow trench isolation region 630 does not overlap with the trench, the shallow trench isolation region 630 does not overlap with the dielectric 400, and the shallow trench isolation region 630 does not overlap with the first electrode region 500. When the trench capacitor is formed earlier than the shallow trench isolation region 630, from a top-view perspective, the shallow trench isolation region 630 overlaps with the trench, the shallow trench isolation region 630 overlaps with the dielectric 400, and the shallow trench isolation region 630 overlaps with the first electrode region 500.

[0074] This application also provides a method for manufacturing a trench capacitor. The method includes: forming a trench in a semiconductor region by at least two etching operations, the trench extending from the upper surface of the semiconductor region into its interior; forming a dielectric covering the inner sidewalls and bottom wall of the trench; and forming a first electrode region filling the trench including the dielectric. The inner sidewalls of the trench include at least two continuous sub-sidewall segments, the uppermost sub-sidewall segment being substantially perpendicular to the upper surface of the semiconductor region, and the remaining sub-sidewall segments inclined to the uppermost sub-sidewall segment. The at least two sub-sidewall segments are formed by the at least two etching operations, the etching angles of which are different, and the sub-sidewall inclined to the uppermost sub-sidewall segment is formed by controlling the etching angles.

[0075] Figures 9-16 It shows the application to manufacturing Figure 6 and Figure 7The method for creating trench capacitors is shown. In this method, the trench capacitors are formed before the shallow trench isolation region 630 is formed.

[0076] A buried layer 200 is formed in a substrate 100, a second well region 700 is formed in the substrate 100, and a first well region 300 is formed in the second well region 700. Exemplarily, the buried layer 200, the first well region 300, and the second well region 700 are all formed by ion implantation. The substrate 100 and the first well region 300 have a first conductivity type, and the buried layer 200 and the second well region 700 have a second conductivity type. The cross-section of the formed device is shown below. Figure 9 As shown.

[0077] The first portion of a trench 301 is formed in the first well region 300 by a first etching process. The inner sidewall of the first portion of the trench 301 is a first sub-sidewall 3311. The first sub-sidewall 3311 is the uppermost sub-sidewall of the trench. The first sub-sidewall 3311 is substantially perpendicular to the upper surface of the first well region 300. The cross-section of the formed device is shown below. Figure 10 As shown.

[0078] A second portion of trench 301 is further formed in the first well region 300 by a second etching. The second portion of trench 301 is located below the first portion, and its inner sidewalls are a first sub-sidewall 3311 and a second sub-sidewall 3312. By controlling the etching angle, the second sub-sidewall 3312 is inclined relative to the first sub-sidewall 3311. The resulting device cross-section is shown below. Figure 11 As shown. For example, the inclination angle A of the second sub-sidewall 3312 with respect to the direction X perpendicular to the first sub-sidewall 3311 is 60 degrees to 90 degrees. For example, the height of the first sub-sidewall 3311 is greater than or equal to two to three times the height of the second sub-sidewall 3312.

[0079] The first and second etching processes can be configured as RAP (Rapid Alternating Process) etching or SSP (Steady State Process) etching. The etching angles of the first and second etching processes are different, thereby forming a second sub-sidewall 3312 that is inclined to the first sub-sidewall 3311.

[0080] The trench 301 includes an inner sidewall and a bottom wall 332. The inner sidewall includes multiple sub-sidewalls formed by multiple etching processes, and the orientation of the sub-sidewalls is controlled by controlling the etching angle. For example, the inner sidewall includes an uppermost sub-sidewall 3311 and multiple non-uppermost sub-sidewalls. The angle between the multiple non-uppermost sub-sidewalls and the uppermost sub-sidewall 3311 increases sequentially along the direction from the upper surface of the semiconductor region to the lower surface of the semiconductor region.

[0081] A second electrode region is formed by ion implantation, which is formed in the first well region 300 and surrounds the contour of the trench 301. The second electrode region and the first well region 300 have the same conductivity type, but the second electrode region has a higher doping concentration.

[0082] The first portion 3201 of the second electrode region is formed by the first ion implantation of the first sub-sidewall 3311 surrounding the trench 301. The cross-section of the formed device is shown below. Figure 12 As shown. For example, the first ion implantation is a tilted implantation.

[0083] The second portion 3202 of the second electrode region, surrounding the second sub-sidewall 3312 of the trench 301, is formed by a second ion implantation. The resulting device cross-section is shown below. Figure 13 As shown. The second electrode region on the outer side of the bottom wall 320 of trench 301 is also formed by a second ion implantation. Exemplarily, the second ion implantation is vertical implantation.

[0084] A dielectric 400 is formed on the inner sidewall and bottom wall of trench 301. Exemplarily, the dielectric 400 is formed on the inner sidewall and bottom wall of trench 301 by thermal oxidation; the dielectric 400 is, for example, silicon dioxide. The cross-section of the formed device is shown below. Figure 14 As shown.

[0085] A first electrode region 500 is filled in a trench 301 including a dielectric 400. For example, the first electrode region 500 is filled in the trench 301 by deposition. The first electrode region 500 is, for example, polysilicon, thereby enabling better process compatibility of this manufacturing method. The polysilicon, for example, has a second conductivity type. The cross-section of the formed device is as follows. Figure 15 As shown.

[0086] A shallow trench isolation region 630 is formed. Exemplarily, a target shallow trench is etched, and then an insulating material is deposited and filled into the target shallow trench to form the shallow trench isolation region 630. The cross-section of the formed device is shown below. Figure 16 As shown. Figure 16 As shown, forming the shallow trench isolation region 630 may consume part of the trench structure, resulting in the dielectric 400 not completely covering the inner sidewalls of the trench. Therefore, from a top view, the shallow trench isolation region 630 overlaps with the trench, the shallow trench isolation region 630 overlaps with the dielectric 400, and the shallow trench isolation region 630 overlaps with the first electrode region 500. In the direction perpendicular to the semiconductor substrate 100, the first electrode region 500 is higher than the dielectric 400.

[0087] Heavily doped regions 310 and 710 are formed, and electrodes 610, 620, and 640 are formed, thereby obtaining... Figure 6 or Figure 7 The trench capacitor is shown. The heavily doped regions 310 and 710 are formed, for example, by ion implantation.

[0088] In the manufacturing method of this embodiment, the trench is formed in the front-end process FEOL, prior to the formation of the shallow trench isolation region 630. For example, in a buck / boost circuit, the trench 301 and the trench capacitor are formed before the transistor in the buck / boost circuit is formed. In the manufacturing method of this embodiment, the dielectric 400 is formed through thermal oxidation of the inner sidewall and bottom wall of the trench. The first electrode region 500 is polycrystalline silicon formed by deposition.

[0089] Figures 17-24 It shows the application to manufacturing Figure 8 The method for creating trench capacitors is shown. In this method, the trench capacitors are formed after the shallow trench isolation region 630 is formed.

[0090] A buried layer 200 is formed in a substrate 100, a second well region 700 is formed in the substrate 100, and a first well region 300 is formed in the second well region 700. Exemplarily, the buried layer 200, the first well region 300, and the second well region 700 are all formed by ion implantation. The substrate 100 and the first well region 300 have a first conductivity type, and the buried layer 200 and the second well region 700 have a second conductivity type. The cross-section of the formed device is shown below. Figure 17 As shown.

[0091] A shallow trench isolation region 630 is formed. Exemplarily, a target shallow trench is etched, and then an insulating material is deposited and filled into the target shallow trench to form the shallow trench isolation region 630. The cross-section of the formed device is shown below. Figure 18 As shown.

[0092] Heavily doped regions 310 and 710 are formed, for example, by ion implantation. The cross-section of the device after formation is shown below. Figure 19 As shown.

[0093] The first portion of a trench 301 is formed in the first well region 300 by a first etching process. The inner sidewall of the first portion of the trench 301 is a first sub-sidewall 3311. The first sub-sidewall 3311 is the uppermost sub-sidewall of the trench. The first sub-sidewall 3311 is substantially perpendicular to the upper surface of the first well region 300. The cross-section of the formed device is shown below. Figure 20 As shown.

[0094] A second portion of trench 301 is further formed in the first well region 300 by a second etching process. The inner sidewalls of the second portion of trench 301 are a first sub-sidewall 3311 and a second sub-sidewall 3312. By controlling the etching angle, the second sub-sidewall 3312 is inclined relative to the first sub-sidewall 3311. The cross-section of the formed device is shown below. Figure 21As shown. For example, the inclination angle between the second sub-sidewall 3312 and the direction perpendicular to the first sub-sidewall 3311 is 60-90 degrees. For example, the height of the first sub-sidewall 3311 is greater than or equal to two to three times the height of the second sub-sidewall 3312.

[0095] The first and second etching processes can be configured as RAP (Rapid Alternating Process) etching or SSP (Steady State Process) etching. The etching angles of the first and second etching processes are different, thereby forming a second sub-sidewall 3312 that is inclined to the first sub-sidewall 3311.

[0096] The trench 301 includes an inner sidewall and a bottom wall 332. The inner sidewall includes multiple sub-sidewalls formed by multiple etching processes, and the orientation of the sub-sidewalls is controlled by controlling the etching angle. For example, the inner sidewall includes an uppermost sub-sidewall 3311 and multiple non-uppermost sub-sidewalls. The angle between the multiple non-uppermost sub-sidewalls and the uppermost sub-sidewall 3311 increases sequentially along the direction from the upper surface of the semiconductor region to the lower surface of the semiconductor region.

[0097] A second electrode region is formed by ion implantation, which is formed in the first well region 300 and surrounds the contour of the trench 301. The second electrode region and the first well region 300 have the same conductivity type, but the second electrode region has a higher doping concentration.

[0098] The first portion of the second electrode region, consisting of the first sub-sidewall 3311 surrounding the trench 301, is formed by a first ion implantation. The second portion of the second electrode region, consisting of the second sub-sidewall 3312 surrounding the trench 301, is formed by a second ion implantation. The cross-section of the formed device is shown below. Figure 22 As shown. The second electrode region on the outer side of the bottom wall 320 of the trench 301 is also formed by a second ion implantation. In an exemplary embodiment, the first ion implantation is an inclined implantation, and the second ion implantation is a vertical implantation.

[0099] A dielectric 400 is formed on the inner sidewall and bottom wall of trench 301. Exemplarily, the dielectric 400 is deposited on the inner sidewall and bottom wall of trench 301 using a low-temperature process. The dielectric 400 is, for example, silicon oxide or a silicon oxide-silicon nitride-silicon oxide stack. The low-temperature process includes in-situ steam generation (ISSG) or low-temperature chemical vapor deposition. A barrier layer-binder layer stack 401 is formed inside the dielectric 400. The barrier layer is, for example, a TiN layer, and the binder layer is, for example, a Ti layer. The resulting device cross-section is shown below. Figure 23As shown. A first electrode region 500 is filled in a trench 301 including a dielectric 400. For example, the first electrode region 500 is filled in the trench 301 by deposition. The first electrode region 500 is a metal. Exemplary metals include tungsten, aluminum, nickel, copper, silver, gold, etc. Preferably, the first electrode region 500 is tungsten. The cross-section of the formed device is shown. Figure 24 As shown.

[0100] In other embodiments, alternatives Figure 23 and Figure 24 The corresponding steps involve forming a dielectric 400 through the inner and bottom walls of the thermal oxidation trench 301, and directly depositing polycrystalline silicon on the dielectric 400 as the first electrode region 500.

[0101] Electrodes 610, 620, and 630 are formed to obtain Figure 8 The trench capacitor shown.

[0102] In the manufacturing method of this embodiment, trench 301 is formed later than shallow trench isolation region 630. Trench 301 can be formed in the later process BEOL or the earlier process FEOL. For the case where trench 301 is formed in the later process BEOL, for example, trench capacitors are used in buck / boost circuits, and trench 301 and trench capacitors are formed after the transistors in the buck / boost circuit are formed.

[0103] In the trench capacitor manufacturing method of this embodiment, during the back-end process BEOL, the dielectric 400 is a silicon oxide-silicon nitride-silicon oxide stack formed by low-temperature deposition. The dielectric 400 and the first electrode region 500 are also provided with a barrier layer and a bonding layer formed by deposition. The first electrode region 500 is metal. In the front-end process FEOL, the dielectric 400 is a thermal oxide layer, and the first electrode region 500 is polycrystalline silicon.

[0104] exist Figures 9-16 The trench capacitor manufacturing method shown and Figures 17-24In the trench capacitor manufacturing method shown, sub-sidewalls 3311 and 3312 are formed by two etching processes. Sub-sidewall 3311 is substantially perpendicular to the upper surface of the semiconductor region, and sub-sidewall 3312 is inclined to sub-sidewall 3311. A second electrode region 320 is formed outside the sub-sidewall 3311 in the first well region 300 by inclined ion implantation. The second electrode region 320 outside the sub-sidewall 3312 and bottom wall 332 is formed in the first well region 300 by vertical ion implantation. The inclined sub-sidewall 3312 facilitates the second ion implantation, ensuring the doping uniformity of the second electrode region 320 in the lower part of the trench and on the outer side of the bottom, thus improving the uniformity and quality of the trench capacitor's electrodes. The second electrode region 320 has uniform doping, and the dielectric 400 formed on the surface of the second electrode region 320 has a higher quality interface, further improving the performance of the trench capacitor.

[0105] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A trench structure, characterized in that, include: Semiconductor region; A trench extends from the upper surface of the semiconductor region into its interior; A dielectric material covers the bottom wall and at least part of the inner sidewall of the trench; as well as The first electrode region is filled in a trench including the dielectric. The inner sidewall includes at least two continuous sub-sidewalls, the uppermost sub-sidewall being substantially perpendicular to the upper surface of the semiconductor region, and the remaining sub-sidewalls being inclined to the uppermost sub-sidewall.

2. The trench structure according to claim 1, wherein, Along the direction from the upper surface of the semiconductor region to the lower surface of the semiconductor region, the angle between the sub-sidewalls of the remaining segments and the sub-sidewall of the uppermost segment increases sequentially.

3. The trench structure according to claim 1, wherein, The inner sidewall includes two sub-sidewalls, wherein the two sub-sidewalls include a first sub-sidewall located in the upper section and a second sub-sidewall located in the lower section, and the height of the first sub-sidewall is greater than or equal to two to three times the height of the second sub-sidewall.

4. The trench structure according to claim 3, wherein, The inclination angle between the second sub-sidewall and the direction perpendicular to the first sub-sidewall is 60-90 degrees.

5. A trench capacitor, comprising: The trench structure according to any one of claims 1-4, The semiconductor region includes: Semiconductor substrate; A first well region is formed on the semiconductor substrate, the first well region having a first conductivity type; and A second electrode region is formed in the first well region and surrounds the contour of the trench, the second electrode region having a first conductivity type.

6. The trench capacitor according to claim 5, wherein, The dielectric is silicon oxide, a silicon oxide-silicon nitride-silicon oxide stack, or a high-K dielectric material.

7. The trench capacitor according to claim 5, wherein, The first electrode region is polycrystalline silicon, which has a first conductivity type or a second conductivity type.

8. The trench capacitor according to claim 5, wherein, The first electrode region is metal, and the dielectric and the first electrode region include a titanium layer and a titanium nitride layer.

9. The trench capacitor according to claim 8, wherein, The metal is tungsten.

10. The trench capacitor according to claim 5, wherein, The semiconductor substrate has a second conductivity type, the first conductivity type is N-type, the second conductivity type is P-type, and the doping concentration of the second electrode region is greater than the doping concentration of the first well region.

11. The trench capacitor according to claim 5, wherein, The trench capacitor further includes a buried layer having a first conductivity type, the buried layer being located between the first well region and the semiconductor substrate.

12. The trench capacitor according to claim 11, wherein, The bottom wall of the trench is located in the buried layer or the first well area.

13. The trench capacitor according to claim 10, wherein, The second electrode region is grounded.

14. The trench capacitor according to claim 5, wherein, The semiconductor substrate has a first conductivity type, which is P-type, and a second conductivity type, which is N-type. The doping concentration of the second electrode region is greater than the doping concentration of the first well region.

15. The trench capacitor according to claim 14, wherein, The trench capacitor further includes a second well region located on the substrate, wherein the first well region is located within the second well region, and the second well region has a second conductivity type.

16. The trench capacitor according to claim 14 or 15, wherein, The trench capacitor further includes a buried layer having a second conductivity type, the buried layer being located between the first well region and the substrate.

17. The trench capacitor according to claim 15, wherein, The bottom wall of the trench is located in the buried layer.

18. The trench capacitor according to claim 15, wherein, The bottom wall of the trench is located in the first well region.

19. A method for manufacturing a trench capacitor, comprising: Trenches are formed in a semiconductor region by at least two etching processes, the trenches extending from the upper surface of the semiconductor region into its interior; A dielectric material is formed covering the inner sidewalls and bottom wall of the trench; as well as A first electrode region is formed and filled in a trench including the dielectric. The inner sidewall comprises at least two continuous sub-sidewall segments, the uppermost sub-sidewall segment being substantially perpendicular to the upper surface of the semiconductor region, and the remaining sub-sidewall segments being inclined to the uppermost sub-sidewall segment. The at least two sub-sidewalls are formed by the at least two etching processes, with different etching angles for the at least two etching processes. The sub-sidewalls inclined to the uppermost sub-sidewall are formed by controlling the etching angles.

20. The manufacturing method according to claim 19, wherein, By controlling the etching angle so that the angle between the sub-sidewalls of the remaining segments and the sub-sidewall of the uppermost segment increases sequentially along the direction from the upper surface of the semiconductor region to the lower surface of the semiconductor region.

21. The manufacturing method according to claim 19, wherein, The semiconductor region includes a semiconductor substrate. The manufacturing method further includes: A first well region is formed in the semiconductor substrate, the first well region having a first conductivity type; and A second electrode region is formed in the first well region, the second electrode region surrounding the contour of the trench and having a first conductivity type.

22. The manufacturing method according to claim 19, wherein, The inner sidewall comprises two sub-sidewall segments, wherein the two sub-sidewall segments include a first sub-sidewall located in the upper segment and a second sub-sidewall located in the lower segment, and the height of the first sub-sidewall is greater than or equal to two to three times the height of the second sub-sidewall. The process of forming a trench in a semiconductor region by at least two etching operations includes: forming a first sub-sidewall of the trench by a first etching operation, and forming a second sub-sidewall of the trench by a second etching operation.

23. The manufacturing method according to claim 22, wherein, By controlling the etching angle, the tilt angle between the second sub-sidewall and the direction perpendicular to the first sub-sidewall is 60-90 degrees.

24. The manufacturing method according to claim 22, wherein, The first and second etching processes can be configured as RAP (Rapid Alternating Process) etching or SSP (Steady State Process) etching.

25. The manufacturing method according to claim 22, wherein, The semiconductor region includes a semiconductor substrate. The manufacturing method further includes: A first well region is formed in a semiconductor substrate, the first well region having a first conductivity type; A first portion of the second electrode region surrounding the first sub-sidewall of the trench is formed by a first ion implantation; and A second portion of the second electrode region is formed by a second ion implantation, surrounding the second sub-sidewall of the trench. The second electrode region has a first conductivity type.

26. The manufacturing method according to claim 25, wherein, The first ion implantation was an inclined implantation, and the second ion implantation was a vertical implantation.

27. The manufacturing method according to claim 19, wherein, The grooves are formed in the front-end of line (FEOL) process. The dielectric forming the inner and bottom walls of the trench includes forming an oxide layer on the inner and bottom walls of the trench by thermal oxidation. The first electrode region is polycrystalline silicon.

28. The manufacturing method according to claim 19, wherein, The grooves are formed in a back-end of line (BEOL) process. The dielectric forming the inner and bottom walls of the trench includes forming a silicon oxide-silicon nitride-silicon oxide stack by a low-temperature process. The formation of the first electrode region in the trench including the dielectric includes filling the trench including the dielectric with metal.

29. The manufacturing method according to claim 28, wherein, The cryogenic process includes in-situ steam generation (ISSG) or cryogenic chemical vapor deposition.

30. The manufacturing method according to claim 28, wherein, The manufacturing method further includes forming a titanium layer and a titanium nitride layer on the inner side of the dielectric.

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