A semiconductor device and a method of fabricating the same

Abstract

This invention discloses a semiconductor device and its fabrication method, belonging to the field of semiconductor technology. The semiconductor device includes: a semiconductor substrate; a shallow trench isolation structure disposed within the semiconductor substrate and defining an active region; a well region disposed within the active region of the semiconductor substrate; a gate insulating layer disposed on the well region; a gate electrode disposed on the gate insulating layer; a source region and a drain region respectively disposed on either side of the gate electrode within the well regions; a lightly doped source region and a lightly doped drain region separated by the well region at the lower part of the gate electrode, overlapping with the gate electrode by a predetermined overlap length; from the boundary of the shallow trench isolation structure, within a predetermined width region of the active region, the gate electrode and the lightly doped drain region have a first overlap length, and in other regions, the gate electrode and the lightly doped drain region have a second overlap length, wherein the first overlap length is less than the second overlap length. This invention can reduce gate-induced drain current while ensuring conduction current.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a semiconductor device and its fabrication method. Background Technology

[0002] In MOS transistors, to prevent performance degradation caused by hot carrier injection, lightly doped regions (LDDs), especially those on the drain side, are used to mitigate the electric field between the channel and drain regions. In MOS transistors with shallow trench isolation (STI) structures, LDDs are formed at the edges of the STI in the drain region, compromising the insulation of the STI and causing a voltage drop. Furthermore, in high-voltage devices, the LDD structure is formed before the gate structure, with some LDDs located below the gate structure, resulting in longer additional LDDs at the STI edges and increased leakage current.

[0003] In MOS transistors, Gate Induced Drain Leakage (GIDL) is the inter-band leakage current generated by the high electric field between the drain and gate when the gate voltage is 0V in the off state. GIDL needs to be reduced, and it is more pronounced in high-voltage and small-size devices. If no LDD region is formed in the active region adjacent to the STI boundary, the channel width decreases, and the conduction current decreases. If a longer additional LDD exists at the STI edge, a larger GID will appear at the STI edge. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same. The semiconductor device and method provided by this invention can reduce the gate-induced drain current while ensuring the conduction current.

[0005] To address the aforementioned technical problems, the present invention provides a semiconductor device comprising at least:

[0006] Semiconductor substrate;

[0007] A shallow trench isolation structure is disposed within the semiconductor substrate and defines an active region;

[0008] A well region is disposed within the semiconductor substrate in the active region;

[0009] A gate insulating layer is disposed on the well region;

[0010] A gate electrode is disposed on the gate insulating layer;

[0011] The source region and the drain region are respectively disposed in the well region on both sides of the gate electrode;

[0012] The lightly doped source region and the lightly doped drain region are separated by the well region at the lower part of the gate electrode, overlap with the gate electrode by a predetermined overlap length, and are connected to the corresponding source region and drain region, respectively.

[0013] Starting from the boundary of the shallow trench isolation structure, within a predetermined width region of the active region, the overlap length of the gate electrode and the lightly doped drain electrode is a first overlap length; outside the predetermined width region, the overlap length of the gate electrode and the lightly doped drain electrode is a second overlap length, wherein the first overlap length is less than the second overlap length.

[0014] In one embodiment of the present invention, the first overlap length is a fixed length less than the second overlap length.

[0015] In one embodiment of the present invention, starting from the boundary of the shallow trench isolation structure, within a predetermined width region of the active region, the overlap length of the gate electrode and the lightly doped drain electrode gradually decreases from the second overlap length to the first overlap length.

[0016] In one embodiment of the present invention, the source lightly doped region and the drain lightly doped region have the same layout shape.

[0017] In one embodiment of the present invention, within a predetermined width region of the active region, the overlap length of the gate electrode and the lightly doped source is equal to the overlap length of the gate electrode and the lightly doped source excluding the predetermined width region.

[0018] In one embodiment of the present invention, the size of the predetermined width region of the active region, starting from the boundary of the shallow trench isolation structure, is 0.01 μm to 0.2 μm.

[0019] In one embodiment of the present invention, the semiconductor device further includes a sidewall structure that covers the sides of the gate insulating layer and the gate electrode.

[0020] The present invention also provides a method for fabricating a semiconductor device, comprising:

[0021] Provide a semiconductor substrate;

[0022] A shallow trench isolation structure is formed within the semiconductor substrate to delineate the active region;

[0023] A well region is formed within the semiconductor substrate in the active region;

[0024] Within the well region, lightly doped source and lightly doped drain regions are formed at intervals.

[0025] A gate insulating layer is formed on the well region;

[0026] A gate electrode is formed on the gate insulating layer; the source lightly doped region and the drain lightly doped region are separated by the well region at the lower part of the gate electrode and overlap with the gate electrode by a predetermined overlap length.

[0027] Source regions and drain regions are formed in the well regions on both sides of the gate electrode, and are connected to their respective source regions and drain regions.

[0028] Starting from the boundary of the shallow trench isolation structure, within a predetermined width region of the active region, the overlap length of the gate electrode and the lightly doped drain electrode is a first overlap length; outside the predetermined width region, the overlap length of the gate electrode and the lightly doped drain electrode is a second overlap length, wherein the first overlap length is less than the second overlap length.

[0029] In one embodiment of the present invention, the method for fabricating the source lightly doped region and the drain lightly doped region includes:

[0030] A patterned photoresist is formed on the well region;

[0031] Ion implantation is performed using the photoresist as a mask;

[0032] The source lightly doped region and the drain lightly doped region are formed, and the photoresist is removed.

[0033] In one embodiment of the present invention, when forming the source lightly doped region and the drain lightly doped region, the first overlap length and the second overlap length are controlled by designing the pattern of the photoresist.

[0034] In summary, this invention provides a semiconductor device and its fabrication method. By improving the structure of the semiconductor device, the unexpected technical effects of this application are: reducing the gate-induced drain current while ensuring the conduction current; reducing the influence of electric field concentration, stress, and / or interface traps in the silicon corner of the trench in the shallow trench isolation structure (STI), thereby reducing the deviation of the gate-induced drain current; and significantly improving the on / off ratio of the semiconductor device. Furthermore, the fabrication process of the semiconductor device is compatible with existing processes and requires no changes to the process flow.

[0035] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 Part 101 in the diagram is a top view of the semiconductor device according to the first embodiment of the present invention. Figure 1 Parts 102 and 103 are schematic diagrams representing the cross-sectional structures along the AA and BB directions in part 101, respectively.

[0038] Figure 2 Parts 201 to 204 in the text represent Figure 1 A schematic diagram of the process steps in the fabrication of semiconductor devices.

[0039] Figure 3 A top view of the semiconductor device according to the second embodiment of the invention.

[0040] Figure 4 Part 401 is a top view of the semiconductor device according to the third embodiment of the present invention. Figure 4 Parts 402 and 403 are schematic diagrams representing the cross-sectional structures along the AA and BB directions in part 401, respectively.

[0041] Figure 5 The graph shows the simulated relationship between gate voltage (Vg) and drain current (Id) in the examples and comparative examples.

[0042] Label Explanation:

[0043] 1. MOS transistor; 10. Semiconductor substrate; 11. Well region; 12. Photoresist; 13. Lightly doped source region; 14. Lightly doped drain region; 15. Gate insulating layer; 16. Gate electrode; 17. Sidewall structure; 18. Source region; 19. Drain region. Detailed Implementation

[0044] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0047] Please see Figure 1 As shown, Figure 1 Part 101 is a top view of the MOS transistor 1 according to the first embodiment of the present invention, and parts 102 and 103 are schematic diagrams showing the cross-sectional structures along the AA and BB directions of part 101, respectively. The MOS transistor 1 is, for example, a medium-voltage MOS transistor or a high-voltage MOS transistor. The operating voltage of the medium-voltage MOS transistor is, for example, 5V to 8V, and the operating voltage of the high-voltage MOS transistor is, for example, greater than 8V and not greater than 50V. In this embodiment, the MOS transistor 1 is described as a p-channel MOS transistor. In the p-channel MOS transistor, the first conductivity type is n-type, and the second conductivity type is p-type.

[0048] Please see Figure 1 As shown, in the first embodiment of the present invention, the MOS transistor 1 includes, for example, a shallow trench isolation structure (STI), a semiconductor substrate 10, and a well region 11. The shallow trench isolation structure (STI) separates the MOS transistor 1, and the well region 11 extends from the surface of the semiconductor substrate 10 into the semiconductor substrate 10. The semiconductor substrate 10 is, for example, a silicon wafer doped with p-type impurities, such as boron (B), and the well region 11 is, for example, formed of silicon doped with n-type impurities, such as phosphorus (P) or arsenic (As).

[0049] Please see Figure 1As shown, in the first embodiment of the present invention, the shallow trench isolation structure (STI) is an insulating region used to insulate adjacent components, and the active region AC is defined by the shallow trench isolation structure (STI). The shallow trench isolation structure (STI) is formed by embedding, for example, a silicon oxide film in the trenches of the semiconductor substrate 10.

[0050] Please see Figure 1 As shown, in the first embodiment of the present invention, the MOS transistor 1 includes a lightly doped source region 13, a lightly doped drain region 14, a gate insulating layer 15, a gate electrode 16, a sidewall spacer 17, a source region 18, and a drain region 19 formed in the active region AC.

[0051] Please see Figure 1 As shown, in the first embodiment of the present invention, a gate insulating layer 15 and a gate electrode 16 are formed on the surface of the well region 11 of the active region AC. The length of the gate electrode 16 is defined as the gate length L in the direction from the source region 18 to the drain region 19, and the length of the gate electrode 16 is defined as the gate width W in a direction orthogonal to the gate length L. The gate insulating layer 15 is formed, for example, of a silicon oxide film, and the gate electrode 16 is formed, for example, of a conductive layer such as polysilicon, in which p-type impurities are doped, for example, including boron. In other embodiments, the gate electrode 16 may also be formed of a stacked structure of a metal layer, a metal silicide layer, a polysilicon layer, and a metal layer or a metal silicide layer.

[0052] Please see Figure 1 As shown, in the first embodiment of the present invention, the gate insulating layer 15 and the gate electrode 16 have coplanar side surfaces. A sidewall structure 17 is formed to cover the side surfaces of the gate insulating layer 15 and the gate electrode 16, and the sidewall structure 17 is formed of, for example, a silicon oxide film, a silicon nitride film, or a stack thereof.

[0053] Please see Figure 1 As shown, in the first embodiment of the present invention, an active electrode region 18 and a drain electrode region 19 are formed on both sides of the gate electrode 16 on the surface of the well region 11 of the active region AC. The source electrode region 18 and the drain electrode region 19 are, for example, doped with p-type impurities, such as boron.

[0054] Please see Figure 1As shown, in the first embodiment of the present invention, a pair of lightly doped regions, namely a source lightly doped region 13 and a drain lightly doped region 14, are provided in the active region AC at the lower part of the gate electrode 16. The pair of lightly doped regions are separated by the well region 11 and overlap with the gate electrode 16 by a predetermined size. The source lightly doped region 13 and the drain lightly doped region 14 are respectively connected to their respective source region 18 and drain region 19, and the source lightly doped region 13 and the drain lightly doped region 14 are, for example, doped with p-type impurities, such as boron. The description of the gate electrode 16 overlapping with the source lightly doped region 13 and the drain lightly doped region 14 means that, in the top view of the MOS transistor 1, the orthographic projection of the gate electrode 16 overlaps with the source lightly doped region 13 and the drain lightly doped region 14. The length of overlap between the gate electrode 16 and the source lightly doped region 13 and the drain lightly doped region 14 when viewed from above is called the overlap length.

[0055] Please see Figure 1 As shown, in the first embodiment of the present invention, in the MOS transistor 1, when a voltage is applied to the drain region 19 and the applied voltage to the gate electrode 16 is lower than a predetermined voltage such as 0V, no current exists between the source region 18 and the drain region 19. However, when a voltage of a predetermined value or higher is applied to the gate electrode 16, a channel is formed on the surface of the well region 11 between the lightly doped source region 13 and the lightly doped drain region 14 at the lower part of the gate electrode 16, and current exists between the source region 18 and the drain region 19.

[0056] Please see Figure 1 As shown, in the first embodiment of the present invention, in the MOS transistor 1, in the gate width direction, near the center of the active region AC, the overlap length between the gate electrode 16 and the lightly doped drain region 14 is a second overlap length d1, and in the boundary region of the active region AC near the shallow trench isolation structure STI, the overlap length between the gate electrode 16 and the lightly doped drain region 14 is a first overlap length d2. The first overlap length d2 is less than the second overlap length d1.

[0057] Please see Figure 1 As shown, in the first embodiment of the present invention, in the gate width direction, starting from the boundary of the shallow trench isolation structure (STI), within a region of a predetermined width w1, the overlap length of the active region AC and the lightly doped drain region 14 is a first overlap length d2, and outside the region of the predetermined width w1, the overlap length of the active region AC and the lightly doped drain region 14 is a second overlap length d1, wherein the first overlap length d2 is less than the second overlap length d1.

[0058] Please see Figure 1 As shown, in the first embodiment of the present invention, in the gate width direction, as Figure 1As shown in section 102, near the center of the active region AC, the lightly doped drain region 14 penetrates deeper into the lower part of the gate electrode 16. (As...) Figure 1 As shown in section 103, from the boundary of the shallow trench isolation structure STI, within a region of a predetermined width w1, the drain lightly doped region 14 in the lower part of the active region AC penetrates to a shallower extent into the lower part of the gate electrode 16.

[0059] Please see Figure 1 As shown, in the first embodiment of the present invention, when the MOS transistor 1 is viewed from above, the overlapping portion of the drain lightly doped region 14 and the gate electrode 16 has a rectangular notch end face, and the rectangular notch end face is adjacent to the shallow trench isolation structure STI on the side of the drain lightly doped region 14.

[0060] Please see Figure 1 As shown, in the first embodiment of the present invention, in the MOS transistor 1, the gate length L is, for example, 0.2 μm to 10 μm, the gate width W is, for example, 0.2 μm to 20 μm, the second overlap length d1 and the first overlap length d2 are, for example, 0 μm to 0.2 μm, and w1 is, for example, 0.01 μm to 0.2 μm. The gate length L and the gate width W are set according to the process node, the second overlap length d1 and the first overlap length d2 are set according to the gate length, and w1 is a distance set to avoid the influence of the shallow trench isolation structure (STI) boundary described later. Therefore, it is almost independent of the process node. Therefore, w1 is, for example, set to 0.01 μm to 0.2 μm. In this embodiment, w1 is, for example, 0.05 μm.

[0061] Please see Figure 1 As shown, in the first embodiment of the present invention, in the MOS transistor 1, in the region of the active region AC close to the boundary of the shallow trench isolation structure (STI), the overlap length between the gate electrode 16 and the lightly doped source region 13 is a first overlap length d2. In the gate width direction, the overlap length between the gate electrode 16 near the center of the active region AC and the lightly doped source region 13 is a second overlap length d1. Alternatively, the first overlap length d2 may be less than the second overlap length d1. That is, the lightly doped source region 13 can be designed with the same layout shape as the lightly doped drain region 14.

[0062] Please see Figure 1 As shown, in the first embodiment of the present invention, the method for manufacturing MOS transistor 1 will be described. Figure 2 Parts 201 to 204 represent Figure 1 A schematic diagram of the fabrication process of the MOS transistor 1. First, as shown... Figure 2Part 201 involves forming a shallow trench isolation structure (STI) (not shown) on a p-type semiconductor substrate 10 to define the active region AC. Next, ion implantation of n-type impurities such as phosphorus or arsenic is performed on the semiconductor substrate 10 to form an n-type well region 11.

[0063] Please see Figure 2 As shown in section 202, in the first embodiment of the present invention, a photoresist 12 patterned on the well region 11 is used as a mask to form lightly doped regions. P-type impurities such as boron are implanted via ion implantation or other methods to form a pair of lightly doped p-type regions, namely a source lightly doped region 13 and a drain lightly doped region 14. When forming the source lightly doped region 13 and the drain lightly doped region 14, the ion implantation conditions include implantation energy and implantation dose, wherein the implantation energy is, for example, 10 keV to 30 keV, and the implantation dose is, for example, 1 × 10⁻⁶. 13 atoms / cm 2 ~1×10 14 atoms / cm 2 The depth of the lightly doped source region 13 and the lightly doped drain region 14 formed is, for example, 200 nm to 400 nm, and the concentration is, for example, 1 × 10⁻⁶. 18 atoms / cm 3 ~1×10 20 atoms / cm 3 .

[0064] Please see Figure 2 As shown in section 203, in the first embodiment of the present invention, after forming the lightly doped region, the photoresist 12 is removed, and a silicon oxide film is formed on the surface of the well region 11, for example by thermal oxidation. A conductive layer such as a polysilicon film is formed on the upper layer of the silicon oxide film by, for example by chemical vapor deposition (CVD). The silicon oxide film and the conductive layer are processed into a pattern of the gate electrode 16, thereby forming the gate insulating layer 15 and the gate electrode 16.

[0065] Please see Figure 2 As shown, in the first embodiment of the present invention, during the process of forming the source lightly doped region 13 and the drain lightly doped region 14 and during the process of forming the gate electrode 16, the mask pattern of the photoresist 12 is designed so that in the region of the active region AC adjacent to the boundary of the shallow trench isolation structure (STI), the first overlap length d2 of the gate electrode 16 and the drain lightly doped region 14 is less than the second overlap length d1 of the gate electrode 16 and the drain lightly doped region 14 near the center of the active region AC in the gate width direction.

[0066] Please see Figure 2As shown, in the first embodiment of the present invention, a silicon oxide film, a silicon nitride film, or a stack thereof is formed on the entire semiconductor substrate 10 by a process such as CVD to cover the gate electrode 16, and a sidewall structure 17 is formed by etch back, the sidewall structure 17 covering the gate insulating layer 15 and the side of the gate electrode 16.

[0067] Please see Figure 2 As shown in section 204, in the first embodiment of the present invention, using the gate electrode 16 with the sidewall structure 17 as a mask, p-type impurity ions such as boron are implanted to form a p-type source region 18 and a drain region 19. The source region 18 and the drain region 19 are respectively connected to the source lightly doped region 13 and the drain lightly doped region 14. The source region 18 and the drain region 19 are self-aligned structures formed relative to the gate electrode 16. The ion implantation conditions for forming the source region 18 and the drain region 19 are: implantation energy, for example, 5 keV to 20 keV, and implantation dose, for example, 1 × 10⁻⁶. 14 atoms / cm 2 ~1×10 16 atoms / cm 2 The depth of the formed source region 18 and drain region 19 is, for example, 100 nm to 200 nm, and the concentration is, for example, 1 × 10⁻⁶. 20 atoms / cm 3 ~1×10 21 atoms / cm 3 Through the above process steps, it is possible to produce... Figure 1 The MOS transistor 1 shown is shown.

[0068] Please see Figure 2 As shown, in the first embodiment of the present invention, during the process of forming the source lightly doped region 13 and the drain lightly doped region 14 and the process of forming the gate electrode 16, the mask pattern of the photoresist 12 is designed such that in the region of the active region AC adjacent to the boundary of the shallow trench isolation structure (STI), the first overlap length d2 of the gate electrode 16 and the source lightly doped region 13 is less than the second overlap length d1 of the gate electrode 16 and the source lightly doped region 13 near the center of the active region AC in the gate width direction.

[0069] In medium-to-high voltage transistors, the overlap length between the gate electrode and the lightly doped region is adjusted to reduce the gate-induced drain current while ensuring conduction current. Studies have found that the gate-induced drain current (GIDL) in the active region near the boundary of a shallow trench isolation (STI) structure is approximately two orders of magnitude larger than that in the active region farther from the STI boundary. This is attributed to the effects of electric field concentration, stress, and / or interface traps in the silicon corners above the STI trench.

[0070] Please see Figure 1 As shown, in the first embodiment of this application, in the MOS transistor 1, near the boundary of the shallow trench isolation structure (STI), the first overlap length d2 of the gate electrode 16 in the active region and the lightly doped drain region 14 is designed to be smaller than the second overlap length d1 of the gate electrode 16 in the region far from the boundary of the shallow trench isolation structure (STI).

[0071] The above structure can reduce the length of the LDD region along the boundary of the shallow trench isolation structure (STI) that is affected by the corner of the STI boundary, thereby reducing GIDL.

[0072] Please see Figure 1 As shown, in the first embodiment of this application, in the MOS transistor 1, the length of the LDD region along the boundary of the shallow trench isolation structure (STI) that is affected by the corner of the STI boundary can be reduced, thereby suppressing the influence caused by the shape, stress and / or interface traps of the corner of the STI and thus reducing the GIDL deviation.

[0073] Please see Figure 1 As shown, in the first embodiment of this application, in the MOS transistor 1, the region where the overlap length between the gate electrode 16 and the lightly doped drain region 14 is small is only a predetermined range w1 from the boundary of the shallow trench isolation structure (STI). Therefore, the impact on the reduction of the on-current can be minimized. Thus, the MOS transistor 1 of this application can obtain an on-current equal to that of a MOS transistor where the overlap length between the gate electrode and the lightly doped region is the second overlap length d1 over the entire region. Consequently, the on / off ratio of the MOS transistor 1 can be significantly improved.

[0074] Please see Figure 1 As shown, in the first embodiment of this application, in the MOS transistor 1, it is possible to reduce GIDL while ensuring the conduction current.

[0075] Please see Figure 2 As shown, in the fabrication method of the MOS transistor 1 provided in this application, a lightly doped source region 13 and a lightly doped drain region 14 are formed before the gate electrode 16 is formed. Therefore, it is possible to form lightly doped source regions 13 and lightly doped drain regions 14 that are not self-aligned with the gate electrode 16. Thus, the following layout design can be achieved: in the region of the active region AC near the edge of the shallow trench isolation structure (STI), the first overlap length d2 of the gate electrode 16 and the lightly doped drain region 14 is less than the second overlap length d1 of the gate electrode 16 and the lightly doped drain region 14 near the center in the gate width direction.

[0076] Please see Figure 1 As shown, the MOS transistor 1 provided in this application can also be applied to an n-channel MOS transistor. In this case, it can be achieved by substituting p-type impurities and n-type impurities for each other in the p-channel MOS transistor described in the first embodiment. In the n-channel MOS transistor, the first conductivity type is p-type and the second conductivity type is n-type. The MOS transistor 1 of this embodiment can be mounted, for example, in a process platform such as a display driver integrated circuit (Display Driver IC).

[0077] Please see Figure 1 As shown, in the first embodiment of the present invention, the MOS transistor 1 adopts the following structure: near the boundary of the shallow trench isolation structure (STI), the first overlap length d2 of the gate electrode 16 and the lightly doped drain region 14 in the active region AC is less than the second overlap length d1 of the gate electrode 16 and the lightly doped drain region 14 near the center of the active region AC in the gate width direction. Although when viewed from above, the overlapping portion of the lightly doped drain region 14 and the gate electrode 16 in the MOS transistor 1 of the first embodiment appears as having a rectangular notch end face, the rectangular notch end face being adjacent to the shallow trench isolation structure (STI) on the side of the lightly doped drain region 14. This achieves the above structure, but the present invention is not limited to this structural form.

[0078] Please see Figure 3 As shown, in the second embodiment of the present invention, Figure 3 This is a top view of the MOS transistor 1. In the MOS transistor 1 of this embodiment, in the gate width direction, near the center of the active region AC, the overlap length between the gate electrode 16 and the lightly doped drain region 14 is a second overlap length d1. At the junction of the active region AC and the shallow trench isolation structure (STI) boundary, the overlap length between the gate electrode 16 and the lightly doped drain region 14 is a first overlap length d2, and the first overlap length d2 is less than the second overlap length d1. Within a predetermined range w1 extending from the boundary of the shallow trench isolation structure (STI) in the gate width direction, the overlap length gradually decreases from the second overlap length d1 to the first overlap length d2.

[0079] Please see Figure 3 As shown, in the second embodiment of the present invention, when the MOS transistor 1 is viewed from above, the overlapping portion of the drain lightly doped region 14 and the gate electrode 16 is presented as having a triangular notch end face, and the triangular notch end face is adjacent to the shallow trench isolation structure STI on the side of the drain lightly doped region 14.

[0080] Please see Figure 3As shown, in the second embodiment of the present invention, in the MOS transistor 1, within a predetermined range w1 extending from the boundary of the shallow trench isolation structure (STI) towards the gate width direction, near the center of the active region AC in the gate width direction, the overlap length between the gate electrode 16 and the lightly doped source region 13 is a second overlap length d1. At the junction of the active region AC and the boundary of the shallow trench isolation structure (STI), the overlap length between the gate electrode 16 and the lightly doped source region 13 is a first overlap length d2, and the first overlap length d2 is less than the second overlap length d1. Within the predetermined range w1 extending from the boundary of the shallow trench isolation structure (STI) towards the gate width direction, the overlap length gradually decreases from the second overlap length d1 to the first overlap length d2. That is, the lightly doped source region 13 can be configured with the same layout shape as the lightly doped drain region 14.

[0081] Please see Figure 3 As shown, in the second embodiment of the present invention, the MOS transistor 1 is identical to the MOS transistor 1 in the first embodiment except for the structure described above.

[0082] In the second embodiment of the present invention, when fabricating the MOS transistor 1, during the formation of the source lightly doped region 13 and the drain lightly doped region 14, and during the formation of the gate electrode 16, the mask pattern of the photoresist 12 is designed such that within a predetermined range w1 extending from the boundary of the shallow trench isolation structure (STI) towards the gate width direction, the overlap length between the gate electrode 16 and the drain lightly doped region 14 gradually decreases from the second overlap length d1 to the first overlap length d2. Except for the above-described process steps, the rest can be fabricated according to the method for fabricating the MOS transistor 1 of the first embodiment.

[0083] In the second embodiment of the present invention, when fabricating the MOS transistor 1, the mask pattern of the photoresist 12 can also be used to make the overlap length between the gate electrode 16 and the lightly doped source region 13 gradually decrease from the second overlap length d1 to the first overlap length d2 within a predetermined range w1 extending from the boundary of the shallow trench isolation structure (STI) to the gate width direction.

[0084] In the second embodiment of the present invention, the MOS transistor 1 is the same as that in the first embodiment, and can suppress the influence of shape, stress, and / or interface traps at the corners of the shallow trench isolation structure (STI), thereby reducing GIDL and decreasing GIDL deviation. Simultaneously, it is possible to obtain a conduction current equal to that of the MOS transistor when the overlap length between the gate electrode and the lightly doped region is the second overlap length d1 over the entire region. Therefore, the on / off ratio of the MOS transistor 1 can be significantly improved.

[0085] Please see Figure 1As shown, in the first embodiment of the present invention, the MOS transistor 1 adopts the following structure: in the region of the active region AC near the boundary of the shallow trench isolation structure STI, the first overlap length d2 of the gate electrode 16 and the lightly doped source region 13 is smaller than the second overlap length d1 of the gate electrode 16 and the lightly doped source region 13 near the center of the active region AC in the gate width direction. However, the present invention is not limited to this structure.

[0086] Please see Figure 4 As shown, in the third embodiment of the present invention, Figure 4 Part 401 is a top view of the MOS transistor 1 according to the third embodiment of the present invention, and parts 402 and 403 are schematic diagrams showing the cross-sectional structures along the AA direction and BB direction in part 401, respectively.

[0087] Please see Figure 4 As shown, in the third embodiment of the present invention, in the MOS transistor 1, the overlap length between the gate electrode 16 and the lightly doped source region 13 in the region of the active region AC near the boundary of the shallow trench isolation structure (STI) is the same as the second overlap length d1 between the gate electrode 16 and the lightly doped source region 13 near the center of the active region AC in the gate width direction. Apart from the above structure, the remaining structure is the same as that of the MOS transistor 1 in the first embodiment.

[0088] Please see Figure 4 As shown, in the third embodiment of the present invention, during the fabrication of the MOS transistor 1, the mask pattern of the photoresist 12 is used to design the process of forming the lightly doped source region 13 and the lightly doped drain region 14, as well as the process of forming the gate electrode 16, so that the overlap length between the gate electrode 16 and the lightly doped source region 13 in the region of the active region AC near the boundary of the shallow trench isolation structure (STI) is the same as the second overlap length d1 between the gate electrode 16 and the lightly doped source region 13 near the center of the active region AC in the gate width direction. Except for the above-described process steps, the rest can be fabricated according to the fabrication method of the MOS transistor 1 in the first embodiment.

[0089] Please see Figure 4As shown, in the third embodiment of the present invention, since GIDL is a phenomenon generated on the drain region 19 side of the MOS transistor, the drain lightly doped region 14 in the MOS transistor 1 is configured with the same structure as in the first embodiment. This suppresses the influence of the shape, stress, and / or interface traps at the corners of the shallow trench isolation structure (STI), thereby reducing GIDL and minimizing GIDL deviation. Simultaneously, it is possible to obtain a MOS transistor with an on-state current equal to the second overlap length d1 across the entire region when the overlap length between the gate electrode and the lightly doped region is the same. Therefore, the on / off ratio of the MOS transistor 1 can be significantly improved.

[0090] In the third embodiment of the present invention, the drain lightly doped region 14 may also have the following structure, namely, the structure of the MOS transistor 1 in the second embodiment, such that within a predetermined range w1 extending from the boundary of the shallow trench isolation structure (STI) towards the gate width direction, the overlap length between the gate electrode 16 and the drain lightly doped region 14 gradually decreases from the second overlap length d1 to the first overlap length d2. In this case, the structure of the source lightly doped region 13 is as follows: in the region of the active region AC near the boundary of the shallow trench isolation structure (STI), the overlap length between the gate electrode 16 and the source lightly doped region 13 is the same as the second overlap length d1 of the overlap length between the gate electrode 16 and the source lightly doped region 13 near the center of the active region AC in the gate width direction.

[0091] In one embodiment of the present invention, the characteristics of the PMOS transistor were verified by simulation. During verification, a MOS transistor according to the first embodiment was used as an example. In the simulation model according to the first embodiment, the following parameters were set: gate length = 0.9 μm, gate width = 0.9 μm, the second overlap length d1 of the gate electrode 16 near the center of the active region AC in the gate width direction with the lightly doped source region 13 = 0.11 μm, the first overlap length d2 of the gate electrode 16 in the active region AC near the boundary of the shallow trench isolation structure STI with the lightly doped source region 13 = 0.05 μm, and the range w1 corresponding to the first overlap length d2 (which is less than the second overlap length d1) along the gate width direction from the edge of the shallow trench isolation structure STI was set to 0.05 μm. With the MOS transistor of the above structure, the drain current (Id) was calculated by simulation by changing the gate voltage (Vg) while applying an 8V drain voltage (Vd).

[0092] In one embodiment of the present invention, a comparative example is provided. In the comparative example, in the region of the active region AC near the boundary of the shallow trench isolation structure (STI), the overlap length of the gate electrode 16 with the lightly doped source region 13 and the lightly doped drain region 14 is the same as the overlap length of the gate electrode 16 with the lightly doped source region 13 and the lightly doped drain region 14 near the center of the gate width direction of the active region AC. That is, the second overlap length d1 is equal to the first overlap length d2. The rest is the same as in the embodiment. The drain current (Id) is calculated by changing the gate voltage (Vg) in the same way as in the embodiment.

[0093] Please see Figure 5 As shown, Figure 5 This is a graph showing the simulated relationship between gate voltage (Vg) and drain current (Id) in the examples and comparative examples. Figure 5 In the diagram, curve A, represented by a dashed line, indicates the Vg-Id characteristic of the example model. Conversely, curve B, represented by a solid line, indicates the Vg-Id characteristic of the comparative model.

[0094] Please see Figure 5 As shown, in the Vg-Id characteristics of the embodiment model, the GIDL is smaller than that in the Vg-Id characteristics of the comparative model.

[0095] Please see Figure 5 As shown, the on-current of the embodiment model is approximately the same as that of the comparative model. Therefore, when the following layout is adopted, the on-current is not substantially reduced, wherein the channel direction length, first overlap length d2, within a predetermined range w1 in the width direction from the edge of the shallow trench isolation structure (STI) to the gate electrode 16, is less than the channel direction length, second overlap length d1, in the region outside the predetermined range w1 in the width direction from the edge of the shallow trench isolation structure (STI) to the gate electrode 16. Since the on-current of the embodiment and the comparative model are comparable, and the GIDL is reduced in the embodiment, resulting in a reduced cutoff current, the switching ratio of the embodiment is improved.

[0096] In summary, this invention provides a semiconductor device and its fabrication method. By improving the structure of the semiconductor device, the unexpected technical effects of this application are: reducing the gate-induced drain current while ensuring the conduction current; reducing the influence of electric field concentration, stress, and / or interface traps in the silicon corner of the shallow trench isolation (STI) structure, thereby reducing the deviation of the gate-induced drain current; and significantly improving the on / off ratio of the semiconductor device. Furthermore, the fabrication process of the semiconductor device is compatible with existing processes and requires no changes to the process flow.

[0097] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A semiconductor device, characterized by, At least including: Semiconductor substrate; A shallow trench isolation structure is disposed within the semiconductor substrate and defines an active region; A well region is disposed within the semiconductor substrate in the active region; A gate insulating layer is disposed on the well region; A gate electrode is disposed on the gate insulating layer; The source region and the drain region are respectively disposed in the well region on both sides of the gate electrode; The lightly doped source region and the lightly doped drain region are separated by the well region at the lower part of the gate electrode, overlap with the gate electrode by a predetermined overlap length, and are connected to the corresponding source region and drain region, respectively. In the gate width direction, starting from the boundary of the shallow trench isolation structure, within a predetermined width region of the active region, the overlap length of the gate electrode and the lightly doped drain region is a first overlap length, and excluding the predetermined width region, the overlap length of the gate electrode and the lightly doped drain region is a second overlap length, wherein the first overlap length is less than the second overlap length; the size of the predetermined width region of the active region is 0.01μm~0.2μm.

2. The semiconductor device according to claim 1, wherein The first overlap length is a fixed length that is less than the second overlap length.

3. The semiconductor device of claim 1, wherein Starting from the boundary of the shallow trench isolation structure, within a predetermined width region of the active region, the overlap length of the gate electrode and the lightly doped drain region gradually decreases from the second overlap length to the first overlap length.

4. The semiconductor device of claim 1, wherein The source lightly doped region and the drain lightly doped region have the same layout shape.

5. The semiconductor device of claim 1, wherein Within a predetermined width region of the active region, the overlap length of the gate electrode and the lightly doped source region is equal to the overlap length of the gate electrode and the lightly doped source region excluding the predetermined width region.

6. The semiconductor device of claim 1, wherein The semiconductor device further includes a sidewall structure that covers the sides of the gate insulating layer and the gate electrode.

7. A method of manufacturing a semiconductor device, characterized by include: Provide a semiconductor substrate; A shallow trench isolation structure is formed within the semiconductor substrate to delineate the active region; A well region is formed within the semiconductor substrate in the active region; Within the well region, lightly doped source and lightly doped drain regions are formed at intervals. A gate insulating layer is formed on the well region; A gate electrode is formed on the gate insulating layer; the source lightly doped region and the drain lightly doped region are separated by the well region at the lower part of the gate electrode and overlap with the gate electrode by a predetermined overlap length. Source regions and drain regions are formed in the well regions on both sides of the gate electrode, and are connected to their respective lightly doped source regions and lightly doped drain regions. In the gate width direction, starting from the boundary of the shallow trench isolation structure, within a predetermined width region of the active region, the overlap length of the gate electrode and the lightly doped drain region is a first overlap length, and excluding the predetermined width region, the overlap length of the gate electrode and the lightly doped drain region is a second overlap length, wherein the first overlap length is less than the second overlap length; the size of the predetermined width region of the active region is 0.01μm~0.2μm.

8. The method of manufacturing a semiconductor device according to Claim 7, wherein The method for fabricating the lightly doped source region and the lightly doped drain region includes: A patterned photoresist is formed on the well region; Ion implantation is performed using the photoresist as a mask; The source lightly doped region and the drain lightly doped region are formed, and the photoresist is removed.

9. The method of fabricating a semiconductor device according to claim 8, wherein When forming the source lightly doped region and the drain lightly doped region, the first overlap length and the second overlap length are controlled by designing the pattern of the photoresist.

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