Interface optimization method for front-surface seed-layer-free electrode of photovoltaic cell and photovoltaic device

Abstract

The invention relates to the field of photovoltaic technology, and discloses an interface optimization method for a front-surface seed-layer-free electrode of a photovoltaic cell and a photovoltaic device. The method comprises the following steps: placing a silicon substrate in PECVD (Plasma Enhanced Chemical Vapor Deposition) equipment, and depositing a SiOxNy composite passivation layer with the thickness of 1-10nm on the surface of a transparent conducting layer on the front surface of the silicon substrate through plasma in-situ deposition; printing low-temperature sintered copper paste of which the sintering temperature is less than or equal to 200 DEG C onto the surface of the SiOxNy composite passivation layer; and curing the printed low-temperature sintered copper paste to obtain the front copper electrode. According to the method, a front seed layer is abandoned, direct combination of a front copper electrode and a front transparent conducting layer of a silicon substrate is achieved, an efficient interface inhibition passivation tunneling layer (namely a thin SiOxNy composite passivation layer) is constructed to block a copper-silicon mutual expansion path, interface contact characteristics are optimized, low-temperature sintering type copper paste is matched, contact resistance is reduced, stability is improved, the whole process is low in temperature, and the method is suitable for large-scale production. The method is compatible with an HJT battery manufacturing system and is low in metallization cost.

Description

Technical Field

[0001] This invention relates to the field of photovoltaic technology, specifically to an interface optimization method and photovoltaic device for a photovoltaic cell without a seed layer electrode on the front side. Background Technology

[0002] Crystalline silicon heterojunction (HJT) cells have become one of the core development directions of the photovoltaic industry due to their advantages such as high conversion efficiency, low temperature coefficient, and good stability. As one of the next-generation mainstream photovoltaic technologies, HJT cells rely on low-temperature silver paste for their metallization process, resulting in silver consumption as high as 8-9 mg per watt (up to 20 mg in the early stages). Silver paste costs account for more than 60% of the non-silicon costs. With the price of silver fluctuating more significantly in 2025 (approximately 6 yuan / gram), the silver paste cost for a single GW of HJT cells exceeded 50 million yuan, far exceeding the high-temperature silver paste cost of TOPCon cells (tunneling oxide passivated contact cells) (approximately 20 million yuan / GW). This cost disadvantage directly restricts the large-scale application of HJT cells.

[0003] To achieve cost reduction and efficiency improvement, the technology route of replacing silver electrodes with copper electrodes has attracted much attention. Although copper electroplating can significantly reduce costs, it requires the deposition of a nickel / silver seed layer to prevent copper-silicon interdiffusion, resulting in a lengthy process (requiring photolithography, etching, and other steps) and difficulty in controlling yield. For example, pinhole defects in the seed layer can cause copper to penetrate into the silicon substrate, generating deep-level impurities and causing the cell efficiency to decrease by more than 5%. Currently, the main solutions for copper-silicon interdiffusion in battery terminals include: silver / nickel seed layers, seedless copper electroplating technology, silver-coated copper paste, and non-silver metallization structures. Among these, the silver / nickel seed layer solution is the most commonly used.

[0004] Silver / nickel seed layer – In existing copper electrode fabrication techniques, to solve the interdiffusion problem between copper and silicon substrates, it is usually necessary to deposit a silver or nickel seed layer between the two (as shown in publication numbers CN116682593A and CN117352578A).

[0005] However, the use of precious metals is still unavoidable with silver seed layers, limiting cost reduction; nickel seed layers, on the other hand, suffer from complex deposition processes and poor compatibility with low-temperature curing systems. More importantly, the introduction of seed layers increases the overall resistance of the electrodes, and defects easily form at the interface between the seed layer and the copper or silicon substrate, affecting the stability and reliability of the battery. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide an interface optimization method and photovoltaic device for a photovoltaic cell without a seed layer electrode on the front side.

[0007] Based on this, the present invention discloses an interface optimization method for a front-side electrode without a seed layer in a photovoltaic cell, comprising the following steps:

[0008] S1. Take a silicon substrate with a transparent conductive layer on the front side, place the silicon substrate in a plasma-enhanced chemical vapor deposition device, and deposit a silicon oxynitride composite passivation layer with a thickness of 1-10 nm on the surface of the transparent conductive layer by plasma in-situ deposition.

[0009] S2. The low-temperature sintering copper paste is uniformly printed on the surface of the silicon oxynitride composite passivation layer; wherein the sintering temperature of the low-temperature sintering copper paste is ≤200℃.

[0010] S3. The printed low-temperature sintering copper paste is cured under inert gas protection to obtain the front copper electrode.

[0011] Preferably, in step S1, the process conditions for plasma in-situ deposition include: using Ar as the carrier gas, SiH4 as the silicon source, N2O and NH3 as reactive gases, controlling the gas flow ratio of N2O, SiH4, NH3 and Ar to be 20-30:1:0-1:5, maintaining the pressure inside the equipment cavity at 0.5-2 Pa, the radio frequency power at 200-400 W, the silicon substrate temperature at ≤200℃, and the processing time at 10-80 s, so as to form a silicon oxynitride composite passivation layer with a thickness of 1-10 nm on the surface of the front transparent conductive layer.

[0012] More preferably, in step S1, the thickness of the silicon oxynitride composite passivation layer is 3-7 nm.

[0013] More preferably, the thickness of the silicon oxynitride composite passivation layer is 5 nm;

[0014] In step S1, the gas flow ratio of N2O, SiH4, NH3, and Ar is controlled to be 30:1:1:5, the pressure inside the equipment cavity is 2Pa, the radio frequency power is 400W, the silicon substrate temperature is 200℃, and the processing time is 60s, so as to form a 5nm thick silicon oxynitride composite passivation layer on the surface of the front transparent conductive layer.

[0015] Preferably, in step S1, before depositing the silicon oxynitride composite passivation layer, the method further includes: first introducing argon gas, and using the plasma generated by ionized argon gas to bombard the surface of the front transparent conductive layer, so as to form active groups on the surface of the front transparent conductive layer, thereby achieving plasma activation treatment of the surface of the front transparent conductive layer.

[0016] Preferably, in step S2, the low-temperature sintering copper paste contains copper powder that is a composite of nano copper powder and flake copper powder; the printing thickness of the low-temperature sintering copper paste is 10-30 μm.

[0017] More preferably, in step S2, the low-temperature sintering copper paste comprises, by mass percentage: 75-90% copper powder and 10-25% organic carrier; the copper powder is a mixture of nano-copper powder with a particle size of 50-200 nm and flake-shaped copper powder with a particle size of 3-4 μm at a mass ratio of 1:(3-5); the organic carrier is an organic solvent.

[0018] Preferably, in step S3, the curing is a stepped curing: first, the temperature is raised to 115-125℃ and held for 7-13 minutes; then the temperature is raised to 180-200℃ and held for 20-30 minutes.

[0019] Preferably, the interface optimization method for a front-side seedless electrode of a photovoltaic cell according to the present invention further includes: before step S1, sequentially preparing a front-side intrinsic amorphous silicon film, a P+ emitter, and a front-side transparent conductive layer on the front side of a silicon substrate, and sequentially preparing a back-side intrinsic amorphous silicon film, an N+ emitter, and a back-side transparent conductive layer on the back side of the silicon substrate; and after step S3, sequentially preparing a silver / nickel seed layer and a back-side copper electrode on the back side of the back-side transparent conductive layer.

[0020] This invention discloses a photovoltaic device, which is fabricated using the interface optimization method for a front-side photovoltaic cell without a seed layer electrode as described above in this invention.

[0021] The photovoltaic device includes: a silicon substrate, wherein the front side of the silicon substrate is sequentially provided with a front intrinsic amorphous silicon film, a P+ emitter, a front transparent conductive layer, a silicon oxynitride composite passivation layer and a front copper electrode, and the back side of the silicon substrate is sequentially provided with a back intrinsic amorphous silicon film, an N+ emitter, a back transparent conductive layer, a silver / nickel seed layer and a back copper electrode.

[0022] Compared with the prior art, the present invention has at least the following beneficial effects:

[0023] This invention discloses an interface optimization method and photovoltaic device for a front-side electrode without a seed layer in a photovoltaic cell. It eliminates the need for a front-side silver / nickel seed layer, achieving direct bonding between the front-side copper electrode and the front-side transparent conductive layer of the silicon substrate. A highly efficient interface suppression passivation tunneling layer (i.e., a 1-10 nm thick silicon oxynitride composite passivation layer) is constructed to block the interdiffusion path of copper and silicon atoms, optimizing interface contact characteristics. Combined with low-temperature sintering copper paste, the contact resistance between the front-side copper electrode and the front-side transparent conductive layer of the silicon substrate is reduced. Furthermore, it enables a fully low-temperature process (≤200℃), compatible with existing HJT cell manufacturing systems. Moreover, the interface optimization method of this invention eliminates the need for precious metals such as silver, significantly reducing metallization costs while ensuring the long-term thermal cycling stability of the photovoltaic device. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the cross-sectional structure of a photovoltaic device according to this embodiment.

[0025] Explanation of reference numerals: 1. Front copper electrode; 2. Silicon oxynitride composite passivation layer; 3. Front transparent conductive layer; 4. P+ emitter; 5. Front intrinsic amorphous silicon film; 6. Silicon substrate; 7. Back intrinsic amorphous silicon film; 8. N+ emitter; 9. Back transparent conductive layer; 10. Silver / nickel seed layer; 11. Back copper electrode. Detailed Implementation

[0026] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] This invention provides an interface optimization method for a seedless electrode on the front side of a photovoltaic cell, see [link to relevant documentation]. Figure 1 It includes the following steps:

[0028] Step 1: Take a silicon substrate 6 with a front transparent conductive layer 3 and a back transparent conductive layer 9, and pre-treat the silicon substrate 6 to remove impurities on the front surface of the front transparent conductive layer 3, so as to ensure the adhesion of the subsequent silicon oxynitride composite passivation layer 2 (i.e., SiOxNy composite passivation layer) deposited on the surface of the front transparent conductive layer 3.

[0029] In step 1, the pretreatment includes: first soaking the silicon substrate 6 in hydrofluoric acid solution, then ultrasonically cleaning it with deionized water, and then drying it.

[0030] Step 2: Place the pretreated silicon substrate 6 in a plasma-enhanced chemical vapor deposition (PECVD) apparatus to perform plasma activation treatment on the surface of the front transparent conductive layer 3 (i.e., bombard the surface of the front transparent conductive layer 3 with ionized plasma to break its surface molecular bonds; for example, first introduce argon gas, and use the plasma generated by the ionized argon gas to bombard the surface of the front transparent conductive layer 3, so that active groups such as hydroxyl and carboxyl groups are formed on its surface, which is conducive to the subsequent deposition of silicon oxynitride composite passivation layer 2). This cleans the surface impurities of the front transparent conductive layer 3 and improves the adhesion and interface density of the subsequent silicon oxynitride composite passivation layer 2 deposited on the surface of the front transparent conductive layer 3. Then, using PECVD technology, the silicon oxynitride composite passivation layer 2 is deposited on the surface of the front transparent conductive layer 3.

[0031] The process conditions for step 2 are as follows: Argon (Ar) is used as the carrier gas, silane (SiH4) as the silicon source, and nitrous oxide (N2O) and ammonia (NH3) as reactive gases. First, argon is passed through the surface of the front transparent conductive layer 3, and the plasma generated by the ionization of argon is used to bombard the surface of the front transparent conductive layer 3, so as to form active groups on the surface of the front transparent conductive layer 3, thereby realizing the plasma activation treatment of the surface of the front transparent conductive layer 3. Then, the gas flow ratio is controlled to be N2O:SiH4:NH3:Ar=(20~30):1:(0~1):5, the cavity pressure of the PECVD equipment is maintained at 0.5~2Pa, the radio frequency power is 200~400W, the silicon substrate temperature is ≤200℃, and the processing time is 10~80s, so as to form a silicon oxynitride composite passivation layer 2 with a thickness of 1~10nm on the surface of the front transparent conductive layer 3. The silicon-oxygen-nitride composite passivation layer 2 forms a covalent bond with the front transparent conductive layer 3 of the silicon substrate 6 through plasma activation, possessing both density and conductivity adjustment capabilities. A SiOxNy composite passivation layer is added to the front surface of the front transparent conductive layer 3. The thinner SiOxNy composite passivation layer can suppress copper-silicon interdiffusion, optimize interface contact characteristics, and enable electron tunneling, reducing the contact resistance between the copper electrode and the silicon substrate 6, achieving low contact resistance, and thus contributing to the realization of a front-side seedless copper electrode interface.

[0032] It should be noted that in step 2, if the SiOxNy composite passivation layer is too thin (e.g., less than 1 nm), it will lead to discontinuities in the SiOxNy composite passivation layer film, increasing the diffusion risk of the copper electrode. This is because: if the SiOxNy composite passivation layer is too thin, it will not be able to completely cover the interface defects of the substrate, leading to an increase in carrier recombination rate and a decrease in open-circuit voltage. On the other hand, if the SiOxNy composite passivation layer is too thick (e.g., greater than 10 nm), it becomes more difficult for the SiOxNy composite passivation layer to achieve electron tunneling, resulting in increased bulk resistance and making it difficult to guarantee its conductivity efficiency.

[0033] Step 3: Using screen printing technology, the low-temperature sintered copper paste is uniformly printed on the surface of the SiOxNy composite passivation layer to form the grid pattern of the front copper electrode 1. The printing thickness is 10-30 μm.

[0034] In step 3, if the copper paste printing thickness is too thin (e.g., 6nm), it will lead to a decrease in cross-sectional area, an increase in bulk resistance, and a reduction in battery efficiency. It may also cause gate breakage issues, as insufficient adhesion between the gate lines and the SiOxNy composite passivation layer can easily lead to detachment. On the other hand, if the copper paste printing thickness is too thick (e.g., 36nm), it will easily lead to an increase in the light-shielding area of ​​the copper paste, resulting in a decrease in short-circuit current. Excessive thickness may also cause the internal solvent to be difficult to completely evaporate, leaving pores and reducing the density of the gate lines.

[0035] In step 3, the low-temperature sintering copper paste comprises, by mass percentage: 75-90% copper powder and 10-25% organic carrier; wherein the copper powder is a mixture of nano-copper powder with a particle size of 50-200nm and flake-shaped copper powder with a particle size of 3-4μm at a mass ratio of 1:(3-5); wherein the organic carrier comprises 90-96% main liquid (ethylene glycol methyl ether and propylene glycol methyl ether mixed at a volume ratio of 1:1) and 4-10% secondary liquid (butyl acetate) by volume percentage, and does not contain polymer binders.

[0036] This low-temperature sintering copper paste formulation, in addition to conventional nano-copper powder, also incorporates flake-shaped copper powder with a particle size of 3–4 μm. The high activity of the nano-copper powder promotes low-temperature sintering, thus facilitating a fully low-temperature process (≤200℃) and ensuring compatibility with existing HJT battery manufacturing systems. Furthermore, the flake-shaped copper powder, when spread and stacked, helps reduce porosity, resulting in higher density and superior conductivity. Moreover, the low-temperature sintering copper paste used in the front copper electrode 1 does not contain other precious metals, significantly reducing metallization costs and making it suitable for mass production.

[0037] Step 4: Place the printed silicon substrate 6 in a hot air curing oven and perform step curing under inert gas protection: first raise the temperature to 115-125℃ at a heating rate of 5℃ / min and hold for 7-13min to remove low-boiling-point solvents; then raise the temperature to 180-200℃ and hold for 20-30min to complete the curing process of the printed low-temperature sintering copper paste and obtain the seedless front copper electrode 1.

[0038] In practice, see Figure 1 Before step 1 of the interface optimization method for a photovoltaic cell without a seed layer electrode, an intrinsic amorphous silicon film 5, a P+ emitter 4, and a transparent conductive layer 3 can be sequentially fabricated on the front side of the silicon substrate 6. On the back side of the silicon substrate 6, an intrinsic amorphous silicon film 7, an N+ emitter 8, and a transparent conductive layer 9 can be sequentially fabricated. After step 4, a silver / nickel seed layer 10 and a copper electrode 11 can be sequentially fabricated on the back side of the transparent conductive layer 9 (since the back current density is lower and the contact resistance requirement is relatively relaxed, the mature silver / nickel seed layer 10 is continued). It should be noted that the fabrication processes before step 1 and after step 4 refer to the existing HJT cell fabrication process, and therefore will not be elaborated upon here. Thus, a photovoltaic device of the present invention (essentially a HJT cell without a seed layer on the front side) is obtained, which includes: a silicon substrate 6, on the front side of the silicon substrate 6 are sequentially provided an intrinsic amorphous silicon film 5, a P+ emitter 4, a transparent conductive layer 3, a SiOxNy composite passivation layer and a copper electrode 1, and on the back side of the silicon substrate 6 are sequentially provided an intrinsic amorphous silicon film 7, an N+ emitter 8, a transparent conductive layer 9, a silver / nickel seed layer 10 and a copper electrode 11.

[0039] The following provides an interface optimization method for a seedless electrode on the front side of a photovoltaic cell and a specific example of a photovoltaic device according to the present invention.

[0040] Example 1

[0041] This embodiment describes an interface optimization method for a photovoltaic cell without a seed layer electrode on the front side. See [link to relevant documentation]. Figure 1 It includes the following steps:

[0042] Step 1: Take a silicon substrate 6 with a front transparent conductive layer 3 and a back transparent conductive layer 9 (that is, the front and back sides of the silicon substrate 6 are respectively provided with a front transparent conductive layer 3 and a back transparent conductive layer 9), and pre-treat the silicon substrate 6 to remove impurities on the front surface of the front transparent conductive layer 3 to ensure the adhesion of the subsequent silicon oxynitride composite passivation layer 2 deposited on the surface of the front transparent conductive layer 3.

[0043] In step 1, the pretreatment includes: taking a silicon substrate 6 with a front transparent conductive layer 3 and a back transparent conductive layer 9, immersing the silicon substrate in a 5% (mass fraction concentration) hydrofluoric acid solution for 30 seconds, then ultrasonically cleaning the silicon substrate with deionized water for 5 minutes, and then drying the silicon substrate at 100°C for 5 minutes to obtain the pretreated silicon substrate 6.

[0044] Step 2: Place the pretreated silicon substrate 6 in a PECVD device. First, argon gas is introduced, and the plasma generated by the ionized argon gas bombards the surface of the front transparent conductive layer 3, forming active groups on the surface of the front transparent conductive layer 3. This plasma activation treatment of the surface of the front transparent conductive layer 3 improves the adhesion and interface density of the subsequent silicon oxynitride composite passivation layer 2 deposited on the surface of the front transparent conductive layer 3. Then, set the gas flow ratio N2O:SiH4:NH3:Ar = 25:1:0.5:5 (where the flow rate of N2O is 500 sccm, the flow rate of SiH4 is 20 sccm, the flow rate of NH3 is 10 sccm, the flow rate of Ar is 100 sccm, and the total gas flow rate is 630 sccm). The cavity pressure of the PECVD device is 1 Pa, the radio frequency power is 300 W, the silicon substrate temperature is 180 °C, and the processing time is 30 s, so as to form a 3 nm thick silicon oxynitride composite passivation layer 2 on the surface of the front transparent conductive layer 3.

[0045] Step 3: Using screen printing technology, the low-temperature sintered copper paste is uniformly printed on the surface of the SiOxNy composite passivation layer to form the grid pattern of the front copper electrode 1, with a printing thickness of 20μm.

[0046] In step 3, the low-temperature sintering copper paste comprises, by mass percentage, 80% copper powder and 20% organic carrier; wherein the copper powder is a mixture of 80nm nano-copper powder and 3μm flake copper powder in a mass ratio of 1:4; wherein the organic carrier, by volume percentage, is 96% main liquid (ethylene glycol methyl ether and propylene glycol methyl ether mixed in a volume ratio of 1:1) + 4% secondary liquid (butyl acetate).

[0047] Step 4: Place the printed silicon substrate 6 in a hot air curing oven and perform step curing under nitrogen protection: first heat up to 120℃ at a heating rate of 5℃ / min and hold for 10min; then heat up to 190℃ and hold for 25min to obtain the front copper electrode 1.

[0048] See Figure 1 Before step 1 of the interface optimization method for a photovoltaic cell without a seed layer electrode, an intrinsic amorphous silicon film 5, a P+ emitter 4, and a transparent conductive layer 3 can be sequentially fabricated on the front side of the silicon substrate 6. On the back side of the silicon substrate 6, an intrinsic amorphous silicon film 7, an N+ emitter 8, and a transparent conductive layer 9 can be sequentially fabricated. After step 4, a silver / nickel seed layer 10 and a copper electrode 11 can be sequentially fabricated on the back side of the transparent conductive layer 9 (since the back current density is lower and the contact resistance requirement is relatively relaxed, the mature silver / nickel seed layer 10 is continued). It should be noted that the fabrication processes before step 1 and after step 4 refer to the existing HJT cell fabrication process, and therefore will not be elaborated upon here. Thus, a photovoltaic device (essentially a HJT cell without a seed layer on the front side) of this embodiment is obtained, which includes: a silicon substrate 6, on the front side of the silicon substrate 6 are sequentially provided an intrinsic amorphous silicon film 5, a P+ emitter 4, a transparent conductive layer 3, a SiOxNy composite passivation layer and a copper electrode 1, and on the back side of the silicon substrate 6 are sequentially provided an intrinsic amorphous silicon film 7, an N+ emitter 8, a transparent conductive layer 9, a silver / nickel seed layer 10 and a copper electrode 11.

[0049] Performance testing in Example 1: SIMS (Secondary Ion Mass Spectrometry) detection showed that the diffusion depth of copper atoms in the front copper electrode 1 was 1.0 nm; Transmission Line Model (TLM) testing showed that the contact resistance of the front copper electrode 1 was 0.8 mΩ·cm. 2 After 800 thermal cycles at -40℃ to 85℃, the efficiency of the photovoltaic device (HJT cell) decreased from 26.60% to 26.10%, with a cell efficiency degradation rate of 1.88%.

[0050] Example 2

[0051] This embodiment describes an interface optimization method and photovoltaic device for a photovoltaic cell with no seed layer electrode on the front side. Referring to Embodiment 1, the difference between Embodiment 1 and Embodiment 1 is as follows:

[0052] In step 2, the gas flow ratio N2O:SiH4:NH3:Ar = 20:1:0:5 (where the flow rate of N2O is 400 sccm, the flow rate of SiH4 is 20 sccm, the flow rate of NH3 is 0 sccm, the flow rate of Ar is 100 sccm, and the total gas flow rate is 520 sccm). The cavity pressure of the PECVD equipment is 0.5 Pa, the RF power is 200 W, the silicon substrate temperature is 150 °C, and the processing time is 80 s, in order to form a 7 nm thick silicon oxynitride composite passivation layer on the surface of the front transparent conductive layer.

[0053] In step 3, the low-temperature sintering copper paste comprises, by mass percentage, 75% copper powder and 25% organic carrier; wherein the copper powder is a mixture of 50nm nano-copper powder and 4μm flake copper powder at a mass ratio of 1:3; and the composition of the organic carrier is as described in Example 1, and therefore will not be repeated here. The printing thickness of the low-temperature sintering copper paste on the surface of the SiOxNy composite passivation layer is 10μm.

[0054] In step 4, a stepped curing process is performed under argon protection: the process parameters for the first curing stage are described in Example 1; the temperature for the second curing stage is 180°C and the holding time is 30 minutes, which will cure the copper electrode on the front side.

[0055] Performance testing in Example 2: The diffusion depth of copper atoms in the front copper electrode was 0.8 nm; the contact resistance of the front copper electrode was 1.0 mΩ·cm. 2 After 800 thermal cycles at -40℃ to 85℃, the efficiency of the photovoltaic device (HJT cell) decreased from 26.30% to 25.80%, with a cell efficiency degradation rate of 1.90%.

[0056] Example 3

[0057] This embodiment describes an interface optimization method and photovoltaic device for a photovoltaic cell with no seed layer electrode on the front side. Referring to Embodiment 1, the difference between Embodiment 1 and Embodiment 1 is as follows:

[0058] In step 2, the gas flow rate ratio N2O:SiH4:NH3:Ar = 30:1:1:5 (where the flow rate of N2O is 600 sccm, the flow rate of SiH4 is 20 sccm, the flow rate of NH3 is 20 sccm, the flow rate of Ar is 100 sccm, and the total gas flow rate is 740 sccm). The cavity pressure of the PECVD equipment is 2 Pa, the radio frequency power is 400 W, the silicon substrate temperature is 200 °C, and the processing time is 60 s, in order to form a 5 nm thick silicon oxynitride composite passivation layer on the surface of the front transparent conductive layer.

[0059] In step 3, the low-temperature sintering copper paste comprises, by mass percentage, 90% copper powder and 10% organic carrier; wherein the copper powder is a mixture of 200nm nano-copper powder and 3μm flake copper powder at a mass ratio of 1:5. The composition of the organic carrier is as described in Example 1 and will not be repeated here. The printing thickness of the low-temperature sintering copper paste on the surface of the SiOxNy composite passivation layer is 30μm.

[0060] In step 4, a stepped curing process is carried out under nitrogen protection: the process parameters for the first curing stage are as described in Example 1; the temperature for the second curing stage is 200°C and the holding time is 20 minutes, which will cure the front copper electrode.

[0061] Performance testing in Example 3: The diffusion depth of copper atoms in the front copper electrode was 0.9 nm; the contact resistance of the front copper electrode was 0.5 mΩ·cm. 2 After 800 thermal cycles at -40℃ to 85℃, the efficiency of the photovoltaic device (HJT cell) decreased from 26.80% to 26.40%, with a cell efficiency degradation rate of 1.49%.

[0062] Example 4

[0063] This embodiment describes an interface optimization method and photovoltaic device for a photovoltaic cell with no seed layer electrode on the front side. Referring to Embodiment 3, the difference between this embodiment and Embodiment 3 is:

[0064] In this embodiment, the nitrogen content during the deposition of the silicon oxynitride composite passivation layer in step 2 is different. The specific process is as follows: the gas flow rate ratio N2O:SiH4:NH3:Ar = 20:1:0:5 (where the flow rate of N2O is 400 sccm, the flow rate of SiH4 is 20 sccm, the flow rate of NH3 is 0 sccm, the flow rate of Ar is 100 sccm, and the total gas flow rate is 520 sccm), the cavity pressure of the PECVD equipment is 0.5 Pa, the radio frequency power is 200 W, the silicon substrate temperature is 150 °C, and the processing time is 80 s, so as to form a 7 nm thick silicon oxynitride composite passivation layer on the surface of the front transparent conductive layer.

[0065] Performance testing in Example 4: The copper atom diffusion depth of the front copper electrode was 0.9 nm; the contact resistance of the front copper electrode was 0.7 mΩ·cm. 2 After 800 thermal cycles at -40℃ to 85℃, the efficiency of the photovoltaic device (HJT cell) decreased from 26.73% to 26.32%, with a cell efficiency degradation rate of 1.53%.

[0066] Comparative Example 1

[0067] The photovoltaic device (HJT cell) of this comparative example, referring to Example 3, has the following structure from front surface to back surface: front copper electrode, front transparent conductive layer, P-type amorphous silicon film (P+ emitter), front intrinsic amorphous silicon film, silicon substrate, back intrinsic amorphous silicon film, N-type amorphous silicon film (N+ emitter), back transparent conductive layer, silver / nickel seed layer, and back copper electrode.

[0068] Therefore, the interface treatment method for the front-side electrode of a photovoltaic cell without a seed layer in this comparative example differs from that in Example 3 in that: the surface of the front transparent conductive layer does not have a silicon oxynitride composite passivation layer (that is, steps 1-2 of Example 3 are omitted), and the front copper electrode is directly prepared on the surface of the front transparent conductive layer (refer to steps 3-4 of Example 3).

[0069] Performance testing of Comparative Example 1: The copper atom diffusion depth of the front copper electrode is 1.2 nm; the contact resistance of the front copper electrode is 1.3 mΩ·cm. 2 After 800 thermal cycles at -40℃ to 85℃, the efficiency of the photovoltaic device (HJT cell) decreased from 26.28% to 25.74%, with a cell efficiency degradation rate of 2.05%.

[0070] Comparative Example 2

[0071] This embodiment describes an interface optimization method and photovoltaic device for a photovoltaic cell with no seed layer electrode on the front side. Referring to Embodiment 3, the difference between this embodiment and Embodiment 3 is:

[0072] In step 3, all the copper powder in the low-temperature sintering copper paste is nano copper powder with a particle size of 200nm (excluding flaky copper powder with a particle size of 3μm), and the other components of the low-temperature sintering copper paste are the same as in Example 3.

[0073] Performance testing of Comparative Example 2: The copper atom diffusion depth of the front copper electrode is 1.0 nm; the contact resistance of the front copper electrode is 1.1 mΩ·cm. 2 After 800 thermal cycles at -40℃ to 85℃, the efficiency of the photovoltaic device (HJT cell) decreased from 26.40% to 25.88%, with a cell efficiency degradation rate of 1.97%.

[0074] Performance test results

[0075] The performance test results of Examples 1-4 and Comparative Examples 1-2 are summarized in Table 1 below:

[0076] Table 1

[0077]

[0078]

[0079] Based on the data in Table 1, we can see that:

[0080] (1) The copper diffusion depth and contact resistance of the front copper electrode in Example 3 are lower than those of Comparative Example 1 (the front side of Comparative Example 1 has no silicon oxynitride composite passivation layer), which proves that the silicon oxynitride composite passivation layer (SiOxNy composite passivation layer) prepared between the front copper electrode and the front transparent conductive layer in Example 3 can effectively reduce the conductivity resistance, block the copper atom migration channel, and solve the problem of copper-silicon interdiffusion without a seed layer.

[0081] (2) The contact resistance of the front copper electrode prepared by the low-temperature sintering copper paste of Example 3 using a copper powder compound scheme of nano copper powder and flake copper powder is significantly lower than that of Comparative Example 2 (which uses a single nano copper powder scheme to prepare the front copper electrode). In addition, the battery efficiency of Example 3 is also higher than that of Comparative Example 2, and the battery efficiency decay rate of Example 3 is also lower than that of Comparative Example 2. This proves that the low-temperature sintering copper paste of the present invention can form a denser conductive network after mixing nano copper powder and flake copper powder, thereby improving the collection efficiency of charge carriers, which helps to reduce the contact resistance of the front copper electrode and improve the battery efficiency and battery efficiency decay rate.

[0082] (3) The difference between Example 3 and Example 4 is that the nitrogen content during the deposition of the SiOxNy composite passivation layer is different, resulting in different thicknesses of the SiOxNy composite passivation layers obtained in the two examples. The test results show that the copper diffusion depth, contact resistance, and battery efficiency decay rate of the front copper electrode of both examples are within a reasonable range. It can be seen that SiOxNy composite passivation layers of different thicknesses in the range of 1 to 10 nm can meet the performance requirements.

[0083] (4) In Example 2, the copper diffusion depth of the front copper electrode is relatively shallow, the contact resistance of the front copper electrode is relatively high, and the thickness of the SiOxNy composite passivation layer is relatively thick (10 μm). In contrast, the contact resistance of the front copper electrode in Example 3 is relatively low, and the copper diffusion depth and the thickness of the SiOxNy composite passivation layer (5 nm) in Example 3 are both between those of Example 1 (3 nm thick SiOxNy composite passivation layer) and Example 2. This indicates that preparing a 5 nm thick SiOxNy composite passivation layer between the front copper electrode and the front transparent conductive layer is the average thickness for hindering copper diffusion and reducing tunneling resistance. An excessively thick SiOxNy composite passivation layer will sacrifice conductivity. By comparing the nitrogen content during the deposition of the SiOxNy composite passivation layer in Examples 1-3 (the nitrogen content in Example 2 is relatively low, while the nitrogen content in Example 3 is relatively high), it was found that appropriate nitrogen doping can further improve the compactness and interfacial bonding of the SiOxNy composite passivation layer and further reduce the contact resistance.

[0084] Therefore, the process parameter combination of the interface optimization method for the front-side seedless electrode of a photovoltaic cell in Example 3 achieves optimal performance. This is because the higher RF power (400W) enhances plasma activity, making the bonding between the SiOxNy composite passivation layer and the front-side transparent conductive layer of the silicon substrate tighter. The 30:1 N2O to SiH4 flow ratio (i.e., appropriately increasing the nitrogen content when depositing the SiOxNy composite passivation layer) optimizes the film density of the SiOxNy composite passivation layer. Combined with a curing temperature of 200℃, the low-temperature sintering copper paste (which adopts a copper powder composite scheme of nano copper powder and flake copper powder) is fully sintered while ensuring low-temperature compatibility. Moreover, the copper powder content in Example 3 is relatively high, which can effectively improve the conductivity of the front-side copper electrode. Therefore, a lower contact resistance of the front-side copper electrode and better thermal cycling stability are obtained (i.e., after 800 thermal cycles at -40℃ to 85℃, the cell efficiency decay rate is lower).

[0085] In summary, the interface optimization method for the front-side seedless electrode of the photovoltaic cell of the present invention, before fabricating the front-side copper electrode, uses plasma in-situ deposition technology to prepare a 1-10 nm thick SiOxNy composite passivation layer (i.e., silicon oxynitride composite passivation layer) on the surface of the front-side transparent conductive layer of the HJT cell silicon substrate, which has both diffusion blocking and conductive contact functions; then, it uses a specially formulated low-temperature sintering copper paste to prepare the front-side copper electrode on the SiOxNy composite passivation layer; thus, the following advantages can be obtained:

[0086] 1. Complete elimination of silver and cost reduction: The front side completely eliminates the silver / nickel seed layer, and the copper paste does not contain precious metal components such as silver. The metallization cost is reduced by more than 60% compared with traditional silver electrodes and by more than 30% compared with copper electrodes containing silver seed layers.

[0087] 2. Highly efficient suppression of copper-silicon interdiffusion: The plasma-formed in-situ SiOxNy composite passivation layer has a dense network structure, which can effectively block the diffusion path of copper atoms to the silicon substrate. Secondary ion mass spectrometry (SIMS) analysis shows that the diffusion depth of copper atoms in the silicon substrate of the front copper electrode is ≤1 nm, lower than the diffusion depth of existing seedless schemes (e.g., the diffusion depth of Comparative Example 1 is 1.2 nm). After thermal cycling testing (-40℃~85℃, 800 cycles), no Cu3Si phase is generated, and the cell efficiency degradation rate of the photovoltaic device is less than 2%.

[0088] 3. Low contact resistance: By optimizing the thickness (1–10 nm) and composition ratio of the SiOxNy composite passivation layer (e.g., an N2O / SiH4 flow ratio of 20–30), a balance between passivation and conductivity is achieved, resulting in contact resistance as low as 0.5–1 mΩ·cm. 2 It is superior to existing nickel seed layer schemes (1.0–1.5 mΩ·cm). 2 ).

[0089] 4. Composite low-temperature sintering copper paste: By combining nano copper powder and flake copper powder, a dense conductive network is formed, which can make the interfacial bonding force and structure of the front copper electrode more stable.

[0090] 5. Low-temperature compatibility throughout the entire process: The temperature of all process steps is controlled below 200℃, avoiding the crystallization damage of the amorphous silicon layer of HJT cells caused by high temperatures. It can be directly adapted to existing HJT cell production lines without the need for equipment modification.

[0091] 6. Simplified process and environmental protection: The low-temperature sintering copper paste does not contain polymer binders, and the curing process does not require a separate glue removal step, reducing waste gas emissions. Moreover, the process flow is shortened by 30% compared to the seed layer solution, which is conducive to improving mass production efficiency.

[0092] Although preferred embodiments of the present invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present invention.

[0093] The technical solution provided by the present invention has been described in detail above. Specific examples have been used to illustrate the principle and implementation of the present invention. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for interface optimization of front side seed layer free electrode of a photovoltaic cell, characterized in that, The method comprises the following steps: S1, taking a silicon substrate with a front transparent conductive layer, placing the silicon substrate in a plasma enhanced chemical vapor deposition device, and depositing a 1-10 nm thick silicon oxynitride composite passivation layer on the surface of the front transparent conductive layer through plasma in-situ deposition; S2, uniformly printing a low-temperature sintering type copper paste on the surface of the silicon oxynitride composite passivation layer; wherein the sintering temperature of the low-temperature sintering type copper paste is ≤200℃; S3, curing the printed low-temperature sintering type copper paste under inert gas protection, thereby obtaining a front copper electrode.

2. The method for interface optimization of a front side seed layer free electrode of a photovoltaic cell according to claim 1, characterized in that, In step S1, the process conditions of the plasma in-situ deposition include: taking Ar as the carrier gas, SiH4 as the silicon source, N2O and NH3 as the reactive gas, controlling the gas flow ratio of N2O, SiH4, NH3, and Ar to be 20-30:1:0-1:5, maintaining the pressure in the device cavity at 0.5-2 Pa, taking the radio frequency power to be 200-400 W, controlling the silicon substrate temperature to be ≤200℃, and taking the processing time to be 10-80 s, so as to form a 1-10 nm thick silicon oxynitride composite passivation layer on the surface of the front transparent conductive layer.

3. The method for interface optimization of a front-side seed layer free electrode of a photovoltaic cell according to claim 1 or 2, characterized in that, In step S1, the thickness of the silicon oxynitride composite passivation layer is 3-7 nm.

4. The method of interface optimization for front side seed layer free electrode of a photovoltaic cell according to claim 3, characterized in that, The thickness of the silicon oxynitride composite passivation layer is 5 nm; In step S1, the gas flow ratio of N2O, SiH4, NH3, and Ar is controlled to be 30:1:1:5, the pressure in the device cavity is 2 Pa, the radio frequency power is 400 W, the silicon substrate temperature is 200℃, and the processing time is 60 s, so as to form a 5 nm thick silicon oxynitride composite passivation layer on the surface of the front transparent conductive layer.

5. The method of interface optimization for front side seed layer free electrode of a photovoltaic cell according to claim 1, wherein, In step S1, before depositing the silicon oxynitride composite passivation layer, it further comprises: first introducing argon, and using the plasma generated by the ionized argon to bombard the surface of the front transparent conductive layer, so as to form active groups on the surface of the front transparent conductive layer, thereby realizing the plasma activation treatment of the surface of the front transparent conductive layer.

6. The method of interface optimization for front side seed layer free electrode of a photovoltaic cell according to claim 1, wherein, In step S2, the low-temperature sintering type copper paste contains copper powder compounded by nano copper powder and flaky copper powder; and the printing thickness of the low-temperature sintering type copper paste is 10-30 μm.

7. The method of interface optimization for front side seed layer free electrode of a photovoltaic cell according to claim 6, characterized in that, In step S2, the low-temperature sintering type copper paste comprises, in terms of mass percentage: 75-90% of copper powder and 10-25% of organic carrier; the copper powder is mixed by 50-200 nm nano copper powder and 3-4 μm flaky copper powder at a mass ratio of 1:(3-5); and the organic carrier is an organic solvent.

8. The method of interface optimization for front side seed layer free electrode of a photovoltaic cell according to claim 1, wherein, In step S3, the curing is stepwise curing: first heating to 115-125℃, and keeping warm for 7-13 min; and then heating to 180-200℃, and keeping warm for 20-30 min.

9. The method of interface optimization for front side seed layer free electrode of a photovoltaic cell according to claim 1, wherein, Further comprising: Before step S1, preparing a front intrinsic amorphous silicon film, a P+ emitter, and a front transparent conductive layer on the front surface of the silicon substrate in sequence, and preparing a back intrinsic amorphous silicon film, an N+ emitter, and a back transparent conductive layer on the back surface of the silicon substrate in sequence; and after step S3, preparing a silver / nickel seed layer and a back copper electrode on the back surface of the back transparent conductive layer in sequence.

10. A photovoltaic device, characterized by The photovoltaic device is prepared by using the interface optimization method without seed layer electrode on the front surface of the photovoltaic cell according to any one of claims 1-9. The photovoltaic device comprises a silicon substrate, a front intrinsic amorphous silicon film, a P+ emitter, a front transparent conductive layer, a silicon oxynitride composite passivation layer and a front copper electrode are sequentially arranged on the front surface of the silicon substrate, a back intrinsic amorphous silicon film, an N+ emitter, a back transparent conductive layer, a silver / nickel seed layer and a back copper electrode are sequentially arranged on the back surface of the silicon substrate.

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