Non-volatile memory including depletion layer having superlattice and related methods

Abstract

A memory device may include an array of memory cells on a semiconductor substrate. Each memory cell may include a first well having a first conductivity type on the semiconductor substrate, a second well adjacent to the first well and having a second conductivity type and defining a depletion layer with the first well, and a superlattice within the depletion layer. The superlattice may include stacked sets of layers, each set of layers including a stacked base semiconductor monolayer defining a base semiconductor portion and a non-semiconductor monolayer (s), the non-semiconductor monolayer (s) being confined within the lattice of adjacent base semiconductor portions. Trap source atoms may also be within the stacked set of layers. Each memory cell may also include spaced apart source and drain regions adjacent the second well and defining a channel therebetween, and a gate overlying the channel.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more specifically, to semiconductor memory devices and related methods. Background Technology

[0002] Structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by increasing charge carrier mobility. For example, U.S. Patent Application No. 2003 / 0057416 by Currie et al. discloses a strained silicon material layer, silicon-germanium, and relaxed silicon, including an impurity-free region (which would otherwise cause performance degradation). The biaxial strain generated in the upper silicon layer alters carrier mobility, thereby allowing for higher speed and / or lower power devices. Published U.S. Patent Application No. 2003 / 0034529 by Fitzgerald et al. discloses a CMOS inverter based on a similar strained silicon technique.

[0003] Takagi's U.S. Patent No. 6,472,685B2 discloses a semiconductor device comprising a silicon-carbon layer sandwiched between silicon layers, such that the conduction band and valence band of the second silicon layer are subjected to tensile strain. Electrons with smaller effective mass and induced by the electric field applied to the gate electrode are confined within the second silicon layer; therefore, it is certain that the n-channel MOSFET has higher mobility.

[0004] U.S. Patent No. 4,937,204 to Ishibashi et al. discloses a superlattice in which multiple layers (fewer than eight monolayers, including partially or binary or binary compound semiconductor layers) are grown alternately and epitaxially. The main current flows perpendicular to the superlattice layers.

[0005] U.S. Patent No. 5,357,119 to Wang et al. discloses a silicon-germanium short-period superlattice with higher mobility achieved by reducing alloy scattering in the superlattice. Following these principles, U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET comprising a channel layer containing an alloy of silicon and a second material present in proportion within the silicon lattice, which places the channel layer under tensile stress.

[0006] Tsu's U.S. Patent No. 5,216,262 discloses a quantum well structure comprising two barrier regions and a thin epitaxially grown semiconductor layer sandwiched between the barriers. Each barrier region comprises alternating SiO2 / Si layers, typically ranging in thickness from 2 to 6 monolayers. A thicker portion of silicon is sandwiched between the barriers.

[0007] Similarly, Tsu's article entitled "Phenomena in silicon nanostructure devices," published online on September 6, 2000, in *Applied Physics and Materials Science & Processing*, pages 391-402, discloses a silicon / oxygen semiconductor-atomic superlattice (SAS). The Si / O superlattice is disclosed as useful in silicon quantum dot devices and light-emitting devices. Specifically, a green electroluminescent diode structure was constructed and tested. Current flow in the diode structure is vertical, i.e., perpendicular to the SAS layer. The disclosed SAS can comprise semiconductor layers separated by adsorbates such as oxygen atoms and CO molecules. The growth of silicon on the adsorbed oxygen monolayer is described as epitaxy with a relatively low defect density. One SAS structure comprises a 1.1 nm thick silicon portion (i.e., approximately 8 silicon atomic layers) and another structure with twice this silicon thickness. In their article "Chemical Design of Direct-Gap Light-Emitting Silicon" published in Physics Review Letters, Vol. 89, No. 7 (August 12, 2002), Luo et al. further discussed Tsu's luminescent SAS structure.

[0008] U.S. Patent No. 7,105,895 to Wang et al. discloses a thin silicon and a barrier structure of oxygen, carbon, nitrogen, phosphorus, antimony, arsenic, or hydrogen, thereby reducing the current flowing vertically through the lattice by more than four orders of magnitude. The insulating / barrier layer allows low-defect epitaxial silicon to be subsequently deposited onto the insulating layer.

[0009] Published UK patent application 2,347,520 by Mears et al. discloses that the principles of aperiodic photonic bandgap (APBG) structures may be suitable for electronic bandgap engineering. Specifically, the application discloses that material parameters (e.g., the location of band minimums, effective mass, etc.) can be set to produce new aperiodic materials with desired band structure properties. Other parameters that can be used to design materials (such as electrical conductivity, thermal conductivity, and dielectric constant or magnetic permeability) are also disclosed.

[0010] Furthermore, U.S. Patent No. 6,376,337 to Wang et al. discloses a method for producing an insulating or barrier layer for a semiconductor device, the method comprising depositing a layer of silicon and at least one additional element on a silicon substrate, wherein the deposited layer is substantially defect-free, thereby allowing substantially defect-free epitaxial silicon to be deposited on the deposited layer. Alternatively, a monolayer of one or more elements (preferably containing oxygen) is adsorbed onto the silicon substrate. Multiple insulating layers sandwiched between the epitaxial silicon form a barrier complex.

[0011] Despite the existence of such methods, further enhancements may be desired to achieve improved performance in semiconductor devices using advanced semiconductor materials and processing techniques. Summary of the Invention

[0012] The memory device may include a semiconductor substrate and an array of memory cells on the semiconductor substrate. Each memory cell may include a first well on the semiconductor substrate having a first conductivity type, a second well adjacent to the first well having a second conductivity type and defining a depletion layer with respect to the first well, and a superlattice within the depletion layer. The superlattice may include multiple stacked layers, wherein each layer includes multiple stacked base semiconductor monolayers and at least one non-semiconductor monolayer, the multiple stacked base semiconductor monolayers defining base semiconductor portions, and the at least one non-semiconductor monolayer being confined within a lattice of an adjacent base semiconductor portion. Multiple trap source atoms may also be present within the multiple stacked layers, wherein the trap source atoms are different from the semiconductor atoms of the base semiconductor monolayers and the non-semiconductor atoms of the at least one non-semiconductor monolayer. Each memory cell may also include spaced-apart source and drain regions adjacent to the second well and defining a channel therebetween, and a gate overlying the channel.

[0013] In one embodiment, each memory cell may further include a body contact region coupled to the first well. In an example implementation, at least one non-semiconductor monolayer may comprise oxygen, and the underlying semiconductor layer may comprise silicon. In one embodiment, the memory cell may comprise a non-volatile memory cell. The memory device may also include corresponding shallow trench isolation (STI) regions adjacent to the source and drain regions and extending into the first well. Furthermore, the trap source atoms may comprise at least one of fluorine, sulfur, and selenium. The memory device may also include multiple word lines and bit lines connecting the multiple memory cells.

[0014] A method for fabricating a memory device may include forming an array of memory cells on a semiconductor substrate. Each memory cell may include a first well having a first conductivity type on the semiconductor substrate, a second well adjacent to the first well having a second conductivity type and defining a depletion layer therebetween, and a superlattice within the depletion layer. The superlattice may include a plurality of stacked layers, wherein each layer includes a plurality of stacked base semiconductor monolayers and at least one non-semiconductor monolayer, the plurality of stacked base semiconductor monolayers defining base semiconductor portions, the at least one non-semiconductor monolayer being confined within a lattice of an adjacent base semiconductor portion, and a plurality of trap source atoms within the plurality of stacked layers, wherein the trap source atoms are different from semiconductor atoms of the base semiconductor monolayers and non-semiconductor atoms of the at least one non-semiconductor monolayer. Each memory cell may also include spaced-apart source and drain regions adjacent to the second well and defining a channel therebetween, and a gate overlying the channel.

[0015] In some embodiments, the method may further include forming a corresponding body contact region coupled to a first well for each memory cell. In an example implementation, at least one non-semiconductor monolayer may comprise oxygen, and the underlying semiconductor layer may comprise silicon.

[0016] In one implementation, the memory cell may comprise a non-volatile memory cell. The method may also include forming a corresponding shallow trench isolation (STI) region adjacent to the source and drain regions of each memory cell and extending into a first well. Furthermore, the trap source atoms may comprise at least one of fluorine, sulfur, and selenium. The method may also include forming multiple word lines and bit lines connecting the array of memory cells. Attached Figure Description

[0017] Figure 1 This is a highly magnified schematic cross-sectional view of a superlattice for use in a semiconductor device according to an example embodiment.

[0018] Figure 2 yes Figure 1 A perspective schematic atomic diagram of a portion of a superlattice is shown in the image.

[0019] Figure 3 This is a high-magnification schematic cross-sectional view of another embodiment of the superlattice according to the example embodiment.

[0020] Figure 4 This is a schematic cross-sectional view of an example implementation of a non-volatile memory cell, which includes a superlattice that enables charge trapping.

[0021] Figure 5A It is a combination shown during programming. Figure 4 The top plan view of the non-volatile memory device of the memory cells, and Figures 5B-5D In programming Figure 5B The memory cell shown during Figure 5A A schematic cross-sectional view of different memory cells within a memory device.

[0022] Figure 6 It is used for Figure 5B A graph showing the current versus voltage during example programming operations of a memory cell.

[0023] Figure 7A It was shown during the erasure process. Figure 5A Top view of the non-volatile memory device, and Figures 7B-7D It is wiping Figure 5B The memory cell shown during Figure 5A A schematic cross-sectional view of different memory cells within a memory device.

[0024] Figure 8 It is used for Figure 5B A graph showing the current versus voltage during an example erase operation of a memory cell.

[0025] Figure 9 This is shown during reading in the example embodiment. Figure 5B A schematic cross-sectional view of a memory cell.

[0026] Figures 10A-10C It is made according to the example embodiment. Figure 4 A series of schematic cross-sectional views of the method for constructing memory cells.

[0027] Figures 11A-11C It is made according to another example embodiment. Figure 4 A series of schematic cross-sectional views of the method for constructing memory cells.

[0028] Figure 12A This is an explanation Figure 4 A graph showing an example doped profile below the channel of a memory cell.

[0029] Figure 12B This is an explanation Figure 4 A graph showing the example doped profiles below the source / drain regions of a memory cell.

[0030] Figure 12C This is an explanation of the example embodiments. Figure 4 A graph showing the drain leakage characteristics of a memory cell.

[0031] Figure 12D This is an explanation in the example implementation. Figure 4 The graph shows the drain breakdown voltage of the memory cell versus NWEL and PWELL doses.

[0032] Figure 13 It is a representative size Figure 4 A transmission electron microscope (TEM) image of an example implementation of a depleted layer of memory cells.

[0033] Figures 14A-14D These are a series of schematic cross-sectional views illustrating another memory cell with a depletion layer having traps and associated fabrication steps in the example implementation.

[0034] Figure 15 It can be used Figure 14D A graph showing the atomic concentration versus depth of the MST-C superlattice used to fabricate memory cells.

[0035] Figure 16 It can be used Figure 14D TEM image of the fabrication of the memory cell in the MST-C superlattice.

[0036] Figure 17 It is after annealing to form nanocrystals Figure 16 TEM image of SiC superlattice. Detailed Implementation

[0037] Example embodiments will now be described more fully below with reference to the accompanying drawings, which illustrate example embodiments. However, embodiments may be embodied in many different forms and should not be construed as being limited to the specific examples set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. The same reference numerals always refer to the same elements, and prime number symbols are used to indicate similar elements in different embodiments.

[0038] Generally, this disclosure relates to semiconductor devices having an enhanced semiconductor superlattice therein to provide performance enhancement characteristics. The enhanced semiconductor superlattice may also be referred to herein as an "MST" layer or "MST technology".

[0039] More specifically, MST technology involves advanced semiconductor materials, such as superlattices 25, which are further described below. In previous work, the applicant has theoretically demonstrated that certain superlattices, as described herein, reduce the effective mass of charge carriers, and that this results in higher charge carrier mobility. See, for example, U.S. Patent No. 6,897,472, which is incorporated herein by reference in its entirety.

[0040] Further developments by the applicant have established that the presence of an MST layer can advantageously improve the mobility of free carriers in semiconductor materials (e.g., at the interface between silicon and an insulator such as SiO2 or HfO2). The applicant has theoretically elucidated, but does not wish to be bound by, that this may occur due to various mechanisms. One mechanism is achieved by reducing the concentration of charged impurities near the interface, by reducing the diffusion of these impurities and / or by trapping impurities so that they do not reach the vicinity of the interface. Charged impurities induce Coulomb scattering, which reduces mobility. Another mechanism is achieved by improving the quality of the interface. For example, oxygen emitted from the MST film can provide oxygen to the Si-SiO2 interface, thereby reducing the substoichiometric SiO2 concentration. x The presence of [something]. Alternatively, the MST layer trapping interstitial atoms can reduce the concentration of interstitial silicon near the Si-SiO2 interface, thereby reducing the formation of substoichiometric SiO2. x The trend of substoichiometry of SiO at the Si-SiO2 interface. x It is known that SiO2 exhibits poor insulating properties relative to stoichiometry. Reducing the substoichiometric SiO2 at the interface... xThe amount of [insert value here] can more effectively confine free carriers (electrons or holes) within silicon, and thus improve the mobility of these carriers due to the electric field applied parallel to the interface, which is standard practice in field-effect transistor (“FET”) structures. Scattering caused by the direct influence of the interface is called “surface roughness scattering,” which can be advantageously reduced by bringing the MST layer closer after annealing or during thermal oxidation.

[0041] In addition to the enhanced mobility properties of the MST structure, as will be discussed further below, they can also be formed or used to provide piezoelectric, thermoelectric, and / or ferroelectric properties, which are advantageous for use in many different types of devices.

[0042] Now for reference Figure 1 and Figure 2 The material or structure is in the form of a superlattice 25, the structure of which is controlled at the atomic or molecular level and can be formed using known atomic or molecular layer deposition techniques. The superlattice 25 comprises multiple layers 45a-45n arranged in a stacked relationship, perhaps with specific references... Figure 1 A schematic cross-sectional view is best understood.

[0043] Each layer group 45a-45n of the superlattice 25 illustratively includes a plurality of stacked basic semiconductor monolayers 46 defining corresponding basic semiconductor portions 46a-46n and one or more non-semiconductor monolayers 50 thereon. For clarity, by... Figure 1 The dotted lines in the diagram indicate a non-semiconductor monolayer 50.

[0044] The non-semiconductor monolayer 50 exemplaryly comprises a non-semiconductor monolayer confined within the lattice of adjacent basic semiconductor portions. "Confined within the lattice of adjacent basic semiconductor portions" means that at least some semiconductor atoms from the opposing basic semiconductor portions 46a-46n are chemically bound together by the intervening non-semiconductor monolayer 50, such as... Figure 2 As seen in [the text]. As will be discussed further below, this configuration can generally be achieved by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n using atomic layer deposition techniques, such that not all available semiconductor bonding sites (i.e., less than full or 100% coverage) are occupied by bonds to non-semiconductor atoms. Therefore, as another monolayer 46 of semiconductor material is deposited on or above the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will occupy the remaining vacant bonding sites of the semiconductor atoms beneath the non-semiconductor monolayer.

[0045] In other embodiments, there may be more than one such non-semiconductor monolayer. It should be noted that the reference to non-semiconductor or semiconductor monolayers herein means that the material used for the monolayer, if formed in bulk, would be either non-semiconductor or semiconductor. That is, those skilled in the art will recognize that a single monolayer of a material such as silicon may not necessarily exhibit the same properties as when it is formed in bulk or as a relatively thick layer.

[0046] The applicant theoretically clarifies (but does not wish to be bound by) that the non-semiconductor monolayer 50 and the adjacent basic semiconductor portions 46a-46n enable the superlattice 25 to have an effective mass of appropriate conductivity for charge carriers in the direction parallel to the layers, which is lower than that present otherwise. Alternatively, this parallel direction is orthogonal to the stacking direction. The band-modification layer 50 also enables the superlattice 25 to have a common band structure, while advantageously acting as an insulator between layers or regions vertically located above and below the superlattice.

[0047] Furthermore, this superlattice structure can also advantageously serve as a barrier to the diffusion of dopants and / or materials between layers vertically located above and below the superlattice 25. Those skilled in the art will appreciate that these properties can therefore advantageously allow the superlattice 25 to provide an interface for high-k dielectrics, which not only reduces the diffusion of high-k materials into the channel region but also advantageously reduces unwanted scattering effects and improves device mobility.

[0048] It can also be theoretically explained that semiconductor devices including superlattice 25 can enjoy higher charge carrier mobility based on a lower effective mass of conductivity than those existing in other ways. In some embodiments, and as a result of band engineering obtained by this embodiment, superlattice 25 can further have a substantially direct bandgap, which is particularly advantageous, for example, for optoelectronic devices.

[0049] The superlattice 25 also illustratively includes a cap layer 52 on the upper layer group 45n. The cap layer 52 may contain a plurality of basic semiconductor monolayers 46. The cap layer 52 may have 2 to 100 monolayers of basic semiconductors, and more preferably between 10 and 50 monolayers.

[0050] Each basic semiconductor portion 46a-46n may contain a basic semiconductor selected from the group consisting of group IV semiconductors, group III-V semiconductors, and group II-VI semiconductors. Of course, those skilled in the art will recognize that the term "group IV semiconductor" also includes group IV-IV semiconductors. More specifically, for example, the basic semiconductor may include at least one of silicon and germanium.

[0051] For example, each non-semiconductor monolayer 50 may contain a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, carbon, and carbon-oxygen. This non-semiconductor remains desirablely thermally stable upon deposition of the next layer, thereby facilitating fabrication. In other embodiments, the non-semiconductor may be additional inorganic or organic elements or compounds compatible with a given semiconductor process, as those skilled in the art will appreciate. More specifically, for example, the base semiconductor may contain at least one of silicon and germanium.

[0052] It should be noted that the term "monolayer" is intended to include both single atomic layers and single molecular layers. It should also be noted that a non-semiconductor monolayer 50 provided by a single monolayer is also intended to include monolayers in which not all possible sites are occupied (i.e., less than all or 100% coverage). For example, see special reference. Figure 2 The atomic illustrations illustrate a 4 / 1 repeating structure using silicon as the base semiconductor material and oxygen as the bandgap modifier. In the illustrated example, only half of the possible sites for oxygen are occupied.

[0053] In other embodiments and / or with different materials, this half-occupancy will not necessarily be apparent to those skilled in the art. Indeed, even in this schematic diagram, it can be seen that individual oxygen atoms in a given monolayer are not aligned along the plane as precisely as those skilled in the art of atomic deposition would recognize. For example, a preferred occupancy range is approximately one-eighth to half the area at which possible oxygen sites are occupied, although other figures may be used in some embodiments.

[0054] Silicon and oxygen are widely used in conventional semiconductor processing, and therefore, manufacturers can readily utilize the materials described herein. Atomic or monolayer deposition is also now widely used. Therefore, those skilled in the art will recognize that the semiconductor device comprising a superlattice 25 according to this embodiment can be readily adopted and implemented.

[0055] Now, additional references Figure 3 Now, another embodiment of the superlattice 25' with different properties according to this embodiment is described. In this embodiment, a repeating pattern of 3 / 1 / 5 / 1 is illustrated. More specifically, the lowest basic semiconductor portion 46a' has three monolayers, and the second lowest basic semiconductor portion 46b' has five monolayers. This pattern is always repeated in the superlattice 25'. Each of the non-semiconductor monolayers 50' may comprise a single monolayer. For such a Si / O superlattice 25', the enhancement of charge carrier mobility is independent of the orientation in the layer plane. Figure 3 Other elements not specifically mentioned above are related to the references above. Figure 1 The elements being discussed are similar and do not require further discussion here.

[0056] In some device embodiments, all the base semiconductor portions of the superlattice may be the same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be of different numbers of monolayers thick. In still other embodiments, all the base semiconductor portions may be of different numbers of monolayers thick.

[0057] Turn now Figure 4 and Figure 5A First, an example non-volatile random access memory (NVRAM) cell 100 and an associated NVRAM device 101 are described. Generally, in the memory cell 100, NWELL / PWELL are enclosed and isolated within PWELL / NWELL, and a depletion layer exists at the junction between the two wells, which utilizes an MST film to enable charge trapping. More specifically, in the memory device 101, a plurality of memory cells 100 are formed on a semiconductor substrate 102 and electrically coupled in an array via word lines 103 and bit lines 104. Each memory cell 100 illustratively includes a first well 105 having a first conductivity type on the semiconductor substrate 102. Figure 4 In the example, it is of type n, which limits it to NWELL (although this could be PWELL in other embodiments).

[0058] The second well 106 is adjacent to (here above) the first well 105 and has a second conductivity type (here p-type, defining PWELL, although this could be NWELL in other embodiments). More specifically, in the illustrated configuration, the second well 106 is closed by the first well 105. Furthermore, the second well 106 and the first well 105 define a depletion layer 107. A superlattice 125, as described above, is located within the depletion layer 107. More specifically, trap source atoms (e.g., fluorine, sulfur, or selenium) are also located within the stacked layer group of the superlattice 125. Each memory cell 100 also illustratively includes a spaced-apart source region 108 and a drain region 109 adjacent to (here within) the second well 106 and defining a channel 110 therebetween. A gate 111 (which may include a gate dielectric and a gate electrode, not shown) is overlaid on the channel 110 over the PWELL 106. The memory device 100 also illustratively includes a body contact region 112 coupled to a first well 105, and a shallow trench isolation (STI) region 113 adjacent to the source region 108, the drain region 109 and the body region 112 and extending into the first well below the superlattice 125, as shown.

[0059] The MST superlattice film 125 provides the technical advantage of allowing embedded traps in the depletion layer 107 to trap electrons / holes to facilitate read and erase operations. The depletion layer 107 is designed to be located above the bottom of the STI region 113, thus providing the further technical advantage of preventing write and erase interference to other cells 100 during programming and erase operations.

[0060] Now for reference Figures 5B-5D This describes the programming of a given memory cell within memory device 101. The cell 100 being programmed is shown in [the image / description]. Figure 5B In the diagram, unprogrammed cells in the same column as the cells being programmed are shown. Figure 5C In the middle, and from columns different from the programmed cells, unprogrammed cells are shown. Figure 5D The voltage levels applied to the source 108, drain 109, gate 111, and body 112 contacts during each of these operations are shown in the figure. Figures 5A-5D In general, the source 108, drain 109, and gate 111 contacts are coupled to ground (GND), and the body 112 contact is coupled to the write voltage (+V). WRITE This is achieved by applying a high reverse body bias. This leads to avalanche breakdown at the depletion region 107 (i.e., at the PWELL / NWELL junction), as... Figure 5B As shown in the diagram. More specifically, this allows the embedded traps in the depletion layer 107 to capture the generated electrons, thereby programming the desired cell 100.

[0061] To avoid interfering with the programming of other cells 100 in the same and different columns, the offset voltage (+V) will be... OS1 The source 108 and drain 109 contacts of other cells are applied. The gate 111 and body 112 contacts of other memory cells 100 are coupled to ground GND, and the body contacts, in addition to those in the same column as the programming cell, are also coupled to the write voltage V. WRITE Also refer to Figure 6 The curve 120, V WRITE and V OS1 It can be determined by the diode's IV characteristics, and can be set, for example, to V. WRITE =5V and V OS1 =0.5V, although other suitable values ​​may be used in different embodiments.

[0062] Turn Figures 7A-7D Now, let's describe the erasure of the same memory cell. For example... Figure 7B As seen in the image, this is achieved by applying V to the body contact 112. ERASEThis is achieved by applying a positive body bias to inject holes into the depletion region 107 (trap layer). The injected holes recombine with the trap electrons to erase the previous programmed state. This can be achieved by applying a V to the body contact 112. ERASE At the same time, apply an appropriate offset voltage (V) OS2 The source 108 and drain 109 contacts of the cells in the same column are applied (see...). Figure 7C ) and V OS2 The source 108, drain 109, and body 112 contacts of the cells in other columns are applied to prevent interference from the programmed values ​​in the other cells 100. See also... Figure 8 The curve 130, V ERASE and V OS2 It can also be determined from the diode's IV characteristic curve, and for example, it can be set to V. ERASE =1V and V OS2 =0.8V, although other suitable values ​​may be used in different embodiments.

[0063] refer to Figure 9 This illustrates an example read operation of memory cell 100. Due to the bulk effect, the trapped electrons increase the MOSFET V. T The current programming state can be read using conventional MOSFET operation, i.e., by applying gate and drain bias voltages to the unit transistor as shown. In this example, source contact 108 is connected to ground (GND), and gate contact 111 is connected to the read voltage V. READ The drain 109 contact is connected to V. DD Furthermore, the base contact 112 is also connected to ground (GND).

[0064] Turn now Figures 10A-10C An example method for fabricating a memory cell 100 is described. In the illustrated example, an MST-O (Si / O) film 125 is formed on a substrate 102 (e.g., a silicon substrate). In this embodiment, the MST-O layer 125 is deposited via blanket epitaxial growth across the entire substrate 102 prior to the STI module. A relatively thick cap layer 152 can be epitaxially formed on the MST-O film 125, followed by the STI module to define the STI region 113. NWELL, trap source atoms (fluorine in this example), and PWELL dopants can then be sequentially introduced to confine atomic fluorine within the depletion region 107. Figure 10C As an example, ion implantation can be used to implant fluorine. Figures 11A-11C A similar process for fabricating memory cell 100 is shown, but here the MST-O film 125 is fabricated by selective epitaxial growth in a silicon trench after the STI module, as shown. NWELL, fluorine, and PWELL implantation can be performed in the same manner as described above. Figure 11C).

[0065] For further reference Figures 12A-12D Figures 160-163 now describe the example well doping process design considerations for an example 180nm baseline. For this implementation, the following example well process sequence was used:

[0066] MST Si cap 300nm (as grown)

[0067] STI module

[0068] P 400keV 3E13 / cm2

[0069] F 140keV 2E14 / cm2

[0070] 1050C 5s RTA

[0071] B 35keV 7E12 / cm2

[0072] B 60keV 1.6E13 / cm2

[0073] 1050C 5s RTA

[0074] P 19keV 2E15 / cm2

[0075] 1050C 5s RTA

[0076] The resulting doping profile below channel 110 is shown in plot 160, while the doping profile below source / drain regions 108, 109 is shown in plot 161. Plots 160 and 161 illustrate how the MST-O film advantageously confines / concentrates fluorine atoms at desired locations within the well, i.e., in depletion layer 107. Furthermore, example drain leakage characteristics are shown in plot 162, and the relationship between drain breakdown voltage (BV) and NWELL and PWELL doses is shown in plot 163. Figure 13 A TEM image 164 of a memory cell 100 with an example size is provided, although it should be understood that other sizes may be used in different embodiments.

[0077] As described above, memory cell 100 includes an MST-O layer 125 located in the PWELL / NWELL depletion region 107, in which atomic fluorine (or other trap source dopants) is confined within one or more MST-O layers. Now turning to Figures 14A-14D An alternative method is described, which utilizes MST layer 225 (see [link]). Figure 16Nanocrystals are fabricated within the NWELL / PWELL depletion region 207 to similarly provide electron / hole trapping. More specifically, this method utilizes the fabrication process of MST film 225 to form SiC nanocrystals 228 within the PWELL / NWELL depletion layer 207.

[0078] The process begins with the formation of an MST-C (Si / C) film 225 on a substrate 202, followed by a thick epitaxial cap layer 252, as shown in the reference above. Figure 10A Similarly, as described above. However, at this point, relatively high-temperature rapid thermal annealing (RTA) is performed, for example, 1100°C, which results in the formation of SiC nanocrystals 228 instead of the MST film 225. Figure 14A Then the subsequent steps described above for fabricating an NFET in a shallow PWELL surrounded by an NWELL (or vice versa) can be performed. More specifically, an STI module can be executed to form STI region 213 ( Figure 14B Then came the injection of NWELL 205, fluorine, and PWELL 206. Figure 14C Then, a gate 211, a source 208, and a drain 209, as well as a body 212, and associated contacts (not shown) can be formed to complete the non-volatile memory cell 200. Figure 14D ).

[0079] Figure 15 Figure 260 provides example carbon dose times and concentrations that can be used to configure MST-C films for SiC nanocrystal formation. Increasing the dose time from 1 second to 3 seconds increases carbon binding to 2.15E15 at / cm. 2 This also increases the carbon binding value measured by X-rays to 0.005%, approximately twice that of a 725°C dose per second at the same carbon level measured by SIMS.

[0080] Figure 16 and Figure 17 TEM images 265 and 270 illustrate an example MST-C method for SiC nanocrystal formation, utilizing annealing at 1100 °C for two minutes, and exemplify the resulting SiC nanocrystals 228. However, it should be noted that other annealing times and temperatures can be used in different embodiments. For example, annealing times are typically in the range of about 2–5 minutes, and temperatures can be in the range of about 945 °C–1100 °C in different embodiments. Generally, as the annealing temperature increases, 800 cm⁻¹… -1 The transverse optical SiC peaks in the vicinity become more prominent.

[0081] Due to the stacked structure of the initial superlattice 225 (see...) Figure 16Therefore, the resulting nanocrystals 228 are similarly confined within the lattice of adjacent semiconductor portions, just like the original superlattice, as discussed further above. Moreover, due to the formation of atomic layers of carbon atoms, the nanocrystals tend to form laterally spaced apart from each other in vertically spaced rows, as... Figure 17 As seen in the image.

[0082] In summary, the programming and erasing of the aforementioned NVRAM cells 100 and 200 can be advantageously controlled by injecting electrons and holes via NWELL body bias. More specifically, a write operation can be achieved by applying forward and reverse bias voltages to the NWELL contacts to induce avalanche breakdown of the PWELL / NWELL junction. Electrons or holes generated by avalanche breakdown are trapped in electron or hole traps in depletion layers 107 or 207. An erase operation can be achieved by applying negative and positive bias voltages to the body contacts 112 and 212 to inject holes or electrons to neutralize the trapped electrons or holes. A read operation can be achieved by applying bias voltages to the gates 111 and 211 and the drains 109 and 209 of the cell transistors.

[0083] Many modifications and other embodiments of the invention will arise for those skilled in the art from the teachings presented in the foregoing description and the associated drawings. Therefore, it should be understood that this disclosure is not limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the claims.

Claims

1. A memory device, comprising: An array of memory cells on a semiconductor substrate, each memory cell comprising: A first well, located on the semiconductor substrate, has a first conductivity type; A second well, which is adjacent to the first well and has a second conductivity type, and defines a depletion layer with respect to the first well; A superlattice, the superlattice being within a depletion layer, and the superlattice comprising... Multiple stacked layers, each layer comprising multiple stacked base semiconductor monolayers and at least one non-semiconductor monolayer, the multiple stacked base semiconductor monolayers defining base semiconductor portions, the at least one non-semiconductor monolayer being constrained within a lattice of an adjacent base semiconductor portion, and Multiple trap source atoms, the multiple trap source atoms being within the multiple stacked layers, the trap source atoms being different from the semiconductor atoms of the base semiconductor monolayer and the non-semiconductor atoms of the at least one non-semiconductor monolayer; The spaced-apart source and drain regions are adjacent to the second well and define a channel therebetween. as well as A gate, which is overlaid on the channel.

2. The memory device according to claim 1, wherein, Each memory cell also includes a body contact region coupled to the first well.

3. The memory device according to claim 1, wherein, The at least one non-semiconductor monolayer includes oxygen.

4. The memory device according to claim 1, wherein, The base semiconductor layer comprises silicon.

5. The memory device according to claim 1, wherein, The memory unit includes a non-volatile memory unit.

6. The memory device of claim 1, comprising a corresponding shallow trench isolation (STI) region adjacent to the source region and the drain region and extending into the first well.

7. The memory device according to claim 1, wherein, The trap source atoms include at least one of fluorine, sulfur, and selenium.

8. The memory device of claim 1, comprising a plurality of word lines and bit lines connecting the array of the memory cells.

9. A method for manufacturing a memory device, comprising: Multiple memory cells are formed on a semiconductor substrate, and the multiple memory cells are electrically coupled in an array, each memory cell including... A first well, located on the semiconductor substrate, has the first conductivity type; A second well, which is adjacent to the first well and has a second conductivity type, and defines a depletion layer with respect to the first well; A superlattice, the superlattice being within the depletion layer, and the superlattice comprising... Multiple stacked layers, each layer comprising multiple stacked base semiconductor monolayers and at least one non-semiconductor monolayer, the multiple stacked base semiconductor monolayers defining base semiconductor portions, the at least one non-semiconductor monolayer being constrained within a lattice of an adjacent base semiconductor portion, and Multiple trap source atoms, the multiple trap source atoms being within the multiple stacked layers, the trap source atoms being different from the semiconductor atoms of the base semiconductor monolayer and the non-semiconductor atoms of the at least one non-semiconductor monolayer; The spaced-apart source and drain regions are adjacent to the second well and define a channel therebetween. as well as A gate is clad over the channel.

10. The method of claim 9, further comprising forming a corresponding body contact region coupled to the first well of each memory cell.

11. The method according to claim 9, wherein, The at least one non-semiconductor monolayer includes oxygen.

12. The method according to claim 9, wherein, The base semiconductor layer comprises silicon.

13. The method according to claim 9, wherein, The memory unit includes a non-volatile memory unit.

14. The method of claim 9, further comprising forming a shallow trench isolation (STI) region adjacent to the source and drain regions of each memory cell and extending into the first well.

15. The method according to claim 9, wherein, The trap source atoms include at least one of fluorine, sulfur, and selenium.

16. The method of claim 9, further comprising forming a plurality of word lines and bit lines connecting the array of the memory cells.

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